2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <dev/drm2/drmP.h>
32 #include <dev/drm2/radeon/radeon_drm.h>
36 #ifdef CONFIG_PPC_PMAC
37 /* not sure which of these are needed */
38 #include <asm/machdep.h>
39 #include <asm/pmac_feature.h>
41 #include <asm/pci-bridge.h>
42 #endif /* CONFIG_PPC_PMAC */
44 /* old legacy ATI BIOS routines */
46 /* COMBIOS table offsets */
47 enum radeon_combios_table_offset {
48 /* absolute offset tables */
49 COMBIOS_ASIC_INIT_1_TABLE,
50 COMBIOS_BIOS_SUPPORT_TABLE,
51 COMBIOS_DAC_PROGRAMMING_TABLE,
52 COMBIOS_MAX_COLOR_DEPTH_TABLE,
53 COMBIOS_CRTC_INFO_TABLE,
54 COMBIOS_PLL_INFO_TABLE,
55 COMBIOS_TV_INFO_TABLE,
56 COMBIOS_DFP_INFO_TABLE,
57 COMBIOS_HW_CONFIG_INFO_TABLE,
58 COMBIOS_MULTIMEDIA_INFO_TABLE,
59 COMBIOS_TV_STD_PATCH_TABLE,
60 COMBIOS_LCD_INFO_TABLE,
61 COMBIOS_MOBILE_INFO_TABLE,
62 COMBIOS_PLL_INIT_TABLE,
63 COMBIOS_MEM_CONFIG_TABLE,
64 COMBIOS_SAVE_MASK_TABLE,
65 COMBIOS_HARDCODED_EDID_TABLE,
66 COMBIOS_ASIC_INIT_2_TABLE,
67 COMBIOS_CONNECTOR_INFO_TABLE,
68 COMBIOS_DYN_CLK_1_TABLE,
69 COMBIOS_RESERVED_MEM_TABLE,
70 COMBIOS_EXT_TMDS_INFO_TABLE,
71 COMBIOS_MEM_CLK_INFO_TABLE,
72 COMBIOS_EXT_DAC_INFO_TABLE,
73 COMBIOS_MISC_INFO_TABLE,
74 COMBIOS_CRT_INFO_TABLE,
75 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
76 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
77 COMBIOS_FAN_SPEED_INFO_TABLE,
78 COMBIOS_OVERDRIVE_INFO_TABLE,
79 COMBIOS_OEM_INFO_TABLE,
80 COMBIOS_DYN_CLK_2_TABLE,
81 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
82 COMBIOS_I2C_INFO_TABLE,
83 /* relative offset tables */
84 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
85 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
86 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
87 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
88 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
89 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
90 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
91 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
92 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
93 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
94 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
97 enum radeon_combios_ddc {
107 enum radeon_combios_connector {
108 CONNECTOR_NONE_LEGACY,
109 CONNECTOR_PROPRIETARY_LEGACY,
110 CONNECTOR_CRT_LEGACY,
111 CONNECTOR_DVI_I_LEGACY,
112 CONNECTOR_DVI_D_LEGACY,
113 CONNECTOR_CTV_LEGACY,
114 CONNECTOR_STV_LEGACY,
115 CONNECTOR_UNSUPPORTED_LEGACY
118 const int legacy_connector_convert[] = {
119 DRM_MODE_CONNECTOR_Unknown,
120 DRM_MODE_CONNECTOR_DVID,
121 DRM_MODE_CONNECTOR_VGA,
122 DRM_MODE_CONNECTOR_DVII,
123 DRM_MODE_CONNECTOR_DVID,
124 DRM_MODE_CONNECTOR_Composite,
125 DRM_MODE_CONNECTOR_SVIDEO,
126 DRM_MODE_CONNECTOR_Unknown,
129 static uint16_t combios_get_table_offset(struct drm_device *dev,
130 enum radeon_combios_table_offset table)
132 struct radeon_device *rdev = dev->dev_private;
134 uint16_t offset = 0, check_offset;
140 /* absolute offset tables */
141 case COMBIOS_ASIC_INIT_1_TABLE:
142 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
144 offset = check_offset;
146 case COMBIOS_BIOS_SUPPORT_TABLE:
147 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
149 offset = check_offset;
151 case COMBIOS_DAC_PROGRAMMING_TABLE:
152 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
154 offset = check_offset;
156 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
157 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
159 offset = check_offset;
161 case COMBIOS_CRTC_INFO_TABLE:
162 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
164 offset = check_offset;
166 case COMBIOS_PLL_INFO_TABLE:
167 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
169 offset = check_offset;
171 case COMBIOS_TV_INFO_TABLE:
172 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
174 offset = check_offset;
176 case COMBIOS_DFP_INFO_TABLE:
177 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
179 offset = check_offset;
181 case COMBIOS_HW_CONFIG_INFO_TABLE:
182 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
184 offset = check_offset;
186 case COMBIOS_MULTIMEDIA_INFO_TABLE:
187 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
189 offset = check_offset;
191 case COMBIOS_TV_STD_PATCH_TABLE:
192 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
194 offset = check_offset;
196 case COMBIOS_LCD_INFO_TABLE:
197 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
199 offset = check_offset;
201 case COMBIOS_MOBILE_INFO_TABLE:
202 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
204 offset = check_offset;
206 case COMBIOS_PLL_INIT_TABLE:
207 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
209 offset = check_offset;
211 case COMBIOS_MEM_CONFIG_TABLE:
212 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
214 offset = check_offset;
216 case COMBIOS_SAVE_MASK_TABLE:
217 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
219 offset = check_offset;
221 case COMBIOS_HARDCODED_EDID_TABLE:
222 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
224 offset = check_offset;
226 case COMBIOS_ASIC_INIT_2_TABLE:
227 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
229 offset = check_offset;
231 case COMBIOS_CONNECTOR_INFO_TABLE:
232 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
234 offset = check_offset;
236 case COMBIOS_DYN_CLK_1_TABLE:
237 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
239 offset = check_offset;
241 case COMBIOS_RESERVED_MEM_TABLE:
242 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
244 offset = check_offset;
246 case COMBIOS_EXT_TMDS_INFO_TABLE:
247 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
249 offset = check_offset;
251 case COMBIOS_MEM_CLK_INFO_TABLE:
252 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
254 offset = check_offset;
256 case COMBIOS_EXT_DAC_INFO_TABLE:
257 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
259 offset = check_offset;
261 case COMBIOS_MISC_INFO_TABLE:
262 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
264 offset = check_offset;
266 case COMBIOS_CRT_INFO_TABLE:
267 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
269 offset = check_offset;
271 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
272 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
274 offset = check_offset;
276 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
277 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
279 offset = check_offset;
281 case COMBIOS_FAN_SPEED_INFO_TABLE:
282 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
284 offset = check_offset;
286 case COMBIOS_OVERDRIVE_INFO_TABLE:
287 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
289 offset = check_offset;
291 case COMBIOS_OEM_INFO_TABLE:
292 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
294 offset = check_offset;
296 case COMBIOS_DYN_CLK_2_TABLE:
297 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
299 offset = check_offset;
301 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
302 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
304 offset = check_offset;
306 case COMBIOS_I2C_INFO_TABLE:
307 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
309 offset = check_offset;
311 /* relative offset tables */
312 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
314 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
316 rev = RBIOS8(check_offset);
318 check_offset = RBIOS16(check_offset + 0x3);
320 offset = check_offset;
324 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
326 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
328 rev = RBIOS8(check_offset);
330 check_offset = RBIOS16(check_offset + 0x5);
332 offset = check_offset;
336 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
338 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
340 rev = RBIOS8(check_offset);
342 check_offset = RBIOS16(check_offset + 0x7);
344 offset = check_offset;
348 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
350 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
352 rev = RBIOS8(check_offset);
354 check_offset = RBIOS16(check_offset + 0x9);
356 offset = check_offset;
360 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
362 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
364 while (RBIOS8(check_offset++));
367 offset = check_offset;
370 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
372 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
374 check_offset = RBIOS16(check_offset + 0x11);
376 offset = check_offset;
379 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
381 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
383 check_offset = RBIOS16(check_offset + 0x13);
385 offset = check_offset;
388 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
390 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
392 check_offset = RBIOS16(check_offset + 0x15);
394 offset = check_offset;
397 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
399 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
401 check_offset = RBIOS16(check_offset + 0x17);
403 offset = check_offset;
406 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
408 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
410 check_offset = RBIOS16(check_offset + 0x2);
412 offset = check_offset;
415 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
417 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
419 check_offset = RBIOS16(check_offset + 0x4);
421 offset = check_offset;
432 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
437 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
441 raw = rdev->bios + edid_info;
442 size = EDID_LENGTH * (raw[0x7e] + 1);
443 edid = malloc(size, DRM_MEM_KMS, M_WAITOK);
447 memcpy((unsigned char *)edid, raw, size);
449 if (!drm_edid_is_valid(edid)) {
450 free(edid, DRM_MEM_KMS);
454 rdev->mode_info.bios_hardcoded_edid = edid;
455 rdev->mode_info.bios_hardcoded_edid_size = size;
459 /* this is used for atom LCDs as well */
461 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
465 if (rdev->mode_info.bios_hardcoded_edid) {
466 edid = malloc(rdev->mode_info.bios_hardcoded_edid_size,
467 DRM_MEM_KMS, M_WAITOK);
469 memcpy((unsigned char *)edid,
470 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
471 rdev->mode_info.bios_hardcoded_edid_size);
478 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
479 enum radeon_combios_ddc ddc,
483 struct radeon_i2c_bus_rec i2c;
487 * DDC_NONE_DETECTED = none
488 * DDC_DVI = RADEON_GPIO_DVI_DDC
489 * DDC_VGA = RADEON_GPIO_VGA_DDC
490 * DDC_LCD = RADEON_GPIOPAD_MASK
491 * DDC_GPIO = RADEON_MDGPIO_MASK
493 * DDC_MONID = RADEON_GPIO_MONID
494 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
496 * DDC_MONID = RADEON_GPIO_MONID
497 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
499 * DDC_MONID = RADEON_GPIO_DVI_DDC
500 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
502 * DDC_MONID = RADEON_GPIO_MONID
503 * DDC_CRT2 = RADEON_GPIO_MONID
505 * DDC_MONID = RADEON_GPIOPAD_MASK
506 * DDC_CRT2 = RADEON_GPIO_MONID
509 case DDC_NONE_DETECTED:
514 ddc_line = RADEON_GPIO_DVI_DDC;
517 ddc_line = RADEON_GPIO_VGA_DDC;
520 ddc_line = RADEON_GPIOPAD_MASK;
523 ddc_line = RADEON_MDGPIO_MASK;
526 if (rdev->family == CHIP_RS300 ||
527 rdev->family == CHIP_RS400 ||
528 rdev->family == CHIP_RS480)
529 ddc_line = RADEON_GPIOPAD_MASK;
530 else if (rdev->family == CHIP_R300 ||
531 rdev->family == CHIP_R350) {
532 ddc_line = RADEON_GPIO_DVI_DDC;
535 ddc_line = RADEON_GPIO_MONID;
538 if (rdev->family == CHIP_R200 ||
539 rdev->family == CHIP_R300 ||
540 rdev->family == CHIP_R350) {
541 ddc_line = RADEON_GPIO_DVI_DDC;
543 } else if (rdev->family == CHIP_RS300 ||
544 rdev->family == CHIP_RS400 ||
545 rdev->family == CHIP_RS480)
546 ddc_line = RADEON_GPIO_MONID;
547 else if (rdev->family >= CHIP_RV350) {
548 ddc_line = RADEON_GPIO_MONID;
551 ddc_line = RADEON_GPIO_CRT2_DDC;
555 if (ddc_line == RADEON_GPIOPAD_MASK) {
556 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
557 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
558 i2c.a_clk_reg = RADEON_GPIOPAD_A;
559 i2c.a_data_reg = RADEON_GPIOPAD_A;
560 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
561 i2c.en_data_reg = RADEON_GPIOPAD_EN;
562 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
563 i2c.y_data_reg = RADEON_GPIOPAD_Y;
564 } else if (ddc_line == RADEON_MDGPIO_MASK) {
565 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
566 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
567 i2c.a_clk_reg = RADEON_MDGPIO_A;
568 i2c.a_data_reg = RADEON_MDGPIO_A;
569 i2c.en_clk_reg = RADEON_MDGPIO_EN;
570 i2c.en_data_reg = RADEON_MDGPIO_EN;
571 i2c.y_clk_reg = RADEON_MDGPIO_Y;
572 i2c.y_data_reg = RADEON_MDGPIO_Y;
574 i2c.mask_clk_reg = ddc_line;
575 i2c.mask_data_reg = ddc_line;
576 i2c.a_clk_reg = ddc_line;
577 i2c.a_data_reg = ddc_line;
578 i2c.en_clk_reg = ddc_line;
579 i2c.en_data_reg = ddc_line;
580 i2c.y_clk_reg = ddc_line;
581 i2c.y_data_reg = ddc_line;
584 if (clk_mask && data_mask) {
585 /* system specific masks */
586 i2c.mask_clk_mask = clk_mask;
587 i2c.mask_data_mask = data_mask;
588 i2c.a_clk_mask = clk_mask;
589 i2c.a_data_mask = data_mask;
590 i2c.en_clk_mask = clk_mask;
591 i2c.en_data_mask = data_mask;
592 i2c.y_clk_mask = clk_mask;
593 i2c.y_data_mask = data_mask;
594 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
595 (ddc_line == RADEON_MDGPIO_MASK)) {
596 /* default gpiopad masks */
597 i2c.mask_clk_mask = (0x20 << 8);
598 i2c.mask_data_mask = 0x80;
599 i2c.a_clk_mask = (0x20 << 8);
600 i2c.a_data_mask = 0x80;
601 i2c.en_clk_mask = (0x20 << 8);
602 i2c.en_data_mask = 0x80;
603 i2c.y_clk_mask = (0x20 << 8);
604 i2c.y_data_mask = 0x80;
606 /* default masks for ddc pads */
607 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
608 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
609 i2c.a_clk_mask = RADEON_GPIO_A_1;
610 i2c.a_data_mask = RADEON_GPIO_A_0;
611 i2c.en_clk_mask = RADEON_GPIO_EN_1;
612 i2c.en_data_mask = RADEON_GPIO_EN_0;
613 i2c.y_clk_mask = RADEON_GPIO_Y_1;
614 i2c.y_data_mask = RADEON_GPIO_Y_0;
617 switch (rdev->family) {
625 case RADEON_GPIO_DVI_DDC:
626 i2c.hw_capable = true;
629 i2c.hw_capable = false;
635 case RADEON_GPIO_DVI_DDC:
636 case RADEON_GPIO_MONID:
637 i2c.hw_capable = true;
640 i2c.hw_capable = false;
647 case RADEON_GPIO_VGA_DDC:
648 case RADEON_GPIO_DVI_DDC:
649 case RADEON_GPIO_CRT2_DDC:
650 i2c.hw_capable = true;
653 i2c.hw_capable = false;
660 case RADEON_GPIO_VGA_DDC:
661 case RADEON_GPIO_DVI_DDC:
662 i2c.hw_capable = true;
665 i2c.hw_capable = false;
674 case RADEON_GPIO_VGA_DDC:
675 case RADEON_GPIO_DVI_DDC:
676 i2c.hw_capable = true;
678 case RADEON_GPIO_MONID:
679 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
680 * reliably on some pre-r4xx hardware; not sure why.
682 i2c.hw_capable = false;
685 i2c.hw_capable = false;
690 i2c.hw_capable = false;
696 i2c.hpd = RADEON_HPD_NONE;
706 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
708 struct drm_device *dev = rdev->ddev;
709 struct radeon_i2c_bus_rec i2c;
711 u8 id, blocks, clk, data;
716 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
718 blocks = RBIOS8(offset + 2);
719 for (i = 0; i < blocks; i++) {
720 id = RBIOS8(offset + 3 + (i * 5) + 0);
722 clk = RBIOS8(offset + 3 + (i * 5) + 3);
723 data = RBIOS8(offset + 3 + (i * 5) + 4);
725 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
726 (1 << clk), (1 << data));
734 void radeon_combios_i2c_init(struct radeon_device *rdev)
736 struct drm_device *dev = rdev->ddev;
737 struct radeon_i2c_bus_rec i2c;
741 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
743 * 0x60, 0x64, 0x68, mm
747 * 0x60, 0x64, 0x68, gpiopads, mm
751 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
752 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
754 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
755 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
759 i2c.hw_capable = true;
762 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
764 if (rdev->family == CHIP_R300 ||
765 rdev->family == CHIP_R350) {
766 /* only 2 sw i2c pads */
767 } else if (rdev->family == CHIP_RS300 ||
768 rdev->family == CHIP_RS400 ||
769 rdev->family == CHIP_RS480) {
771 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
772 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
775 i2c = radeon_combios_get_i2c_info_from_table(rdev);
777 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
778 } else if ((rdev->family == CHIP_R200) ||
779 (rdev->family >= CHIP_R300)) {
781 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
782 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
785 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
786 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
788 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
789 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
793 bool radeon_combios_get_clock_info(struct drm_device *dev)
795 struct radeon_device *rdev = dev->dev_private;
797 struct radeon_pll *p1pll = &rdev->clock.p1pll;
798 struct radeon_pll *p2pll = &rdev->clock.p2pll;
799 struct radeon_pll *spll = &rdev->clock.spll;
800 struct radeon_pll *mpll = &rdev->clock.mpll;
804 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
806 rev = RBIOS8(pll_info);
809 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
810 p1pll->reference_div = RBIOS16(pll_info + 0x10);
811 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
812 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
813 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
814 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
817 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
818 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
820 p1pll->pll_in_min = 40;
821 p1pll->pll_in_max = 500;
826 spll->reference_freq = RBIOS16(pll_info + 0x1a);
827 spll->reference_div = RBIOS16(pll_info + 0x1c);
828 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
829 spll->pll_out_max = RBIOS32(pll_info + 0x22);
832 spll->pll_in_min = RBIOS32(pll_info + 0x48);
833 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
836 spll->pll_in_min = 40;
837 spll->pll_in_max = 500;
841 mpll->reference_freq = RBIOS16(pll_info + 0x26);
842 mpll->reference_div = RBIOS16(pll_info + 0x28);
843 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
844 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
847 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
848 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
851 mpll->pll_in_min = 40;
852 mpll->pll_in_max = 500;
855 /* default sclk/mclk */
856 sclk = RBIOS16(pll_info + 0xa);
857 mclk = RBIOS16(pll_info + 0x8);
863 rdev->clock.default_sclk = sclk;
864 rdev->clock.default_mclk = mclk;
866 if (RBIOS32(pll_info + 0x16))
867 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
869 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
876 bool radeon_combios_sideport_present(struct radeon_device *rdev)
878 struct drm_device *dev = rdev->ddev;
881 /* sideport is AMD only */
882 if (rdev->family == CHIP_RS400)
885 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
888 if (RBIOS16(igp_info + 0x4))
894 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
895 0x00000808, /* r100 */
896 0x00000808, /* rv100 */
897 0x00000808, /* rs100 */
898 0x00000808, /* rv200 */
899 0x00000808, /* rs200 */
900 0x00000808, /* r200 */
901 0x00000808, /* rv250 */
902 0x00000000, /* rs300 */
903 0x00000808, /* rv280 */
904 0x00000808, /* r300 */
905 0x00000808, /* r350 */
906 0x00000808, /* rv350 */
907 0x00000808, /* rv380 */
908 0x00000808, /* r420 */
909 0x00000808, /* r423 */
910 0x00000808, /* rv410 */
911 0x00000000, /* rs400 */
912 0x00000000, /* rs480 */
915 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
916 struct radeon_encoder_primary_dac *p_dac)
918 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
922 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
926 struct drm_device *dev = encoder->base.dev;
927 struct radeon_device *rdev = dev->dev_private;
929 uint8_t rev, bg, dac;
930 struct radeon_encoder_primary_dac *p_dac = NULL;
933 p_dac = malloc(sizeof(struct radeon_encoder_primary_dac),
934 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
939 /* check CRT table */
940 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
942 rev = RBIOS8(dac_info) & 0x3;
944 bg = RBIOS8(dac_info + 0x2) & 0xf;
945 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
946 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
948 bg = RBIOS8(dac_info + 0x2) & 0xf;
949 dac = RBIOS8(dac_info + 0x3) & 0xf;
950 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
952 /* if the values are all zeros, use the table */
953 if (p_dac->ps2_pdac_adj)
957 if (!found) /* fallback to defaults */
958 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
964 radeon_combios_get_tv_info(struct radeon_device *rdev)
966 struct drm_device *dev = rdev->ddev;
968 enum radeon_tv_std tv_std = TV_STD_NTSC;
970 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
972 if (RBIOS8(tv_info + 6) == 'T') {
973 switch (RBIOS8(tv_info + 7) & 0xf) {
975 tv_std = TV_STD_NTSC;
976 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
980 DRM_DEBUG_KMS("Default TV standard: PAL\n");
983 tv_std = TV_STD_PAL_M;
984 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
987 tv_std = TV_STD_PAL_60;
988 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
991 tv_std = TV_STD_NTSC_J;
992 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
995 tv_std = TV_STD_SCART_PAL;
996 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
999 tv_std = TV_STD_NTSC;
1001 ("Unknown TV standard; defaulting to NTSC\n");
1005 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1007 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1010 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1013 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1016 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1026 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1027 0x00000000, /* r100 */
1028 0x00280000, /* rv100 */
1029 0x00000000, /* rs100 */
1030 0x00880000, /* rv200 */
1031 0x00000000, /* rs200 */
1032 0x00000000, /* r200 */
1033 0x00770000, /* rv250 */
1034 0x00290000, /* rs300 */
1035 0x00560000, /* rv280 */
1036 0x00780000, /* r300 */
1037 0x00770000, /* r350 */
1038 0x00780000, /* rv350 */
1039 0x00780000, /* rv380 */
1040 0x01080000, /* r420 */
1041 0x01080000, /* r423 */
1042 0x01080000, /* rv410 */
1043 0x00780000, /* rs400 */
1044 0x00780000, /* rs480 */
1047 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1048 struct radeon_encoder_tv_dac *tv_dac)
1050 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1051 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1052 tv_dac->ps2_tvdac_adj = 0x00880000;
1053 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1054 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1058 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1062 struct drm_device *dev = encoder->base.dev;
1063 struct radeon_device *rdev = dev->dev_private;
1065 uint8_t rev, bg, dac;
1066 struct radeon_encoder_tv_dac *tv_dac = NULL;
1069 tv_dac = malloc(sizeof(struct radeon_encoder_tv_dac),
1070 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1074 /* first check TV table */
1075 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1077 rev = RBIOS8(dac_info + 0x3);
1079 bg = RBIOS8(dac_info + 0xc) & 0xf;
1080 dac = RBIOS8(dac_info + 0xd) & 0xf;
1081 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1083 bg = RBIOS8(dac_info + 0xe) & 0xf;
1084 dac = RBIOS8(dac_info + 0xf) & 0xf;
1085 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1087 bg = RBIOS8(dac_info + 0x10) & 0xf;
1088 dac = RBIOS8(dac_info + 0x11) & 0xf;
1089 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1090 /* if the values are all zeros, use the table */
1091 if (tv_dac->ps2_tvdac_adj)
1093 } else if (rev > 1) {
1094 bg = RBIOS8(dac_info + 0xc) & 0xf;
1095 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1096 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1098 bg = RBIOS8(dac_info + 0xd) & 0xf;
1099 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1100 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1102 bg = RBIOS8(dac_info + 0xe) & 0xf;
1103 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1104 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1105 /* if the values are all zeros, use the table */
1106 if (tv_dac->ps2_tvdac_adj)
1109 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1112 /* then check CRT table */
1114 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1116 rev = RBIOS8(dac_info) & 0x3;
1118 bg = RBIOS8(dac_info + 0x3) & 0xf;
1119 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1120 tv_dac->ps2_tvdac_adj =
1121 (bg << 16) | (dac << 20);
1122 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1123 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1124 /* if the values are all zeros, use the table */
1125 if (tv_dac->ps2_tvdac_adj)
1128 bg = RBIOS8(dac_info + 0x4) & 0xf;
1129 dac = RBIOS8(dac_info + 0x5) & 0xf;
1130 tv_dac->ps2_tvdac_adj =
1131 (bg << 16) | (dac << 20);
1132 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1133 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1134 /* if the values are all zeros, use the table */
1135 if (tv_dac->ps2_tvdac_adj)
1139 DRM_INFO("No TV DAC info found in BIOS\n");
1143 if (!found) /* fallback to defaults */
1144 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1149 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1153 struct radeon_encoder_lvds *lvds = NULL;
1154 uint32_t fp_vert_stretch, fp_horz_stretch;
1155 uint32_t ppll_div_sel, ppll_val;
1156 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1158 lvds = malloc(sizeof(struct radeon_encoder_lvds),
1159 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1164 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1165 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1167 /* These should be fail-safe defaults, fingers crossed */
1168 lvds->panel_pwr_delay = 200;
1169 lvds->panel_vcc_delay = 2000;
1171 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1172 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1173 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1175 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1176 lvds->native_mode.vdisplay =
1177 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1178 RADEON_VERT_PANEL_SHIFT) + 1;
1180 lvds->native_mode.vdisplay =
1181 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1183 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1184 lvds->native_mode.hdisplay =
1185 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1186 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1188 lvds->native_mode.hdisplay =
1189 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1191 if ((lvds->native_mode.hdisplay < 640) ||
1192 (lvds->native_mode.vdisplay < 480)) {
1193 lvds->native_mode.hdisplay = 640;
1194 lvds->native_mode.vdisplay = 480;
1197 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1198 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1199 if ((ppll_val & 0x000707ff) == 0x1bb)
1200 lvds->use_bios_dividers = false;
1202 lvds->panel_ref_divider =
1203 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1204 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1205 lvds->panel_fb_divider = ppll_val & 0x7ff;
1207 if ((lvds->panel_ref_divider != 0) &&
1208 (lvds->panel_fb_divider > 3))
1209 lvds->use_bios_dividers = true;
1211 lvds->panel_vcc_delay = 200;
1213 DRM_INFO("Panel info derived from registers\n");
1214 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1215 lvds->native_mode.vdisplay);
1220 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1223 struct drm_device *dev = encoder->base.dev;
1224 struct radeon_device *rdev = dev->dev_private;
1226 uint32_t panel_setup;
1229 struct radeon_encoder_lvds *lvds = NULL;
1231 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1234 lvds = malloc(sizeof(struct radeon_encoder_lvds),
1235 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1240 for (i = 0; i < 24; i++)
1241 stmp[i] = RBIOS8(lcd_info + i + 1);
1244 DRM_INFO("Panel ID String: %s\n", stmp);
1246 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1247 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1249 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1250 lvds->native_mode.vdisplay);
1252 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1253 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1255 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1256 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1257 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1259 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1260 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1261 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1262 if ((lvds->panel_ref_divider != 0) &&
1263 (lvds->panel_fb_divider > 3))
1264 lvds->use_bios_dividers = true;
1266 panel_setup = RBIOS32(lcd_info + 0x39);
1267 lvds->lvds_gen_cntl = 0xff00;
1268 if (panel_setup & 0x1)
1269 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1271 if ((panel_setup >> 4) & 0x1)
1272 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1274 switch ((panel_setup >> 8) & 0x7) {
1276 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1279 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1282 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1288 if ((panel_setup >> 16) & 0x1)
1289 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1291 if ((panel_setup >> 17) & 0x1)
1292 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1294 if ((panel_setup >> 18) & 0x1)
1295 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1297 if ((panel_setup >> 23) & 0x1)
1298 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1300 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1302 for (i = 0; i < 32; i++) {
1303 tmp = RBIOS16(lcd_info + 64 + i * 2);
1307 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1308 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1309 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1310 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1311 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1312 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1313 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1314 (RBIOS8(tmp + 23) * 8);
1316 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1317 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1318 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1319 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1320 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1321 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1323 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1324 lvds->native_mode.flags = 0;
1325 /* set crtc values */
1326 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1331 DRM_INFO("No panel info found in BIOS\n");
1332 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1336 encoder->native_mode = lvds->native_mode;
1340 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1341 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1342 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1343 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1344 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1345 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1346 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1347 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1348 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1349 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1350 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1351 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1352 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1353 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1354 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1355 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1356 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1357 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1358 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1361 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1362 struct radeon_encoder_int_tmds *tmds)
1364 struct drm_device *dev = encoder->base.dev;
1365 struct radeon_device *rdev = dev->dev_private;
1368 for (i = 0; i < 4; i++) {
1369 tmds->tmds_pll[i].value =
1370 default_tmds_pll[rdev->family][i].value;
1371 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1377 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1378 struct radeon_encoder_int_tmds *tmds)
1380 struct drm_device *dev = encoder->base.dev;
1381 struct radeon_device *rdev = dev->dev_private;
1386 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1389 ver = RBIOS8(tmds_info);
1390 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1392 n = RBIOS8(tmds_info + 5) + 1;
1395 for (i = 0; i < n; i++) {
1396 tmds->tmds_pll[i].value =
1397 RBIOS32(tmds_info + i * 10 + 0x08);
1398 tmds->tmds_pll[i].freq =
1399 RBIOS16(tmds_info + i * 10 + 0x10);
1400 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1401 tmds->tmds_pll[i].freq,
1402 tmds->tmds_pll[i].value);
1404 } else if (ver == 4) {
1406 n = RBIOS8(tmds_info + 5) + 1;
1409 for (i = 0; i < n; i++) {
1410 tmds->tmds_pll[i].value =
1411 RBIOS32(tmds_info + stride + 0x08);
1412 tmds->tmds_pll[i].freq =
1413 RBIOS16(tmds_info + stride + 0x10);
1418 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1419 tmds->tmds_pll[i].freq,
1420 tmds->tmds_pll[i].value);
1424 DRM_INFO("No TMDS info found in BIOS\n");
1430 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1431 struct radeon_encoder_ext_tmds *tmds)
1433 struct drm_device *dev = encoder->base.dev;
1434 struct radeon_device *rdev = dev->dev_private;
1435 struct radeon_i2c_bus_rec i2c_bus;
1437 /* default for macs */
1438 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1439 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1441 /* XXX some macs have duallink chips */
1442 switch (rdev->mode_info.connector_table) {
1443 case CT_POWERBOOK_EXTERNAL:
1444 case CT_MINI_EXTERNAL:
1446 tmds->dvo_chip = DVO_SIL164;
1447 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1454 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1455 struct radeon_encoder_ext_tmds *tmds)
1457 struct drm_device *dev = encoder->base.dev;
1458 struct radeon_device *rdev = dev->dev_private;
1461 enum radeon_combios_ddc gpio;
1462 struct radeon_i2c_bus_rec i2c_bus;
1464 tmds->i2c_bus = NULL;
1465 if (rdev->flags & RADEON_IS_IGP) {
1466 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1467 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1468 tmds->dvo_chip = DVO_SIL164;
1469 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1471 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1473 ver = RBIOS8(offset);
1474 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1475 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1476 tmds->slave_addr >>= 1; /* 7 bit addressing */
1477 gpio = RBIOS8(offset + 4 + 3);
1478 if (gpio == DDC_LCD) {
1480 i2c_bus.valid = true;
1481 i2c_bus.hw_capable = true;
1482 i2c_bus.mm_i2c = true;
1483 i2c_bus.i2c_id = 0xa0;
1485 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1486 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1490 if (!tmds->i2c_bus) {
1491 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1498 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1500 struct radeon_device *rdev = dev->dev_private;
1501 struct radeon_i2c_bus_rec ddc_i2c;
1502 struct radeon_hpd hpd;
1504 rdev->mode_info.connector_table = radeon_connector_table;
1505 if (rdev->mode_info.connector_table == CT_NONE) {
1506 #ifdef CONFIG_PPC_PMAC
1507 if (of_machine_is_compatible("PowerBook3,3")) {
1508 /* powerbook with VGA */
1509 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1510 } else if (of_machine_is_compatible("PowerBook3,4") ||
1511 of_machine_is_compatible("PowerBook3,5")) {
1512 /* powerbook with internal tmds */
1513 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1514 } else if (of_machine_is_compatible("PowerBook5,1") ||
1515 of_machine_is_compatible("PowerBook5,2") ||
1516 of_machine_is_compatible("PowerBook5,3") ||
1517 of_machine_is_compatible("PowerBook5,4") ||
1518 of_machine_is_compatible("PowerBook5,5")) {
1519 /* powerbook with external single link tmds (sil164) */
1520 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1521 } else if (of_machine_is_compatible("PowerBook5,6")) {
1522 /* powerbook with external dual or single link tmds */
1523 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1524 } else if (of_machine_is_compatible("PowerBook5,7") ||
1525 of_machine_is_compatible("PowerBook5,8") ||
1526 of_machine_is_compatible("PowerBook5,9")) {
1527 /* PowerBook6,2 ? */
1528 /* powerbook with external dual link tmds (sil1178?) */
1529 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1530 } else if (of_machine_is_compatible("PowerBook4,1") ||
1531 of_machine_is_compatible("PowerBook4,2") ||
1532 of_machine_is_compatible("PowerBook4,3") ||
1533 of_machine_is_compatible("PowerBook6,3") ||
1534 of_machine_is_compatible("PowerBook6,5") ||
1535 of_machine_is_compatible("PowerBook6,7")) {
1537 rdev->mode_info.connector_table = CT_IBOOK;
1538 } else if (of_machine_is_compatible("PowerMac3,5")) {
1539 /* PowerMac G4 Silver radeon 7500 */
1540 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1541 } else if (of_machine_is_compatible("PowerMac4,4")) {
1543 rdev->mode_info.connector_table = CT_EMAC;
1544 } else if (of_machine_is_compatible("PowerMac10,1")) {
1545 /* mini with internal tmds */
1546 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1547 } else if (of_machine_is_compatible("PowerMac10,2")) {
1548 /* mini with external tmds */
1549 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1550 } else if (of_machine_is_compatible("PowerMac12,1")) {
1552 /* imac g5 isight */
1553 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1554 } else if ((dev->pci_device == 0x4a48) &&
1555 (dev->pci_subvendor == 0x1002) &&
1556 (dev->pci_subdevice == 0x4a48)) {
1558 rdev->mode_info.connector_table = CT_MAC_X800;
1559 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1560 of_machine_is_compatible("PowerMac7,3")) &&
1561 (dev->pci_device == 0x4150) &&
1562 (dev->pci_subvendor == 0x1002) &&
1563 (dev->pci_subdevice == 0x4150)) {
1564 /* Mac G5 tower 9600 */
1565 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1566 } else if ((dev->pci_device == 0x4c66) &&
1567 (dev->pci_subvendor == 0x1002) &&
1568 (dev->pci_subdevice == 0x4c66)) {
1569 /* SAM440ep RV250 embedded board */
1570 rdev->mode_info.connector_table = CT_SAM440EP;
1572 #endif /* CONFIG_PPC_PMAC */
1574 if (ASIC_IS_RN50(rdev))
1575 rdev->mode_info.connector_table = CT_RN50_POWER;
1578 rdev->mode_info.connector_table = CT_GENERIC;
1581 switch (rdev->mode_info.connector_table) {
1583 DRM_INFO("Connector Table: %d (generic)\n",
1584 rdev->mode_info.connector_table);
1585 /* these are the most common settings */
1586 if (rdev->flags & RADEON_SINGLE_CRTC) {
1587 /* VGA - primary dac */
1588 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1589 hpd.hpd = RADEON_HPD_NONE;
1590 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_enum(dev,
1592 ATOM_DEVICE_CRT1_SUPPORT,
1594 ATOM_DEVICE_CRT1_SUPPORT);
1595 radeon_add_legacy_connector(dev, 0,
1596 ATOM_DEVICE_CRT1_SUPPORT,
1597 DRM_MODE_CONNECTOR_VGA,
1599 CONNECTOR_OBJECT_ID_VGA,
1601 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1603 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1604 hpd.hpd = RADEON_HPD_NONE;
1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_enum(dev,
1607 ATOM_DEVICE_LCD1_SUPPORT,
1609 ATOM_DEVICE_LCD1_SUPPORT);
1610 radeon_add_legacy_connector(dev, 0,
1611 ATOM_DEVICE_LCD1_SUPPORT,
1612 DRM_MODE_CONNECTOR_LVDS,
1614 CONNECTOR_OBJECT_ID_LVDS,
1617 /* VGA - primary dac */
1618 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1619 hpd.hpd = RADEON_HPD_NONE;
1620 radeon_add_legacy_encoder(dev,
1621 radeon_get_encoder_enum(dev,
1622 ATOM_DEVICE_CRT1_SUPPORT,
1624 ATOM_DEVICE_CRT1_SUPPORT);
1625 radeon_add_legacy_connector(dev, 1,
1626 ATOM_DEVICE_CRT1_SUPPORT,
1627 DRM_MODE_CONNECTOR_VGA,
1629 CONNECTOR_OBJECT_ID_VGA,
1632 /* DVI-I - tv dac, int tmds */
1633 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1634 hpd.hpd = RADEON_HPD_1;
1635 radeon_add_legacy_encoder(dev,
1636 radeon_get_encoder_enum(dev,
1637 ATOM_DEVICE_DFP1_SUPPORT,
1639 ATOM_DEVICE_DFP1_SUPPORT);
1640 radeon_add_legacy_encoder(dev,
1641 radeon_get_encoder_enum(dev,
1642 ATOM_DEVICE_CRT2_SUPPORT,
1644 ATOM_DEVICE_CRT2_SUPPORT);
1645 radeon_add_legacy_connector(dev, 0,
1646 ATOM_DEVICE_DFP1_SUPPORT |
1647 ATOM_DEVICE_CRT2_SUPPORT,
1648 DRM_MODE_CONNECTOR_DVII,
1650 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1653 /* VGA - primary dac */
1654 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1655 hpd.hpd = RADEON_HPD_NONE;
1656 radeon_add_legacy_encoder(dev,
1657 radeon_get_encoder_enum(dev,
1658 ATOM_DEVICE_CRT1_SUPPORT,
1660 ATOM_DEVICE_CRT1_SUPPORT);
1661 radeon_add_legacy_connector(dev, 1,
1662 ATOM_DEVICE_CRT1_SUPPORT,
1663 DRM_MODE_CONNECTOR_VGA,
1665 CONNECTOR_OBJECT_ID_VGA,
1669 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1671 ddc_i2c.valid = false;
1672 hpd.hpd = RADEON_HPD_NONE;
1673 radeon_add_legacy_encoder(dev,
1674 radeon_get_encoder_enum(dev,
1675 ATOM_DEVICE_TV1_SUPPORT,
1677 ATOM_DEVICE_TV1_SUPPORT);
1678 radeon_add_legacy_connector(dev, 2,
1679 ATOM_DEVICE_TV1_SUPPORT,
1680 DRM_MODE_CONNECTOR_SVIDEO,
1682 CONNECTOR_OBJECT_ID_SVIDEO,
1687 DRM_INFO("Connector Table: %d (ibook)\n",
1688 rdev->mode_info.connector_table);
1690 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1691 hpd.hpd = RADEON_HPD_NONE;
1692 radeon_add_legacy_encoder(dev,
1693 radeon_get_encoder_enum(dev,
1694 ATOM_DEVICE_LCD1_SUPPORT,
1696 ATOM_DEVICE_LCD1_SUPPORT);
1697 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1698 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1699 CONNECTOR_OBJECT_ID_LVDS,
1702 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1703 hpd.hpd = RADEON_HPD_NONE;
1704 radeon_add_legacy_encoder(dev,
1705 radeon_get_encoder_enum(dev,
1706 ATOM_DEVICE_CRT2_SUPPORT,
1708 ATOM_DEVICE_CRT2_SUPPORT);
1709 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1710 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1711 CONNECTOR_OBJECT_ID_VGA,
1714 ddc_i2c.valid = false;
1715 hpd.hpd = RADEON_HPD_NONE;
1716 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_enum(dev,
1718 ATOM_DEVICE_TV1_SUPPORT,
1720 ATOM_DEVICE_TV1_SUPPORT);
1721 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1722 DRM_MODE_CONNECTOR_SVIDEO,
1724 CONNECTOR_OBJECT_ID_SVIDEO,
1727 case CT_POWERBOOK_EXTERNAL:
1728 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1729 rdev->mode_info.connector_table);
1731 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1732 hpd.hpd = RADEON_HPD_NONE;
1733 radeon_add_legacy_encoder(dev,
1734 radeon_get_encoder_enum(dev,
1735 ATOM_DEVICE_LCD1_SUPPORT,
1737 ATOM_DEVICE_LCD1_SUPPORT);
1738 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1739 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1740 CONNECTOR_OBJECT_ID_LVDS,
1742 /* DVI-I - primary dac, ext tmds */
1743 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1744 hpd.hpd = RADEON_HPD_2; /* ??? */
1745 radeon_add_legacy_encoder(dev,
1746 radeon_get_encoder_enum(dev,
1747 ATOM_DEVICE_DFP2_SUPPORT,
1749 ATOM_DEVICE_DFP2_SUPPORT);
1750 radeon_add_legacy_encoder(dev,
1751 radeon_get_encoder_enum(dev,
1752 ATOM_DEVICE_CRT1_SUPPORT,
1754 ATOM_DEVICE_CRT1_SUPPORT);
1755 /* XXX some are SL */
1756 radeon_add_legacy_connector(dev, 1,
1757 ATOM_DEVICE_DFP2_SUPPORT |
1758 ATOM_DEVICE_CRT1_SUPPORT,
1759 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1760 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1763 ddc_i2c.valid = false;
1764 hpd.hpd = RADEON_HPD_NONE;
1765 radeon_add_legacy_encoder(dev,
1766 radeon_get_encoder_enum(dev,
1767 ATOM_DEVICE_TV1_SUPPORT,
1769 ATOM_DEVICE_TV1_SUPPORT);
1770 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1771 DRM_MODE_CONNECTOR_SVIDEO,
1773 CONNECTOR_OBJECT_ID_SVIDEO,
1776 case CT_POWERBOOK_INTERNAL:
1777 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1778 rdev->mode_info.connector_table);
1780 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1781 hpd.hpd = RADEON_HPD_NONE;
1782 radeon_add_legacy_encoder(dev,
1783 radeon_get_encoder_enum(dev,
1784 ATOM_DEVICE_LCD1_SUPPORT,
1786 ATOM_DEVICE_LCD1_SUPPORT);
1787 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1788 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1789 CONNECTOR_OBJECT_ID_LVDS,
1791 /* DVI-I - primary dac, int tmds */
1792 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1793 hpd.hpd = RADEON_HPD_1; /* ??? */
1794 radeon_add_legacy_encoder(dev,
1795 radeon_get_encoder_enum(dev,
1796 ATOM_DEVICE_DFP1_SUPPORT,
1798 ATOM_DEVICE_DFP1_SUPPORT);
1799 radeon_add_legacy_encoder(dev,
1800 radeon_get_encoder_enum(dev,
1801 ATOM_DEVICE_CRT1_SUPPORT,
1803 ATOM_DEVICE_CRT1_SUPPORT);
1804 radeon_add_legacy_connector(dev, 1,
1805 ATOM_DEVICE_DFP1_SUPPORT |
1806 ATOM_DEVICE_CRT1_SUPPORT,
1807 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1808 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1811 ddc_i2c.valid = false;
1812 hpd.hpd = RADEON_HPD_NONE;
1813 radeon_add_legacy_encoder(dev,
1814 radeon_get_encoder_enum(dev,
1815 ATOM_DEVICE_TV1_SUPPORT,
1817 ATOM_DEVICE_TV1_SUPPORT);
1818 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1819 DRM_MODE_CONNECTOR_SVIDEO,
1821 CONNECTOR_OBJECT_ID_SVIDEO,
1824 case CT_POWERBOOK_VGA:
1825 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1826 rdev->mode_info.connector_table);
1828 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1829 hpd.hpd = RADEON_HPD_NONE;
1830 radeon_add_legacy_encoder(dev,
1831 radeon_get_encoder_enum(dev,
1832 ATOM_DEVICE_LCD1_SUPPORT,
1834 ATOM_DEVICE_LCD1_SUPPORT);
1835 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1836 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1837 CONNECTOR_OBJECT_ID_LVDS,
1839 /* VGA - primary dac */
1840 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1841 hpd.hpd = RADEON_HPD_NONE;
1842 radeon_add_legacy_encoder(dev,
1843 radeon_get_encoder_enum(dev,
1844 ATOM_DEVICE_CRT1_SUPPORT,
1846 ATOM_DEVICE_CRT1_SUPPORT);
1847 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1848 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1849 CONNECTOR_OBJECT_ID_VGA,
1852 ddc_i2c.valid = false;
1853 hpd.hpd = RADEON_HPD_NONE;
1854 radeon_add_legacy_encoder(dev,
1855 radeon_get_encoder_enum(dev,
1856 ATOM_DEVICE_TV1_SUPPORT,
1858 ATOM_DEVICE_TV1_SUPPORT);
1859 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1860 DRM_MODE_CONNECTOR_SVIDEO,
1862 CONNECTOR_OBJECT_ID_SVIDEO,
1865 case CT_MINI_EXTERNAL:
1866 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1867 rdev->mode_info.connector_table);
1868 /* DVI-I - tv dac, ext tmds */
1869 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1870 hpd.hpd = RADEON_HPD_2; /* ??? */
1871 radeon_add_legacy_encoder(dev,
1872 radeon_get_encoder_enum(dev,
1873 ATOM_DEVICE_DFP2_SUPPORT,
1875 ATOM_DEVICE_DFP2_SUPPORT);
1876 radeon_add_legacy_encoder(dev,
1877 radeon_get_encoder_enum(dev,
1878 ATOM_DEVICE_CRT2_SUPPORT,
1880 ATOM_DEVICE_CRT2_SUPPORT);
1881 /* XXX are any DL? */
1882 radeon_add_legacy_connector(dev, 0,
1883 ATOM_DEVICE_DFP2_SUPPORT |
1884 ATOM_DEVICE_CRT2_SUPPORT,
1885 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1886 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1889 ddc_i2c.valid = false;
1890 hpd.hpd = RADEON_HPD_NONE;
1891 radeon_add_legacy_encoder(dev,
1892 radeon_get_encoder_enum(dev,
1893 ATOM_DEVICE_TV1_SUPPORT,
1895 ATOM_DEVICE_TV1_SUPPORT);
1896 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1897 DRM_MODE_CONNECTOR_SVIDEO,
1899 CONNECTOR_OBJECT_ID_SVIDEO,
1902 case CT_MINI_INTERNAL:
1903 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1904 rdev->mode_info.connector_table);
1905 /* DVI-I - tv dac, int tmds */
1906 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1907 hpd.hpd = RADEON_HPD_1; /* ??? */
1908 radeon_add_legacy_encoder(dev,
1909 radeon_get_encoder_enum(dev,
1910 ATOM_DEVICE_DFP1_SUPPORT,
1912 ATOM_DEVICE_DFP1_SUPPORT);
1913 radeon_add_legacy_encoder(dev,
1914 radeon_get_encoder_enum(dev,
1915 ATOM_DEVICE_CRT2_SUPPORT,
1917 ATOM_DEVICE_CRT2_SUPPORT);
1918 radeon_add_legacy_connector(dev, 0,
1919 ATOM_DEVICE_DFP1_SUPPORT |
1920 ATOM_DEVICE_CRT2_SUPPORT,
1921 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1922 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1925 ddc_i2c.valid = false;
1926 hpd.hpd = RADEON_HPD_NONE;
1927 radeon_add_legacy_encoder(dev,
1928 radeon_get_encoder_enum(dev,
1929 ATOM_DEVICE_TV1_SUPPORT,
1931 ATOM_DEVICE_TV1_SUPPORT);
1932 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1933 DRM_MODE_CONNECTOR_SVIDEO,
1935 CONNECTOR_OBJECT_ID_SVIDEO,
1938 case CT_IMAC_G5_ISIGHT:
1939 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1940 rdev->mode_info.connector_table);
1941 /* DVI-D - int tmds */
1942 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1943 hpd.hpd = RADEON_HPD_1; /* ??? */
1944 radeon_add_legacy_encoder(dev,
1945 radeon_get_encoder_enum(dev,
1946 ATOM_DEVICE_DFP1_SUPPORT,
1948 ATOM_DEVICE_DFP1_SUPPORT);
1949 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1950 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1951 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1954 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1955 hpd.hpd = RADEON_HPD_NONE;
1956 radeon_add_legacy_encoder(dev,
1957 radeon_get_encoder_enum(dev,
1958 ATOM_DEVICE_CRT2_SUPPORT,
1960 ATOM_DEVICE_CRT2_SUPPORT);
1961 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1962 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1963 CONNECTOR_OBJECT_ID_VGA,
1966 ddc_i2c.valid = false;
1967 hpd.hpd = RADEON_HPD_NONE;
1968 radeon_add_legacy_encoder(dev,
1969 radeon_get_encoder_enum(dev,
1970 ATOM_DEVICE_TV1_SUPPORT,
1972 ATOM_DEVICE_TV1_SUPPORT);
1973 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1974 DRM_MODE_CONNECTOR_SVIDEO,
1976 CONNECTOR_OBJECT_ID_SVIDEO,
1980 DRM_INFO("Connector Table: %d (emac)\n",
1981 rdev->mode_info.connector_table);
1982 /* VGA - primary dac */
1983 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1984 hpd.hpd = RADEON_HPD_NONE;
1985 radeon_add_legacy_encoder(dev,
1986 radeon_get_encoder_enum(dev,
1987 ATOM_DEVICE_CRT1_SUPPORT,
1989 ATOM_DEVICE_CRT1_SUPPORT);
1990 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1991 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1992 CONNECTOR_OBJECT_ID_VGA,
1995 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1996 hpd.hpd = RADEON_HPD_NONE;
1997 radeon_add_legacy_encoder(dev,
1998 radeon_get_encoder_enum(dev,
1999 ATOM_DEVICE_CRT2_SUPPORT,
2001 ATOM_DEVICE_CRT2_SUPPORT);
2002 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2003 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2004 CONNECTOR_OBJECT_ID_VGA,
2007 ddc_i2c.valid = false;
2008 hpd.hpd = RADEON_HPD_NONE;
2009 radeon_add_legacy_encoder(dev,
2010 radeon_get_encoder_enum(dev,
2011 ATOM_DEVICE_TV1_SUPPORT,
2013 ATOM_DEVICE_TV1_SUPPORT);
2014 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2015 DRM_MODE_CONNECTOR_SVIDEO,
2017 CONNECTOR_OBJECT_ID_SVIDEO,
2021 DRM_INFO("Connector Table: %d (rn50-power)\n",
2022 rdev->mode_info.connector_table);
2023 /* VGA - primary dac */
2024 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2025 hpd.hpd = RADEON_HPD_NONE;
2026 radeon_add_legacy_encoder(dev,
2027 radeon_get_encoder_enum(dev,
2028 ATOM_DEVICE_CRT1_SUPPORT,
2030 ATOM_DEVICE_CRT1_SUPPORT);
2031 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2032 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2033 CONNECTOR_OBJECT_ID_VGA,
2035 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2036 hpd.hpd = RADEON_HPD_NONE;
2037 radeon_add_legacy_encoder(dev,
2038 radeon_get_encoder_enum(dev,
2039 ATOM_DEVICE_CRT2_SUPPORT,
2041 ATOM_DEVICE_CRT2_SUPPORT);
2042 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2043 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2044 CONNECTOR_OBJECT_ID_VGA,
2048 DRM_INFO("Connector Table: %d (mac x800)\n",
2049 rdev->mode_info.connector_table);
2050 /* DVI - primary dac, internal tmds */
2051 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2052 hpd.hpd = RADEON_HPD_1; /* ??? */
2053 radeon_add_legacy_encoder(dev,
2054 radeon_get_encoder_enum(dev,
2055 ATOM_DEVICE_DFP1_SUPPORT,
2057 ATOM_DEVICE_DFP1_SUPPORT);
2058 radeon_add_legacy_encoder(dev,
2059 radeon_get_encoder_enum(dev,
2060 ATOM_DEVICE_CRT1_SUPPORT,
2062 ATOM_DEVICE_CRT1_SUPPORT);
2063 radeon_add_legacy_connector(dev, 0,
2064 ATOM_DEVICE_DFP1_SUPPORT |
2065 ATOM_DEVICE_CRT1_SUPPORT,
2066 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2067 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2069 /* DVI - tv dac, dvo */
2070 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2071 hpd.hpd = RADEON_HPD_2; /* ??? */
2072 radeon_add_legacy_encoder(dev,
2073 radeon_get_encoder_enum(dev,
2074 ATOM_DEVICE_DFP2_SUPPORT,
2076 ATOM_DEVICE_DFP2_SUPPORT);
2077 radeon_add_legacy_encoder(dev,
2078 radeon_get_encoder_enum(dev,
2079 ATOM_DEVICE_CRT2_SUPPORT,
2081 ATOM_DEVICE_CRT2_SUPPORT);
2082 radeon_add_legacy_connector(dev, 1,
2083 ATOM_DEVICE_DFP2_SUPPORT |
2084 ATOM_DEVICE_CRT2_SUPPORT,
2085 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2086 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2089 case CT_MAC_G5_9600:
2090 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2091 rdev->mode_info.connector_table);
2092 /* DVI - tv dac, dvo */
2093 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2094 hpd.hpd = RADEON_HPD_1; /* ??? */
2095 radeon_add_legacy_encoder(dev,
2096 radeon_get_encoder_enum(dev,
2097 ATOM_DEVICE_DFP2_SUPPORT,
2099 ATOM_DEVICE_DFP2_SUPPORT);
2100 radeon_add_legacy_encoder(dev,
2101 radeon_get_encoder_enum(dev,
2102 ATOM_DEVICE_CRT2_SUPPORT,
2104 ATOM_DEVICE_CRT2_SUPPORT);
2105 radeon_add_legacy_connector(dev, 0,
2106 ATOM_DEVICE_DFP2_SUPPORT |
2107 ATOM_DEVICE_CRT2_SUPPORT,
2108 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2109 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2111 /* ADC - primary dac, internal tmds */
2112 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2113 hpd.hpd = RADEON_HPD_2; /* ??? */
2114 radeon_add_legacy_encoder(dev,
2115 radeon_get_encoder_enum(dev,
2116 ATOM_DEVICE_DFP1_SUPPORT,
2118 ATOM_DEVICE_DFP1_SUPPORT);
2119 radeon_add_legacy_encoder(dev,
2120 radeon_get_encoder_enum(dev,
2121 ATOM_DEVICE_CRT1_SUPPORT,
2123 ATOM_DEVICE_CRT1_SUPPORT);
2124 radeon_add_legacy_connector(dev, 1,
2125 ATOM_DEVICE_DFP1_SUPPORT |
2126 ATOM_DEVICE_CRT1_SUPPORT,
2127 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2128 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2131 ddc_i2c.valid = false;
2132 hpd.hpd = RADEON_HPD_NONE;
2133 radeon_add_legacy_encoder(dev,
2134 radeon_get_encoder_enum(dev,
2135 ATOM_DEVICE_TV1_SUPPORT,
2137 ATOM_DEVICE_TV1_SUPPORT);
2138 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2139 DRM_MODE_CONNECTOR_SVIDEO,
2141 CONNECTOR_OBJECT_ID_SVIDEO,
2145 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2146 rdev->mode_info.connector_table);
2148 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2149 hpd.hpd = RADEON_HPD_NONE;
2150 radeon_add_legacy_encoder(dev,
2151 radeon_get_encoder_enum(dev,
2152 ATOM_DEVICE_LCD1_SUPPORT,
2154 ATOM_DEVICE_LCD1_SUPPORT);
2155 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2156 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2157 CONNECTOR_OBJECT_ID_LVDS,
2159 /* DVI-I - secondary dac, int tmds */
2160 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2161 hpd.hpd = RADEON_HPD_1; /* ??? */
2162 radeon_add_legacy_encoder(dev,
2163 radeon_get_encoder_enum(dev,
2164 ATOM_DEVICE_DFP1_SUPPORT,
2166 ATOM_DEVICE_DFP1_SUPPORT);
2167 radeon_add_legacy_encoder(dev,
2168 radeon_get_encoder_enum(dev,
2169 ATOM_DEVICE_CRT2_SUPPORT,
2171 ATOM_DEVICE_CRT2_SUPPORT);
2172 radeon_add_legacy_connector(dev, 1,
2173 ATOM_DEVICE_DFP1_SUPPORT |
2174 ATOM_DEVICE_CRT2_SUPPORT,
2175 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2176 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2178 /* VGA - primary dac */
2179 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2180 hpd.hpd = RADEON_HPD_NONE;
2181 radeon_add_legacy_encoder(dev,
2182 radeon_get_encoder_enum(dev,
2183 ATOM_DEVICE_CRT1_SUPPORT,
2185 ATOM_DEVICE_CRT1_SUPPORT);
2186 radeon_add_legacy_connector(dev, 2,
2187 ATOM_DEVICE_CRT1_SUPPORT,
2188 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2189 CONNECTOR_OBJECT_ID_VGA,
2192 ddc_i2c.valid = false;
2193 hpd.hpd = RADEON_HPD_NONE;
2194 radeon_add_legacy_encoder(dev,
2195 radeon_get_encoder_enum(dev,
2196 ATOM_DEVICE_TV1_SUPPORT,
2198 ATOM_DEVICE_TV1_SUPPORT);
2199 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2200 DRM_MODE_CONNECTOR_SVIDEO,
2202 CONNECTOR_OBJECT_ID_SVIDEO,
2205 case CT_MAC_G4_SILVER:
2206 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2207 rdev->mode_info.connector_table);
2208 /* DVI-I - tv dac, int tmds */
2209 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2210 hpd.hpd = RADEON_HPD_1; /* ??? */
2211 radeon_add_legacy_encoder(dev,
2212 radeon_get_encoder_enum(dev,
2213 ATOM_DEVICE_DFP1_SUPPORT,
2215 ATOM_DEVICE_DFP1_SUPPORT);
2216 radeon_add_legacy_encoder(dev,
2217 radeon_get_encoder_enum(dev,
2218 ATOM_DEVICE_CRT2_SUPPORT,
2220 ATOM_DEVICE_CRT2_SUPPORT);
2221 radeon_add_legacy_connector(dev, 0,
2222 ATOM_DEVICE_DFP1_SUPPORT |
2223 ATOM_DEVICE_CRT2_SUPPORT,
2224 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2225 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2227 /* VGA - primary dac */
2228 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2229 hpd.hpd = RADEON_HPD_NONE;
2230 radeon_add_legacy_encoder(dev,
2231 radeon_get_encoder_enum(dev,
2232 ATOM_DEVICE_CRT1_SUPPORT,
2234 ATOM_DEVICE_CRT1_SUPPORT);
2235 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2236 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2237 CONNECTOR_OBJECT_ID_VGA,
2240 ddc_i2c.valid = false;
2241 hpd.hpd = RADEON_HPD_NONE;
2242 radeon_add_legacy_encoder(dev,
2243 radeon_get_encoder_enum(dev,
2244 ATOM_DEVICE_TV1_SUPPORT,
2246 ATOM_DEVICE_TV1_SUPPORT);
2247 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2248 DRM_MODE_CONNECTOR_SVIDEO,
2250 CONNECTOR_OBJECT_ID_SVIDEO,
2254 DRM_INFO("Connector table: %d (invalid)\n",
2255 rdev->mode_info.connector_table);
2259 radeon_link_encoder_connector(dev);
2264 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2266 enum radeon_combios_connector
2268 struct radeon_i2c_bus_rec *ddc_i2c,
2269 struct radeon_hpd *hpd)
2272 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2273 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2274 if (dev->pci_device == 0x515e &&
2275 dev->pci_subvendor == 0x1014) {
2276 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2277 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2281 /* X300 card with extra non-existent DVI port */
2282 if (dev->pci_device == 0x5B60 &&
2283 dev->pci_subvendor == 0x17af &&
2284 dev->pci_subdevice == 0x201e && bios_index == 2) {
2285 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2292 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2294 /* Acer 5102 has non-existent TV port */
2295 if (dev->pci_device == 0x5975 &&
2296 dev->pci_subvendor == 0x1025 &&
2297 dev->pci_subdevice == 0x009f)
2300 /* HP dc5750 has non-existent TV port */
2301 if (dev->pci_device == 0x5974 &&
2302 dev->pci_subvendor == 0x103c &&
2303 dev->pci_subdevice == 0x280a)
2306 /* MSI S270 has non-existent TV port */
2307 if (dev->pci_device == 0x5955 &&
2308 dev->pci_subvendor == 0x1462 &&
2309 dev->pci_subdevice == 0x0131)
2315 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2317 struct radeon_device *rdev = dev->dev_private;
2318 uint32_t ext_tmds_info;
2320 if (rdev->flags & RADEON_IS_IGP) {
2322 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2324 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2326 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2327 if (ext_tmds_info) {
2328 uint8_t rev = RBIOS8(ext_tmds_info);
2329 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2332 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2334 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2338 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2340 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2345 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2347 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2350 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2352 struct radeon_device *rdev = dev->dev_private;
2353 uint32_t conn_info, entry, devices;
2354 uint16_t tmp, connector_object_id;
2355 enum radeon_combios_ddc ddc_type;
2356 enum radeon_combios_connector connector;
2358 struct radeon_i2c_bus_rec ddc_i2c;
2359 struct radeon_hpd hpd;
2361 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2363 for (i = 0; i < 4; i++) {
2364 entry = conn_info + 2 + i * 2;
2366 if (!RBIOS16(entry))
2369 tmp = RBIOS16(entry);
2371 connector = (tmp >> 12) & 0xf;
2373 ddc_type = (tmp >> 8) & 0xf;
2375 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2377 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2379 switch (connector) {
2380 case CONNECTOR_PROPRIETARY_LEGACY:
2381 case CONNECTOR_DVI_I_LEGACY:
2382 case CONNECTOR_DVI_D_LEGACY:
2383 if ((tmp >> 4) & 0x1)
2384 hpd.hpd = RADEON_HPD_2;
2386 hpd.hpd = RADEON_HPD_1;
2389 hpd.hpd = RADEON_HPD_NONE;
2393 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2397 switch (connector) {
2398 case CONNECTOR_PROPRIETARY_LEGACY:
2399 if ((tmp >> 4) & 0x1)
2400 devices = ATOM_DEVICE_DFP2_SUPPORT;
2402 devices = ATOM_DEVICE_DFP1_SUPPORT;
2403 radeon_add_legacy_encoder(dev,
2404 radeon_get_encoder_enum
2407 radeon_add_legacy_connector(dev, i, devices,
2408 legacy_connector_convert
2411 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2414 case CONNECTOR_CRT_LEGACY:
2416 devices = ATOM_DEVICE_CRT2_SUPPORT;
2417 radeon_add_legacy_encoder(dev,
2418 radeon_get_encoder_enum
2420 ATOM_DEVICE_CRT2_SUPPORT,
2422 ATOM_DEVICE_CRT2_SUPPORT);
2424 devices = ATOM_DEVICE_CRT1_SUPPORT;
2425 radeon_add_legacy_encoder(dev,
2426 radeon_get_encoder_enum
2428 ATOM_DEVICE_CRT1_SUPPORT,
2430 ATOM_DEVICE_CRT1_SUPPORT);
2432 radeon_add_legacy_connector(dev,
2435 legacy_connector_convert
2438 CONNECTOR_OBJECT_ID_VGA,
2441 case CONNECTOR_DVI_I_LEGACY:
2444 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2445 radeon_add_legacy_encoder(dev,
2446 radeon_get_encoder_enum
2448 ATOM_DEVICE_CRT2_SUPPORT,
2450 ATOM_DEVICE_CRT2_SUPPORT);
2452 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2453 radeon_add_legacy_encoder(dev,
2454 radeon_get_encoder_enum
2456 ATOM_DEVICE_CRT1_SUPPORT,
2458 ATOM_DEVICE_CRT1_SUPPORT);
2460 /* RV100 board with external TDMS bit mis-set.
2461 * Actually uses internal TMDS, clear the bit.
2463 if (dev->pci_device == 0x5159 &&
2464 dev->pci_subvendor == 0x1014 &&
2465 dev->pci_subdevice == 0x029A) {
2468 if ((tmp >> 4) & 0x1) {
2469 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2470 radeon_add_legacy_encoder(dev,
2471 radeon_get_encoder_enum
2473 ATOM_DEVICE_DFP2_SUPPORT,
2475 ATOM_DEVICE_DFP2_SUPPORT);
2476 connector_object_id = combios_check_dl_dvi(dev, 0);
2478 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2479 radeon_add_legacy_encoder(dev,
2480 radeon_get_encoder_enum
2482 ATOM_DEVICE_DFP1_SUPPORT,
2484 ATOM_DEVICE_DFP1_SUPPORT);
2485 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2487 radeon_add_legacy_connector(dev,
2490 legacy_connector_convert
2493 connector_object_id,
2496 case CONNECTOR_DVI_D_LEGACY:
2497 if ((tmp >> 4) & 0x1) {
2498 devices = ATOM_DEVICE_DFP2_SUPPORT;
2499 connector_object_id = combios_check_dl_dvi(dev, 1);
2501 devices = ATOM_DEVICE_DFP1_SUPPORT;
2502 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2504 radeon_add_legacy_encoder(dev,
2505 radeon_get_encoder_enum
2508 radeon_add_legacy_connector(dev, i, devices,
2509 legacy_connector_convert
2512 connector_object_id,
2515 case CONNECTOR_CTV_LEGACY:
2516 case CONNECTOR_STV_LEGACY:
2517 radeon_add_legacy_encoder(dev,
2518 radeon_get_encoder_enum
2520 ATOM_DEVICE_TV1_SUPPORT,
2522 ATOM_DEVICE_TV1_SUPPORT);
2523 radeon_add_legacy_connector(dev, i,
2524 ATOM_DEVICE_TV1_SUPPORT,
2525 legacy_connector_convert
2528 CONNECTOR_OBJECT_ID_SVIDEO,
2532 DRM_ERROR("Unknown connector type: %d\n",
2539 uint16_t tmds_info =
2540 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2542 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2544 radeon_add_legacy_encoder(dev,
2545 radeon_get_encoder_enum(dev,
2546 ATOM_DEVICE_CRT1_SUPPORT,
2548 ATOM_DEVICE_CRT1_SUPPORT);
2549 radeon_add_legacy_encoder(dev,
2550 radeon_get_encoder_enum(dev,
2551 ATOM_DEVICE_DFP1_SUPPORT,
2553 ATOM_DEVICE_DFP1_SUPPORT);
2555 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2556 hpd.hpd = RADEON_HPD_1;
2557 radeon_add_legacy_connector(dev,
2559 ATOM_DEVICE_CRT1_SUPPORT |
2560 ATOM_DEVICE_DFP1_SUPPORT,
2561 DRM_MODE_CONNECTOR_DVII,
2563 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2567 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2568 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2570 radeon_add_legacy_encoder(dev,
2571 radeon_get_encoder_enum(dev,
2572 ATOM_DEVICE_CRT1_SUPPORT,
2574 ATOM_DEVICE_CRT1_SUPPORT);
2575 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2576 hpd.hpd = RADEON_HPD_NONE;
2577 radeon_add_legacy_connector(dev,
2579 ATOM_DEVICE_CRT1_SUPPORT,
2580 DRM_MODE_CONNECTOR_VGA,
2582 CONNECTOR_OBJECT_ID_VGA,
2585 DRM_DEBUG_KMS("No connector info found\n");
2591 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2593 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2595 uint16_t lcd_ddc_info =
2596 combios_get_table_offset(dev,
2597 COMBIOS_LCD_DDC_INFO_TABLE);
2599 radeon_add_legacy_encoder(dev,
2600 radeon_get_encoder_enum(dev,
2601 ATOM_DEVICE_LCD1_SUPPORT,
2603 ATOM_DEVICE_LCD1_SUPPORT);
2606 ddc_type = RBIOS8(lcd_ddc_info + 2);
2610 combios_setup_i2c_bus(rdev,
2612 RBIOS32(lcd_ddc_info + 3),
2613 RBIOS32(lcd_ddc_info + 7));
2614 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2618 combios_setup_i2c_bus(rdev,
2620 RBIOS32(lcd_ddc_info + 3),
2621 RBIOS32(lcd_ddc_info + 7));
2622 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2626 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2629 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2631 ddc_i2c.valid = false;
2633 hpd.hpd = RADEON_HPD_NONE;
2634 radeon_add_legacy_connector(dev,
2636 ATOM_DEVICE_LCD1_SUPPORT,
2637 DRM_MODE_CONNECTOR_LVDS,
2639 CONNECTOR_OBJECT_ID_LVDS,
2644 /* check TV table */
2645 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2647 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2649 if (RBIOS8(tv_info + 6) == 'T') {
2650 if (radeon_apply_legacy_tv_quirks(dev)) {
2651 hpd.hpd = RADEON_HPD_NONE;
2652 ddc_i2c.valid = false;
2653 radeon_add_legacy_encoder(dev,
2654 radeon_get_encoder_enum
2656 ATOM_DEVICE_TV1_SUPPORT,
2658 ATOM_DEVICE_TV1_SUPPORT);
2659 radeon_add_legacy_connector(dev, 6,
2660 ATOM_DEVICE_TV1_SUPPORT,
2661 DRM_MODE_CONNECTOR_SVIDEO,
2663 CONNECTOR_OBJECT_ID_SVIDEO,
2670 radeon_link_encoder_connector(dev);
2675 static const char *thermal_controller_names[] = {
2681 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2683 struct drm_device *dev = rdev->ddev;
2684 u16 offset, misc, misc2 = 0;
2685 u8 rev, blocks, tmp;
2686 int state_index = 0;
2687 struct radeon_i2c_bus_rec i2c_bus;
2689 rdev->pm.default_power_state_index = -1;
2691 /* allocate 2 power states */
2692 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) * 2,
2693 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2694 if (rdev->pm.power_state) {
2695 /* allocate 1 clock mode per state */
2696 rdev->pm.power_state[0].clock_info =
2697 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2698 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2699 rdev->pm.power_state[1].clock_info =
2700 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2701 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2702 if (!rdev->pm.power_state[0].clock_info ||
2703 !rdev->pm.power_state[1].clock_info)
2708 /* check for a thermal chip */
2709 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2711 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2713 rev = RBIOS8(offset);
2716 thermal_controller = RBIOS8(offset + 3);
2717 gpio = RBIOS8(offset + 4) & 0x3f;
2718 i2c_addr = RBIOS8(offset + 5);
2719 } else if (rev == 1) {
2720 thermal_controller = RBIOS8(offset + 4);
2721 gpio = RBIOS8(offset + 5) & 0x3f;
2722 i2c_addr = RBIOS8(offset + 6);
2723 } else if (rev == 2) {
2724 thermal_controller = RBIOS8(offset + 4);
2725 gpio = RBIOS8(offset + 5) & 0x3f;
2726 i2c_addr = RBIOS8(offset + 6);
2727 clk_bit = RBIOS8(offset + 0xa);
2728 data_bit = RBIOS8(offset + 0xb);
2730 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2731 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2732 thermal_controller_names[thermal_controller],
2734 if (gpio == DDC_LCD) {
2736 i2c_bus.valid = true;
2737 i2c_bus.hw_capable = true;
2738 i2c_bus.mm_i2c = true;
2739 i2c_bus.i2c_id = 0xa0;
2740 } else if (gpio == DDC_GPIO)
2741 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2743 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2744 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2745 if (rdev->pm.i2c_bus) {
2747 struct i2c_board_info info = { };
2748 const char *name = thermal_controller_names[thermal_controller];
2749 info.addr = i2c_addr >> 1;
2750 strlcpy(info.type, name, sizeof(info.type));
2751 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2752 #endif /* DUMBBELL_WIP */
2756 /* boards with a thermal chip, but no overdrive table */
2758 /* Asus 9600xt has an f75375 on the monid bus */
2759 if ((dev->pci_device == 0x4152) &&
2760 (dev->pci_subvendor == 0x1043) &&
2761 (dev->pci_subdevice == 0xc002)) {
2762 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2763 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2764 if (rdev->pm.i2c_bus) {
2766 struct i2c_board_info info = { };
2767 const char *name = "f75375";
2769 strlcpy(info.type, name, sizeof(info.type));
2770 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2771 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2773 #endif /* DUMBBELL_WIP */
2778 if (rdev->flags & RADEON_IS_MOBILITY) {
2779 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2781 rev = RBIOS8(offset);
2782 blocks = RBIOS8(offset + 0x2);
2783 /* power mode 0 tends to be the only valid one */
2784 rdev->pm.power_state[state_index].num_clock_modes = 1;
2785 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2786 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2787 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2788 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2790 rdev->pm.power_state[state_index].type =
2791 POWER_STATE_TYPE_BATTERY;
2792 misc = RBIOS16(offset + 0x5 + 0x0);
2794 misc2 = RBIOS16(offset + 0x5 + 0xe);
2795 rdev->pm.power_state[state_index].misc = misc;
2796 rdev->pm.power_state[state_index].misc2 = misc2;
2798 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2800 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2803 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2805 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2807 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2808 RBIOS16(offset + 0x5 + 0xb) * 4;
2809 tmp = RBIOS8(offset + 0x5 + 0xd);
2810 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2812 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2813 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2814 if (entries && voltage_table_offset) {
2815 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2816 RBIOS16(voltage_table_offset) * 4;
2817 tmp = RBIOS8(voltage_table_offset + 0x2);
2818 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2820 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2822 switch ((misc2 & 0x700) >> 8) {
2825 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2828 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2831 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2834 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2837 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2841 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2843 rdev->pm.power_state[state_index].pcie_lanes =
2844 RBIOS8(offset + 0x5 + 0x10);
2845 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2848 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2851 /* XXX figure out some good default low power mode for desktop cards */
2855 /* add the default mode */
2856 rdev->pm.power_state[state_index].type =
2857 POWER_STATE_TYPE_DEFAULT;
2858 rdev->pm.power_state[state_index].num_clock_modes = 1;
2859 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2860 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2861 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2862 if ((state_index > 0) &&
2863 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2864 rdev->pm.power_state[state_index].clock_info[0].voltage =
2865 rdev->pm.power_state[0].clock_info[0].voltage;
2867 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2868 rdev->pm.power_state[state_index].pcie_lanes = 16;
2869 rdev->pm.power_state[state_index].flags = 0;
2870 rdev->pm.default_power_state_index = state_index;
2871 rdev->pm.num_power_states = state_index + 1;
2873 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2874 rdev->pm.current_clock_mode_index = 0;
2878 rdev->pm.default_power_state_index = state_index;
2879 rdev->pm.num_power_states = 0;
2881 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2882 rdev->pm.current_clock_mode_index = 0;
2885 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2887 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2888 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2893 switch (tmds->dvo_chip) {
2896 radeon_i2c_put_byte(tmds->i2c_bus,
2899 radeon_i2c_put_byte(tmds->i2c_bus,
2902 radeon_i2c_put_byte(tmds->i2c_bus,
2905 radeon_i2c_put_byte(tmds->i2c_bus,
2908 radeon_i2c_put_byte(tmds->i2c_bus,
2913 /* sil 1178 - untested */
2932 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2934 struct drm_device *dev = encoder->dev;
2935 struct radeon_device *rdev = dev->dev_private;
2936 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2938 uint8_t blocks, slave_addr, rev;
2940 uint32_t reg, val, and_mask, or_mask;
2941 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2946 if (rdev->flags & RADEON_IS_IGP) {
2947 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2948 rev = RBIOS8(offset);
2950 rev = RBIOS8(offset);
2952 blocks = RBIOS8(offset + 3);
2954 while (blocks > 0) {
2955 id = RBIOS16(index);
2959 reg = (id & 0x1fff) * 4;
2960 val = RBIOS32(index);
2965 reg = (id & 0x1fff) * 4;
2966 and_mask = RBIOS32(index);
2968 or_mask = RBIOS32(index);
2971 val = (val & and_mask) | or_mask;
2975 val = RBIOS16(index);
2980 val = RBIOS16(index);
2985 slave_addr = id & 0xff;
2986 slave_addr >>= 1; /* 7 bit addressing */
2988 reg = RBIOS8(index);
2990 val = RBIOS8(index);
2992 radeon_i2c_put_byte(tmds->i2c_bus,
2997 DRM_ERROR("Unknown id %d\n", id >> 13);
3006 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
3008 index = offset + 10;
3009 id = RBIOS16(index);
3010 while (id != 0xffff) {
3014 reg = (id & 0x1fff) * 4;
3015 val = RBIOS32(index);
3019 reg = (id & 0x1fff) * 4;
3020 and_mask = RBIOS32(index);
3022 or_mask = RBIOS32(index);
3025 val = (val & and_mask) | or_mask;
3029 val = RBIOS16(index);
3035 and_mask = RBIOS32(index);
3037 or_mask = RBIOS32(index);
3039 val = RREG32_PLL(reg);
3040 val = (val & and_mask) | or_mask;
3041 WREG32_PLL(reg, val);
3045 val = RBIOS8(index);
3047 radeon_i2c_put_byte(tmds->i2c_bus,
3052 DRM_ERROR("Unknown id %d\n", id >> 13);
3055 id = RBIOS16(index);
3063 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3065 struct radeon_device *rdev = dev->dev_private;
3068 while (RBIOS16(offset)) {
3069 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3070 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3071 uint32_t val, and_mask, or_mask;
3077 val = RBIOS32(offset);
3082 val = RBIOS32(offset);
3087 and_mask = RBIOS32(offset);
3089 or_mask = RBIOS32(offset);
3097 and_mask = RBIOS32(offset);
3099 or_mask = RBIOS32(offset);
3107 val = RBIOS16(offset);
3112 val = RBIOS16(offset);
3119 (RADEON_CLK_PWRMGT_CNTL) &
3126 if ((RREG32(RADEON_MC_STATUS) &
3142 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3144 struct radeon_device *rdev = dev->dev_private;
3147 while (RBIOS8(offset)) {
3148 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3149 uint8_t addr = (RBIOS8(offset) & 0x3f);
3150 uint32_t val, shift, tmp;
3151 uint32_t and_mask, or_mask;
3156 val = RBIOS32(offset);
3158 WREG32_PLL(addr, val);
3161 shift = RBIOS8(offset) * 8;
3163 and_mask = RBIOS8(offset) << shift;
3164 and_mask |= ~(0xff << shift);
3166 or_mask = RBIOS8(offset) << shift;
3168 tmp = RREG32_PLL(addr);
3171 WREG32_PLL(addr, tmp);
3187 (RADEON_CLK_PWRMGT_CNTL) &
3195 (RADEON_CLK_PWRMGT_CNTL) &
3202 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3203 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3205 uint32_t mclk_cntl =
3208 mclk_cntl &= 0xffff0000;
3209 /*mclk_cntl |= 0x00001111;*//* ??? */
3210 WREG32_PLL(RADEON_MCLK_CNTL,
3215 (RADEON_CLK_PWRMGT_CNTL,
3217 ~RADEON_CG_NO1_DEBUG_0);
3232 static void combios_parse_ram_reset_table(struct drm_device *dev,
3235 struct radeon_device *rdev = dev->dev_private;
3239 uint8_t val = RBIOS8(offset);
3240 while (val != 0xff) {
3244 uint32_t channel_complete_mask;
3246 if (ASIC_IS_R300(rdev))
3247 channel_complete_mask =
3248 R300_MEM_PWRUP_COMPLETE;
3250 channel_complete_mask =
3251 RADEON_MEM_PWRUP_COMPLETE;
3254 if ((RREG32(RADEON_MEM_STR_CNTL) &
3255 channel_complete_mask) ==
3256 channel_complete_mask)
3260 uint32_t or_mask = RBIOS16(offset);
3263 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3264 tmp &= RADEON_SDRAM_MODE_MASK;
3266 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3268 or_mask = val << 24;
3269 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3270 tmp &= RADEON_B3MEM_RESET_MASK;
3272 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3274 val = RBIOS8(offset);
3279 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3280 int mem_addr_mapping)
3282 struct radeon_device *rdev = dev->dev_private;
3287 mem_cntl = RREG32(RADEON_MEM_CNTL);
3288 if (mem_cntl & RV100_HALF_MODE)
3291 mem_cntl &= ~(0xff << 8);
3292 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3293 WREG32(RADEON_MEM_CNTL, mem_cntl);
3294 RREG32(RADEON_MEM_CNTL);
3298 /* something like this???? */
3300 addr = ram * 1024 * 1024;
3301 /* write to each page */
3302 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3303 /* read back and verify */
3304 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3311 static void combios_write_ram_size(struct drm_device *dev)
3313 struct radeon_device *rdev = dev->dev_private;
3316 uint32_t mem_size = 0;
3317 uint32_t mem_cntl = 0;
3319 /* should do something smarter here I guess... */
3320 if (rdev->flags & RADEON_IS_IGP)
3323 /* first check detected mem table */
3324 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3326 rev = RBIOS8(offset);
3328 mem_cntl = RBIOS32(offset + 1);
3329 mem_size = RBIOS16(offset + 5);
3330 if ((rdev->family < CHIP_R200) &&
3331 !ASIC_IS_RN50(rdev))
3332 WREG32(RADEON_MEM_CNTL, mem_cntl);
3338 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3340 rev = RBIOS8(offset - 1);
3342 if ((rdev->family < CHIP_R200)
3343 && !ASIC_IS_RN50(rdev)) {
3345 int mem_addr_mapping = 0;
3347 while (RBIOS8(offset)) {
3348 ram = RBIOS8(offset);
3351 if (mem_addr_mapping != 0x25)
3354 combios_detect_ram(dev, ram,
3361 mem_size = RBIOS8(offset);
3363 mem_size = RBIOS8(offset);
3364 mem_size *= 2; /* convert to MB */
3369 mem_size *= (1024 * 1024); /* convert to bytes */
3370 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3373 void radeon_combios_asic_init(struct drm_device *dev)
3375 struct radeon_device *rdev = dev->dev_private;
3378 /* port hardcoded mac stuff from radeonfb */
3379 if (rdev->bios == NULL)
3383 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3385 combios_parse_mmio_table(dev, table);
3388 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3390 combios_parse_pll_table(dev, table);
3393 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3395 combios_parse_mmio_table(dev, table);
3397 if (!(rdev->flags & RADEON_IS_IGP)) {
3400 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3402 combios_parse_mmio_table(dev, table);
3405 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3407 combios_parse_ram_reset_table(dev, table);
3411 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3413 combios_parse_mmio_table(dev, table);
3415 /* write CONFIG_MEMSIZE */
3416 combios_write_ram_size(dev);
3419 /* quirk for rs4xx HP nx6125 laptop to make it resume
3420 * - it hangs on resume inside the dynclk 1 table.
3422 if (rdev->family == CHIP_RS480 &&
3423 dev->pci_subvendor == 0x103c &&
3424 dev->pci_subdevice == 0x308b)
3427 /* quirk for rs4xx HP dv5000 laptop to make it resume
3428 * - it hangs on resume inside the dynclk 1 table.
3430 if (rdev->family == CHIP_RS480 &&
3431 dev->pci_subvendor == 0x103c &&
3432 dev->pci_subdevice == 0x30a4)
3435 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3436 * - it hangs on resume inside the dynclk 1 table.
3438 if (rdev->family == CHIP_RS480 &&
3439 dev->pci_subvendor == 0x103c &&
3440 dev->pci_subdevice == 0x30ae)
3444 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3446 combios_parse_pll_table(dev, table);
3450 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3452 struct radeon_device *rdev = dev->dev_private;
3453 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3455 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3456 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3457 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3459 /* let the bios control the backlight */
3460 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3462 /* tell the bios not to handle mode switching */
3463 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3464 RADEON_ACC_MODE_CHANGE);
3466 /* tell the bios a driver is loaded */
3467 bios_7_scratch |= RADEON_DRV_LOADED;
3469 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3470 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3471 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3474 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3476 struct drm_device *dev = encoder->dev;
3477 struct radeon_device *rdev = dev->dev_private;
3478 uint32_t bios_6_scratch;
3480 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3483 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3485 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3487 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3491 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3492 struct drm_encoder *encoder,
3495 struct drm_device *dev = connector->dev;
3496 struct radeon_device *rdev = dev->dev_private;
3497 struct radeon_connector *radeon_connector =
3498 to_radeon_connector(connector);
3499 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3500 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3501 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3503 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3504 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3506 DRM_DEBUG_KMS("TV1 connected\n");
3508 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3509 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3510 bios_5_scratch |= RADEON_TV1_ON;
3511 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3513 DRM_DEBUG_KMS("TV1 disconnected\n");
3514 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3515 bios_5_scratch &= ~RADEON_TV1_ON;
3516 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3519 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3520 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3522 DRM_DEBUG_KMS("LCD1 connected\n");
3523 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3524 bios_5_scratch |= RADEON_LCD1_ON;
3525 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3527 DRM_DEBUG_KMS("LCD1 disconnected\n");
3528 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3529 bios_5_scratch &= ~RADEON_LCD1_ON;
3530 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3533 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3534 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3536 DRM_DEBUG_KMS("CRT1 connected\n");
3537 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3538 bios_5_scratch |= RADEON_CRT1_ON;
3539 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3541 DRM_DEBUG_KMS("CRT1 disconnected\n");
3542 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3543 bios_5_scratch &= ~RADEON_CRT1_ON;
3544 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3547 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3548 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3550 DRM_DEBUG_KMS("CRT2 connected\n");
3551 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3552 bios_5_scratch |= RADEON_CRT2_ON;
3553 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3555 DRM_DEBUG_KMS("CRT2 disconnected\n");
3556 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3557 bios_5_scratch &= ~RADEON_CRT2_ON;
3558 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3561 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3562 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3564 DRM_DEBUG_KMS("DFP1 connected\n");
3565 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3566 bios_5_scratch |= RADEON_DFP1_ON;
3567 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3569 DRM_DEBUG_KMS("DFP1 disconnected\n");
3570 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3571 bios_5_scratch &= ~RADEON_DFP1_ON;
3572 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3575 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3576 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3578 DRM_DEBUG_KMS("DFP2 connected\n");
3579 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3580 bios_5_scratch |= RADEON_DFP2_ON;
3581 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3583 DRM_DEBUG_KMS("DFP2 disconnected\n");
3584 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3585 bios_5_scratch &= ~RADEON_DFP2_ON;
3586 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3589 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3590 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3594 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3596 struct drm_device *dev = encoder->dev;
3597 struct radeon_device *rdev = dev->dev_private;
3598 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3599 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3601 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3602 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3603 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3605 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3606 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3607 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3609 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3610 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3611 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3613 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3614 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3615 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3617 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3618 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3619 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3621 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3622 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3623 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3625 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3629 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3631 struct drm_device *dev = encoder->dev;
3632 struct radeon_device *rdev = dev->dev_private;
3633 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3634 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3636 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3638 bios_6_scratch |= RADEON_TV_DPMS_ON;
3640 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3642 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3644 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3646 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3648 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3650 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3652 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3654 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3656 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3658 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3660 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);