2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm_crtc_helper.h>
34 #include <dev/drm2/radeon/radeon_drm.h>
35 #include "radeon_reg.h"
39 static const char radeon_family_name[][16] = {
99 * radeon_surface_init - Clear GPU surface registers.
101 * @rdev: radeon_device pointer
103 * Clear GPU surface registers (r1xx-r5xx).
105 void radeon_surface_init(struct radeon_device *rdev)
107 /* FIXME: check this out */
108 if (rdev->family < CHIP_R600) {
111 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
112 if (rdev->surface_regs[i].bo)
113 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
115 radeon_clear_surface_reg(rdev, i);
117 /* enable surfaces */
118 WREG32(RADEON_SURFACE_CNTL, 0);
123 * GPU scratch registers helpers function.
126 * radeon_scratch_init - Init scratch register driver information.
128 * @rdev: radeon_device pointer
130 * Init CP scratch register driver information (r1xx-r5xx)
132 void radeon_scratch_init(struct radeon_device *rdev)
136 /* FIXME: check this out */
137 if (rdev->family < CHIP_R300) {
138 rdev->scratch.num_reg = 5;
140 rdev->scratch.num_reg = 7;
142 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
143 for (i = 0; i < rdev->scratch.num_reg; i++) {
144 rdev->scratch.free[i] = true;
145 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
150 * radeon_scratch_get - Allocate a scratch register
152 * @rdev: radeon_device pointer
153 * @reg: scratch register mmio offset
155 * Allocate a CP scratch register for use by the driver (all asics).
156 * Returns 0 on success or -EINVAL on failure.
158 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
162 for (i = 0; i < rdev->scratch.num_reg; i++) {
163 if (rdev->scratch.free[i]) {
164 rdev->scratch.free[i] = false;
165 *reg = rdev->scratch.reg[i];
173 * radeon_scratch_free - Free a scratch register
175 * @rdev: radeon_device pointer
176 * @reg: scratch register mmio offset
178 * Free a CP scratch register allocated for use by the driver (all asics)
180 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
184 for (i = 0; i < rdev->scratch.num_reg; i++) {
185 if (rdev->scratch.reg[i] == reg) {
186 rdev->scratch.free[i] = true;
194 * Writeback is the the method by which the the GPU updates special pages
195 * in memory with the status of certain GPU events (fences, ring pointers,
200 * radeon_wb_disable - Disable Writeback
202 * @rdev: radeon_device pointer
204 * Disables Writeback (all asics). Used for suspend.
206 void radeon_wb_disable(struct radeon_device *rdev)
210 if (rdev->wb.wb_obj) {
211 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
212 if (unlikely(r != 0))
214 radeon_bo_kunmap(rdev->wb.wb_obj);
215 radeon_bo_unpin(rdev->wb.wb_obj);
216 radeon_bo_unreserve(rdev->wb.wb_obj);
218 rdev->wb.enabled = false;
222 * radeon_wb_fini - Disable Writeback and free memory
224 * @rdev: radeon_device pointer
226 * Disables Writeback and frees the Writeback memory (all asics).
227 * Used at driver shutdown.
229 void radeon_wb_fini(struct radeon_device *rdev)
231 radeon_wb_disable(rdev);
232 if (rdev->wb.wb_obj) {
233 radeon_bo_unref(&rdev->wb.wb_obj);
235 rdev->wb.wb_obj = NULL;
240 * radeon_wb_init- Init Writeback driver info and allocate memory
242 * @rdev: radeon_device pointer
244 * Disables Writeback and frees the Writeback memory (all asics).
245 * Used at driver startup.
246 * Returns 0 on success or an -error on failure.
248 int radeon_wb_init(struct radeon_device *rdev)
253 if (rdev->wb.wb_obj == NULL) {
254 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
255 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
257 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
261 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
262 if (unlikely(r != 0)) {
263 radeon_wb_fini(rdev);
266 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
269 radeon_bo_unreserve(rdev->wb.wb_obj);
270 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
271 radeon_wb_fini(rdev);
274 wb_ptr = &rdev->wb.wb;
275 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr);
276 radeon_bo_unreserve(rdev->wb.wb_obj);
278 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
279 radeon_wb_fini(rdev);
283 /* clear wb memory */
284 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE);
285 /* disable event_write fences */
286 rdev->wb.use_event = false;
287 /* disabled via module param */
288 if (radeon_no_wb == 1) {
289 rdev->wb.enabled = false;
291 if (rdev->flags & RADEON_IS_AGP) {
292 /* often unreliable on AGP */
293 rdev->wb.enabled = false;
294 } else if (rdev->family < CHIP_R300) {
295 /* often unreliable on pre-r300 */
296 rdev->wb.enabled = false;
298 rdev->wb.enabled = true;
299 /* event_write fences are only available on r600+ */
300 if (rdev->family >= CHIP_R600) {
301 rdev->wb.use_event = true;
305 /* always use writeback/events on NI, APUs */
306 if (rdev->family >= CHIP_PALM) {
307 rdev->wb.enabled = true;
308 rdev->wb.use_event = true;
311 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
317 * radeon_vram_location - try to find VRAM location
318 * @rdev: radeon device structure holding all necessary informations
319 * @mc: memory controller structure holding memory informations
320 * @base: base address at which to put VRAM
322 * Function will place try to place VRAM at base address provided
323 * as parameter (which is so far either PCI aperture address or
324 * for IGP TOM base address).
326 * If there is not enough space to fit the unvisible VRAM in the 32bits
327 * address space then we limit the VRAM size to the aperture.
329 * If we are using AGP and if the AGP aperture doesn't allow us to have
330 * room for all the VRAM than we restrict the VRAM to the PCI aperture
331 * size and print a warning.
333 * This function will never fails, worst case are limiting VRAM.
335 * Note: GTT start, end, size should be initialized before calling this
336 * function on AGP platform.
338 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
339 * this shouldn't be a problem as we are using the PCI aperture as a reference.
340 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
343 * Note: we use mc_vram_size as on some board we need to program the mc to
344 * cover the whole aperture even if VRAM size is inferior to aperture size
345 * Novell bug 204882 + along with lots of ubuntu ones
347 * Note: when limiting vram it's safe to overwritte real_vram_size because
348 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
349 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
352 * Note: IGP TOM addr should be the same as the aperture addr, we don't
353 * explicitly check for that thought.
355 * FIXME: when reducing VRAM size align new size on power of 2.
357 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
359 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
361 mc->vram_start = base;
362 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
364 mc->real_vram_size = mc->aper_size;
365 mc->mc_vram_size = mc->aper_size;
367 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
368 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
369 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
370 mc->real_vram_size = mc->aper_size;
371 mc->mc_vram_size = mc->aper_size;
373 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
374 if (limit && limit < mc->real_vram_size)
375 mc->real_vram_size = limit;
376 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
377 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
378 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
382 * radeon_gtt_location - try to find GTT location
383 * @rdev: radeon device structure holding all necessary informations
384 * @mc: memory controller structure holding memory informations
386 * Function will place try to place GTT before or after VRAM.
388 * If GTT size is bigger than space left then we ajust GTT size.
389 * Thus function will never fails.
391 * FIXME: when reducing GTT size align new size on power of 2.
393 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
395 u64 size_af, size_bf;
397 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
398 size_bf = mc->vram_start & ~mc->gtt_base_align;
399 if (size_bf > size_af) {
400 if (mc->gtt_size > size_bf) {
401 dev_warn(rdev->dev, "limiting GTT\n");
402 mc->gtt_size = size_bf;
404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
406 if (mc->gtt_size > size_af) {
407 dev_warn(rdev->dev, "limiting GTT\n");
408 mc->gtt_size = size_af;
410 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
412 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
413 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n",
414 (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end);
418 * GPU helpers function.
421 * radeon_card_posted - check if the hw has already been initialized
423 * @rdev: radeon_device pointer
425 * Check if the asic has been initialized (all asics).
426 * Used at driver startup.
427 * Returns true if initialized or false if not.
429 bool radeon_card_posted(struct radeon_device *rdev)
434 if (efi_enabled(EFI_BOOT) &&
435 rdev->dev->pci_subvendor == PCI_VENDOR_ID_APPLE)
437 #endif /* DUMBBELL_WIP */
439 /* first check CRTCs */
440 if (ASIC_IS_DCE41(rdev)) {
441 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
442 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
443 if (reg & EVERGREEN_CRTC_MASTER_EN)
445 } else if (ASIC_IS_DCE4(rdev)) {
446 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
447 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
450 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
451 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
452 if (reg & EVERGREEN_CRTC_MASTER_EN)
454 } else if (ASIC_IS_AVIVO(rdev)) {
455 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
456 RREG32(AVIVO_D2CRTC_CONTROL);
457 if (reg & AVIVO_CRTC_EN) {
461 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
462 RREG32(RADEON_CRTC2_GEN_CNTL);
463 if (reg & RADEON_CRTC_EN) {
468 /* then check MEM_SIZE, in case the crtcs are off */
469 if (rdev->family >= CHIP_R600)
470 reg = RREG32(R600_CONFIG_MEMSIZE);
472 reg = RREG32(RADEON_CONFIG_MEMSIZE);
482 * radeon_update_bandwidth_info - update display bandwidth params
484 * @rdev: radeon_device pointer
486 * Used when sclk/mclk are switched or display modes are set.
487 * params are used to calculate display watermarks (all asics)
489 void radeon_update_bandwidth_info(struct radeon_device *rdev)
492 u32 sclk = rdev->pm.current_sclk;
493 u32 mclk = rdev->pm.current_mclk;
495 /* sclk/mclk in Mhz */
496 a.full = dfixed_const(100);
497 rdev->pm.sclk.full = dfixed_const(sclk);
498 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
499 rdev->pm.mclk.full = dfixed_const(mclk);
500 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
502 if (rdev->flags & RADEON_IS_IGP) {
503 a.full = dfixed_const(16);
504 /* core_bandwidth = sclk(Mhz) * 16 */
505 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
510 * radeon_boot_test_post_card - check and possibly initialize the hw
512 * @rdev: radeon_device pointer
514 * Check if the asic is initialized and if not, attempt to initialize
516 * Returns true if initialized or false if not.
518 bool radeon_boot_test_post_card(struct radeon_device *rdev)
520 if (radeon_card_posted(rdev))
524 DRM_INFO("GPU not posted. posting now...\n");
525 if (rdev->is_atom_bios)
526 atom_asic_init(rdev->mode_info.atom_context);
528 radeon_combios_asic_init(rdev->ddev);
531 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
537 * radeon_dummy_page_init - init dummy page used by the driver
539 * @rdev: radeon_device pointer
541 * Allocate the dummy page used by the driver (all asics).
542 * This dummy page is used by the driver as a filler for gart entries
543 * when pages are taken out of the GART
544 * Returns 0 on sucess, -ENOMEM on failure.
546 int radeon_dummy_page_init(struct radeon_device *rdev)
548 if (rdev->dummy_page.dmah)
550 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev,
551 PAGE_SIZE, PAGE_SIZE, BUS_SPACE_MAXSIZE_32BIT);
552 if (rdev->dummy_page.dmah == NULL)
554 rdev->dummy_page.addr = rdev->dummy_page.dmah->busaddr;
559 * radeon_dummy_page_fini - free dummy page used by the driver
561 * @rdev: radeon_device pointer
563 * Frees the dummy page used by the driver (all asics).
565 void radeon_dummy_page_fini(struct radeon_device *rdev)
567 if (rdev->dummy_page.dmah == NULL)
569 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah);
570 rdev->dummy_page.dmah = NULL;
571 rdev->dummy_page.addr = 0;
575 /* ATOM accessor methods */
577 * ATOM is an interpreted byte code stored in tables in the vbios. The
578 * driver registers callbacks to access registers and the interpreter
579 * in the driver parses the tables and executes then to program specific
580 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
581 * atombios.h, and atom.c
585 * cail_pll_read - read PLL register
587 * @info: atom card_info pointer
588 * @reg: PLL register offset
590 * Provides a PLL register accessor for the atom interpreter (r4xx+).
591 * Returns the value of the PLL register.
593 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
595 struct radeon_device *rdev = info->dev->dev_private;
598 r = rdev->pll_rreg(rdev, reg);
603 * cail_pll_write - write PLL register
605 * @info: atom card_info pointer
606 * @reg: PLL register offset
607 * @val: value to write to the pll register
609 * Provides a PLL register accessor for the atom interpreter (r4xx+).
611 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
613 struct radeon_device *rdev = info->dev->dev_private;
615 rdev->pll_wreg(rdev, reg, val);
619 * cail_mc_read - read MC (Memory Controller) register
621 * @info: atom card_info pointer
622 * @reg: MC register offset
624 * Provides an MC register accessor for the atom interpreter (r4xx+).
625 * Returns the value of the MC register.
627 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
629 struct radeon_device *rdev = info->dev->dev_private;
632 r = rdev->mc_rreg(rdev, reg);
637 * cail_mc_write - write MC (Memory Controller) register
639 * @info: atom card_info pointer
640 * @reg: MC register offset
641 * @val: value to write to the pll register
643 * Provides a MC register accessor for the atom interpreter (r4xx+).
645 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
647 struct radeon_device *rdev = info->dev->dev_private;
649 rdev->mc_wreg(rdev, reg, val);
653 * cail_reg_write - write MMIO register
655 * @info: atom card_info pointer
656 * @reg: MMIO register offset
657 * @val: value to write to the pll register
659 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
661 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
663 struct radeon_device *rdev = info->dev->dev_private;
669 * cail_reg_read - read MMIO register
671 * @info: atom card_info pointer
672 * @reg: MMIO register offset
674 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
675 * Returns the value of the MMIO register.
677 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
679 struct radeon_device *rdev = info->dev->dev_private;
687 * cail_ioreg_write - write IO register
689 * @info: atom card_info pointer
690 * @reg: IO register offset
691 * @val: value to write to the pll register
693 * Provides a IO register accessor for the atom interpreter (r4xx+).
695 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
697 struct radeon_device *rdev = info->dev->dev_private;
699 WREG32_IO(reg*4, val);
703 * cail_ioreg_read - read IO register
705 * @info: atom card_info pointer
706 * @reg: IO register offset
708 * Provides an IO register accessor for the atom interpreter (r4xx+).
709 * Returns the value of the IO register.
711 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
713 struct radeon_device *rdev = info->dev->dev_private;
716 r = RREG32_IO(reg*4);
721 * radeon_atombios_init - init the driver info and callbacks for atombios
723 * @rdev: radeon_device pointer
725 * Initializes the driver info and register access callbacks for the
726 * ATOM interpreter (r4xx+).
727 * Returns 0 on sucess, -ENOMEM on failure.
728 * Called at driver startup.
730 int radeon_atombios_init(struct radeon_device *rdev)
732 struct card_info *atom_card_info =
733 malloc(sizeof(struct card_info),
734 DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
739 rdev->mode_info.atom_card_info = atom_card_info;
740 atom_card_info->dev = rdev->ddev;
741 atom_card_info->reg_read = cail_reg_read;
742 atom_card_info->reg_write = cail_reg_write;
743 /* needed for iio ops */
745 atom_card_info->ioreg_read = cail_ioreg_read;
746 atom_card_info->ioreg_write = cail_ioreg_write;
748 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
749 atom_card_info->ioreg_read = cail_reg_read;
750 atom_card_info->ioreg_write = cail_reg_write;
752 atom_card_info->mc_read = cail_mc_read;
753 atom_card_info->mc_write = cail_mc_write;
754 atom_card_info->pll_read = cail_pll_read;
755 atom_card_info->pll_write = cail_pll_write;
757 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
758 sx_init(&rdev->mode_info.atom_context->mutex,
759 "drm__radeon_device__mode_info__atom_context__mutex");
760 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
761 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
766 * radeon_atombios_fini - free the driver info and callbacks for atombios
768 * @rdev: radeon_device pointer
770 * Frees the driver info and register access callbacks for the ATOM
771 * interpreter (r4xx+).
772 * Called at driver shutdown.
774 void radeon_atombios_fini(struct radeon_device *rdev)
776 if (rdev->mode_info.atom_context) {
777 free(rdev->mode_info.atom_context->scratch, DRM_MEM_DRIVER);
778 atom_destroy(rdev->mode_info.atom_context);
780 free(rdev->mode_info.atom_card_info, DRM_MEM_DRIVER);
785 * COMBIOS is the bios format prior to ATOM. It provides
786 * command tables similar to ATOM, but doesn't have a unified
787 * parser. See radeon_combios.c
791 * radeon_combios_init - init the driver info for combios
793 * @rdev: radeon_device pointer
795 * Initializes the driver info for combios (r1xx-r3xx).
796 * Returns 0 on sucess.
797 * Called at driver startup.
799 int radeon_combios_init(struct radeon_device *rdev)
801 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
806 * radeon_combios_fini - free the driver info for combios
808 * @rdev: radeon_device pointer
810 * Frees the driver info for combios (r1xx-r3xx).
811 * Called at driver shutdown.
813 void radeon_combios_fini(struct radeon_device *rdev)
818 /* if we get transitioned to only one device, take VGA back */
820 * radeon_vga_set_decode - enable/disable vga decode
822 * @cookie: radeon_device pointer
823 * @state: enable/disable vga decode
825 * Enable/disable vga decode (all asics).
826 * Returns VGA resource flags.
828 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
830 struct radeon_device *rdev = cookie;
831 radeon_vga_set_state(rdev, state);
833 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
834 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
836 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
838 #endif /* DUMBBELL_WIP */
841 * radeon_check_pot_argument - check that argument is a power of two
843 * @arg: value to check
845 * Validates that a certain argument is a power of two (all asics).
846 * Returns true if argument is valid.
848 static bool radeon_check_pot_argument(int arg)
850 return (arg & (arg - 1)) == 0;
854 * radeon_check_arguments - validate module params
856 * @rdev: radeon_device pointer
858 * Validates certain module parameters and updates
859 * the associated values used by the driver (all asics).
861 static void radeon_check_arguments(struct radeon_device *rdev)
863 /* vramlimit must be a power of two */
864 if (!radeon_check_pot_argument(radeon_vram_limit)) {
865 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
867 radeon_vram_limit = 0;
870 /* gtt size must be power of two and greater or equal to 32M */
871 if (radeon_gart_size < 32) {
872 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
874 radeon_gart_size = 512;
876 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
877 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
879 radeon_gart_size = 512;
881 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
883 /* AGP mode can only be -1, 1, 2, 4, 8 */
884 switch (radeon_agpmode) {
893 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
894 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
901 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
902 * needed for waking up.
904 * @pdev: pci dev pointer
907 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
910 /* 6600m in a macbook pro */
911 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
912 pdev->subsystem_device == 0x00e2) {
913 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
919 #endif /* DUMBBELL_WIP */
922 * radeon_switcheroo_set_state - set switcheroo state
924 * @pdev: pci dev pointer
925 * @state: vga switcheroo state
927 * Callback for the switcheroo driver. Suspends or resumes the
928 * the asics before or after it is powered up using ACPI methods.
931 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
933 struct drm_device *dev = pci_get_drvdata(pdev);
934 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
935 if (state == VGA_SWITCHEROO_ON) {
936 unsigned d3_delay = dev->pdev->d3_delay;
938 printk(KERN_INFO "radeon: switched on\n");
939 /* don't suspend or resume card normally */
940 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
942 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
943 dev->pdev->d3_delay = 20;
945 radeon_resume_kms(dev);
947 dev->pdev->d3_delay = d3_delay;
949 dev->switch_power_state = DRM_SWITCH_POWER_ON;
950 drm_kms_helper_poll_enable(dev);
952 printk(KERN_INFO "radeon: switched off\n");
953 drm_kms_helper_poll_disable(dev);
954 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
955 radeon_suspend_kms(dev, pmm);
956 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
959 #endif /* DUMBBELL_WIP */
962 * radeon_switcheroo_can_switch - see if switcheroo state can change
964 * @pdev: pci dev pointer
966 * Callback for the switcheroo driver. Check of the switcheroo
967 * state can be changed.
968 * Returns true if the state can be changed, false if not.
971 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
973 struct drm_device *dev = pci_get_drvdata(pdev);
976 spin_lock(&dev->count_lock);
977 can_switch = (dev->open_count == 0);
978 spin_unlock(&dev->count_lock);
982 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
983 .set_gpu_state = radeon_switcheroo_set_state,
985 .can_switch = radeon_switcheroo_can_switch,
987 #endif /* DUMBBELL_WIP */
990 * radeon_device_init - initialize the driver
992 * @rdev: radeon_device pointer
993 * @pdev: drm dev pointer
994 * @flags: driver flags
996 * Initializes the driver info and hw (all asics).
997 * Returns 0 for success or an error on failure.
998 * Called at driver startup.
1000 int radeon_device_init(struct radeon_device *rdev,
1001 struct drm_device *ddev,
1007 rdev->shutdown = false;
1008 rdev->dev = ddev->device;
1010 rdev->flags = flags;
1011 rdev->family = flags & RADEON_FAMILY_MASK;
1012 rdev->is_atom_bios = false;
1013 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1014 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1015 rdev->accel_working = false;
1016 rdev->fictitious_range_registered = false;
1017 /* set up ring ids */
1018 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1019 rdev->ring[i].idx = i;
1022 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1023 radeon_family_name[rdev->family], ddev->pci_vendor, ddev->pci_device,
1024 ddev->pci_subvendor, ddev->pci_subdevice);
1026 /* mutex initialization are all done here so we
1027 * can recall function without having locking issues */
1028 sx_init(&rdev->ring_lock, "drm__radeon_device__ring_lock");
1029 sx_init(&rdev->dc_hw_i2c_mutex, "drm__radeon_device__dc_hw_i2c_mutex");
1030 atomic_set(&rdev->ih.lock, 0);
1031 sx_init(&rdev->gem.mutex, "drm__radeon_device__gem__mutex");
1032 sx_init(&rdev->pm.mutex, "drm__radeon_device__pm__mutex");
1033 sx_init(&rdev->gpu_clock_mutex, "drm__radeon_device__gpu_clock_mutex");
1034 sx_init(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock");
1035 sx_init(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock");
1036 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue);
1037 r = radeon_gem_init(rdev);
1040 /* initialize vm here */
1041 sx_init(&rdev->vm_manager.lock, "drm__radeon_device__vm_manager__lock");
1042 /* Adjust VM size here.
1043 * Currently set to 4GB ((1 << 20) 4k pages).
1044 * Max GPUVM size for cayman and SI is 40 bits.
1046 rdev->vm_manager.max_pfn = 1 << 20;
1047 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1049 /* Set asic functions */
1050 r = radeon_asic_init(rdev);
1053 radeon_check_arguments(rdev);
1055 /* all of the newer IGP chips have an internal gart
1056 * However some rs4xx report as AGP, so remove that here.
1058 if ((rdev->family >= CHIP_RS400) &&
1059 (rdev->flags & RADEON_IS_IGP)) {
1060 rdev->flags &= ~RADEON_IS_AGP;
1063 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1064 radeon_agp_disable(rdev);
1067 /* set DMA mask + need_dma32 flags.
1068 * PCIE - can handle 40-bits.
1069 * IGP - can handle 40-bits
1070 * AGP - generally dma32 is safest
1071 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1073 rdev->need_dma32 = false;
1074 if (rdev->flags & RADEON_IS_AGP)
1075 rdev->need_dma32 = true;
1076 if ((rdev->flags & RADEON_IS_PCI) &&
1077 (rdev->family <= CHIP_RS740))
1078 rdev->need_dma32 = true;
1080 dma_bits = rdev->need_dma32 ? 32 : 40;
1082 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1084 rdev->need_dma32 = true;
1086 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1088 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1090 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1091 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1093 #endif /* DUMBBELL_WIP */
1095 /* Registers mapping */
1096 /* TODO: block userspace mapping of io register */
1097 DRM_SPININIT(&rdev->mmio_idx_lock, "drm__radeon_device__mmio_idx_lock");
1098 rdev->rmmio_rid = PCIR_BAR(2);
1099 rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY,
1100 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE);
1101 if (rdev->rmmio == NULL) {
1104 rdev->rmmio_base = rman_get_start(rdev->rmmio);
1105 rdev->rmmio_size = rman_get_size(rdev->rmmio);
1106 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1107 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1109 /* io port mapping */
1110 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) {
1113 data = pci_read_config(rdev->dev, PCIR_BAR(i), 4);
1114 if (PCI_BAR_IO(data)) {
1115 rdev->rio_rid = PCIR_BAR(i);
1116 rdev->rio_mem = bus_alloc_resource_any(rdev->dev,
1117 SYS_RES_IOPORT, &rdev->rio_rid,
1118 RF_ACTIVE | RF_SHAREABLE);
1122 if (rdev->rio_mem == NULL)
1123 DRM_ERROR("Unable to find PCI I/O BAR\n");
1125 rdev->tq = taskqueue_create("radeonkms", M_WAITOK,
1126 taskqueue_thread_enqueue, &rdev->tq);
1127 taskqueue_start_threads(&rdev->tq, 1, PWAIT, "radeon taskq");
1130 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1131 /* this will fail for cards that aren't VGA class devices, just
1133 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1134 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1135 #endif /* DUMBBELL_WIP */
1137 r = radeon_init(rdev);
1141 r = radeon_ib_ring_tests(rdev);
1143 DRM_ERROR("ib ring test failed (%d).\n", r);
1145 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1146 /* Acceleration not working on AGP card try again
1147 * with fallback to PCI or PCIE GART
1149 radeon_asic_reset(rdev);
1151 radeon_agp_disable(rdev);
1152 r = radeon_init(rdev);
1157 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1158 __func__, (uintmax_t)rdev->mc.aper_base,
1159 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size);
1160 r = vm_phys_fictitious_reg_range(
1162 rdev->mc.aper_base + rdev->mc.visible_vram_size,
1163 VM_MEMATTR_WRITE_COMBINING);
1165 DRM_ERROR("Failed to register fictitious range "
1166 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base,
1167 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r);
1170 rdev->fictitious_range_registered = true;
1172 if ((radeon_testing & 1)) {
1173 radeon_test_moves(rdev);
1175 if ((radeon_testing & 2)) {
1176 radeon_test_syncing(rdev);
1178 if (radeon_benchmarking) {
1179 radeon_benchmark(rdev, radeon_benchmarking);
1185 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1186 #endif /* DUMBBELL_WIP */
1189 * radeon_device_fini - tear down the driver
1191 * @rdev: radeon_device pointer
1193 * Tear down the driver info (all asics).
1194 * Called at driver shutdown.
1196 void radeon_device_fini(struct radeon_device *rdev)
1198 DRM_INFO("radeon: finishing device.\n");
1199 rdev->shutdown = true;
1200 /* evict vram memory */
1201 radeon_bo_evict_vram(rdev);
1203 if (rdev->fictitious_range_registered) {
1204 vm_phys_fictitious_unreg_range(
1206 rdev->mc.aper_base + rdev->mc.visible_vram_size);
1211 vga_switcheroo_unregister_client(rdev->pdev);
1212 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1213 #endif /* DUMBBELL_WIP */
1215 if (rdev->tq != NULL) {
1216 taskqueue_free(rdev->tq);
1221 bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid,
1223 rdev->rio_mem = NULL;
1224 bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid,
1228 radeon_debugfs_remove_files(rdev);
1229 #endif /* DUMBBELL_WIP */
1237 * radeon_suspend_kms - initiate device suspend
1239 * @pdev: drm dev pointer
1240 * @state: suspend state
1242 * Puts the hw in the suspend state (all asics).
1243 * Returns 0 for success or an error on failure.
1244 * Called at driver suspend.
1246 int radeon_suspend_kms(struct drm_device *dev)
1248 struct radeon_device *rdev;
1249 struct drm_crtc *crtc;
1250 struct drm_connector *connector;
1252 bool force_completion = false;
1254 if (dev == NULL || dev->dev_private == NULL) {
1258 if (state.event == PM_EVENT_PRETHAW) {
1261 #endif /* DUMBBELL_WIP */
1262 rdev = dev->dev_private;
1264 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1267 drm_kms_helper_poll_disable(dev);
1269 /* turn off display hw */
1270 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1271 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1274 /* unpin the front buffers */
1275 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1276 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1277 struct radeon_bo *robj;
1279 if (rfb == NULL || rfb->obj == NULL) {
1282 robj = gem_to_radeon_bo(rfb->obj);
1283 /* don't unpin kernel fb objects */
1284 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1285 r = radeon_bo_reserve(robj, false);
1287 radeon_bo_unpin(robj);
1288 radeon_bo_unreserve(robj);
1292 /* evict vram memory */
1293 radeon_bo_evict_vram(rdev);
1295 sx_xlock(&rdev->ring_lock);
1296 /* wait for gpu to finish processing current batch */
1297 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1298 r = radeon_fence_wait_empty_locked(rdev, i);
1300 /* delay GPU reset to resume */
1301 force_completion = true;
1304 if (force_completion) {
1305 radeon_fence_driver_force_completion(rdev);
1307 sx_xunlock(&rdev->ring_lock);
1309 radeon_save_bios_scratch_regs(rdev);
1311 radeon_pm_suspend(rdev);
1312 radeon_suspend(rdev);
1313 radeon_hpd_fini(rdev);
1314 /* evict remaining vram memory */
1315 radeon_bo_evict_vram(rdev);
1317 radeon_agp_suspend(rdev);
1319 pci_save_state(device_get_parent(rdev->dev));
1321 if (state.event == PM_EVENT_SUSPEND) {
1322 /* Shut down the device */
1323 pci_disable_device(dev->pdev);
1324 #endif /* DUMBBELL_WIP */
1325 pci_set_powerstate(dev->device, PCI_POWERSTATE_D3);
1329 #endif /* DUMBBELL_WIP */
1330 radeon_fbdev_set_suspend(rdev, 1);
1333 #endif /* DUMBBELL_WIP */
1338 * radeon_resume_kms - initiate device resume
1340 * @pdev: drm dev pointer
1342 * Bring the hw back to operating state (all asics).
1343 * Returns 0 for success or an error on failure.
1344 * Called at driver resume.
1346 int radeon_resume_kms(struct drm_device *dev)
1348 struct drm_connector *connector;
1349 struct radeon_device *rdev = dev->dev_private;
1352 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1357 #endif /* DUMBBELL_WIP */
1358 pci_set_powerstate(dev->device, PCI_POWERSTATE_D0);
1359 pci_restore_state(device_get_parent(rdev->dev));
1361 if (pci_enable_device(dev->pdev)) {
1365 #endif /* DUMBBELL_WIP */
1366 /* resume AGP if in use */
1367 radeon_agp_resume(rdev);
1368 radeon_resume(rdev);
1370 r = radeon_ib_ring_tests(rdev);
1372 DRM_ERROR("ib ring test failed (%d).\n", r);
1374 radeon_pm_resume(rdev);
1375 radeon_restore_bios_scratch_regs(rdev);
1377 radeon_fbdev_set_suspend(rdev, 0);
1380 #endif /* DUMBBELL_WIP */
1382 /* init dig PHYs, disp eng pll */
1383 if (rdev->is_atom_bios) {
1384 radeon_atom_encoder_init(rdev);
1385 radeon_atom_disp_eng_pll_init(rdev);
1386 /* turn on the BL */
1387 if (rdev->mode_info.bl_encoder) {
1388 u8 bl_level = radeon_get_backlight_level(rdev,
1389 rdev->mode_info.bl_encoder);
1390 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1394 /* reset hpd state */
1395 radeon_hpd_init(rdev);
1396 /* blat the mode back in */
1397 drm_helper_resume_force_mode(dev);
1398 /* turn on display hw */
1399 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1400 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1403 drm_kms_helper_poll_enable(dev);
1408 * radeon_gpu_reset - reset the asic
1410 * @rdev: radeon device pointer
1412 * Attempt the reset the GPU if it has hung (all asics).
1413 * Returns 0 for success or an error on failure.
1415 int radeon_gpu_reset(struct radeon_device *rdev)
1417 unsigned ring_sizes[RADEON_NUM_RINGS];
1418 uint32_t *ring_data[RADEON_NUM_RINGS];
1425 sx_xlock(&rdev->exclusive_lock);
1426 radeon_save_bios_scratch_regs(rdev);
1428 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1429 radeon_suspend(rdev);
1431 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1432 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1434 if (ring_sizes[i]) {
1436 dev_info(rdev->dev, "Saved %d dwords of commands "
1437 "on ring %d.\n", ring_sizes[i], i);
1442 r = radeon_asic_reset(rdev);
1444 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1445 radeon_resume(rdev);
1448 radeon_restore_bios_scratch_regs(rdev);
1451 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1452 radeon_ring_restore(rdev, &rdev->ring[i],
1453 ring_sizes[i], ring_data[i]);
1455 ring_data[i] = NULL;
1458 r = radeon_ib_ring_tests(rdev);
1460 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1463 radeon_suspend(rdev);
1468 radeon_fence_driver_force_completion(rdev);
1469 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1470 free(ring_data[i], DRM_MEM_DRIVER);
1474 drm_helper_resume_force_mode(rdev->ddev);
1476 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1478 /* bad news, how to tell it to userspace ? */
1479 dev_info(rdev->dev, "GPU reset failed\n");
1482 sx_xunlock(&rdev->exclusive_lock);
1491 int radeon_debugfs_add_files(struct radeon_device *rdev,
1492 struct drm_info_list *files,
1497 for (i = 0; i < rdev->debugfs_count; i++) {
1498 if (rdev->debugfs[i].files == files) {
1499 /* Already registered */
1504 i = rdev->debugfs_count + 1;
1505 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1506 DRM_ERROR("Reached maximum number of debugfs components.\n");
1507 DRM_ERROR("Report so we increase "
1508 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1511 rdev->debugfs[rdev->debugfs_count].files = files;
1512 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1513 rdev->debugfs_count = i;
1514 #if defined(CONFIG_DEBUG_FS)
1515 drm_debugfs_create_files(files, nfiles,
1516 rdev->ddev->control->debugfs_root,
1517 rdev->ddev->control);
1518 drm_debugfs_create_files(files, nfiles,
1519 rdev->ddev->primary->debugfs_root,
1520 rdev->ddev->primary);
1525 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1527 #if defined(CONFIG_DEBUG_FS)
1530 for (i = 0; i < rdev->debugfs_count; i++) {
1531 drm_debugfs_remove_files(rdev->debugfs[i].files,
1532 rdev->debugfs[i].num_files,
1533 rdev->ddev->control);
1534 drm_debugfs_remove_files(rdev->debugfs[i].files,
1535 rdev->debugfs[i].num_files,
1536 rdev->ddev->primary);
1541 #if defined(CONFIG_DEBUG_FS)
1542 int radeon_debugfs_init(struct drm_minor *minor)
1547 void radeon_debugfs_cleanup(struct drm_minor *minor)
1550 #endif /* DUMBBELL_WIP */