2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/drm_crtc_helper.h>
32 #include <dev/drm2/radeon/radeon_drm.h>
34 #include "radeon_asic.h"
37 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
39 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
40 struct drm_encoder_helper_funcs *encoder_funcs;
42 encoder_funcs = encoder->helper_private;
43 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
44 radeon_encoder->active_device = 0;
47 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
49 struct drm_device *dev = encoder->dev;
50 struct radeon_device *rdev = dev->dev_private;
51 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
52 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
53 int panel_pwr_delay = 2000;
55 uint8_t backlight_level;
58 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
59 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
61 if (radeon_encoder->enc_priv) {
62 if (rdev->is_atom_bios) {
63 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
64 panel_pwr_delay = lvds->panel_pwr_delay;
66 backlight_level = lvds->backlight_level;
68 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
69 panel_pwr_delay = lvds->panel_pwr_delay;
71 backlight_level = lvds->backlight_level;
75 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
76 * Taken from radeonfb.
78 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
79 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
80 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
81 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
85 case DRM_MODE_DPMS_ON:
86 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
87 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
88 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
89 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
90 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
91 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
94 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
95 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
96 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
98 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
99 RADEON_LVDS_BL_MOD_LEVEL_MASK);
100 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
101 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
102 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
104 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
105 DRM_MDELAY(panel_pwr_delay);
106 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
108 case DRM_MODE_DPMS_STANDBY:
109 case DRM_MODE_DPMS_SUSPEND:
110 case DRM_MODE_DPMS_OFF:
111 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
112 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
113 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
115 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
116 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
117 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
119 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
120 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
122 DRM_MDELAY(panel_pwr_delay);
123 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
124 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
125 DRM_MDELAY(panel_pwr_delay);
129 if (rdev->is_atom_bios)
130 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
132 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
136 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
138 struct radeon_device *rdev = encoder->dev->dev_private;
139 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
142 if (radeon_encoder->enc_priv) {
143 if (rdev->is_atom_bios) {
144 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
145 lvds->dpms_mode = mode;
147 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
148 lvds->dpms_mode = mode;
152 radeon_legacy_lvds_update(encoder, mode);
155 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
157 struct radeon_device *rdev = encoder->dev->dev_private;
159 if (rdev->is_atom_bios)
160 radeon_atom_output_lock(encoder, true);
162 radeon_combios_output_lock(encoder, true);
163 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
166 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
168 struct radeon_device *rdev = encoder->dev->dev_private;
170 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
171 if (rdev->is_atom_bios)
172 radeon_atom_output_lock(encoder, false);
174 radeon_combios_output_lock(encoder, false);
177 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
178 struct drm_display_mode *mode,
179 struct drm_display_mode *adjusted_mode)
181 struct drm_device *dev = encoder->dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
184 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
185 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
189 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
190 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
192 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
193 if (rdev->is_atom_bios) {
194 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
195 * need to call that on resume to set up the reg properly.
197 radeon_encoder->pixel_clock = adjusted_mode->clock;
198 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
199 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
201 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
203 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
204 lvds_gen_cntl = lvds->lvds_gen_cntl;
205 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
206 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
207 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
208 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
210 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
212 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
213 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
218 if (ASIC_IS_R300(rdev))
219 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
221 if (radeon_crtc->crtc_id == 0) {
222 if (ASIC_IS_R300(rdev)) {
223 if (radeon_encoder->rmx_type != RMX_OFF)
224 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
226 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
228 if (ASIC_IS_R300(rdev))
229 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
231 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
234 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
235 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
236 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
238 if (rdev->family == CHIP_RV410)
239 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
241 if (rdev->is_atom_bios)
242 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
247 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
248 const struct drm_display_mode *mode,
249 struct drm_display_mode *adjusted_mode)
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
253 /* set the active encoder to connector routing */
254 radeon_encoder_set_active_device(encoder);
255 drm_mode_set_crtcinfo(adjusted_mode, 0);
257 /* get the native mode for LVDS */
258 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
259 radeon_panel_mode_fixup(encoder, adjusted_mode);
264 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
265 .dpms = radeon_legacy_lvds_dpms,
266 .mode_fixup = radeon_legacy_mode_fixup,
267 .prepare = radeon_legacy_lvds_prepare,
268 .mode_set = radeon_legacy_lvds_mode_set,
269 .commit = radeon_legacy_lvds_commit,
270 .disable = radeon_legacy_encoder_disable,
274 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
276 struct drm_device *dev = radeon_encoder->base.dev;
277 struct radeon_device *rdev = dev->dev_private;
280 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
281 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
283 return backlight_level;
287 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
289 struct drm_device *dev = radeon_encoder->base.dev;
290 struct radeon_device *rdev = dev->dev_private;
291 int dpms_mode = DRM_MODE_DPMS_ON;
293 if (radeon_encoder->enc_priv) {
294 if (rdev->is_atom_bios) {
295 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
296 if (lvds->backlight_level > 0)
297 dpms_mode = lvds->dpms_mode;
299 dpms_mode = DRM_MODE_DPMS_OFF;
300 lvds->backlight_level = level;
302 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
303 if (lvds->backlight_level > 0)
304 dpms_mode = lvds->dpms_mode;
306 dpms_mode = DRM_MODE_DPMS_OFF;
307 lvds->backlight_level = level;
311 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
314 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
316 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
318 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
321 /* Convert brightness to hardware level */
322 if (bd->props.brightness < 0)
324 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
325 level = RADEON_MAX_BL_LEVEL;
327 level = bd->props.brightness;
330 level = RADEON_MAX_BL_LEVEL - level;
335 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
337 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
338 struct radeon_encoder *radeon_encoder = pdata->encoder;
340 radeon_legacy_set_backlight_level(radeon_encoder,
341 radeon_legacy_lvds_level(bd));
346 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
348 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
349 struct radeon_encoder *radeon_encoder = pdata->encoder;
350 struct drm_device *dev = radeon_encoder->base.dev;
351 struct radeon_device *rdev = dev->dev_private;
352 uint8_t backlight_level;
354 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
355 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
357 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
360 static const struct backlight_ops radeon_backlight_ops = {
361 .get_brightness = radeon_legacy_backlight_get_brightness,
362 .update_status = radeon_legacy_backlight_update_status,
365 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
366 struct drm_connector *drm_connector)
368 struct drm_device *dev = radeon_encoder->base.dev;
369 struct radeon_device *rdev = dev->dev_private;
370 struct backlight_device *bd;
371 struct backlight_properties props;
372 struct radeon_backlight_privdata *pdata;
373 uint8_t backlight_level;
376 if (!radeon_encoder->enc_priv)
379 #ifdef CONFIG_PMAC_BACKLIGHT
380 if (!pmac_has_backlight_type("ati") &&
381 !pmac_has_backlight_type("mnca"))
385 pdata = malloc(sizeof(struct radeon_backlight_privdata),
386 DRM_MEM_DRIVER, M_WAITOK);
388 DRM_ERROR("Memory allocation failed\n");
392 memset(&props, 0, sizeof(props));
393 props.max_brightness = RADEON_MAX_BL_LEVEL;
394 props.type = BACKLIGHT_RAW;
395 snprintf(bl_name, sizeof(bl_name),
396 "radeon_bl%d", dev->primary->index);
397 bd = backlight_device_register(bl_name, &drm_connector->kdev,
398 pdata, &radeon_backlight_ops, &props);
400 DRM_ERROR("Backlight registration failed\n");
404 pdata->encoder = radeon_encoder;
406 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
407 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
409 /* First, try to detect backlight level sense based on the assumption
410 * that firmware set it up at full brightness
412 if (backlight_level == 0)
413 pdata->negative = true;
414 else if (backlight_level == 0xff)
415 pdata->negative = false;
417 /* XXX hack... maybe some day we can figure out in what direction
418 * backlight should work on a given panel?
420 pdata->negative = (rdev->family != CHIP_RV200 &&
421 rdev->family != CHIP_RV250 &&
422 rdev->family != CHIP_RV280 &&
423 rdev->family != CHIP_RV350);
425 #ifdef CONFIG_PMAC_BACKLIGHT
426 pdata->negative = (pdata->negative ||
427 of_machine_is_compatible("PowerBook4,3") ||
428 of_machine_is_compatible("PowerBook6,3") ||
429 of_machine_is_compatible("PowerBook6,5"));
433 if (rdev->is_atom_bios) {
434 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
437 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
441 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
442 bd->props.power = FB_BLANK_UNBLANK;
443 backlight_update_status(bd);
445 DRM_INFO("radeon legacy LVDS backlight initialized\n");
450 free(pdata, DRM_MEM_DRIVER);
454 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
456 struct drm_device *dev = radeon_encoder->base.dev;
457 struct radeon_device *rdev = dev->dev_private;
458 struct backlight_device *bd = NULL;
460 if (!radeon_encoder->enc_priv)
463 if (rdev->is_atom_bios) {
464 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
468 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
474 struct radeon_backlight_privdata *pdata;
476 pdata = bl_get_data(bd);
477 backlight_device_unregister(bd);
478 free(pdata, DRM_MEM_DRIVER);
480 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
484 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
486 void radeon_legacy_backlight_init(struct radeon_encoder *encoder,
487 struct drm_connector *drm_connector)
491 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
498 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
500 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
502 if (radeon_encoder->enc_priv) {
503 radeon_legacy_backlight_exit(radeon_encoder);
504 free(radeon_encoder->enc_priv, DRM_MEM_DRIVER);
506 drm_encoder_cleanup(encoder);
507 free(radeon_encoder, DRM_MEM_DRIVER);
510 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
511 .destroy = radeon_lvds_enc_destroy,
514 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
516 struct drm_device *dev = encoder->dev;
517 struct radeon_device *rdev = dev->dev_private;
518 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
519 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
520 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
525 case DRM_MODE_DPMS_ON:
526 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
527 dac_cntl &= ~RADEON_DAC_PDWN;
528 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
532 case DRM_MODE_DPMS_STANDBY:
533 case DRM_MODE_DPMS_SUSPEND:
534 case DRM_MODE_DPMS_OFF:
535 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
536 dac_cntl |= RADEON_DAC_PDWN;
537 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
543 /* handled in radeon_crtc_dpms() */
544 if (!(rdev->flags & RADEON_SINGLE_CRTC))
545 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
546 WREG32(RADEON_DAC_CNTL, dac_cntl);
547 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
549 if (rdev->is_atom_bios)
550 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
552 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
556 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
558 struct radeon_device *rdev = encoder->dev->dev_private;
560 if (rdev->is_atom_bios)
561 radeon_atom_output_lock(encoder, true);
563 radeon_combios_output_lock(encoder, true);
564 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
567 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
569 struct radeon_device *rdev = encoder->dev->dev_private;
571 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
573 if (rdev->is_atom_bios)
574 radeon_atom_output_lock(encoder, false);
576 radeon_combios_output_lock(encoder, false);
579 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
580 struct drm_display_mode *mode,
581 struct drm_display_mode *adjusted_mode)
583 struct drm_device *dev = encoder->dev;
584 struct radeon_device *rdev = dev->dev_private;
585 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
586 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
587 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
591 if (radeon_crtc->crtc_id == 0) {
592 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
593 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
594 ~(RADEON_DISP_DAC_SOURCE_MASK);
595 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
597 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
598 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
601 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
602 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
603 ~(RADEON_DISP_DAC_SOURCE_MASK);
604 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
605 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
607 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
608 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
612 dac_cntl = (RADEON_DAC_MASK_ALL |
613 RADEON_DAC_VGA_ADR_EN |
617 WREG32_P(RADEON_DAC_CNTL,
619 RADEON_DAC_RANGE_CNTL |
620 RADEON_DAC_BLANKING);
622 if (radeon_encoder->enc_priv) {
623 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
624 dac_macro_cntl = p_dac->ps2_pdac_adj;
626 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
627 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
628 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
630 if (rdev->is_atom_bios)
631 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
633 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
636 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
637 struct drm_connector *connector)
639 struct drm_device *dev = encoder->dev;
640 struct radeon_device *rdev = dev->dev_private;
641 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
642 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
643 enum drm_connector_status found = connector_status_disconnected;
646 /* just don't bother on RN50 those chip are often connected to remoting
647 * console hw and often we get failure to load detect those. So to make
648 * everyone happy report the encoder as always connected.
650 if (ASIC_IS_RN50(rdev)) {
651 return connector_status_connected;
654 /* save the regs we need */
655 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
656 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
657 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
658 dac_cntl = RREG32(RADEON_DAC_CNTL);
659 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
661 tmp = vclk_ecp_cntl &
662 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
663 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
665 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
666 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
668 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
669 RADEON_DAC_FORCE_DATA_EN;
672 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
674 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
676 if (ASIC_IS_R300(rdev))
677 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
678 else if (ASIC_IS_RV100(rdev))
679 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
681 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
683 WREG32(RADEON_DAC_EXT_CNTL, tmp);
685 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
686 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
687 WREG32(RADEON_DAC_CNTL, tmp);
689 tmp = dac_macro_cntl;
690 tmp &= ~(RADEON_DAC_PDWN_R |
694 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
698 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
699 found = connector_status_connected;
701 /* restore the regs we used */
702 WREG32(RADEON_DAC_CNTL, dac_cntl);
703 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
704 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
705 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
706 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
711 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
712 .dpms = radeon_legacy_primary_dac_dpms,
713 .mode_fixup = radeon_legacy_mode_fixup,
714 .prepare = radeon_legacy_primary_dac_prepare,
715 .mode_set = radeon_legacy_primary_dac_mode_set,
716 .commit = radeon_legacy_primary_dac_commit,
717 .detect = radeon_legacy_primary_dac_detect,
718 .disable = radeon_legacy_encoder_disable,
722 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
723 .destroy = radeon_enc_destroy,
726 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
728 struct drm_device *dev = encoder->dev;
729 struct radeon_device *rdev = dev->dev_private;
730 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
734 case DRM_MODE_DPMS_ON:
735 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
737 case DRM_MODE_DPMS_STANDBY:
738 case DRM_MODE_DPMS_SUSPEND:
739 case DRM_MODE_DPMS_OFF:
740 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
744 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
746 if (rdev->is_atom_bios)
747 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
749 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
753 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
755 struct radeon_device *rdev = encoder->dev->dev_private;
757 if (rdev->is_atom_bios)
758 radeon_atom_output_lock(encoder, true);
760 radeon_combios_output_lock(encoder, true);
761 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
764 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
766 struct radeon_device *rdev = encoder->dev->dev_private;
768 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
770 if (rdev->is_atom_bios)
771 radeon_atom_output_lock(encoder, true);
773 radeon_combios_output_lock(encoder, true);
776 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
777 struct drm_display_mode *mode,
778 struct drm_display_mode *adjusted_mode)
780 struct drm_device *dev = encoder->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
783 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
784 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
789 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
791 if (rdev->family == CHIP_RV280) {
792 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
794 tmds_pll_cntl ^= (1 << 22);
797 if (radeon_encoder->enc_priv) {
798 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
800 for (i = 0; i < 4; i++) {
801 if (tmds->tmds_pll[i].freq == 0)
803 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
804 tmp = tmds->tmds_pll[i].value ;
810 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
811 if (tmp & 0xfff00000)
814 tmds_pll_cntl &= 0xfff00000;
815 tmds_pll_cntl |= tmp;
820 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
821 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
823 if (rdev->family == CHIP_R200 ||
824 rdev->family == CHIP_R100 ||
826 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
827 else /* RV chips got this bit reversed */
828 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
830 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
831 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
832 RADEON_FP_CRTC_DONT_SHADOW_HEND));
834 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
836 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
837 RADEON_FP_DFP_SYNC_SEL |
838 RADEON_FP_CRT_SYNC_SEL |
839 RADEON_FP_CRTC_LOCK_8DOT |
840 RADEON_FP_USE_SHADOW_EN |
841 RADEON_FP_CRTC_USE_SHADOW_VEND |
842 RADEON_FP_CRT_SYNC_ALT);
844 if (1) /* FIXME rgbBits == 8 */
845 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
847 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
849 if (radeon_crtc->crtc_id == 0) {
850 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
851 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
852 if (radeon_encoder->rmx_type != RMX_OFF)
853 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
855 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
857 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
859 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
860 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
861 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
863 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
866 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
867 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
868 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
870 if (rdev->is_atom_bios)
871 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
873 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
876 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
877 .dpms = radeon_legacy_tmds_int_dpms,
878 .mode_fixup = radeon_legacy_mode_fixup,
879 .prepare = radeon_legacy_tmds_int_prepare,
880 .mode_set = radeon_legacy_tmds_int_mode_set,
881 .commit = radeon_legacy_tmds_int_commit,
882 .disable = radeon_legacy_encoder_disable,
886 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
887 .destroy = radeon_enc_destroy,
890 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
892 struct drm_device *dev = encoder->dev;
893 struct radeon_device *rdev = dev->dev_private;
894 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
898 case DRM_MODE_DPMS_ON:
899 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
900 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
902 case DRM_MODE_DPMS_STANDBY:
903 case DRM_MODE_DPMS_SUSPEND:
904 case DRM_MODE_DPMS_OFF:
905 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
906 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
910 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
912 if (rdev->is_atom_bios)
913 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
915 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
919 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
921 struct radeon_device *rdev = encoder->dev->dev_private;
923 if (rdev->is_atom_bios)
924 radeon_atom_output_lock(encoder, true);
926 radeon_combios_output_lock(encoder, true);
927 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
930 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
932 struct radeon_device *rdev = encoder->dev->dev_private;
933 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
935 if (rdev->is_atom_bios)
936 radeon_atom_output_lock(encoder, false);
938 radeon_combios_output_lock(encoder, false);
941 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
942 struct drm_display_mode *mode,
943 struct drm_display_mode *adjusted_mode)
945 struct drm_device *dev = encoder->dev;
946 struct radeon_device *rdev = dev->dev_private;
947 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
948 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
949 uint32_t fp2_gen_cntl;
953 if (rdev->is_atom_bios) {
954 radeon_encoder->pixel_clock = adjusted_mode->clock;
955 atombios_dvo_setup(encoder, ATOM_ENABLE);
956 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
958 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
960 if (1) /* FIXME rgbBits == 8 */
961 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
963 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
965 fp2_gen_cntl &= ~(RADEON_FP2_ON |
967 RADEON_FP2_DVO_RATE_SEL_SDR);
969 /* XXX: these are oem specific */
970 if (ASIC_IS_R300(rdev)) {
971 if ((dev->pci_device == 0x4850) &&
972 (dev->pci_subvendor == 0x1028) &&
973 (dev->pci_subdevice == 0x2001)) /* Dell Inspiron 8600 */
974 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
976 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
978 /*if (mode->clock > 165000)
979 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
981 if (!radeon_combios_external_tmds_setup(encoder))
982 radeon_external_tmds_setup(encoder);
985 if (radeon_crtc->crtc_id == 0) {
986 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
987 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
988 if (radeon_encoder->rmx_type != RMX_OFF)
989 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
991 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
993 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
995 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
996 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
997 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
999 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1002 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1004 if (rdev->is_atom_bios)
1005 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1007 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1010 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1012 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1013 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1014 free(radeon_encoder->enc_priv, DRM_MEM_DRIVER);
1015 drm_encoder_cleanup(encoder);
1016 free(radeon_encoder, DRM_MEM_DRIVER);
1019 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1020 .dpms = radeon_legacy_tmds_ext_dpms,
1021 .mode_fixup = radeon_legacy_mode_fixup,
1022 .prepare = radeon_legacy_tmds_ext_prepare,
1023 .mode_set = radeon_legacy_tmds_ext_mode_set,
1024 .commit = radeon_legacy_tmds_ext_commit,
1025 .disable = radeon_legacy_encoder_disable,
1029 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1030 .destroy = radeon_ext_tmds_enc_destroy,
1033 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1035 struct drm_device *dev = encoder->dev;
1036 struct radeon_device *rdev = dev->dev_private;
1037 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1038 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1039 uint32_t tv_master_cntl = 0;
1041 DRM_DEBUG_KMS("\n");
1043 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1045 if (rdev->family == CHIP_R200)
1046 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1049 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1051 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1052 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1056 case DRM_MODE_DPMS_ON:
1057 if (rdev->family == CHIP_R200) {
1058 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1061 tv_master_cntl |= RADEON_TV_ON;
1063 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1065 if (rdev->family == CHIP_R420 ||
1066 rdev->family == CHIP_R423 ||
1067 rdev->family == CHIP_RV410)
1068 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1069 R420_TV_DAC_GDACPD |
1070 R420_TV_DAC_BDACPD |
1071 RADEON_TV_DAC_BGSLEEP);
1073 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1074 RADEON_TV_DAC_GDACPD |
1075 RADEON_TV_DAC_BDACPD |
1076 RADEON_TV_DAC_BGSLEEP);
1079 case DRM_MODE_DPMS_STANDBY:
1080 case DRM_MODE_DPMS_SUSPEND:
1081 case DRM_MODE_DPMS_OFF:
1082 if (rdev->family == CHIP_R200)
1083 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1086 tv_master_cntl &= ~RADEON_TV_ON;
1088 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1090 if (rdev->family == CHIP_R420 ||
1091 rdev->family == CHIP_R423 ||
1092 rdev->family == CHIP_RV410)
1093 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1094 R420_TV_DAC_GDACPD |
1095 R420_TV_DAC_BDACPD |
1096 RADEON_TV_DAC_BGSLEEP);
1098 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1099 RADEON_TV_DAC_GDACPD |
1100 RADEON_TV_DAC_BDACPD |
1101 RADEON_TV_DAC_BGSLEEP);
1106 if (rdev->family == CHIP_R200) {
1107 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1110 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1111 /* handled in radeon_crtc_dpms() */
1112 else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1113 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1114 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1117 if (rdev->is_atom_bios)
1118 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1120 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1124 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1126 struct radeon_device *rdev = encoder->dev->dev_private;
1128 if (rdev->is_atom_bios)
1129 radeon_atom_output_lock(encoder, true);
1131 radeon_combios_output_lock(encoder, true);
1132 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1135 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1137 struct radeon_device *rdev = encoder->dev->dev_private;
1139 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1141 if (rdev->is_atom_bios)
1142 radeon_atom_output_lock(encoder, true);
1144 radeon_combios_output_lock(encoder, true);
1147 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1148 struct drm_display_mode *mode,
1149 struct drm_display_mode *adjusted_mode)
1151 struct drm_device *dev = encoder->dev;
1152 struct radeon_device *rdev = dev->dev_private;
1153 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1155 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1156 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1157 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1160 DRM_DEBUG_KMS("\n");
1162 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1164 if (rdev->family != CHIP_R200) {
1165 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1166 if (rdev->family == CHIP_R420 ||
1167 rdev->family == CHIP_R423 ||
1168 rdev->family == CHIP_RV410) {
1169 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1170 RADEON_TV_DAC_BGADJ_MASK |
1171 R420_TV_DAC_DACADJ_MASK |
1172 R420_TV_DAC_RDACPD |
1173 R420_TV_DAC_GDACPD |
1174 R420_TV_DAC_BDACPD |
1175 R420_TV_DAC_TVENABLE);
1177 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1178 RADEON_TV_DAC_BGADJ_MASK |
1179 RADEON_TV_DAC_DACADJ_MASK |
1180 RADEON_TV_DAC_RDACPD |
1181 RADEON_TV_DAC_GDACPD |
1182 RADEON_TV_DAC_BDACPD);
1185 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1188 if (tv_dac->tv_std == TV_STD_NTSC ||
1189 tv_dac->tv_std == TV_STD_NTSC_J ||
1190 tv_dac->tv_std == TV_STD_PAL_M ||
1191 tv_dac->tv_std == TV_STD_PAL_60)
1192 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1194 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1196 if (tv_dac->tv_std == TV_STD_NTSC ||
1197 tv_dac->tv_std == TV_STD_NTSC_J)
1198 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1200 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1202 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1203 tv_dac->ps2_tvdac_adj);
1205 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1208 if (ASIC_IS_R300(rdev)) {
1209 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1210 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1211 } else if (rdev->family != CHIP_R200)
1212 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1213 else if (rdev->family == CHIP_R200)
1214 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1216 if (rdev->family >= CHIP_R200)
1217 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1222 dac_cntl = RREG32(RADEON_DAC_CNTL);
1223 dac_cntl &= ~RADEON_DAC_TVO_EN;
1224 WREG32(RADEON_DAC_CNTL, dac_cntl);
1226 if (ASIC_IS_R300(rdev))
1227 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1229 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1230 if (radeon_crtc->crtc_id == 0) {
1231 if (ASIC_IS_R300(rdev)) {
1232 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1233 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1234 RADEON_DISP_TV_SOURCE_CRTC);
1236 if (rdev->family >= CHIP_R200) {
1237 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1239 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1242 if (ASIC_IS_R300(rdev)) {
1243 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1244 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1246 if (rdev->family >= CHIP_R200) {
1247 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1249 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1252 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1255 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1257 if (radeon_crtc->crtc_id == 0) {
1258 if (ASIC_IS_R300(rdev)) {
1259 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1260 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1261 } else if (rdev->family == CHIP_R200) {
1262 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1263 RADEON_FP2_DVO_RATE_SEL_SDR);
1265 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1267 if (ASIC_IS_R300(rdev)) {
1268 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1269 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1270 } else if (rdev->family == CHIP_R200) {
1271 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1272 RADEON_FP2_DVO_RATE_SEL_SDR);
1273 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1275 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1277 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1280 if (ASIC_IS_R300(rdev)) {
1281 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1282 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1283 } else if (rdev->family != CHIP_R200)
1284 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1285 else if (rdev->family == CHIP_R200)
1286 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1288 if (rdev->family >= CHIP_R200)
1289 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1292 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1294 if (rdev->is_atom_bios)
1295 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1297 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1301 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1302 struct drm_connector *connector)
1304 struct drm_device *dev = encoder->dev;
1305 struct radeon_device *rdev = dev->dev_private;
1306 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1307 uint32_t disp_output_cntl, gpiopad_a, tmp;
1310 /* save regs needed */
1311 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1312 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1313 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1314 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1315 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1316 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1318 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1320 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1322 WREG32(RADEON_CRTC2_GEN_CNTL,
1323 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1325 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1326 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1327 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1329 WREG32(RADEON_DAC_EXT_CNTL,
1330 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1331 RADEON_DAC2_FORCE_DATA_EN |
1332 RADEON_DAC_FORCE_DATA_SEL_RGB |
1333 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1335 WREG32(RADEON_TV_DAC_CNTL,
1336 RADEON_TV_DAC_STD_NTSC |
1337 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1338 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1340 RREG32(RADEON_TV_DAC_CNTL);
1343 WREG32(RADEON_TV_DAC_CNTL,
1344 RADEON_TV_DAC_NBLANK |
1345 RADEON_TV_DAC_NHOLD |
1346 RADEON_TV_MONITOR_DETECT_EN |
1347 RADEON_TV_DAC_STD_NTSC |
1348 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1349 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1351 RREG32(RADEON_TV_DAC_CNTL);
1354 tmp = RREG32(RADEON_TV_DAC_CNTL);
1355 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1357 DRM_DEBUG_KMS("S-video TV connection detected\n");
1358 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1360 DRM_DEBUG_KMS("Composite TV connection detected\n");
1363 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1364 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1365 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1366 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1367 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1368 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1372 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1373 struct drm_connector *connector)
1375 struct drm_device *dev = encoder->dev;
1376 struct radeon_device *rdev = dev->dev_private;
1377 uint32_t tv_dac_cntl, dac_cntl2;
1378 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1381 if (ASIC_IS_R300(rdev))
1382 return r300_legacy_tv_detect(encoder, connector);
1384 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1385 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1386 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1387 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1388 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1390 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1391 WREG32(RADEON_DAC_CNTL2, tmp);
1393 tmp = tv_master_cntl | RADEON_TV_ON;
1394 tmp &= ~(RADEON_TV_ASYNC_RST |
1395 RADEON_RESTART_PHASE_FIX |
1396 RADEON_CRT_FIFO_CE_EN |
1397 RADEON_TV_FIFO_CE_EN |
1398 RADEON_RE_SYNC_NOW_SEL_MASK);
1399 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1400 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1402 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1403 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1404 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1406 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1407 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1409 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1410 WREG32(RADEON_TV_DAC_CNTL, tmp);
1412 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1413 RADEON_RED_MX_FORCE_DAC_DATA |
1414 RADEON_GRN_MX_FORCE_DAC_DATA |
1415 RADEON_BLU_MX_FORCE_DAC_DATA |
1416 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1417 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1420 tmp = RREG32(RADEON_TV_DAC_CNTL);
1421 if (tmp & RADEON_TV_DAC_GDACDET) {
1423 DRM_DEBUG_KMS("S-video TV connection detected\n");
1424 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1426 DRM_DEBUG_KMS("Composite TV connection detected\n");
1429 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1430 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1431 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1432 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1436 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1437 struct drm_connector *connector)
1439 struct drm_device *dev = encoder->dev;
1440 struct radeon_device *rdev = dev->dev_private;
1441 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1442 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1443 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1444 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1445 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1449 /* save the regs we need */
1450 gpio_monid = RREG32(RADEON_GPIO_MONID);
1451 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1452 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1453 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1454 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1455 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1456 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1457 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1458 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1459 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1460 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1461 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1462 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1463 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1465 tmp = RREG32(RADEON_GPIO_MONID);
1466 tmp &= ~RADEON_GPIO_A_0;
1467 WREG32(RADEON_GPIO_MONID, tmp);
1469 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1470 RADEON_FP2_PANEL_FORMAT |
1471 R200_FP2_SOURCE_SEL_TRANS_UNIT |
1473 R200_FP2_DVO_RATE_SEL_SDR));
1475 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1476 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1478 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1479 RADEON_CRTC2_DISP_REQ_EN_B));
1481 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1482 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1483 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1484 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1485 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1486 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1488 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1489 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1490 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1491 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1493 for (i = 0; i < 200; i++) {
1494 tmp = RREG32(RADEON_GPIO_MONID);
1495 if (tmp & RADEON_GPIO_Y_0)
1502 if (!drm_can_sleep())
1508 /* restore the regs we used */
1509 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1510 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1511 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1512 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1513 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1514 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1515 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1516 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1517 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1518 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1519 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1520 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1521 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1522 WREG32(RADEON_GPIO_MONID, gpio_monid);
1527 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1528 struct drm_connector *connector)
1530 struct drm_device *dev = encoder->dev;
1531 struct radeon_device *rdev = dev->dev_private;
1532 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1533 uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1534 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1535 enum drm_connector_status found = connector_status_disconnected;
1536 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1537 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1539 struct drm_crtc *crtc;
1541 /* find out if crtc2 is in use or if this encoder is using it */
1542 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1543 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1544 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1545 if (encoder->crtc != crtc) {
1546 return connector_status_disconnected;
1551 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1552 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1553 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1556 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1557 return connector_status_disconnected;
1559 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1560 if (tv_detect && tv_dac)
1561 found = connector_status_connected;
1565 /* don't probe if the encoder is being used for something else not CRT related */
1566 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1567 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1568 return connector_status_disconnected;
1571 /* R200 uses an external DAC for secondary DAC */
1572 if (rdev->family == CHIP_R200) {
1573 if (radeon_legacy_ext_dac_detect(encoder, connector))
1574 found = connector_status_connected;
1578 /* save the regs we need */
1579 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1581 if (rdev->flags & RADEON_SINGLE_CRTC) {
1582 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1584 if (ASIC_IS_R300(rdev)) {
1585 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1586 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1588 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1590 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1592 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1593 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1594 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1596 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1597 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1598 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1600 if (rdev->flags & RADEON_SINGLE_CRTC) {
1601 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1602 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1604 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1605 tmp |= RADEON_CRTC2_CRT2_ON |
1606 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1607 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1609 if (ASIC_IS_R300(rdev)) {
1610 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1611 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1612 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1613 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1615 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1616 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1620 tmp = RADEON_TV_DAC_NBLANK |
1621 RADEON_TV_DAC_NHOLD |
1622 RADEON_TV_MONITOR_DETECT_EN |
1623 RADEON_TV_DAC_STD_PS2;
1625 WREG32(RADEON_TV_DAC_CNTL, tmp);
1627 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1628 RADEON_DAC2_FORCE_DATA_EN;
1631 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1633 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1635 if (ASIC_IS_R300(rdev))
1636 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1638 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1640 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1642 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1643 WREG32(RADEON_DAC_CNTL2, tmp);
1647 if (ASIC_IS_R300(rdev)) {
1648 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1649 found = connector_status_connected;
1651 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1652 found = connector_status_connected;
1655 /* restore regs we used */
1656 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1657 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1658 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1660 if (rdev->flags & RADEON_SINGLE_CRTC) {
1661 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1663 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1664 if (ASIC_IS_R300(rdev)) {
1665 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1666 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1668 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1672 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1678 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1679 .dpms = radeon_legacy_tv_dac_dpms,
1680 .mode_fixup = radeon_legacy_mode_fixup,
1681 .prepare = radeon_legacy_tv_dac_prepare,
1682 .mode_set = radeon_legacy_tv_dac_mode_set,
1683 .commit = radeon_legacy_tv_dac_commit,
1684 .detect = radeon_legacy_tv_dac_detect,
1685 .disable = radeon_legacy_encoder_disable,
1689 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1690 .destroy = radeon_enc_destroy,
1694 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1696 struct drm_device *dev = encoder->base.dev;
1697 struct radeon_device *rdev = dev->dev_private;
1698 struct radeon_encoder_int_tmds *tmds = NULL;
1701 tmds = malloc(sizeof(struct radeon_encoder_int_tmds),
1702 DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
1707 if (rdev->is_atom_bios)
1708 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1710 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1713 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1718 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1720 struct drm_device *dev = encoder->base.dev;
1721 struct radeon_device *rdev = dev->dev_private;
1722 struct radeon_encoder_ext_tmds *tmds = NULL;
1725 if (rdev->is_atom_bios)
1728 tmds = malloc(sizeof(struct radeon_encoder_ext_tmds),
1729 DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
1734 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1737 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1743 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1745 struct radeon_device *rdev = dev->dev_private;
1746 struct drm_encoder *encoder;
1747 struct radeon_encoder *radeon_encoder;
1749 /* see if we already added it */
1750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1751 radeon_encoder = to_radeon_encoder(encoder);
1752 if (radeon_encoder->encoder_enum == encoder_enum) {
1753 radeon_encoder->devices |= supported_device;
1760 radeon_encoder = malloc(sizeof(struct radeon_encoder),
1761 DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
1762 if (!radeon_encoder)
1765 encoder = &radeon_encoder->base;
1766 if (rdev->flags & RADEON_SINGLE_CRTC)
1767 encoder->possible_crtcs = 0x1;
1769 encoder->possible_crtcs = 0x3;
1771 radeon_encoder->enc_priv = NULL;
1773 radeon_encoder->encoder_enum = encoder_enum;
1774 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1775 radeon_encoder->devices = supported_device;
1776 radeon_encoder->rmx_type = RMX_OFF;
1778 switch (radeon_encoder->encoder_id) {
1779 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1780 encoder->possible_crtcs = 0x1;
1781 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1782 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1783 if (rdev->is_atom_bios)
1784 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1786 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1787 radeon_encoder->rmx_type = RMX_FULL;
1789 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1790 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1791 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1792 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1794 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1795 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1796 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1797 if (rdev->is_atom_bios)
1798 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1800 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1802 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1803 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1804 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1805 if (rdev->is_atom_bios)
1806 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1808 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1810 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1811 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1812 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1813 if (!rdev->is_atom_bios)
1814 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);