1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 * 82580 Gigabit Network Connection
42 * I350 Gigabit Network Connection
45 #include "e1000_api.h"
46 #include "e1000_i210.h"
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 u32 offset, u16 *data);
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 u32 offset, u16 data);
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 u32 offset, u16 data);
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
84 u16 *speed, u16 *duplex);
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
107 static void e1000_i2c_start(struct e1000_hw *hw);
108 static void e1000_i2c_stop(struct e1000_hw *hw);
109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
117 static bool e1000_get_i2c_data(u32 *i2cctl);
119 static const u16 e1000_82580_rxpbs_table[] = {
120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
121 #define E1000_82580_RXPBS_TABLE_SIZE \
122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
127 * @hw: pointer to the HW structure
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
135 bool ext_mdio = FALSE;
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
149 reg = E1000_READ_REG(hw, E1000_MDICNFG);
150 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
159 * e1000_init_phy_params_82575 - Init PHY func ptrs.
160 * @hw: pointer to the HW structure
162 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
164 struct e1000_phy_info *phy = &hw->phy;
165 s32 ret_val = E1000_SUCCESS;
168 DEBUGFUNC("e1000_init_phy_params_82575");
170 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
173 if (hw->phy.media_type != e1000_media_type_copper) {
174 phy->type = e1000_phy_none;
178 phy->ops.power_up = e1000_power_up_phy_copper;
179 phy->ops.power_down = e1000_power_down_phy_copper_82575;
181 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
182 phy->reset_delay_us = 100;
184 phy->ops.acquire = e1000_acquire_phy_82575;
185 phy->ops.check_reset_block = e1000_check_reset_block_generic;
186 phy->ops.commit = e1000_phy_sw_reset_generic;
187 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
188 phy->ops.release = e1000_release_phy_82575;
190 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
192 if (e1000_sgmii_active_82575(hw)) {
193 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194 ctrl_ext |= E1000_CTRL_I2C_ENA;
196 phy->ops.reset = e1000_phy_hw_reset_generic;
197 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
200 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201 e1000_reset_mdicnfg_82580(hw);
203 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
207 switch (hw->mac.type) {
210 phy->ops.read_reg = e1000_read_phy_reg_82580;
211 phy->ops.write_reg = e1000_write_phy_reg_82580;
215 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
216 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
219 phy->ops.read_reg = e1000_read_phy_reg_igp;
220 phy->ops.write_reg = e1000_write_phy_reg_igp;
224 /* Set phy->phy_addr and phy->id. */
225 ret_val = e1000_get_phy_id_82575(hw);
227 /* Verify phy id and set remaining function pointers */
229 case I347AT4_E_PHY_ID:
230 case M88E1112_E_PHY_ID:
231 case M88E1340M_E_PHY_ID:
232 case M88E1111_I_PHY_ID:
233 phy->type = e1000_phy_m88;
234 phy->ops.check_polarity = e1000_check_polarity_m88;
235 phy->ops.get_info = e1000_get_phy_info_m88;
236 if (phy->id == I347AT4_E_PHY_ID ||
237 phy->id == M88E1112_E_PHY_ID ||
238 phy->id == M88E1340M_E_PHY_ID)
239 phy->ops.get_cable_length =
240 e1000_get_cable_length_m88_gen2;
242 phy->ops.get_cable_length = e1000_get_cable_length_m88;
243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
245 case IGP03E1000_E_PHY_ID:
246 case IGP04E1000_E_PHY_ID:
247 phy->type = e1000_phy_igp_3;
248 phy->ops.check_polarity = e1000_check_polarity_igp;
249 phy->ops.get_info = e1000_get_phy_info_igp;
250 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
252 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
253 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
255 case I82580_I_PHY_ID:
257 phy->type = e1000_phy_82580;
258 phy->ops.check_polarity = e1000_check_polarity_82577;
259 phy->ops.force_speed_duplex =
260 e1000_phy_force_speed_duplex_82577;
261 phy->ops.get_cable_length = e1000_get_cable_length_82577;
262 phy->ops.get_info = e1000_get_phy_info_82577;
263 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
264 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
267 phy->type = e1000_phy_i210;
268 phy->ops.check_polarity = e1000_check_polarity_m88;
269 phy->ops.get_info = e1000_get_phy_info_m88;
270 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
273 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
276 ret_val = -E1000_ERR_PHY;
285 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
286 * @hw: pointer to the HW structure
288 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
290 struct e1000_nvm_info *nvm = &hw->nvm;
291 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
294 DEBUGFUNC("e1000_init_nvm_params_82575");
296 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
297 E1000_EECD_SIZE_EX_SHIFT);
299 * Added to a constant, "size" becomes the left-shift value
300 * for setting word_size.
302 size += NVM_WORD_SIZE_BASE_SHIFT;
304 /* Just in case size is out of range, cap it to the largest
305 * EEPROM size supported
310 nvm->word_size = 1 << size;
311 if (hw->mac.type < e1000_i210) {
312 nvm->opcode_bits = 8;
315 switch (nvm->override) {
316 case e1000_nvm_override_spi_large:
318 nvm->address_bits = 16;
320 case e1000_nvm_override_spi_small:
322 nvm->address_bits = 8;
325 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
326 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
330 if (nvm->word_size == (1 << 15))
331 nvm->page_size = 128;
333 nvm->type = e1000_nvm_eeprom_spi;
335 nvm->type = e1000_nvm_flash_hw;
338 /* Function Pointers */
339 nvm->ops.acquire = e1000_acquire_nvm_82575;
340 nvm->ops.release = e1000_release_nvm_82575;
341 if (nvm->word_size < (1 << 15))
342 nvm->ops.read = e1000_read_nvm_eerd;
344 nvm->ops.read = e1000_read_nvm_spi;
346 nvm->ops.write = e1000_write_nvm_spi;
347 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
348 nvm->ops.update = e1000_update_nvm_checksum_generic;
349 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
351 /* override generic family function pointers for specific descendants */
352 switch (hw->mac.type) {
354 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
355 nvm->ops.update = e1000_update_nvm_checksum_82580;
358 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
359 nvm->ops.update = e1000_update_nvm_checksum_i350;
365 return E1000_SUCCESS;
369 * e1000_init_mac_params_82575 - Init MAC func ptrs.
370 * @hw: pointer to the HW structure
372 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
374 struct e1000_mac_info *mac = &hw->mac;
375 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
377 DEBUGFUNC("e1000_init_mac_params_82575");
379 /* Derives media type */
380 e1000_get_media_type_82575(hw);
381 /* Set mta register count */
382 mac->mta_reg_count = 128;
383 /* Set uta register count */
384 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
385 /* Set rar entry count */
386 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
387 if (mac->type == e1000_82576)
388 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
389 if (mac->type == e1000_82580)
390 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
391 if (mac->type == e1000_i350)
392 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
394 /* Enable EEE default settings for EEE supported devices */
395 if (mac->type >= e1000_i350)
396 dev_spec->eee_disable = FALSE;
398 /* Allow a single clear of the SW semaphore on I210 and newer */
399 if (mac->type >= e1000_i210)
400 dev_spec->clear_semaphore_once = TRUE;
402 /* Set if part includes ASF firmware */
403 mac->asf_firmware_present = TRUE;
405 mac->has_fwsm = TRUE;
406 /* ARC supported; valid only if manageability features are enabled. */
407 mac->arc_subsystem_valid =
408 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
410 /* Function pointers */
412 /* bus type/speed/width */
413 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
415 if (mac->type >= e1000_82580)
416 mac->ops.reset_hw = e1000_reset_hw_82580;
418 mac->ops.reset_hw = e1000_reset_hw_82575;
419 /* hw initialization */
420 mac->ops.init_hw = e1000_init_hw_82575;
422 mac->ops.setup_link = e1000_setup_link_generic;
423 /* physical interface link setup */
424 mac->ops.setup_physical_interface =
425 (hw->phy.media_type == e1000_media_type_copper)
426 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
427 /* physical interface shutdown */
428 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
429 /* physical interface power up */
430 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
432 mac->ops.check_for_link = e1000_check_for_link_82575;
433 /* read mac address */
434 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
435 /* configure collision distance */
436 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
437 /* multicast address update */
438 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
439 if (mac->type == e1000_i350) {
441 mac->ops.write_vfta = e1000_write_vfta_i350;
443 mac->ops.clear_vfta = e1000_clear_vfta_i350;
446 mac->ops.write_vfta = e1000_write_vfta_generic;
448 mac->ops.clear_vfta = e1000_clear_vfta_generic;
450 if (hw->mac.type >= e1000_82580)
451 mac->ops.validate_mdi_setting =
452 e1000_validate_mdi_setting_crossover_generic;
454 mac->ops.id_led_init = e1000_id_led_init_generic;
456 mac->ops.blink_led = e1000_blink_led_generic;
458 mac->ops.setup_led = e1000_setup_led_generic;
460 mac->ops.cleanup_led = e1000_cleanup_led_generic;
461 /* turn on/off LED */
462 mac->ops.led_on = e1000_led_on_generic;
463 mac->ops.led_off = e1000_led_off_generic;
464 /* clear hardware counters */
465 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
467 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
468 /* acquire SW_FW sync */
469 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
470 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
471 if (mac->type >= e1000_i210) {
472 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
473 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
476 /* set lan id for port to determine which phy lock to use */
477 hw->mac.ops.set_lan_id(hw);
479 return E1000_SUCCESS;
483 * e1000_init_function_pointers_82575 - Init func ptrs.
484 * @hw: pointer to the HW structure
486 * Called to initialize all function pointers and parameters.
488 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
490 DEBUGFUNC("e1000_init_function_pointers_82575");
492 hw->mac.ops.init_params = e1000_init_mac_params_82575;
493 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
494 hw->phy.ops.init_params = e1000_init_phy_params_82575;
495 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
499 * e1000_acquire_phy_82575 - Acquire rights to access PHY
500 * @hw: pointer to the HW structure
502 * Acquire access rights to the correct PHY.
504 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
506 u16 mask = E1000_SWFW_PHY0_SM;
508 DEBUGFUNC("e1000_acquire_phy_82575");
510 if (hw->bus.func == E1000_FUNC_1)
511 mask = E1000_SWFW_PHY1_SM;
512 else if (hw->bus.func == E1000_FUNC_2)
513 mask = E1000_SWFW_PHY2_SM;
514 else if (hw->bus.func == E1000_FUNC_3)
515 mask = E1000_SWFW_PHY3_SM;
517 return hw->mac.ops.acquire_swfw_sync(hw, mask);
521 * e1000_release_phy_82575 - Release rights to access PHY
522 * @hw: pointer to the HW structure
524 * A wrapper to release access rights to the correct PHY.
526 static void e1000_release_phy_82575(struct e1000_hw *hw)
528 u16 mask = E1000_SWFW_PHY0_SM;
530 DEBUGFUNC("e1000_release_phy_82575");
532 if (hw->bus.func == E1000_FUNC_1)
533 mask = E1000_SWFW_PHY1_SM;
534 else if (hw->bus.func == E1000_FUNC_2)
535 mask = E1000_SWFW_PHY2_SM;
536 else if (hw->bus.func == E1000_FUNC_3)
537 mask = E1000_SWFW_PHY3_SM;
539 hw->mac.ops.release_swfw_sync(hw, mask);
543 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
544 * @hw: pointer to the HW structure
545 * @offset: register offset to be read
546 * @data: pointer to the read data
548 * Reads the PHY register at offset using the serial gigabit media independent
549 * interface and stores the retrieved information in data.
551 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
554 s32 ret_val = -E1000_ERR_PARAM;
556 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
558 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
559 DEBUGOUT1("PHY Address %u is out of range\n", offset);
563 ret_val = hw->phy.ops.acquire(hw);
567 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
569 hw->phy.ops.release(hw);
576 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
577 * @hw: pointer to the HW structure
578 * @offset: register offset to write to
579 * @data: data to write at register offset
581 * Writes the data to PHY register at the offset using the serial gigabit
582 * media independent interface.
584 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
587 s32 ret_val = -E1000_ERR_PARAM;
589 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
591 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
592 DEBUGOUT1("PHY Address %d is out of range\n", offset);
596 ret_val = hw->phy.ops.acquire(hw);
600 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
602 hw->phy.ops.release(hw);
609 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
610 * @hw: pointer to the HW structure
612 * Retrieves the PHY address and ID for both PHY's which do and do not use
615 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
617 struct e1000_phy_info *phy = &hw->phy;
618 s32 ret_val = E1000_SUCCESS;
623 DEBUGFUNC("e1000_get_phy_id_82575");
626 * For SGMII PHYs, we try the list of possible addresses until
627 * we find one that works. For non-SGMII PHYs
628 * (e.g. integrated copper PHYs), an address of 1 should
629 * work. The result of this function should mean phy->phy_addr
630 * and phy->id are set correctly.
632 if (!e1000_sgmii_active_82575(hw)) {
634 ret_val = e1000_get_phy_id(hw);
638 if (e1000_sgmii_uses_mdio_82575(hw)) {
639 switch (hw->mac.type) {
642 mdic = E1000_READ_REG(hw, E1000_MDIC);
643 mdic &= E1000_MDIC_PHY_MASK;
644 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
650 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
651 mdic &= E1000_MDICNFG_PHY_MASK;
652 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
655 ret_val = -E1000_ERR_PHY;
659 ret_val = e1000_get_phy_id(hw);
663 /* Power on sgmii phy if it is disabled */
664 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
665 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
666 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
667 E1000_WRITE_FLUSH(hw);
671 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
672 * Therefore, we need to test 1-7
674 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
675 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
676 if (ret_val == E1000_SUCCESS) {
677 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
680 * At the time of this writing, The M88 part is
681 * the only supported SGMII PHY product.
683 if (phy_id == M88_VENDOR)
686 DEBUGOUT1("PHY address %u was unreadable\n",
691 /* A valid PHY type couldn't be found. */
692 if (phy->addr == 8) {
694 ret_val = -E1000_ERR_PHY;
696 ret_val = e1000_get_phy_id(hw);
699 /* restore previous sfp cage power state */
700 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
707 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
708 * @hw: pointer to the HW structure
710 * Resets the PHY using the serial gigabit media independent interface.
712 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
714 s32 ret_val = E1000_SUCCESS;
716 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
719 * This isn't a TRUE "hard" reset, but is the only reset
720 * available to us at this time.
723 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
725 if (!(hw->phy.ops.write_reg))
729 * SFP documentation requires the following to configure the SPF module
730 * to work on SGMII. No further documentation is given.
732 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
736 ret_val = hw->phy.ops.commit(hw);
743 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
744 * @hw: pointer to the HW structure
745 * @active: TRUE to enable LPLU, FALSE to disable
747 * Sets the LPLU D0 state according to the active flag. When
748 * activating LPLU this function also disables smart speed
749 * and vice versa. LPLU will not be activated unless the
750 * device autonegotiation advertisement meets standards of
751 * either 10 or 10/100 or 10/100/1000 at all duplexes.
752 * This is a function pointer entry point only called by
753 * PHY setup routines.
755 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
757 struct e1000_phy_info *phy = &hw->phy;
758 s32 ret_val = E1000_SUCCESS;
761 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
763 if (!(hw->phy.ops.read_reg))
766 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
771 data |= IGP02E1000_PM_D0_LPLU;
772 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
777 /* When LPLU is enabled, we should disable SmartSpeed */
778 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
780 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
786 data &= ~IGP02E1000_PM_D0_LPLU;
787 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
790 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
791 * during Dx states where the power conservation is most
792 * important. During driver activity we should enable
793 * SmartSpeed, so performance is maintained.
795 if (phy->smart_speed == e1000_smart_speed_on) {
796 ret_val = phy->ops.read_reg(hw,
797 IGP01E1000_PHY_PORT_CONFIG,
802 data |= IGP01E1000_PSCFR_SMART_SPEED;
803 ret_val = phy->ops.write_reg(hw,
804 IGP01E1000_PHY_PORT_CONFIG,
808 } else if (phy->smart_speed == e1000_smart_speed_off) {
809 ret_val = phy->ops.read_reg(hw,
810 IGP01E1000_PHY_PORT_CONFIG,
815 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
816 ret_val = phy->ops.write_reg(hw,
817 IGP01E1000_PHY_PORT_CONFIG,
829 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
830 * @hw: pointer to the HW structure
831 * @active: TRUE to enable LPLU, FALSE to disable
833 * Sets the LPLU D0 state according to the active flag. When
834 * activating LPLU this function also disables smart speed
835 * and vice versa. LPLU will not be activated unless the
836 * device autonegotiation advertisement meets standards of
837 * either 10 or 10/100 or 10/100/1000 at all duplexes.
838 * This is a function pointer entry point only called by
839 * PHY setup routines.
841 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
843 struct e1000_phy_info *phy = &hw->phy;
844 s32 ret_val = E1000_SUCCESS;
847 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
849 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
852 data |= E1000_82580_PM_D0_LPLU;
854 /* When LPLU is enabled, we should disable SmartSpeed */
855 data &= ~E1000_82580_PM_SPD;
857 data &= ~E1000_82580_PM_D0_LPLU;
860 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
861 * during Dx states where the power conservation is most
862 * important. During driver activity we should enable
863 * SmartSpeed, so performance is maintained.
865 if (phy->smart_speed == e1000_smart_speed_on)
866 data |= E1000_82580_PM_SPD;
867 else if (phy->smart_speed == e1000_smart_speed_off)
868 data &= ~E1000_82580_PM_SPD;
871 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
876 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
877 * @hw: pointer to the HW structure
878 * @active: boolean used to enable/disable lplu
880 * Success returns 0, Failure returns 1
882 * The low power link up (lplu) state is set to the power management level D3
883 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
884 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
885 * is used during Dx states where the power conservation is most important.
886 * During driver activity, SmartSpeed should be enabled so performance is
889 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
891 struct e1000_phy_info *phy = &hw->phy;
892 s32 ret_val = E1000_SUCCESS;
895 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
897 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
900 data &= ~E1000_82580_PM_D3_LPLU;
902 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
903 * during Dx states where the power conservation is most
904 * important. During driver activity we should enable
905 * SmartSpeed, so performance is maintained.
907 if (phy->smart_speed == e1000_smart_speed_on)
908 data |= E1000_82580_PM_SPD;
909 else if (phy->smart_speed == e1000_smart_speed_off)
910 data &= ~E1000_82580_PM_SPD;
911 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
912 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
913 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
914 data |= E1000_82580_PM_D3_LPLU;
915 /* When LPLU is enabled, we should disable SmartSpeed */
916 data &= ~E1000_82580_PM_SPD;
919 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
924 * e1000_acquire_nvm_82575 - Request for access to EEPROM
925 * @hw: pointer to the HW structure
927 * Acquire the necessary semaphores for exclusive access to the EEPROM.
928 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
929 * Return successful if access grant bit set, else clear the request for
930 * EEPROM access and return -E1000_ERR_NVM (-1).
932 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
936 DEBUGFUNC("e1000_acquire_nvm_82575");
938 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
943 * Check if there is some access
944 * error this access may hook on
946 if (hw->mac.type == e1000_i350) {
947 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
948 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
949 E1000_EECD_TIMEOUT)) {
950 /* Clear all access error flags */
951 E1000_WRITE_REG(hw, E1000_EECD, eecd |
952 E1000_EECD_ERROR_CLR);
953 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
956 if (hw->mac.type == e1000_82580) {
957 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
958 if (eecd & E1000_EECD_BLOCKED) {
959 /* Clear access error flag */
960 E1000_WRITE_REG(hw, E1000_EECD, eecd |
962 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
967 ret_val = e1000_acquire_nvm_generic(hw);
969 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
976 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
977 * @hw: pointer to the HW structure
979 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
980 * then release the semaphores acquired.
982 static void e1000_release_nvm_82575(struct e1000_hw *hw)
984 DEBUGFUNC("e1000_release_nvm_82575");
986 e1000_release_nvm_generic(hw);
988 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
992 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
993 * @hw: pointer to the HW structure
994 * @mask: specifies which semaphore to acquire
996 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
997 * will also specify which port we're acquiring the lock for.
999 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1003 u32 fwmask = mask << 16;
1004 s32 ret_val = E1000_SUCCESS;
1005 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1007 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1009 while (i < timeout) {
1010 if (e1000_get_hw_semaphore_generic(hw)) {
1011 ret_val = -E1000_ERR_SWFW_SYNC;
1015 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1016 if (!(swfw_sync & (fwmask | swmask)))
1020 * Firmware currently using resource (fwmask)
1021 * or other software thread using resource (swmask)
1023 e1000_put_hw_semaphore_generic(hw);
1029 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1030 ret_val = -E1000_ERR_SWFW_SYNC;
1034 swfw_sync |= swmask;
1035 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1037 e1000_put_hw_semaphore_generic(hw);
1044 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1045 * @hw: pointer to the HW structure
1046 * @mask: specifies which semaphore to acquire
1048 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1049 * will also specify which port we're releasing the lock for.
1051 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1055 DEBUGFUNC("e1000_release_swfw_sync_82575");
1057 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1060 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1062 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1064 e1000_put_hw_semaphore_generic(hw);
1068 * e1000_get_cfg_done_82575 - Read config done bit
1069 * @hw: pointer to the HW structure
1071 * Read the management control register for the config done bit for
1072 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1073 * to read the config done bit, so an error is *ONLY* logged and returns
1074 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1075 * would not be able to be reset or change link.
1077 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1079 s32 timeout = PHY_CFG_TIMEOUT;
1080 s32 ret_val = E1000_SUCCESS;
1081 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1083 DEBUGFUNC("e1000_get_cfg_done_82575");
1085 if (hw->bus.func == E1000_FUNC_1)
1086 mask = E1000_NVM_CFG_DONE_PORT_1;
1087 else if (hw->bus.func == E1000_FUNC_2)
1088 mask = E1000_NVM_CFG_DONE_PORT_2;
1089 else if (hw->bus.func == E1000_FUNC_3)
1090 mask = E1000_NVM_CFG_DONE_PORT_3;
1092 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1098 DEBUGOUT("MNG configuration cycle has not completed.\n");
1100 /* If EEPROM is not marked present, init the PHY manually */
1101 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1102 (hw->phy.type == e1000_phy_igp_3))
1103 e1000_phy_init_script_igp3(hw);
1109 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1110 * @hw: pointer to the HW structure
1111 * @speed: stores the current speed
1112 * @duplex: stores the current duplex
1114 * This is a wrapper function, if using the serial gigabit media independent
1115 * interface, use PCS to retrieve the link speed and duplex information.
1116 * Otherwise, use the generic function to get the link speed and duplex info.
1118 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1123 DEBUGFUNC("e1000_get_link_up_info_82575");
1125 if (hw->phy.media_type != e1000_media_type_copper)
1126 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1129 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1136 * e1000_check_for_link_82575 - Check for link
1137 * @hw: pointer to the HW structure
1139 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1140 * use the generic interface for determining link.
1142 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1147 DEBUGFUNC("e1000_check_for_link_82575");
1149 if (hw->phy.media_type != e1000_media_type_copper) {
1150 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1153 * Use this flag to determine if link needs to be checked or
1154 * not. If we have link clear the flag so that we do not
1155 * continue to check for link.
1157 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1160 * Configure Flow Control now that Auto-Neg has completed.
1161 * First, we need to restore the desired flow control
1162 * settings because we may have had to re-autoneg with a
1163 * different link partner.
1165 ret_val = e1000_config_fc_after_link_up_generic(hw);
1167 DEBUGOUT("Error configuring flow control\n");
1169 ret_val = e1000_check_for_copper_link_generic(hw);
1176 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1177 * @hw: pointer to the HW structure
1179 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1183 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1185 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1186 !e1000_sgmii_active_82575(hw))
1189 /* Enable PCS to turn on link */
1190 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1191 reg |= E1000_PCS_CFG_PCS_EN;
1192 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1194 /* Power up the laser */
1195 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1196 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1197 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1199 /* flush the write to verify completion */
1200 E1000_WRITE_FLUSH(hw);
1205 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1206 * @hw: pointer to the HW structure
1207 * @speed: stores the current speed
1208 * @duplex: stores the current duplex
1210 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1211 * duplex, then store the values in the pointers provided.
1213 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1214 u16 *speed, u16 *duplex)
1216 struct e1000_mac_info *mac = &hw->mac;
1219 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1222 * Read the PCS Status register for link state. For non-copper mode,
1223 * the status register is not accurate. The PCS status register is
1226 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1229 * The link up bit determines when link is up on autoneg.
1231 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1232 mac->serdes_has_link = TRUE;
1234 /* Detect and store PCS speed */
1235 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1236 *speed = SPEED_1000;
1237 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1242 /* Detect and store PCS duplex */
1243 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1244 *duplex = FULL_DUPLEX;
1246 *duplex = HALF_DUPLEX;
1249 mac->serdes_has_link = FALSE;
1254 return E1000_SUCCESS;
1258 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1259 * @hw: pointer to the HW structure
1261 * In the case of serdes shut down sfp and PCS on driver unload
1262 * when management pass thru is not enabled.
1264 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1268 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1271 !e1000_sgmii_active_82575(hw))
1274 if (!e1000_enable_mng_pass_thru(hw)) {
1275 /* Disable PCS to turn off link */
1276 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1277 reg &= ~E1000_PCS_CFG_PCS_EN;
1278 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1280 /* shutdown the laser */
1281 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1282 reg |= E1000_CTRL_EXT_SDP3_DATA;
1283 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1285 /* flush the write to verify completion */
1286 E1000_WRITE_FLUSH(hw);
1294 * e1000_reset_hw_82575 - Reset hardware
1295 * @hw: pointer to the HW structure
1297 * This resets the hardware into a known state.
1299 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1304 DEBUGFUNC("e1000_reset_hw_82575");
1307 * Prevent the PCI-E bus from sticking if there is no TLP connection
1308 * on the last TLP read/write transaction when MAC is reset.
1310 ret_val = e1000_disable_pcie_master_generic(hw);
1312 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1314 /* set the completion timeout for interface */
1315 ret_val = e1000_set_pcie_completion_timeout(hw);
1317 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1319 DEBUGOUT("Masking off all interrupts\n");
1320 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1322 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1323 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1324 E1000_WRITE_FLUSH(hw);
1328 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1330 DEBUGOUT("Issuing a global reset to MAC\n");
1331 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1333 ret_val = e1000_get_auto_rd_done_generic(hw);
1336 * When auto config read does not complete, do not
1337 * return with an error. This can happen in situations
1338 * where there is no eeprom and prevents getting link.
1340 DEBUGOUT("Auto Read Done did not complete\n");
1343 /* If EEPROM is not present, run manual init scripts */
1344 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1345 e1000_reset_init_script_82575(hw);
1347 /* Clear any pending interrupt events. */
1348 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1349 E1000_READ_REG(hw, E1000_ICR);
1351 /* Install any alternate MAC address into RAR0 */
1352 ret_val = e1000_check_alt_mac_addr_generic(hw);
1358 * e1000_init_hw_82575 - Initialize hardware
1359 * @hw: pointer to the HW structure
1361 * This inits the hardware readying it for operation.
1363 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1365 struct e1000_mac_info *mac = &hw->mac;
1367 u16 i, rar_count = mac->rar_entry_count;
1369 DEBUGFUNC("e1000_init_hw_82575");
1371 /* Initialize identification LED */
1372 ret_val = mac->ops.id_led_init(hw);
1374 DEBUGOUT("Error initializing identification LED\n");
1375 /* This is not fatal and we should not stop init due to this */
1378 /* Disabling VLAN filtering */
1379 DEBUGOUT("Initializing the IEEE VLAN\n");
1380 mac->ops.clear_vfta(hw);
1382 /* Setup the receive address */
1383 e1000_init_rx_addrs_generic(hw, rar_count);
1385 /* Zero out the Multicast HASH table */
1386 DEBUGOUT("Zeroing the MTA\n");
1387 for (i = 0; i < mac->mta_reg_count; i++)
1388 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1390 /* Zero out the Unicast HASH table */
1391 DEBUGOUT("Zeroing the UTA\n");
1392 for (i = 0; i < mac->uta_reg_count; i++)
1393 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1395 /* Setup link and flow control */
1396 ret_val = mac->ops.setup_link(hw);
1398 /* Set the default MTU size */
1399 hw->dev_spec._82575.mtu = 1500;
1402 * Clear all of the statistics registers (clear on read). It is
1403 * important that we do this after we have tried to establish link
1404 * because the symbol error count will increment wildly if there
1407 e1000_clear_hw_cntrs_82575(hw);
1413 * e1000_setup_copper_link_82575 - Configure copper link settings
1414 * @hw: pointer to the HW structure
1416 * Configures the link for auto-neg or forced speed and duplex. Then we check
1417 * for link, once link is established calls to configure collision distance
1418 * and flow control are called.
1420 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1426 DEBUGFUNC("e1000_setup_copper_link_82575");
1428 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1429 ctrl |= E1000_CTRL_SLU;
1430 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1431 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1433 /* Clear Go Link Disconnect bit */
1434 if (hw->mac.type >= e1000_82580) {
1435 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1436 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1437 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1440 ret_val = e1000_setup_serdes_link_82575(hw);
1444 if (e1000_sgmii_active_82575(hw)) {
1445 /* allow time for SFP cage time to power up phy */
1448 ret_val = hw->phy.ops.reset(hw);
1450 DEBUGOUT("Error resetting the PHY.\n");
1454 switch (hw->phy.type) {
1455 case e1000_phy_i210:
1457 switch (hw->phy.id) {
1458 case I347AT4_E_PHY_ID:
1459 case M88E1112_E_PHY_ID:
1460 case M88E1340M_E_PHY_ID:
1462 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1465 ret_val = e1000_copper_link_setup_m88(hw);
1469 case e1000_phy_igp_3:
1470 ret_val = e1000_copper_link_setup_igp(hw);
1472 case e1000_phy_82580:
1473 ret_val = e1000_copper_link_setup_82577(hw);
1476 ret_val = -E1000_ERR_PHY;
1483 ret_val = e1000_setup_copper_link_generic(hw);
1489 * e1000_setup_serdes_link_82575 - Setup link for serdes
1490 * @hw: pointer to the HW structure
1492 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1493 * used on copper connections where the serialized gigabit media independent
1494 * interface (sgmii), or serdes fiber is being used. Configures the link
1495 * for auto-negotiation or forces speed/duplex.
1497 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1499 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1501 s32 ret_val = E1000_SUCCESS;
1504 DEBUGFUNC("e1000_setup_serdes_link_82575");
1506 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1507 !e1000_sgmii_active_82575(hw))
1511 * On the 82575, SerDes loopback mode persists until it is
1512 * explicitly turned off or a power cycle is performed. A read to
1513 * the register does not indicate its status. Therefore, we ensure
1514 * loopback mode is disabled during initialization.
1516 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1518 /* power on the sfp cage if present */
1519 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1520 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1521 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1523 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1524 ctrl_reg |= E1000_CTRL_SLU;
1526 /* set both sw defined pins on 82575/82576*/
1527 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1528 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1530 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1532 /* default pcs_autoneg to the same setting as mac autoneg */
1533 pcs_autoneg = hw->mac.autoneg;
1535 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1536 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1537 /* sgmii mode lets the phy handle forcing speed/duplex */
1539 /* autoneg time out should be disabled for SGMII mode */
1540 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1542 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1543 /* disable PCS autoneg and support parallel detect only */
1544 pcs_autoneg = FALSE;
1545 /* fall through to default case */
1547 if (hw->mac.type == e1000_82575 ||
1548 hw->mac.type == e1000_82576) {
1549 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1551 DEBUGOUT("NVM Read Error\n");
1555 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1556 pcs_autoneg = FALSE;
1560 * non-SGMII modes only supports a speed of 1000/Full for the
1561 * link so it is best to just force the MAC and let the pcs
1562 * link either autoneg or be forced to 1000/Full
1564 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1565 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1567 /* set speed of 1000/Full if speed/duplex is forced */
1568 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1572 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1575 * New SerDes mode allows for forcing speed or autonegotiating speed
1576 * at 1gb. Autoneg should be default set by most drivers. This is the
1577 * mode that will be compatible with older link partners and switches.
1578 * However, both are supported by the hardware and some drivers/tools.
1580 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1581 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1584 /* Set PCS register for autoneg */
1585 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1586 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1588 /* Disable force flow control for autoneg */
1589 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1591 /* Configure flow control advertisement for autoneg */
1592 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1593 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1595 switch (hw->fc.requested_mode) {
1597 case e1000_fc_rx_pause:
1598 anadv_reg |= E1000_TXCW_ASM_DIR;
1599 anadv_reg |= E1000_TXCW_PAUSE;
1601 case e1000_fc_tx_pause:
1602 anadv_reg |= E1000_TXCW_ASM_DIR;
1608 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1610 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1612 /* Set PCS register for forced link */
1613 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1615 /* Force flow control for forced link */
1616 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1618 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1621 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1623 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1624 e1000_force_mac_fc_generic(hw);
1630 * e1000_get_media_type_82575 - derives current media type.
1631 * @hw: pointer to the HW structure
1633 * The media type is chosen reflecting few settings.
1634 * The following are taken into account:
1635 * - link mode set in the current port Init Control Word #3
1636 * - current link mode settings in CSR register
1637 * - MDIO vs. I2C PHY control interface chosen
1638 * - SFP module media type
1640 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1642 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1643 s32 ret_val = E1000_SUCCESS;
1647 /* Set internal phy as default */
1648 dev_spec->sgmii_active = FALSE;
1649 dev_spec->module_plugged = FALSE;
1651 /* Get CSR setting */
1652 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1654 /* extract link mode setting */
1655 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1657 switch (link_mode) {
1658 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1659 hw->phy.media_type = e1000_media_type_internal_serdes;
1661 case E1000_CTRL_EXT_LINK_MODE_GMII:
1662 hw->phy.media_type = e1000_media_type_copper;
1664 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1665 /* Get phy control interface type set (MDIO vs. I2C)*/
1666 if (e1000_sgmii_uses_mdio_82575(hw)) {
1667 hw->phy.media_type = e1000_media_type_copper;
1668 dev_spec->sgmii_active = TRUE;
1671 /* fall through for I2C based SGMII */
1672 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1673 /* read media type from SFP EEPROM */
1674 ret_val = e1000_set_sfp_media_type_82575(hw);
1675 if ((ret_val != E1000_SUCCESS) ||
1676 (hw->phy.media_type == e1000_media_type_unknown)) {
1678 * If media type was not identified then return media
1679 * type defined by the CTRL_EXT settings.
1681 hw->phy.media_type = e1000_media_type_internal_serdes;
1683 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1684 hw->phy.media_type = e1000_media_type_copper;
1685 dev_spec->sgmii_active = TRUE;
1691 /* do not change link mode for 100BaseFX */
1692 if (dev_spec->eth_flags.e100_base_fx)
1695 /* change current link mode setting */
1696 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1698 if (hw->phy.media_type == e1000_media_type_copper)
1699 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1701 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1712 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1713 * @hw: pointer to the HW structure
1715 * The media type is chosen based on SFP module.
1716 * compatibility flags retrieved from SFP ID EEPROM.
1718 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1720 s32 ret_val = E1000_ERR_CONFIG;
1722 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1723 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1724 u8 tranceiver_type = 0;
1727 /* Turn I2C interface ON and power on sfp cage */
1728 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1729 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1730 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1732 E1000_WRITE_FLUSH(hw);
1734 /* Read SFP module data */
1736 ret_val = e1000_read_sfp_data_byte(hw,
1737 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1739 if (ret_val == E1000_SUCCESS)
1744 if (ret_val != E1000_SUCCESS)
1747 ret_val = e1000_read_sfp_data_byte(hw,
1748 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1750 if (ret_val != E1000_SUCCESS)
1753 /* Check if there is some SFP module plugged and powered */
1754 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1755 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1756 dev_spec->module_plugged = TRUE;
1757 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1758 hw->phy.media_type = e1000_media_type_internal_serdes;
1759 } else if (eth_flags->e100_base_fx) {
1760 dev_spec->sgmii_active = TRUE;
1761 hw->phy.media_type = e1000_media_type_internal_serdes;
1762 } else if (eth_flags->e1000_base_t) {
1763 dev_spec->sgmii_active = TRUE;
1764 hw->phy.media_type = e1000_media_type_copper;
1766 hw->phy.media_type = e1000_media_type_unknown;
1767 DEBUGOUT("PHY module has not been recognized\n");
1771 hw->phy.media_type = e1000_media_type_unknown;
1773 ret_val = E1000_SUCCESS;
1775 /* Restore I2C interface setting */
1776 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1781 * e1000_valid_led_default_82575 - Verify a valid default LED config
1782 * @hw: pointer to the HW structure
1783 * @data: pointer to the NVM (EEPROM)
1785 * Read the EEPROM for the current default LED configuration. If the
1786 * LED configuration is not valid, set to a valid LED configuration.
1788 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1792 DEBUGFUNC("e1000_valid_led_default_82575");
1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1796 DEBUGOUT("NVM Read Error\n");
1800 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1801 switch (hw->phy.media_type) {
1802 case e1000_media_type_internal_serdes:
1803 *data = ID_LED_DEFAULT_82575_SERDES;
1805 case e1000_media_type_copper:
1807 *data = ID_LED_DEFAULT;
1816 * e1000_sgmii_active_82575 - Return sgmii state
1817 * @hw: pointer to the HW structure
1819 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1820 * which can be enabled for use in the embedded applications. Simply
1821 * return the current state of the sgmii interface.
1823 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1826 return dev_spec->sgmii_active;
1830 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1831 * @hw: pointer to the HW structure
1833 * Inits recommended HW defaults after a reset when there is no EEPROM
1834 * detected. This is only for the 82575.
1836 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1838 DEBUGFUNC("e1000_reset_init_script_82575");
1840 if (hw->mac.type == e1000_82575) {
1841 DEBUGOUT("Running reset init script for 82575\n");
1842 /* SerDes configuration via SERDESCTRL */
1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1845 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1846 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1848 /* CCM configuration via CCMCTL register */
1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1850 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1852 /* PCIe lanes configuration */
1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1855 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1856 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1858 /* PCIe PLL Configuration */
1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1861 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1864 return E1000_SUCCESS;
1868 * e1000_read_mac_addr_82575 - Read device MAC address
1869 * @hw: pointer to the HW structure
1871 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1873 s32 ret_val = E1000_SUCCESS;
1875 DEBUGFUNC("e1000_read_mac_addr_82575");
1878 * If there's an alternate MAC address place it in RAR0
1879 * so that it will override the Si installed default perm
1882 ret_val = e1000_check_alt_mac_addr_generic(hw);
1886 ret_val = e1000_read_mac_addr_generic(hw);
1893 * e1000_config_collision_dist_82575 - Configure collision distance
1894 * @hw: pointer to the HW structure
1896 * Configures the collision distance to the default value and is used
1897 * during link setup.
1899 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1903 DEBUGFUNC("e1000_config_collision_dist_82575");
1905 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1907 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1908 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1910 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1911 E1000_WRITE_FLUSH(hw);
1915 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1916 * @hw: pointer to the HW structure
1918 * In the case of a PHY power down to save power, or to turn off link during a
1919 * driver unload, or wake on lan is not enabled, remove the link.
1921 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1923 struct e1000_phy_info *phy = &hw->phy;
1925 if (!(phy->ops.check_reset_block))
1928 /* If the management interface is not enabled, then power down */
1929 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1930 e1000_power_down_phy_copper(hw);
1936 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1937 * @hw: pointer to the HW structure
1939 * Clears the hardware counters by reading the counter registers.
1941 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1943 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1945 e1000_clear_hw_cntrs_base_generic(hw);
1947 E1000_READ_REG(hw, E1000_PRC64);
1948 E1000_READ_REG(hw, E1000_PRC127);
1949 E1000_READ_REG(hw, E1000_PRC255);
1950 E1000_READ_REG(hw, E1000_PRC511);
1951 E1000_READ_REG(hw, E1000_PRC1023);
1952 E1000_READ_REG(hw, E1000_PRC1522);
1953 E1000_READ_REG(hw, E1000_PTC64);
1954 E1000_READ_REG(hw, E1000_PTC127);
1955 E1000_READ_REG(hw, E1000_PTC255);
1956 E1000_READ_REG(hw, E1000_PTC511);
1957 E1000_READ_REG(hw, E1000_PTC1023);
1958 E1000_READ_REG(hw, E1000_PTC1522);
1960 E1000_READ_REG(hw, E1000_ALGNERRC);
1961 E1000_READ_REG(hw, E1000_RXERRC);
1962 E1000_READ_REG(hw, E1000_TNCRS);
1963 E1000_READ_REG(hw, E1000_CEXTERR);
1964 E1000_READ_REG(hw, E1000_TSCTC);
1965 E1000_READ_REG(hw, E1000_TSCTFC);
1967 E1000_READ_REG(hw, E1000_MGTPRC);
1968 E1000_READ_REG(hw, E1000_MGTPDC);
1969 E1000_READ_REG(hw, E1000_MGTPTC);
1971 E1000_READ_REG(hw, E1000_IAC);
1972 E1000_READ_REG(hw, E1000_ICRXOC);
1974 E1000_READ_REG(hw, E1000_ICRXPTC);
1975 E1000_READ_REG(hw, E1000_ICRXATC);
1976 E1000_READ_REG(hw, E1000_ICTXPTC);
1977 E1000_READ_REG(hw, E1000_ICTXATC);
1978 E1000_READ_REG(hw, E1000_ICTXQEC);
1979 E1000_READ_REG(hw, E1000_ICTXQMTC);
1980 E1000_READ_REG(hw, E1000_ICRXDMTC);
1982 E1000_READ_REG(hw, E1000_CBTMPC);
1983 E1000_READ_REG(hw, E1000_HTDPMC);
1984 E1000_READ_REG(hw, E1000_CBRMPC);
1985 E1000_READ_REG(hw, E1000_RPTHC);
1986 E1000_READ_REG(hw, E1000_HGPTC);
1987 E1000_READ_REG(hw, E1000_HTCBDPC);
1988 E1000_READ_REG(hw, E1000_HGORCL);
1989 E1000_READ_REG(hw, E1000_HGORCH);
1990 E1000_READ_REG(hw, E1000_HGOTCL);
1991 E1000_READ_REG(hw, E1000_HGOTCH);
1992 E1000_READ_REG(hw, E1000_LENERRS);
1994 /* This register should not be read in copper configurations */
1995 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1996 e1000_sgmii_active_82575(hw))
1997 E1000_READ_REG(hw, E1000_SCVPC);
2001 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2002 * @hw: pointer to the HW structure
2004 * After rx enable if managability is enabled then there is likely some
2005 * bad data at the start of the fifo and possibly in the DMA fifo. This
2006 * function clears the fifos and flushes any packets that came in as rx was
2009 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2011 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2014 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2015 if (hw->mac.type != e1000_82575 ||
2016 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2019 /* Disable all Rx queues */
2020 for (i = 0; i < 4; i++) {
2021 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2022 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2023 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2025 /* Poll all queues to verify they have shut down */
2026 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2029 for (i = 0; i < 4; i++)
2030 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2031 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2036 DEBUGOUT("Queue disable timed out after 10ms\n");
2038 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2039 * incoming packets are rejected. Set enable and wait 2ms so that
2040 * any packet that was coming in as RCTL.EN was set is flushed
2042 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2043 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2045 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2046 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2048 rctl = E1000_READ_REG(hw, E1000_RCTL);
2049 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2050 temp_rctl |= E1000_RCTL_LPE;
2052 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2053 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2054 E1000_WRITE_FLUSH(hw);
2057 /* Enable Rx queues that were previously enabled and restore our
2060 for (i = 0; i < 4; i++)
2061 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2062 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2063 E1000_WRITE_FLUSH(hw);
2065 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2066 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2068 /* Flush receive errors generated by workaround */
2069 E1000_READ_REG(hw, E1000_ROC);
2070 E1000_READ_REG(hw, E1000_RNBC);
2071 E1000_READ_REG(hw, E1000_MPC);
2075 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2076 * @hw: pointer to the HW structure
2078 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2079 * however the hardware default for these parts is 500us to 1ms which is less
2080 * than the 10ms recommended by the pci-e spec. To address this we need to
2081 * increase the value to either 10ms to 200ms for capability version 1 config,
2082 * or 16ms to 55ms for version 2.
2084 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2086 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2087 s32 ret_val = E1000_SUCCESS;
2090 /* only take action if timeout value is defaulted to 0 */
2091 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2095 * if capababilities version is type 1 we can write the
2096 * timeout of 10ms to 200ms through the GCR register
2098 if (!(gcr & E1000_GCR_CAP_VER2)) {
2099 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2104 * for version 2 capabilities we need to write the config space
2105 * directly in order to set the completion timeout value for
2108 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2113 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2115 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2118 /* disable completion timeout resend */
2119 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2121 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2126 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2127 * @hw: pointer to the hardware struct
2128 * @enable: state to enter, either enabled or disabled
2129 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2131 * enables/disables L2 switch anti-spoofing functionality.
2133 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2137 switch (hw->mac.type) {
2139 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2141 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2142 E1000_DTXSWC_VLAN_SPOOF_MASK);
2143 /* The PF can spoof - it has to in order to
2144 * support emulation mode NICs */
2145 dtxswc ^= (1 << pf | 1 << (pf +
2146 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2148 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2149 E1000_DTXSWC_VLAN_SPOOF_MASK);
2151 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2154 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2156 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2157 E1000_DTXSWC_VLAN_SPOOF_MASK);
2158 /* The PF can spoof - it has to in order to
2159 * support emulation mode NICs
2161 dtxswc ^= (1 << pf | 1 << (pf +
2162 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2164 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2165 E1000_DTXSWC_VLAN_SPOOF_MASK);
2167 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2174 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2175 * @hw: pointer to the hardware struct
2176 * @enable: state to enter, either enabled or disabled
2178 * enables/disables L2 switch loopback functionality.
2180 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2184 switch (hw->mac.type) {
2186 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2188 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2190 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2191 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2194 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2196 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2198 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2199 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2202 /* Currently no other hardware supports loopback */
2210 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2211 * @hw: pointer to the hardware struct
2212 * @enable: state to enter, either enabled or disabled
2214 * enables/disables replication of packets across multiple pools.
2216 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2218 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2221 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2223 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2225 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2229 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2230 * @hw: pointer to the HW structure
2231 * @offset: register offset to be read
2232 * @data: pointer to the read data
2234 * Reads the MDI control register in the PHY at offset and stores the
2235 * information read to data.
2237 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2241 DEBUGFUNC("e1000_read_phy_reg_82580");
2243 ret_val = hw->phy.ops.acquire(hw);
2247 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2249 hw->phy.ops.release(hw);
2256 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2257 * @hw: pointer to the HW structure
2258 * @offset: register offset to write to
2259 * @data: data to write to register at offset
2261 * Writes data to MDI control register in the PHY at offset.
2263 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2267 DEBUGFUNC("e1000_write_phy_reg_82580");
2269 ret_val = hw->phy.ops.acquire(hw);
2273 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2275 hw->phy.ops.release(hw);
2282 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2283 * @hw: pointer to the HW structure
2285 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2286 * the values found in the EEPROM. This addresses an issue in which these
2287 * bits are not restored from EEPROM after reset.
2289 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2291 s32 ret_val = E1000_SUCCESS;
2295 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2297 if (hw->mac.type != e1000_82580)
2299 if (!e1000_sgmii_active_82575(hw))
2302 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2303 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2306 DEBUGOUT("NVM Read Error\n");
2310 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2311 if (nvm_data & NVM_WORD24_EXT_MDIO)
2312 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2313 if (nvm_data & NVM_WORD24_COM_MDIO)
2314 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2315 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2321 * e1000_reset_hw_82580 - Reset hardware
2322 * @hw: pointer to the HW structure
2324 * This resets function or entire device (all ports, etc.)
2327 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2329 s32 ret_val = E1000_SUCCESS;
2330 /* BH SW mailbox bit in SW_FW_SYNC */
2331 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2333 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2335 DEBUGFUNC("e1000_reset_hw_82580");
2337 hw->dev_spec._82575.global_device_reset = FALSE;
2339 /* 82580 does not reliably do global_device_reset due to hw errata */
2340 if (hw->mac.type == e1000_82580)
2341 global_device_reset = FALSE;
2343 /* Get current control state. */
2344 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2347 * Prevent the PCI-E bus from sticking if there is no TLP connection
2348 * on the last TLP read/write transaction when MAC is reset.
2350 ret_val = e1000_disable_pcie_master_generic(hw);
2352 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2354 DEBUGOUT("Masking off all interrupts\n");
2355 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2356 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2357 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2358 E1000_WRITE_FLUSH(hw);
2362 /* Determine whether or not a global dev reset is requested */
2363 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2365 global_device_reset = FALSE;
2367 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2368 E1000_STAT_DEV_RST_SET))
2369 ctrl |= E1000_CTRL_DEV_RST;
2371 ctrl |= E1000_CTRL_RST;
2373 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2374 E1000_WRITE_FLUSH(hw);
2376 /* Add delay to insure DEV_RST has time to complete */
2377 if (global_device_reset)
2380 ret_val = e1000_get_auto_rd_done_generic(hw);
2383 * When auto config read does not complete, do not
2384 * return with an error. This can happen in situations
2385 * where there is no eeprom and prevents getting link.
2387 DEBUGOUT("Auto Read Done did not complete\n");
2390 /* If EEPROM is not present, run manual init scripts */
2391 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2392 e1000_reset_init_script_82575(hw);
2394 /* clear global device reset status bit */
2395 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2397 /* Clear any pending interrupt events. */
2398 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2399 E1000_READ_REG(hw, E1000_ICR);
2401 ret_val = e1000_reset_mdicnfg_82580(hw);
2403 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2405 /* Install any alternate MAC address into RAR0 */
2406 ret_val = e1000_check_alt_mac_addr_generic(hw);
2408 /* Release semaphore */
2409 if (global_device_reset)
2410 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2416 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2417 * @data: data received by reading RXPBS register
2419 * The 82580 uses a table based approach for packet buffer allocation sizes.
2420 * This function converts the retrieved value into the correct table value
2421 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2422 * 0x0 36 72 144 1 2 4 8 16
2423 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2425 u16 e1000_rxpbs_adjust_82580(u32 data)
2429 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2430 ret_val = e1000_82580_rxpbs_table[data];
2436 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2438 * @hw: pointer to the HW structure
2439 * @offset: offset in words of the checksum protected region
2441 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2442 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2444 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2446 s32 ret_val = E1000_SUCCESS;
2450 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2452 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2453 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2455 DEBUGOUT("NVM Read Error\n");
2458 checksum += nvm_data;
2461 if (checksum != (u16) NVM_SUM) {
2462 DEBUGOUT("NVM Checksum Invalid\n");
2463 ret_val = -E1000_ERR_NVM;
2472 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2474 * @hw: pointer to the HW structure
2475 * @offset: offset in words of the checksum protected region
2477 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2478 * up to the checksum. Then calculates the EEPROM checksum and writes the
2479 * value to the EEPROM.
2481 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2487 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2489 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2490 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2492 DEBUGOUT("NVM Read Error while updating checksum.\n");
2495 checksum += nvm_data;
2497 checksum = (u16) NVM_SUM - checksum;
2498 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2501 DEBUGOUT("NVM Write Error while updating checksum.\n");
2508 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2509 * @hw: pointer to the HW structure
2511 * Calculates the EEPROM section checksum by reading/adding each word of
2512 * the EEPROM and then verifies that the sum of the EEPROM is
2515 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2517 s32 ret_val = E1000_SUCCESS;
2518 u16 eeprom_regions_count = 1;
2522 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2524 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2526 DEBUGOUT("NVM Read Error\n");
2530 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2531 /* if chekcsums compatibility bit is set validate checksums
2532 * for all 4 ports. */
2533 eeprom_regions_count = 4;
2536 for (j = 0; j < eeprom_regions_count; j++) {
2537 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2538 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2540 if (ret_val != E1000_SUCCESS)
2549 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2550 * @hw: pointer to the HW structure
2552 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2553 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2554 * checksum and writes the value to the EEPROM.
2556 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2562 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2564 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2566 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2570 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2571 /* set compatibility bit to validate checksums appropriately */
2572 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2573 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2576 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2581 for (j = 0; j < 4; j++) {
2582 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2583 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2593 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2594 * @hw: pointer to the HW structure
2596 * Calculates the EEPROM section checksum by reading/adding each word of
2597 * the EEPROM and then verifies that the sum of the EEPROM is
2600 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2602 s32 ret_val = E1000_SUCCESS;
2606 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2608 for (j = 0; j < 4; j++) {
2609 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2610 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2612 if (ret_val != E1000_SUCCESS)
2621 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2622 * @hw: pointer to the HW structure
2624 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2625 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2626 * checksum and writes the value to the EEPROM.
2628 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2630 s32 ret_val = E1000_SUCCESS;
2634 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2636 for (j = 0; j < 4; j++) {
2637 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2638 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2639 if (ret_val != E1000_SUCCESS)
2648 * e1000_set_eee_i350 - Enable/disable EEE support
2649 * @hw: pointer to the HW structure
2651 * Enable/disable EEE based on setting in dev_spec structure.
2654 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2656 s32 ret_val = E1000_SUCCESS;
2659 DEBUGFUNC("e1000_set_eee_i350");
2661 if ((hw->mac.type < e1000_i350) ||
2662 (hw->phy.media_type != e1000_media_type_copper))
2664 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2665 eeer = E1000_READ_REG(hw, E1000_EEER);
2667 /* enable or disable per user setting */
2668 if (!(hw->dev_spec._82575.eee_disable)) {
2669 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2671 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2672 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2675 /* This bit should not be set in normal operation. */
2676 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2677 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2679 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2680 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2683 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2684 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2685 E1000_READ_REG(hw, E1000_IPCNFG);
2686 E1000_READ_REG(hw, E1000_EEER);
2692 /* Due to a hw errata, if the host tries to configure the VFTA register
2693 * while performing queries from the BMC or DMA, then the VFTA in some
2694 * cases won't be written.
2698 * e1000_clear_vfta_i350 - Clear VLAN filter table
2699 * @hw: pointer to the HW structure
2701 * Clears the register array which contains the VLAN filter table by
2702 * setting all the values to 0.
2704 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2709 DEBUGFUNC("e1000_clear_vfta_350");
2711 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2712 for (i = 0; i < 10; i++)
2713 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2715 E1000_WRITE_FLUSH(hw);
2720 * e1000_write_vfta_i350 - Write value to VLAN filter table
2721 * @hw: pointer to the HW structure
2722 * @offset: register offset in VLAN filter table
2723 * @value: register value written to VLAN filter table
2725 * Writes value at the given offset in the register array which stores
2726 * the VLAN filter table.
2728 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2732 DEBUGFUNC("e1000_write_vfta_350");
2734 for (i = 0; i < 10; i++)
2735 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2737 E1000_WRITE_FLUSH(hw);
2742 * e1000_set_i2c_bb - Enable I2C bit-bang
2743 * @hw: pointer to the HW structure
2745 * Enable I2C bit-bang interface
2748 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2750 s32 ret_val = E1000_SUCCESS;
2751 u32 ctrl_ext, i2cparams;
2753 DEBUGFUNC("e1000_set_i2c_bb");
2755 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2756 ctrl_ext |= E1000_CTRL_I2C_ENA;
2757 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2758 E1000_WRITE_FLUSH(hw);
2760 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2761 i2cparams |= E1000_I2CBB_EN;
2762 i2cparams |= E1000_I2C_DATA_OE_N;
2763 i2cparams |= E1000_I2C_CLK_OE_N;
2764 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2765 E1000_WRITE_FLUSH(hw);
2771 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2772 * @hw: pointer to hardware structure
2773 * @byte_offset: byte offset to read
2774 * @dev_addr: device address
2777 * Performs byte read operation over I2C interface at
2778 * a specified device address.
2780 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2781 u8 dev_addr, u8 *data)
2783 s32 status = E1000_SUCCESS;
2790 DEBUGFUNC("e1000_read_i2c_byte_generic");
2792 swfw_mask = E1000_SWFW_PHY0_SM;
2795 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2797 status = E1000_ERR_SWFW_SYNC;
2801 e1000_i2c_start(hw);
2803 /* Device Address and write indication */
2804 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2805 if (status != E1000_SUCCESS)
2808 status = e1000_get_i2c_ack(hw);
2809 if (status != E1000_SUCCESS)
2812 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2813 if (status != E1000_SUCCESS)
2816 status = e1000_get_i2c_ack(hw);
2817 if (status != E1000_SUCCESS)
2820 e1000_i2c_start(hw);
2822 /* Device Address and read indication */
2823 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2824 if (status != E1000_SUCCESS)
2827 status = e1000_get_i2c_ack(hw);
2828 if (status != E1000_SUCCESS)
2831 status = e1000_clock_in_i2c_byte(hw, data);
2832 if (status != E1000_SUCCESS)
2835 status = e1000_clock_out_i2c_bit(hw, nack);
2836 if (status != E1000_SUCCESS)
2843 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2845 e1000_i2c_bus_clear(hw);
2847 if (retry < max_retry)
2848 DEBUGOUT("I2C byte read error - Retrying.\n");
2850 DEBUGOUT("I2C byte read error.\n");
2852 } while (retry < max_retry);
2854 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2862 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2863 * @hw: pointer to hardware structure
2864 * @byte_offset: byte offset to write
2865 * @dev_addr: device address
2866 * @data: value to write
2868 * Performs byte write operation over I2C interface at
2869 * a specified device address.
2871 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2872 u8 dev_addr, u8 data)
2874 s32 status = E1000_SUCCESS;
2879 DEBUGFUNC("e1000_write_i2c_byte_generic");
2881 swfw_mask = E1000_SWFW_PHY0_SM;
2883 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2884 status = E1000_ERR_SWFW_SYNC;
2885 goto write_byte_out;
2889 e1000_i2c_start(hw);
2891 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2892 if (status != E1000_SUCCESS)
2895 status = e1000_get_i2c_ack(hw);
2896 if (status != E1000_SUCCESS)
2899 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2900 if (status != E1000_SUCCESS)
2903 status = e1000_get_i2c_ack(hw);
2904 if (status != E1000_SUCCESS)
2907 status = e1000_clock_out_i2c_byte(hw, data);
2908 if (status != E1000_SUCCESS)
2911 status = e1000_get_i2c_ack(hw);
2912 if (status != E1000_SUCCESS)
2919 e1000_i2c_bus_clear(hw);
2921 if (retry < max_retry)
2922 DEBUGOUT("I2C byte write error - Retrying.\n");
2924 DEBUGOUT("I2C byte write error.\n");
2925 } while (retry < max_retry);
2927 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2935 * e1000_i2c_start - Sets I2C start condition
2936 * @hw: pointer to hardware structure
2938 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2940 static void e1000_i2c_start(struct e1000_hw *hw)
2942 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2944 DEBUGFUNC("e1000_i2c_start");
2946 /* Start condition must begin with data and clock high */
2947 e1000_set_i2c_data(hw, &i2cctl, 1);
2948 e1000_raise_i2c_clk(hw, &i2cctl);
2950 /* Setup time for start condition (4.7us) */
2951 usec_delay(E1000_I2C_T_SU_STA);
2953 e1000_set_i2c_data(hw, &i2cctl, 0);
2955 /* Hold time for start condition (4us) */
2956 usec_delay(E1000_I2C_T_HD_STA);
2958 e1000_lower_i2c_clk(hw, &i2cctl);
2960 /* Minimum low period of clock is 4.7 us */
2961 usec_delay(E1000_I2C_T_LOW);
2966 * e1000_i2c_stop - Sets I2C stop condition
2967 * @hw: pointer to hardware structure
2969 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2971 static void e1000_i2c_stop(struct e1000_hw *hw)
2973 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2975 DEBUGFUNC("e1000_i2c_stop");
2977 /* Stop condition must begin with data low and clock high */
2978 e1000_set_i2c_data(hw, &i2cctl, 0);
2979 e1000_raise_i2c_clk(hw, &i2cctl);
2981 /* Setup time for stop condition (4us) */
2982 usec_delay(E1000_I2C_T_SU_STO);
2984 e1000_set_i2c_data(hw, &i2cctl, 1);
2986 /* bus free time between stop and start (4.7us)*/
2987 usec_delay(E1000_I2C_T_BUF);
2991 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
2992 * @hw: pointer to hardware structure
2993 * @data: data byte to clock in
2995 * Clocks in one byte data via I2C data/clock
2997 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3002 DEBUGFUNC("e1000_clock_in_i2c_byte");
3005 for (i = 7; i >= 0; i--) {
3006 e1000_clock_in_i2c_bit(hw, &bit);
3010 return E1000_SUCCESS;
3014 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3015 * @hw: pointer to hardware structure
3016 * @data: data byte clocked out
3018 * Clocks out one byte data via I2C data/clock
3020 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3022 s32 status = E1000_SUCCESS;
3027 DEBUGFUNC("e1000_clock_out_i2c_byte");
3029 for (i = 7; i >= 0; i--) {
3030 bit = (data >> i) & 0x1;
3031 status = e1000_clock_out_i2c_bit(hw, bit);
3033 if (status != E1000_SUCCESS)
3037 /* Release SDA line (set high) */
3038 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3040 i2cctl |= E1000_I2C_DATA_OE_N;
3041 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3042 E1000_WRITE_FLUSH(hw);
3048 * e1000_get_i2c_ack - Polls for I2C ACK
3049 * @hw: pointer to hardware structure
3051 * Clocks in/out one bit via I2C data/clock
3053 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3055 s32 status = E1000_SUCCESS;
3057 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3061 DEBUGFUNC("e1000_get_i2c_ack");
3063 e1000_raise_i2c_clk(hw, &i2cctl);
3065 /* Minimum high period of clock is 4us */
3066 usec_delay(E1000_I2C_T_HIGH);
3068 /* Wait until SCL returns high */
3069 for (i = 0; i < timeout; i++) {
3071 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3072 if (i2cctl & E1000_I2C_CLK_IN)
3075 if (!(i2cctl & E1000_I2C_CLK_IN))
3076 return E1000_ERR_I2C;
3078 ack = e1000_get_i2c_data(&i2cctl);
3080 DEBUGOUT("I2C ack was not received.\n");
3081 status = E1000_ERR_I2C;
3084 e1000_lower_i2c_clk(hw, &i2cctl);
3086 /* Minimum low period of clock is 4.7 us */
3087 usec_delay(E1000_I2C_T_LOW);
3093 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3094 * @hw: pointer to hardware structure
3095 * @data: read data value
3097 * Clocks in one bit via I2C data/clock
3099 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3101 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3103 DEBUGFUNC("e1000_clock_in_i2c_bit");
3105 e1000_raise_i2c_clk(hw, &i2cctl);
3107 /* Minimum high period of clock is 4us */
3108 usec_delay(E1000_I2C_T_HIGH);
3110 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3111 *data = e1000_get_i2c_data(&i2cctl);
3113 e1000_lower_i2c_clk(hw, &i2cctl);
3115 /* Minimum low period of clock is 4.7 us */
3116 usec_delay(E1000_I2C_T_LOW);
3118 return E1000_SUCCESS;
3122 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3123 * @hw: pointer to hardware structure
3124 * @data: data value to write
3126 * Clocks out one bit via I2C data/clock
3128 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3131 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3133 DEBUGFUNC("e1000_clock_out_i2c_bit");
3135 status = e1000_set_i2c_data(hw, &i2cctl, data);
3136 if (status == E1000_SUCCESS) {
3137 e1000_raise_i2c_clk(hw, &i2cctl);
3139 /* Minimum high period of clock is 4us */
3140 usec_delay(E1000_I2C_T_HIGH);
3142 e1000_lower_i2c_clk(hw, &i2cctl);
3144 /* Minimum low period of clock is 4.7 us.
3145 * This also takes care of the data hold time.
3147 usec_delay(E1000_I2C_T_LOW);
3149 status = E1000_ERR_I2C;
3150 DEBUGOUT1("I2C data was not set to %X\n", data);
3156 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3157 * @hw: pointer to hardware structure
3158 * @i2cctl: Current value of I2CCTL register
3160 * Raises the I2C clock line '0'->'1'
3162 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3164 DEBUGFUNC("e1000_raise_i2c_clk");
3166 *i2cctl |= E1000_I2C_CLK_OUT;
3167 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3168 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3169 E1000_WRITE_FLUSH(hw);
3171 /* SCL rise time (1000ns) */
3172 usec_delay(E1000_I2C_T_RISE);
3176 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3177 * @hw: pointer to hardware structure
3178 * @i2cctl: Current value of I2CCTL register
3180 * Lowers the I2C clock line '1'->'0'
3182 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3185 DEBUGFUNC("e1000_lower_i2c_clk");
3187 *i2cctl &= ~E1000_I2C_CLK_OUT;
3188 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3189 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3190 E1000_WRITE_FLUSH(hw);
3192 /* SCL fall time (300ns) */
3193 usec_delay(E1000_I2C_T_FALL);
3197 * e1000_set_i2c_data - Sets the I2C data bit
3198 * @hw: pointer to hardware structure
3199 * @i2cctl: Current value of I2CCTL register
3200 * @data: I2C data value (0 or 1) to set
3202 * Sets the I2C data bit
3204 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3206 s32 status = E1000_SUCCESS;
3208 DEBUGFUNC("e1000_set_i2c_data");
3211 *i2cctl |= E1000_I2C_DATA_OUT;
3213 *i2cctl &= ~E1000_I2C_DATA_OUT;
3215 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3216 *i2cctl |= E1000_I2C_CLK_OE_N;
3217 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3218 E1000_WRITE_FLUSH(hw);
3220 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3221 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3223 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3224 if (data != e1000_get_i2c_data(i2cctl)) {
3225 status = E1000_ERR_I2C;
3226 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3233 * e1000_get_i2c_data - Reads the I2C SDA data bit
3234 * @hw: pointer to hardware structure
3235 * @i2cctl: Current value of I2CCTL register
3237 * Returns the I2C data bit value
3239 static bool e1000_get_i2c_data(u32 *i2cctl)
3243 DEBUGFUNC("e1000_get_i2c_data");
3245 if (*i2cctl & E1000_I2C_DATA_IN)
3254 * e1000_i2c_bus_clear - Clears the I2C bus
3255 * @hw: pointer to hardware structure
3257 * Clears the I2C bus by sending nine clock pulses.
3258 * Used when data line is stuck low.
3260 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3262 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3265 DEBUGFUNC("e1000_i2c_bus_clear");
3267 e1000_i2c_start(hw);
3269 e1000_set_i2c_data(hw, &i2cctl, 1);
3271 for (i = 0; i < 9; i++) {
3272 e1000_raise_i2c_clk(hw, &i2cctl);
3274 /* Min high period of clock is 4us */
3275 usec_delay(E1000_I2C_T_HIGH);
3277 e1000_lower_i2c_clk(hw, &i2cctl);
3279 /* Min low period of clock is 4.7us*/
3280 usec_delay(E1000_I2C_T_LOW);
3283 e1000_i2c_start(hw);
3285 /* Put the i2c bus back to default state */