1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_82574LA 0x10F6
98 #define E1000_DEV_ID_82583V 0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
104 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
105 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
106 #define E1000_DEV_ID_ICH8_IFE 0x104C
107 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
108 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
109 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
110 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
111 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
112 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
113 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
114 #define E1000_DEV_ID_ICH9_BM 0x10E5
115 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
116 #define E1000_DEV_ID_ICH9_IFE 0x10C0
117 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
118 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
119 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
120 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
121 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
122 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
123 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
124 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
125 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
126 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
127 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
128 #define E1000_DEV_ID_82576 0x10C9
129 #define E1000_DEV_ID_82576_FIBER 0x10E6
130 #define E1000_DEV_ID_82576_SERDES 0x10E7
131 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
132 #define E1000_DEV_ID_82576_NS 0x150A
133 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
134 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
135 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
136 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
137 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
138 #define E1000_REVISION_0 0
139 #define E1000_REVISION_1 1
140 #define E1000_REVISION_2 2
141 #define E1000_REVISION_3 3
142 #define E1000_REVISION_4 4
144 #define E1000_FUNC_0 0
145 #define E1000_FUNC_1 1
147 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
148 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
150 enum e1000_mac_type {
176 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
179 enum e1000_media_type {
180 e1000_media_type_unknown = 0,
181 e1000_media_type_copper = 1,
182 e1000_media_type_fiber = 2,
183 e1000_media_type_internal_serdes = 3,
184 e1000_num_media_types
187 enum e1000_nvm_type {
188 e1000_nvm_unknown = 0,
190 e1000_nvm_eeprom_spi,
191 e1000_nvm_eeprom_microwire,
196 enum e1000_nvm_override {
197 e1000_nvm_override_none = 0,
198 e1000_nvm_override_spi_small,
199 e1000_nvm_override_spi_large,
200 e1000_nvm_override_microwire_small,
201 e1000_nvm_override_microwire_large
204 enum e1000_phy_type {
205 e1000_phy_unknown = 0,
219 enum e1000_bus_type {
220 e1000_bus_type_unknown = 0,
223 e1000_bus_type_pci_express,
224 e1000_bus_type_reserved
227 enum e1000_bus_speed {
228 e1000_bus_speed_unknown = 0,
234 e1000_bus_speed_2500,
235 e1000_bus_speed_5000,
236 e1000_bus_speed_reserved
239 enum e1000_bus_width {
240 e1000_bus_width_unknown = 0,
241 e1000_bus_width_pcie_x1,
242 e1000_bus_width_pcie_x2,
243 e1000_bus_width_pcie_x4 = 4,
244 e1000_bus_width_pcie_x8 = 8,
247 e1000_bus_width_reserved
250 enum e1000_1000t_rx_status {
251 e1000_1000t_rx_status_not_ok = 0,
252 e1000_1000t_rx_status_ok,
253 e1000_1000t_rx_status_undefined = 0xFF
256 enum e1000_rev_polarity {
257 e1000_rev_polarity_normal = 0,
258 e1000_rev_polarity_reversed,
259 e1000_rev_polarity_undefined = 0xFF
267 e1000_fc_default = 0xFF
270 enum e1000_ffe_config {
271 e1000_ffe_config_enabled = 0,
272 e1000_ffe_config_active,
273 e1000_ffe_config_blocked
276 enum e1000_dsp_config {
277 e1000_dsp_config_disabled = 0,
278 e1000_dsp_config_enabled,
279 e1000_dsp_config_activated,
280 e1000_dsp_config_undefined = 0xFF
284 e1000_ms_hw_default = 0,
285 e1000_ms_force_master,
286 e1000_ms_force_slave,
290 enum e1000_smart_speed {
291 e1000_smart_speed_default = 0,
292 e1000_smart_speed_on,
293 e1000_smart_speed_off
296 enum e1000_serdes_link_state {
297 e1000_serdes_link_down = 0,
298 e1000_serdes_link_autoneg_progress,
299 e1000_serdes_link_autoneg_complete,
300 e1000_serdes_link_forced_up
303 /* Receive Descriptor */
304 struct e1000_rx_desc {
305 __le64 buffer_addr; /* Address of the descriptor's data buffer */
306 __le16 length; /* Length of data DMAed into data buffer */
307 __le16 csum; /* Packet checksum */
308 u8 status; /* Descriptor status */
309 u8 errors; /* Descriptor Errors */
313 /* Receive Descriptor - Extended */
314 union e1000_rx_desc_extended {
321 __le32 mrq; /* Multiple Rx Queues */
323 __le32 rss; /* RSS Hash */
325 __le16 ip_id; /* IP id */
326 __le16 csum; /* Packet Checksum */
331 __le32 status_error; /* ext status/error */
333 __le16 vlan; /* VLAN tag */
335 } wb; /* writeback */
338 #define MAX_PS_BUFFERS 4
339 /* Receive Descriptor - Packet Split */
340 union e1000_rx_desc_packet_split {
342 /* one buffer for protocol header(s), three data buffers */
343 __le64 buffer_addr[MAX_PS_BUFFERS];
347 __le32 mrq; /* Multiple Rx Queues */
349 __le32 rss; /* RSS Hash */
351 __le16 ip_id; /* IP id */
352 __le16 csum; /* Packet Checksum */
357 __le32 status_error; /* ext status/error */
358 __le16 length0; /* length of buffer 0 */
359 __le16 vlan; /* VLAN tag */
362 __le16 header_status;
363 __le16 length[3]; /* length of buffers 1-3 */
366 } wb; /* writeback */
369 /* Transmit Descriptor */
370 struct e1000_tx_desc {
371 __le64 buffer_addr; /* Address of the descriptor's data buffer */
375 __le16 length; /* Data buffer length */
376 u8 cso; /* Checksum offset */
377 u8 cmd; /* Descriptor control */
383 u8 status; /* Descriptor status */
384 u8 css; /* Checksum start */
390 /* Offload Context Descriptor */
391 struct e1000_context_desc {
395 u8 ipcss; /* IP checksum start */
396 u8 ipcso; /* IP checksum offset */
397 __le16 ipcse; /* IP checksum end */
403 u8 tucss; /* TCP checksum start */
404 u8 tucso; /* TCP checksum offset */
405 __le16 tucse; /* TCP checksum end */
408 __le32 cmd_and_length;
412 u8 status; /* Descriptor status */
413 u8 hdr_len; /* Header length */
414 __le16 mss; /* Maximum segment size */
419 /* Offload data descriptor */
420 struct e1000_data_desc {
421 __le64 buffer_addr; /* Address of the descriptor's buffer address */
425 __le16 length; /* Data buffer length */
433 u8 status; /* Descriptor status */
434 u8 popts; /* Packet Options */
440 /* Statistics counters collected by the MAC */
441 struct e1000_hw_stats {
521 struct e1000_phy_stats {
526 struct e1000_host_mng_dhcp_cookie {
537 /* Host Interface "Rev 1" */
538 struct e1000_host_command_header {
545 #define E1000_HI_MAX_DATA_LENGTH 252
546 struct e1000_host_command_info {
547 struct e1000_host_command_header command_header;
548 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
551 /* Host Interface "Rev 2" */
552 struct e1000_host_mng_command_header {
560 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
561 struct e1000_host_mng_command_info {
562 struct e1000_host_mng_command_header command_header;
563 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
566 #include "e1000_mac.h"
567 #include "e1000_phy.h"
568 #include "e1000_nvm.h"
569 #include "e1000_manage.h"
571 struct e1000_mac_operations {
572 /* Function pointers for the MAC. */
573 s32 (*init_params)(struct e1000_hw *);
574 s32 (*id_led_init)(struct e1000_hw *);
575 s32 (*blink_led)(struct e1000_hw *);
576 s32 (*check_for_link)(struct e1000_hw *);
577 bool (*check_mng_mode)(struct e1000_hw *hw);
578 s32 (*cleanup_led)(struct e1000_hw *);
579 void (*clear_hw_cntrs)(struct e1000_hw *);
580 void (*clear_vfta)(struct e1000_hw *);
581 s32 (*get_bus_info)(struct e1000_hw *);
582 void (*set_lan_id)(struct e1000_hw *);
583 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
584 s32 (*led_on)(struct e1000_hw *);
585 s32 (*led_off)(struct e1000_hw *);
586 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
587 s32 (*reset_hw)(struct e1000_hw *);
588 s32 (*init_hw)(struct e1000_hw *);
589 void (*shutdown_serdes)(struct e1000_hw *);
590 s32 (*setup_link)(struct e1000_hw *);
591 s32 (*setup_physical_interface)(struct e1000_hw *);
592 s32 (*setup_led)(struct e1000_hw *);
593 void (*write_vfta)(struct e1000_hw *, u32, u32);
594 void (*mta_set)(struct e1000_hw *, u32);
595 void (*config_collision_dist)(struct e1000_hw *);
596 void (*rar_set)(struct e1000_hw *, u8*, u32);
597 s32 (*read_mac_addr)(struct e1000_hw *);
598 s32 (*validate_mdi_setting)(struct e1000_hw *);
599 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
600 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
601 struct e1000_host_mng_command_header*);
602 s32 (*mng_enable_host_if)(struct e1000_hw *);
603 s32 (*wait_autoneg)(struct e1000_hw *);
606 struct e1000_phy_operations {
607 s32 (*init_params)(struct e1000_hw *);
608 s32 (*acquire)(struct e1000_hw *);
609 s32 (*cfg_on_link_up)(struct e1000_hw *);
610 s32 (*check_polarity)(struct e1000_hw *);
611 s32 (*check_reset_block)(struct e1000_hw *);
612 s32 (*commit)(struct e1000_hw *);
613 s32 (*force_speed_duplex)(struct e1000_hw *);
614 s32 (*get_cfg_done)(struct e1000_hw *hw);
615 s32 (*get_cable_length)(struct e1000_hw *);
616 s32 (*get_info)(struct e1000_hw *);
617 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
618 void (*release)(struct e1000_hw *);
619 s32 (*reset)(struct e1000_hw *);
620 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
621 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
622 s32 (*write_reg)(struct e1000_hw *, u32, u16);
623 void (*power_up)(struct e1000_hw *);
624 void (*power_down)(struct e1000_hw *);
627 struct e1000_nvm_operations {
628 s32 (*init_params)(struct e1000_hw *);
629 s32 (*acquire)(struct e1000_hw *);
630 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
631 void (*release)(struct e1000_hw *);
632 void (*reload)(struct e1000_hw *);
633 s32 (*update)(struct e1000_hw *);
634 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
635 s32 (*validate)(struct e1000_hw *);
636 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
639 struct e1000_mac_info {
640 struct e1000_mac_operations ops;
644 enum e1000_mac_type type;
661 /* Maximum size of the MTA register table in all supported adapters */
662 #define MAX_MTA_REG 128
663 u32 mta_shadow[MAX_MTA_REG];
666 u8 forced_speed_duplex;
669 bool arc_subsystem_valid;
670 bool asf_firmware_present;
673 bool get_link_status;
675 bool report_tx_early;
676 enum e1000_serdes_link_state serdes_link_state;
677 bool serdes_has_link;
678 bool tx_pkt_filtering;
681 struct e1000_phy_info {
682 struct e1000_phy_operations ops;
683 enum e1000_phy_type type;
685 enum e1000_1000t_rx_status local_rx;
686 enum e1000_1000t_rx_status remote_rx;
687 enum e1000_ms_type ms_type;
688 enum e1000_ms_type original_ms_type;
689 enum e1000_rev_polarity cable_polarity;
690 enum e1000_smart_speed smart_speed;
694 u32 reset_delay_us; /* in usec */
697 enum e1000_media_type media_type;
699 u16 autoneg_advertised;
702 u16 max_cable_length;
703 u16 min_cable_length;
707 bool disable_polarity_correction;
709 bool polarity_correction;
711 bool speed_downgraded;
712 bool autoneg_wait_to_complete;
715 struct e1000_nvm_info {
716 struct e1000_nvm_operations ops;
717 enum e1000_nvm_type type;
718 enum e1000_nvm_override override;
730 struct e1000_bus_info {
731 enum e1000_bus_type type;
732 enum e1000_bus_speed speed;
733 enum e1000_bus_width width;
739 struct e1000_fc_info {
740 u32 high_water; /* Flow control high-water mark */
741 u32 low_water; /* Flow control low-water mark */
742 u16 pause_time; /* Flow control pause timer */
743 bool send_xon; /* Flow control send XON */
744 bool strict_ieee; /* Strict IEEE mode */
745 enum e1000_fc_mode current_mode; /* FC mode in effect */
746 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
749 struct e1000_dev_spec_82541 {
750 enum e1000_dsp_config dsp_config;
751 enum e1000_ffe_config ffe_config;
753 bool phy_init_script;
756 struct e1000_dev_spec_82542 {
760 struct e1000_dev_spec_82543 {
761 u32 tbi_compatibility;
763 bool init_phy_disabled;
766 struct e1000_dev_spec_82571 {
771 struct e1000_shadow_ram {
776 #define E1000_SHADOW_RAM_WORDS 2048
778 struct e1000_dev_spec_ich8lan {
779 bool kmrn_lock_loss_workaround_enabled;
780 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
783 struct e1000_dev_spec_82575 {
785 bool global_device_reset;
788 struct e1000_dev_spec_vf {
799 unsigned long io_base;
801 struct e1000_mac_info mac;
802 struct e1000_fc_info fc;
803 struct e1000_phy_info phy;
804 struct e1000_nvm_info nvm;
805 struct e1000_bus_info bus;
806 struct e1000_host_mng_dhcp_cookie mng_cookie;
809 struct e1000_dev_spec_82541 _82541;
810 struct e1000_dev_spec_82542 _82542;
811 struct e1000_dev_spec_82543 _82543;
812 struct e1000_dev_spec_82571 _82571;
813 struct e1000_dev_spec_ich8lan ich8lan;
814 struct e1000_dev_spec_82575 _82575;
815 struct e1000_dev_spec_vf vf;
819 u16 subsystem_vendor_id;
820 u16 subsystem_device_id;
826 #include "e1000_82541.h"
827 #include "e1000_82543.h"
828 #include "e1000_82571.h"
829 #include "e1000_80003es2lan.h"
830 #include "e1000_ich8lan.h"
831 #include "e1000_82575.h"
833 /* These functions must be implemented by drivers */
834 void e1000_pci_clear_mwi(struct e1000_hw *hw);
835 void e1000_pci_set_mwi(struct e1000_hw *hw);
836 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
837 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
838 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
839 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);