sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                      0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  50 #define E1000_DEV_ID_82544GC_LOM                0x100D
  51 #define E1000_DEV_ID_82540EM                    0x100E
  52 #define E1000_DEV_ID_82540EM_LOM                0x1015
  53 #define E1000_DEV_ID_82540EP_LOM                0x1016
  54 #define E1000_DEV_ID_82540EP                    0x1017
  55 #define E1000_DEV_ID_82540EP_LP                 0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  70 #define E1000_DEV_ID_82541EI                    0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  72 #define E1000_DEV_ID_82541ER_LOM                0x1014
  73 #define E1000_DEV_ID_82541ER                    0x1078
  74 #define E1000_DEV_ID_82541GI                    0x1076
  75 #define E1000_DEV_ID_82541GI_LF                 0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  77 #define E1000_DEV_ID_82547EI                    0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  79 #define E1000_DEV_ID_82547GI                    0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  92 #define E1000_DEV_ID_82572EI                    0x10B9
  93 #define E1000_DEV_ID_82573E                     0x108B
  94 #define E1000_DEV_ID_82573E_IAMT                0x108C
  95 #define E1000_DEV_ID_82573L                     0x109A
  96 #define E1000_DEV_ID_82574L                     0x10D3
  97 #define E1000_DEV_ID_82574LA                    0x10F6
  98 #define E1000_DEV_ID_82583V                     0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 123 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 124 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 125 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 126 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 127 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 128 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 129 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 130 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 131 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 132 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 133 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 136 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 137 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 138 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 139 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 140 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 143 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 145 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 146 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 147 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 148 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 149 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
 150 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
 151 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
 152 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
 153 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
 154 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
 155 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
 156 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
 157 #define E1000_DEV_ID_82576                      0x10C9
 158 #define E1000_DEV_ID_82576_FIBER                0x10E6
 159 #define E1000_DEV_ID_82576_SERDES               0x10E7
 160 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 161 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 162 #define E1000_DEV_ID_82576_NS                   0x150A
 163 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 164 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 165 #define E1000_DEV_ID_82576_VF                   0x10CA
 166 #define E1000_DEV_ID_82576_VF_HV                0x152D
 167 #define E1000_DEV_ID_I350_VF                    0x1520
 168 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 169 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 170 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 171 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 172 #define E1000_DEV_ID_82580_COPPER               0x150E
 173 #define E1000_DEV_ID_82580_FIBER                0x150F
 174 #define E1000_DEV_ID_82580_SERDES               0x1510
 175 #define E1000_DEV_ID_82580_SGMII                0x1511
 176 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 177 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 178 #define E1000_DEV_ID_I350_COPPER                0x1521
 179 #define E1000_DEV_ID_I350_FIBER                 0x1522
 180 #define E1000_DEV_ID_I350_SERDES                0x1523
 181 #define E1000_DEV_ID_I350_SGMII                 0x1524
 182 #define E1000_DEV_ID_I350_DA4                   0x1546
 183 #define E1000_DEV_ID_I210_COPPER                0x1533
 184 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 185 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 186 #define E1000_DEV_ID_I210_FIBER                 0x1536
 187 #define E1000_DEV_ID_I210_SERDES                0x1537
 188 #define E1000_DEV_ID_I210_SGMII                 0x1538
 189 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 190 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 191 #define E1000_DEV_ID_I211_COPPER                0x1539
 192 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 193 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 194 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 195 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 196 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 197 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 198 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 199
 200 #define E1000_REVISION_0        0
 201 #define E1000_REVISION_1        1
 202 #define E1000_REVISION_2        2
 203 #define E1000_REVISION_3        3
 204 #define E1000_REVISION_4        4
 205
 206 #define E1000_FUNC_0            0
 207 #define E1000_FUNC_1            1
 208 #define E1000_FUNC_2            2
 209 #define E1000_FUNC_3            3
 210
 211 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 212 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 213 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 214 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 215
 216 enum e1000_mac_type {
 217         e1000_undefined = 0,
 218         e1000_82542,
 219         e1000_82543,
 220         e1000_82544,
 221         e1000_82540,
 222         e1000_82545,
 223         e1000_82545_rev_3,
 224         e1000_82546,
 225         e1000_82546_rev_3,
 226         e1000_82541,
 227         e1000_82541_rev_2,
 228         e1000_82547,
 229         e1000_82547_rev_2,
 230         e1000_82571,
 231         e1000_82572,
 232         e1000_82573,
 233         e1000_82574,
 234         e1000_82583,
 235         e1000_80003es2lan,
 236         e1000_ich8lan,
 237         e1000_ich9lan,
 238         e1000_ich10lan,
 239         e1000_pchlan,
 240         e1000_pch2lan,
 241         e1000_pch_lpt,
 242         e1000_pch_spt,
 243         e1000_pch_cnp,
 244         e1000_82575,
 245         e1000_82576,
 246         e1000_82580,
 247         e1000_i350,
 248         e1000_i354,
 249         e1000_i210,
 250         e1000_i211,
 251         e1000_vfadapt,
 252         e1000_vfadapt_i350,
 253         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 254 };
 255
 256 enum e1000_media_type {
 257         e1000_media_type_unknown = 0,
 258         e1000_media_type_copper = 1,
 259         e1000_media_type_fiber = 2,
 260         e1000_media_type_internal_serdes = 3,
 261         e1000_num_media_types
 262 };
 263
 264 enum e1000_nvm_type {
 265         e1000_nvm_unknown = 0,
 266         e1000_nvm_none,
 267         e1000_nvm_eeprom_spi,
 268         e1000_nvm_eeprom_microwire,
 269         e1000_nvm_flash_hw,
 270         e1000_nvm_invm,
 271         e1000_nvm_flash_sw
 272 };
 273
 274 enum e1000_nvm_override {
 275         e1000_nvm_override_none = 0,
 276         e1000_nvm_override_spi_small,
 277         e1000_nvm_override_spi_large,
 278         e1000_nvm_override_microwire_small,
 279         e1000_nvm_override_microwire_large
 280 };
 281
 282 enum e1000_phy_type {
 283         e1000_phy_unknown = 0,
 284         e1000_phy_none,
 285         e1000_phy_m88,
 286         e1000_phy_igp,
 287         e1000_phy_igp_2,
 288         e1000_phy_gg82563,
 289         e1000_phy_igp_3,
 290         e1000_phy_ife,
 291         e1000_phy_bm,
 292         e1000_phy_82578,
 293         e1000_phy_82577,
 294         e1000_phy_82579,
 295         e1000_phy_i217,
 296         e1000_phy_82580,
 297         e1000_phy_vf,
 298         e1000_phy_i210,
 299 };
 300
 301 enum e1000_bus_type {
 302         e1000_bus_type_unknown = 0,
 303         e1000_bus_type_pci,
 304         e1000_bus_type_pcix,
 305         e1000_bus_type_pci_express,
 306         e1000_bus_type_reserved
 307 };
 308
 309 enum e1000_bus_speed {
 310         e1000_bus_speed_unknown = 0,
 311         e1000_bus_speed_33,
 312         e1000_bus_speed_66,
 313         e1000_bus_speed_100,
 314         e1000_bus_speed_120,
 315         e1000_bus_speed_133,
 316         e1000_bus_speed_2500,
 317         e1000_bus_speed_5000,
 318         e1000_bus_speed_reserved
 319 };
 320
 321 enum e1000_bus_width {
 322         e1000_bus_width_unknown = 0,
 323         e1000_bus_width_pcie_x1,
 324         e1000_bus_width_pcie_x2,
 325         e1000_bus_width_pcie_x4 = 4,
 326         e1000_bus_width_pcie_x8 = 8,
 327         e1000_bus_width_32,
 328         e1000_bus_width_64,
 329         e1000_bus_width_reserved
 330 };
 331
 332 enum e1000_1000t_rx_status {
 333         e1000_1000t_rx_status_not_ok = 0,
 334         e1000_1000t_rx_status_ok,
 335         e1000_1000t_rx_status_undefined = 0xFF
 336 };
 337
 338 enum e1000_rev_polarity {
 339         e1000_rev_polarity_normal = 0,
 340         e1000_rev_polarity_reversed,
 341         e1000_rev_polarity_undefined = 0xFF
 342 };
 343
 344 enum e1000_fc_mode {
 345         e1000_fc_none = 0,
 346         e1000_fc_rx_pause,
 347         e1000_fc_tx_pause,
 348         e1000_fc_full,
 349         e1000_fc_default = 0xFF
 350 };
 351
 352 enum e1000_ffe_config {
 353         e1000_ffe_config_enabled = 0,
 354         e1000_ffe_config_active,
 355         e1000_ffe_config_blocked
 356 };
 357
 358 enum e1000_dsp_config {
 359         e1000_dsp_config_disabled = 0,
 360         e1000_dsp_config_enabled,
 361         e1000_dsp_config_activated,
 362         e1000_dsp_config_undefined = 0xFF
 363 };
 364
 365 enum e1000_ms_type {
 366         e1000_ms_hw_default = 0,
 367         e1000_ms_force_master,
 368         e1000_ms_force_slave,
 369         e1000_ms_auto
 370 };
 371
 372 enum e1000_smart_speed {
 373         e1000_smart_speed_default = 0,
 374         e1000_smart_speed_on,
 375         e1000_smart_speed_off
 376 };
 377
 378 enum e1000_serdes_link_state {
 379         e1000_serdes_link_down = 0,
 380         e1000_serdes_link_autoneg_progress,
 381         e1000_serdes_link_autoneg_complete,
 382         e1000_serdes_link_forced_up
 383 };
 384
 385 #define __le16 u16
 386 #define __le32 u32
 387 #define __le64 u64
 388 /* Receive Descriptor */
 389 struct e1000_rx_desc {
 390         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 391         __le16 length;      /* Length of data DMAed into data buffer */
 392         __le16 csum; /* Packet checksum */
 393         u8  status;  /* Descriptor status */
 394         u8  errors;  /* Descriptor Errors */
 395         __le16 special;
 396 };
 397
 398 /* Receive Descriptor - Extended */
 399 union e1000_rx_desc_extended {
 400         struct {
 401                 __le64 buffer_addr;
 402                 __le64 reserved;
 403         } read;
 404         struct {
 405                 struct {
 406                         __le32 mrq; /* Multiple Rx Queues */
 407                         union {
 408                                 __le32 rss; /* RSS Hash */
 409                                 struct {
 410                                         __le16 ip_id;  /* IP id */
 411                                         __le16 csum;   /* Packet Checksum */
 412                                 } csum_ip;
 413                         } hi_dword;
 414                 } lower;
 415                 struct {
 416                         __le32 status_error;  /* ext status/error */
 417                         __le16 length;
 418                         __le16 vlan; /* VLAN tag */
 419                 } upper;
 420         } wb;  /* writeback */
 421 };
 422
 423 #define MAX_PS_BUFFERS 4
 424
 425 /* Number of packet split data buffers (not including the header buffer) */
 426 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 427
 428 /* Receive Descriptor - Packet Split */
 429 union e1000_rx_desc_packet_split {
 430         struct {
 431                 /* one buffer for protocol header(s), three data buffers */
 432                 __le64 buffer_addr[MAX_PS_BUFFERS];
 433         } read;
 434         struct {
 435                 struct {
 436                         __le32 mrq;  /* Multiple Rx Queues */
 437                         union {
 438                                 __le32 rss; /* RSS Hash */
 439                                 struct {
 440                                         __le16 ip_id;    /* IP id */
 441                                         __le16 csum;     /* Packet Checksum */
 442                                 } csum_ip;
 443                         } hi_dword;
 444                 } lower;
 445                 struct {
 446                         __le32 status_error;  /* ext status/error */
 447                         __le16 length0;  /* length of buffer 0 */
 448                         __le16 vlan;  /* VLAN tag */
 449                 } middle;
 450                 struct {
 451                         __le16 header_status;
 452                         /* length of buffers 1-3 */
 453                         __le16 length[PS_PAGE_BUFFERS];
 454                 } upper;
 455                 __le64 reserved;
 456         } wb; /* writeback */
 457 };
 458
 459 /* Transmit Descriptor */
 460 struct e1000_tx_desc {
 461         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 462         union {
 463                 __le32 data;
 464                 struct {
 465                         __le16 length;  /* Data buffer length */
 466                         u8 cso;  /* Checksum offset */
 467                         u8 cmd;  /* Descriptor control */
 468                 } flags;
 469         } lower;
 470         union {
 471                 __le32 data;
 472                 struct {
 473                         u8 status; /* Descriptor status */
 474                         u8 css;  /* Checksum start */
 475                         __le16 special;
 476                 } fields;
 477         } upper;
 478 };
 479
 480 /* Offload Context Descriptor */
 481 struct e1000_context_desc {
 482         union {
 483                 __le32 ip_config;
 484                 struct {
 485                         u8 ipcss;  /* IP checksum start */
 486                         u8 ipcso;  /* IP checksum offset */
 487                         __le16 ipcse;  /* IP checksum end */
 488                 } ip_fields;
 489         } lower_setup;
 490         union {
 491                 __le32 tcp_config;
 492                 struct {
 493                         u8 tucss;  /* TCP checksum start */
 494                         u8 tucso;  /* TCP checksum offset */
 495                         __le16 tucse;  /* TCP checksum end */
 496                 } tcp_fields;
 497         } upper_setup;
 498         __le32 cmd_and_length;
 499         union {
 500                 __le32 data;
 501                 struct {
 502                         u8 status;  /* Descriptor status */
 503                         u8 hdr_len;  /* Header length */
 504                         __le16 mss;  /* Maximum segment size */
 505                 } fields;
 506         } tcp_seg_setup;
 507 };
 508
 509 /* Offload data descriptor */
 510 struct e1000_data_desc {
 511         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 512         union {
 513                 __le32 data;
 514                 struct {
 515                         __le16 length;  /* Data buffer length */
 516                         u8 typ_len_ext;
 517                         u8 cmd;
 518                 } flags;
 519         } lower;
 520         union {
 521                 __le32 data;
 522                 struct {
 523                         u8 status;  /* Descriptor status */
 524                         u8 popts;  /* Packet Options */
 525                         __le16 special;
 526                 } fields;
 527         } upper;
 528 };
 529
 530 /* Statistics counters collected by the MAC */
 531 struct e1000_hw_stats {
 532         u64 crcerrs;
 533         u64 algnerrc;
 534         u64 symerrs;
 535         u64 rxerrc;
 536         u64 mpc;
 537         u64 scc;
 538         u64 ecol;
 539         u64 mcc;
 540         u64 latecol;
 541         u64 colc;
 542         u64 dc;
 543         u64 tncrs;
 544         u64 sec;
 545         u64 cexterr;
 546         u64 rlec;
 547         u64 xonrxc;
 548         u64 xontxc;
 549         u64 xoffrxc;
 550         u64 xofftxc;
 551         u64 fcruc;
 552         u64 prc64;
 553         u64 prc127;
 554         u64 prc255;
 555         u64 prc511;
 556         u64 prc1023;
 557         u64 prc1522;
 558         u64 gprc;
 559         u64 bprc;
 560         u64 mprc;
 561         u64 gptc;
 562         u64 gorc;
 563         u64 gotc;
 564         u64 rnbc;
 565         u64 ruc;
 566         u64 rfc;
 567         u64 roc;
 568         u64 rjc;
 569         u64 mgprc;
 570         u64 mgpdc;
 571         u64 mgptc;
 572         u64 tor;
 573         u64 tot;
 574         u64 tpr;
 575         u64 tpt;
 576         u64 ptc64;
 577         u64 ptc127;
 578         u64 ptc255;
 579         u64 ptc511;
 580         u64 ptc1023;
 581         u64 ptc1522;
 582         u64 mptc;
 583         u64 bptc;
 584         u64 tsctc;
 585         u64 tsctfc;
 586         u64 iac;
 587         u64 icrxptc;
 588         u64 icrxatc;
 589         u64 ictxptc;
 590         u64 ictxatc;
 591         u64 ictxqec;
 592         u64 ictxqmtc;
 593         u64 icrxdmtc;
 594         u64 icrxoc;
 595         u64 cbtmpc;
 596         u64 htdpmc;
 597         u64 cbrdpc;
 598         u64 cbrmpc;
 599         u64 rpthc;
 600         u64 hgptc;
 601         u64 htcbdpc;
 602         u64 hgorc;
 603         u64 hgotc;
 604         u64 lenerrs;
 605         u64 scvpc;
 606         u64 hrmpc;
 607         u64 doosync;
 608         u64 o2bgptc;
 609         u64 o2bspc;
 610         u64 b2ospc;
 611         u64 b2ogprc;
 612 };
 613
 614 struct e1000_vf_stats {
 615         u64 base_gprc;
 616         u64 base_gptc;
 617         u64 base_gorc;
 618         u64 base_gotc;
 619         u64 base_mprc;
 620         u64 base_gotlbc;
 621         u64 base_gptlbc;
 622         u64 base_gorlbc;
 623         u64 base_gprlbc;
 624
 625         u32 last_gprc;
 626         u32 last_gptc;
 627         u32 last_gorc;
 628         u32 last_gotc;
 629         u32 last_mprc;
 630         u32 last_gotlbc;
 631         u32 last_gptlbc;
 632         u32 last_gorlbc;
 633         u32 last_gprlbc;
 634
 635         u64 gprc;
 636         u64 gptc;
 637         u64 gorc;
 638         u64 gotc;
 639         u64 mprc;
 640         u64 gotlbc;
 641         u64 gptlbc;
 642         u64 gorlbc;
 643         u64 gprlbc;
 644 };
 645
 646 struct e1000_phy_stats {
 647         u32 idle_errors;
 648         u32 receive_errors;
 649 };
 650
 651 struct e1000_host_mng_dhcp_cookie {
 652         u32 signature;
 653         u8  status;
 654         u8  reserved0;
 655         u16 vlan_id;
 656         u32 reserved1;
 657         u16 reserved2;
 658         u8  reserved3;
 659         u8  checksum;
 660 };
 661
 662 /* Host Interface "Rev 1" */
 663 struct e1000_host_command_header {
 664         u8 command_id;
 665         u8 command_length;
 666         u8 command_options;
 667         u8 checksum;
 668 };
 669
 670 #define E1000_HI_MAX_DATA_LENGTH        252
 671 struct e1000_host_command_info {
 672         struct e1000_host_command_header command_header;
 673         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 674 };
 675
 676 /* Host Interface "Rev 2" */
 677 struct e1000_host_mng_command_header {
 678         u8  command_id;
 679         u8  checksum;
 680         u16 reserved1;
 681         u16 reserved2;
 682         u16 command_length;
 683 };
 684
 685 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 686 struct e1000_host_mng_command_info {
 687         struct e1000_host_mng_command_header command_header;
 688         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 689 };
 690
 691 #include "e1000_mac.h"
 692 #include "e1000_phy.h"
 693 #include "e1000_nvm.h"
 694 #include "e1000_manage.h"
 695 #include "e1000_mbx.h"
 696
 697 /* Function pointers for the MAC. */
 698 struct e1000_mac_operations {
 699         s32  (*init_params)(struct e1000_hw *);
 700         s32  (*id_led_init)(struct e1000_hw *);
 701         s32  (*blink_led)(struct e1000_hw *);
 702         bool (*check_mng_mode)(struct e1000_hw *);
 703         s32  (*check_for_link)(struct e1000_hw *);
 704         s32  (*cleanup_led)(struct e1000_hw *);
 705         void (*clear_hw_cntrs)(struct e1000_hw *);
 706         void (*clear_vfta)(struct e1000_hw *);
 707         s32  (*get_bus_info)(struct e1000_hw *);
 708         void (*set_lan_id)(struct e1000_hw *);
 709         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 710         s32  (*led_on)(struct e1000_hw *);
 711         s32  (*led_off)(struct e1000_hw *);
 712         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 713         s32  (*reset_hw)(struct e1000_hw *);
 714         s32  (*init_hw)(struct e1000_hw *);
 715         void (*shutdown_serdes)(struct e1000_hw *);
 716         void (*power_up_serdes)(struct e1000_hw *);
 717         s32  (*setup_link)(struct e1000_hw *);
 718         s32  (*setup_physical_interface)(struct e1000_hw *);
 719         s32  (*setup_led)(struct e1000_hw *);
 720         void (*write_vfta)(struct e1000_hw *, u32, u32);
 721         void (*config_collision_dist)(struct e1000_hw *);
 722         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 723         s32  (*read_mac_addr)(struct e1000_hw *);
 724         s32  (*validate_mdi_setting)(struct e1000_hw *);
 725         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 726         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 727         void (*release_swfw_sync)(struct e1000_hw *, u16);
 728 };
 729
 730 /* When to use various PHY register access functions:
 731  *
 732  *                 Func   Caller
 733  *   Function      Does   Does    When to use
 734  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 735  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 736  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 737  *                                on different pages
 738  *   X_reg_page    A      L,P     for multiple accesses of different regs
 739  *                                on the same page
 740  *
 741  * Where X=[read|write], L=locking, P=sets page, A=register access
 742  *
 743  */
 744 struct e1000_phy_operations {
 745         s32  (*init_params)(struct e1000_hw *);
 746         s32  (*acquire)(struct e1000_hw *);
 747         s32  (*cfg_on_link_up)(struct e1000_hw *);
 748         s32  (*check_polarity)(struct e1000_hw *);
 749         s32  (*check_reset_block)(struct e1000_hw *);
 750         s32  (*commit)(struct e1000_hw *);
 751         s32  (*force_speed_duplex)(struct e1000_hw *);
 752         s32  (*get_cfg_done)(struct e1000_hw *hw);
 753         s32  (*get_cable_length)(struct e1000_hw *);
 754         s32  (*get_info)(struct e1000_hw *);
 755         s32  (*set_page)(struct e1000_hw *, u16);
 756         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 757         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 758         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 759         void (*release)(struct e1000_hw *);
 760         s32  (*reset)(struct e1000_hw *);
 761         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 762         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 763         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 764         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 765         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 766         void (*power_up)(struct e1000_hw *);
 767         void (*power_down)(struct e1000_hw *);
 768         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 769         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 770 };
 771
 772 /* Function pointers for the NVM. */
 773 struct e1000_nvm_operations {
 774         s32  (*init_params)(struct e1000_hw *);
 775         s32  (*acquire)(struct e1000_hw *);
 776         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 777         void (*release)(struct e1000_hw *);
 778         void (*reload)(struct e1000_hw *);
 779         s32  (*update)(struct e1000_hw *);
 780         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 781         s32  (*validate)(struct e1000_hw *);
 782         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 783 };
 784
 785 struct e1000_mac_info {
 786         struct e1000_mac_operations ops;
 787         u8 addr[ETH_ADDR_LEN];
 788         u8 perm_addr[ETH_ADDR_LEN];
 789
 790         enum e1000_mac_type type;
 791
 792         u32 collision_delta;
 793         u32 ledctl_default;
 794         u32 ledctl_mode1;
 795         u32 ledctl_mode2;
 796         u32 mc_filter_type;
 797         u32 tx_packet_delta;
 798         u32 txcw;
 799
 800         u16 current_ifs_val;
 801         u16 ifs_max_val;
 802         u16 ifs_min_val;
 803         u16 ifs_ratio;
 804         u16 ifs_step_size;
 805         u16 mta_reg_count;
 806         u16 uta_reg_count;
 807
 808         /* Maximum size of the MTA register table in all supported adapters */
 809 #define MAX_MTA_REG 128
 810         u32 mta_shadow[MAX_MTA_REG];
 811         u16 rar_entry_count;
 812
 813         u8  forced_speed_duplex;
 814
 815         bool adaptive_ifs;
 816         bool has_fwsm;
 817         bool arc_subsystem_valid;
 818         bool asf_firmware_present;
 819         bool autoneg;
 820         bool autoneg_failed;
 821         bool get_link_status;
 822         bool in_ifs_mode;
 823         bool report_tx_early;
 824         enum e1000_serdes_link_state serdes_link_state;
 825         bool serdes_has_link;
 826         bool tx_pkt_filtering;
 827         u32  max_frame_size;
 828 };
 829
 830 struct e1000_phy_info {
 831         struct e1000_phy_operations ops;
 832         enum e1000_phy_type type;
 833
 834         enum e1000_1000t_rx_status local_rx;
 835         enum e1000_1000t_rx_status remote_rx;
 836         enum e1000_ms_type ms_type;
 837         enum e1000_ms_type original_ms_type;
 838         enum e1000_rev_polarity cable_polarity;
 839         enum e1000_smart_speed smart_speed;
 840
 841         u32 addr;
 842         u32 id;
 843         u32 reset_delay_us; /* in usec */
 844         u32 revision;
 845
 846         enum e1000_media_type media_type;
 847
 848         u16 autoneg_advertised;
 849         u16 autoneg_mask;
 850         u16 cable_length;
 851         u16 max_cable_length;
 852         u16 min_cable_length;
 853
 854         u8 mdix;
 855
 856         bool disable_polarity_correction;
 857         bool is_mdix;
 858         bool polarity_correction;
 859         bool speed_downgraded;
 860         bool autoneg_wait_to_complete;
 861 };
 862
 863 struct e1000_nvm_info {
 864         struct e1000_nvm_operations ops;
 865         enum e1000_nvm_type type;
 866         enum e1000_nvm_override override;
 867
 868         u32 flash_bank_size;
 869         u32 flash_base_addr;
 870
 871         u16 word_size;
 872         u16 delay_usec;
 873         u16 address_bits;
 874         u16 opcode_bits;
 875         u16 page_size;
 876 };
 877
 878 struct e1000_bus_info {
 879         enum e1000_bus_type type;
 880         enum e1000_bus_speed speed;
 881         enum e1000_bus_width width;
 882
 883         u16 func;
 884         u16 pci_cmd_word;
 885 };
 886
 887 struct e1000_fc_info {
 888         u32 high_water;  /* Flow control high-water mark */
 889         u32 low_water;  /* Flow control low-water mark */
 890         u16 pause_time;  /* Flow control pause timer */
 891         u16 refresh_time;  /* Flow control refresh timer */
 892         bool send_xon;  /* Flow control send XON */
 893         bool strict_ieee;  /* Strict IEEE mode */
 894         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 895         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 896 };
 897
 898 struct e1000_mbx_operations {
 899         s32 (*init_params)(struct e1000_hw *hw);
 900         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 901         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 902         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 903         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 904         s32 (*check_for_msg)(struct e1000_hw *, u16);
 905         s32 (*check_for_ack)(struct e1000_hw *, u16);
 906         s32 (*check_for_rst)(struct e1000_hw *, u16);
 907 };
 908
 909 struct e1000_mbx_stats {
 910         u32 msgs_tx;
 911         u32 msgs_rx;
 912
 913         u32 acks;
 914         u32 reqs;
 915         u32 rsts;
 916 };
 917
 918 struct e1000_mbx_info {
 919         struct e1000_mbx_operations ops;
 920         struct e1000_mbx_stats stats;
 921         u32 timeout;
 922         u32 usec_delay;
 923         u16 size;
 924 };
 925
 926 struct e1000_dev_spec_82541 {
 927         enum e1000_dsp_config dsp_config;
 928         enum e1000_ffe_config ffe_config;
 929         u16 spd_default;
 930         bool phy_init_script;
 931 };
 932
 933 struct e1000_dev_spec_82542 {
 934         bool dma_fairness;
 935 };
 936
 937 struct e1000_dev_spec_82543 {
 938         u32  tbi_compatibility;
 939         bool dma_fairness;
 940         bool init_phy_disabled;
 941 };
 942
 943 struct e1000_dev_spec_82571 {
 944         bool laa_is_present;
 945         u32 smb_counter;
 946         E1000_MUTEX swflag_mutex;
 947 };
 948
 949 struct e1000_dev_spec_80003es2lan {
 950         bool  mdic_wa_enable;
 951 };
 952
 953 struct e1000_shadow_ram {
 954         u16  value;
 955         bool modified;
 956 };
 957
 958 #define E1000_SHADOW_RAM_WORDS          2048
 959
 960 /* I218 PHY Ultra Low Power (ULP) states */
 961 enum e1000_ulp_state {
 962         e1000_ulp_state_unknown,
 963         e1000_ulp_state_off,
 964         e1000_ulp_state_on,
 965 };
 966
 967 struct e1000_dev_spec_ich8lan {
 968         bool kmrn_lock_loss_workaround_enabled;
 969         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 970         E1000_MUTEX nvm_mutex;
 971         E1000_MUTEX swflag_mutex;
 972         bool nvm_k1_enabled;
 973         bool disable_k1_off;
 974         bool eee_disable;
 975         u16 eee_lp_ability;
 976         enum e1000_ulp_state ulp_state;
 977         bool ulp_capability_disabled;
 978         bool during_suspend_flow;
 979         bool during_dpg_exit;
 980 };
 981
 982 struct e1000_dev_spec_82575 {
 983         bool sgmii_active;
 984         bool global_device_reset;
 985         bool eee_disable;
 986         bool module_plugged;
 987         bool clear_semaphore_once;
 988         u32 mtu;
 989         struct sfp_e1000_flags eth_flags;
 990         u8 media_port;
 991         bool media_changed;
 992 };
 993
 994 struct e1000_dev_spec_vf {
 995         u32 vf_number;
 996         u32 v2p_mailbox;
 997 };
 998
 999 struct e1000_hw {
1000         void *back;
1001
1002         u8 *hw_addr;
1003         u8 *flash_address;
1004         unsigned long io_base;
1005
1006         struct e1000_mac_info  mac;
1007         struct e1000_fc_info   fc;
1008         struct e1000_phy_info  phy;
1009         struct e1000_nvm_info  nvm;
1010         struct e1000_bus_info  bus;
1011         struct e1000_mbx_info mbx;
1012         struct e1000_host_mng_dhcp_cookie mng_cookie;
1013
1014         union {
1015                 struct e1000_dev_spec_82541 _82541;
1016                 struct e1000_dev_spec_82542 _82542;
1017                 struct e1000_dev_spec_82543 _82543;
1018                 struct e1000_dev_spec_82571 _82571;
1019                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1020                 struct e1000_dev_spec_ich8lan ich8lan;
1021                 struct e1000_dev_spec_82575 _82575;
1022                 struct e1000_dev_spec_vf vf;
1023         } dev_spec;
1024
1025         u16 device_id;
1026         u16 subsystem_vendor_id;
1027         u16 subsystem_device_id;
1028         u16 vendor_id;
1029
1030         u8  revision_id;
1031 };
1032
1033 #include "e1000_82541.h"
1034 #include "e1000_82543.h"
1035 #include "e1000_82571.h"
1036 #include "e1000_80003es2lan.h"
1037 #include "e1000_ich8lan.h"
1038 #include "e1000_82575.h"
1039 #include "e1000_i210.h"
1040
1041 /* These functions must be implemented by drivers */
1042 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1043 void e1000_pci_set_mwi(struct e1000_hw *hw);
1044 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1045 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1046 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1047 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1048
1049 #endif