1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_82574LA 0x10F6
98 #define E1000_DEV_ID_82583V 0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
107 #define E1000_DEV_ID_ICH8_IFE 0x104C
108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115 #define E1000_DEV_ID_ICH9_BM 0x10E5
116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
117 #define E1000_DEV_ID_ICH9_IFE 0x10C0
118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
131 #define E1000_DEV_ID_PCH2_LV_V 0x1503
132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
140 #define E1000_DEV_ID_82576 0x10C9
141 #define E1000_DEV_ID_82576_FIBER 0x10E6
142 #define E1000_DEV_ID_82576_SERDES 0x10E7
143 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
144 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
145 #define E1000_DEV_ID_82576_NS 0x150A
146 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
147 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
148 #define E1000_DEV_ID_82576_VF 0x10CA
149 #define E1000_DEV_ID_82576_VF_HV 0x152D
150 #define E1000_DEV_ID_I350_VF 0x1520
151 #define E1000_DEV_ID_I350_VF_HV 0x152F
152 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
153 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
154 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
155 #define E1000_DEV_ID_82580_COPPER 0x150E
156 #define E1000_DEV_ID_82580_FIBER 0x150F
157 #define E1000_DEV_ID_82580_SERDES 0x1510
158 #define E1000_DEV_ID_82580_SGMII 0x1511
159 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
160 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
161 #define E1000_DEV_ID_I350_COPPER 0x1521
162 #define E1000_DEV_ID_I350_FIBER 0x1522
163 #define E1000_DEV_ID_I350_SERDES 0x1523
164 #define E1000_DEV_ID_I350_SGMII 0x1524
165 #define E1000_DEV_ID_I350_DA4 0x1546
166 #define E1000_DEV_ID_I210_COPPER 0x1533
167 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
168 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
169 #define E1000_DEV_ID_I210_FIBER 0x1536
170 #define E1000_DEV_ID_I210_SERDES 0x1537
171 #define E1000_DEV_ID_I210_SGMII 0x1538
172 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
173 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
174 #define E1000_DEV_ID_I211_COPPER 0x1539
175 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
176 #define E1000_DEV_ID_I354_SGMII 0x1F41
177 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
178 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
179 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
180 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
181 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
183 #define E1000_REVISION_0 0
184 #define E1000_REVISION_1 1
185 #define E1000_REVISION_2 2
186 #define E1000_REVISION_3 3
187 #define E1000_REVISION_4 4
189 #define E1000_FUNC_0 0
190 #define E1000_FUNC_1 1
191 #define E1000_FUNC_2 2
192 #define E1000_FUNC_3 3
194 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
195 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
196 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
197 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
199 enum e1000_mac_type {
234 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
237 enum e1000_media_type {
238 e1000_media_type_unknown = 0,
239 e1000_media_type_copper = 1,
240 e1000_media_type_fiber = 2,
241 e1000_media_type_internal_serdes = 3,
242 e1000_num_media_types
245 enum e1000_nvm_type {
246 e1000_nvm_unknown = 0,
248 e1000_nvm_eeprom_spi,
249 e1000_nvm_eeprom_microwire,
255 enum e1000_nvm_override {
256 e1000_nvm_override_none = 0,
257 e1000_nvm_override_spi_small,
258 e1000_nvm_override_spi_large,
259 e1000_nvm_override_microwire_small,
260 e1000_nvm_override_microwire_large
263 enum e1000_phy_type {
264 e1000_phy_unknown = 0,
282 enum e1000_bus_type {
283 e1000_bus_type_unknown = 0,
286 e1000_bus_type_pci_express,
287 e1000_bus_type_reserved
290 enum e1000_bus_speed {
291 e1000_bus_speed_unknown = 0,
297 e1000_bus_speed_2500,
298 e1000_bus_speed_5000,
299 e1000_bus_speed_reserved
302 enum e1000_bus_width {
303 e1000_bus_width_unknown = 0,
304 e1000_bus_width_pcie_x1,
305 e1000_bus_width_pcie_x2,
306 e1000_bus_width_pcie_x4 = 4,
307 e1000_bus_width_pcie_x8 = 8,
310 e1000_bus_width_reserved
313 enum e1000_1000t_rx_status {
314 e1000_1000t_rx_status_not_ok = 0,
315 e1000_1000t_rx_status_ok,
316 e1000_1000t_rx_status_undefined = 0xFF
319 enum e1000_rev_polarity {
320 e1000_rev_polarity_normal = 0,
321 e1000_rev_polarity_reversed,
322 e1000_rev_polarity_undefined = 0xFF
330 e1000_fc_default = 0xFF
333 enum e1000_ffe_config {
334 e1000_ffe_config_enabled = 0,
335 e1000_ffe_config_active,
336 e1000_ffe_config_blocked
339 enum e1000_dsp_config {
340 e1000_dsp_config_disabled = 0,
341 e1000_dsp_config_enabled,
342 e1000_dsp_config_activated,
343 e1000_dsp_config_undefined = 0xFF
347 e1000_ms_hw_default = 0,
348 e1000_ms_force_master,
349 e1000_ms_force_slave,
353 enum e1000_smart_speed {
354 e1000_smart_speed_default = 0,
355 e1000_smart_speed_on,
356 e1000_smart_speed_off
359 enum e1000_serdes_link_state {
360 e1000_serdes_link_down = 0,
361 e1000_serdes_link_autoneg_progress,
362 e1000_serdes_link_autoneg_complete,
363 e1000_serdes_link_forced_up
369 /* Receive Descriptor */
370 struct e1000_rx_desc {
371 __le64 buffer_addr; /* Address of the descriptor's data buffer */
372 __le16 length; /* Length of data DMAed into data buffer */
373 __le16 csum; /* Packet checksum */
374 u8 status; /* Descriptor status */
375 u8 errors; /* Descriptor Errors */
379 /* Receive Descriptor - Extended */
380 union e1000_rx_desc_extended {
387 __le32 mrq; /* Multiple Rx Queues */
389 __le32 rss; /* RSS Hash */
391 __le16 ip_id; /* IP id */
392 __le16 csum; /* Packet Checksum */
397 __le32 status_error; /* ext status/error */
399 __le16 vlan; /* VLAN tag */
401 } wb; /* writeback */
404 #define MAX_PS_BUFFERS 4
406 /* Number of packet split data buffers (not including the header buffer) */
407 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
409 /* Receive Descriptor - Packet Split */
410 union e1000_rx_desc_packet_split {
412 /* one buffer for protocol header(s), three data buffers */
413 __le64 buffer_addr[MAX_PS_BUFFERS];
417 __le32 mrq; /* Multiple Rx Queues */
419 __le32 rss; /* RSS Hash */
421 __le16 ip_id; /* IP id */
422 __le16 csum; /* Packet Checksum */
427 __le32 status_error; /* ext status/error */
428 __le16 length0; /* length of buffer 0 */
429 __le16 vlan; /* VLAN tag */
432 __le16 header_status;
433 /* length of buffers 1-3 */
434 __le16 length[PS_PAGE_BUFFERS];
437 } wb; /* writeback */
440 /* Transmit Descriptor */
441 struct e1000_tx_desc {
442 __le64 buffer_addr; /* Address of the descriptor's data buffer */
446 __le16 length; /* Data buffer length */
447 u8 cso; /* Checksum offset */
448 u8 cmd; /* Descriptor control */
454 u8 status; /* Descriptor status */
455 u8 css; /* Checksum start */
461 /* Offload Context Descriptor */
462 struct e1000_context_desc {
466 u8 ipcss; /* IP checksum start */
467 u8 ipcso; /* IP checksum offset */
468 __le16 ipcse; /* IP checksum end */
474 u8 tucss; /* TCP checksum start */
475 u8 tucso; /* TCP checksum offset */
476 __le16 tucse; /* TCP checksum end */
479 __le32 cmd_and_length;
483 u8 status; /* Descriptor status */
484 u8 hdr_len; /* Header length */
485 __le16 mss; /* Maximum segment size */
490 /* Offload data descriptor */
491 struct e1000_data_desc {
492 __le64 buffer_addr; /* Address of the descriptor's buffer address */
496 __le16 length; /* Data buffer length */
504 u8 status; /* Descriptor status */
505 u8 popts; /* Packet Options */
511 /* Statistics counters collected by the MAC */
512 struct e1000_hw_stats {
595 struct e1000_vf_stats {
627 struct e1000_phy_stats {
632 struct e1000_host_mng_dhcp_cookie {
643 /* Host Interface "Rev 1" */
644 struct e1000_host_command_header {
651 #define E1000_HI_MAX_DATA_LENGTH 252
652 struct e1000_host_command_info {
653 struct e1000_host_command_header command_header;
654 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
657 /* Host Interface "Rev 2" */
658 struct e1000_host_mng_command_header {
666 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
667 struct e1000_host_mng_command_info {
668 struct e1000_host_mng_command_header command_header;
669 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
672 #include "e1000_mac.h"
673 #include "e1000_phy.h"
674 #include "e1000_nvm.h"
675 #include "e1000_manage.h"
676 #include "e1000_mbx.h"
678 /* Function pointers for the MAC. */
679 struct e1000_mac_operations {
680 s32 (*init_params)(struct e1000_hw *);
681 s32 (*id_led_init)(struct e1000_hw *);
682 s32 (*blink_led)(struct e1000_hw *);
683 bool (*check_mng_mode)(struct e1000_hw *);
684 s32 (*check_for_link)(struct e1000_hw *);
685 s32 (*cleanup_led)(struct e1000_hw *);
686 void (*clear_hw_cntrs)(struct e1000_hw *);
687 void (*clear_vfta)(struct e1000_hw *);
688 s32 (*get_bus_info)(struct e1000_hw *);
689 void (*set_lan_id)(struct e1000_hw *);
690 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
691 s32 (*led_on)(struct e1000_hw *);
692 s32 (*led_off)(struct e1000_hw *);
693 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
694 s32 (*reset_hw)(struct e1000_hw *);
695 s32 (*init_hw)(struct e1000_hw *);
696 void (*shutdown_serdes)(struct e1000_hw *);
697 void (*power_up_serdes)(struct e1000_hw *);
698 s32 (*setup_link)(struct e1000_hw *);
699 s32 (*setup_physical_interface)(struct e1000_hw *);
700 s32 (*setup_led)(struct e1000_hw *);
701 void (*write_vfta)(struct e1000_hw *, u32, u32);
702 void (*config_collision_dist)(struct e1000_hw *);
703 int (*rar_set)(struct e1000_hw *, u8*, u32);
704 s32 (*read_mac_addr)(struct e1000_hw *);
705 s32 (*validate_mdi_setting)(struct e1000_hw *);
706 s32 (*set_obff_timer)(struct e1000_hw *, u32);
707 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
708 void (*release_swfw_sync)(struct e1000_hw *, u16);
711 /* When to use various PHY register access functions:
714 * Function Does Does When to use
715 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
716 * X_reg L,P,A n/a for simple PHY reg accesses
717 * X_reg_locked P,A L for multiple accesses of different regs
719 * X_reg_page A L,P for multiple accesses of different regs
722 * Where X=[read|write], L=locking, P=sets page, A=register access
725 struct e1000_phy_operations {
726 s32 (*init_params)(struct e1000_hw *);
727 s32 (*acquire)(struct e1000_hw *);
728 s32 (*cfg_on_link_up)(struct e1000_hw *);
729 s32 (*check_polarity)(struct e1000_hw *);
730 s32 (*check_reset_block)(struct e1000_hw *);
731 s32 (*commit)(struct e1000_hw *);
732 s32 (*force_speed_duplex)(struct e1000_hw *);
733 s32 (*get_cfg_done)(struct e1000_hw *hw);
734 s32 (*get_cable_length)(struct e1000_hw *);
735 s32 (*get_info)(struct e1000_hw *);
736 s32 (*set_page)(struct e1000_hw *, u16);
737 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
738 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
739 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
740 void (*release)(struct e1000_hw *);
741 s32 (*reset)(struct e1000_hw *);
742 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
743 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
744 s32 (*write_reg)(struct e1000_hw *, u32, u16);
745 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
746 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
747 void (*power_up)(struct e1000_hw *);
748 void (*power_down)(struct e1000_hw *);
749 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
750 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
753 /* Function pointers for the NVM. */
754 struct e1000_nvm_operations {
755 s32 (*init_params)(struct e1000_hw *);
756 s32 (*acquire)(struct e1000_hw *);
757 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
758 void (*release)(struct e1000_hw *);
759 void (*reload)(struct e1000_hw *);
760 s32 (*update)(struct e1000_hw *);
761 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
762 s32 (*validate)(struct e1000_hw *);
763 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
766 struct e1000_mac_info {
767 struct e1000_mac_operations ops;
768 u8 addr[ETH_ADDR_LEN];
769 u8 perm_addr[ETH_ADDR_LEN];
771 enum e1000_mac_type type;
789 /* Maximum size of the MTA register table in all supported adapters */
790 #define MAX_MTA_REG 128
791 u32 mta_shadow[MAX_MTA_REG];
794 u8 forced_speed_duplex;
798 bool arc_subsystem_valid;
799 bool asf_firmware_present;
802 bool get_link_status;
804 bool report_tx_early;
805 enum e1000_serdes_link_state serdes_link_state;
806 bool serdes_has_link;
807 bool tx_pkt_filtering;
811 struct e1000_phy_info {
812 struct e1000_phy_operations ops;
813 enum e1000_phy_type type;
815 enum e1000_1000t_rx_status local_rx;
816 enum e1000_1000t_rx_status remote_rx;
817 enum e1000_ms_type ms_type;
818 enum e1000_ms_type original_ms_type;
819 enum e1000_rev_polarity cable_polarity;
820 enum e1000_smart_speed smart_speed;
824 u32 reset_delay_us; /* in usec */
827 enum e1000_media_type media_type;
829 u16 autoneg_advertised;
832 u16 max_cable_length;
833 u16 min_cable_length;
837 bool disable_polarity_correction;
839 bool polarity_correction;
840 bool speed_downgraded;
841 bool autoneg_wait_to_complete;
844 struct e1000_nvm_info {
845 struct e1000_nvm_operations ops;
846 enum e1000_nvm_type type;
847 enum e1000_nvm_override override;
859 struct e1000_bus_info {
860 enum e1000_bus_type type;
861 enum e1000_bus_speed speed;
862 enum e1000_bus_width width;
868 struct e1000_fc_info {
869 u32 high_water; /* Flow control high-water mark */
870 u32 low_water; /* Flow control low-water mark */
871 u16 pause_time; /* Flow control pause timer */
872 u16 refresh_time; /* Flow control refresh timer */
873 bool send_xon; /* Flow control send XON */
874 bool strict_ieee; /* Strict IEEE mode */
875 enum e1000_fc_mode current_mode; /* FC mode in effect */
876 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
879 struct e1000_mbx_operations {
880 s32 (*init_params)(struct e1000_hw *hw);
881 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
882 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
883 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
884 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
885 s32 (*check_for_msg)(struct e1000_hw *, u16);
886 s32 (*check_for_ack)(struct e1000_hw *, u16);
887 s32 (*check_for_rst)(struct e1000_hw *, u16);
890 struct e1000_mbx_stats {
899 struct e1000_mbx_info {
900 struct e1000_mbx_operations ops;
901 struct e1000_mbx_stats stats;
907 struct e1000_dev_spec_82541 {
908 enum e1000_dsp_config dsp_config;
909 enum e1000_ffe_config ffe_config;
911 bool phy_init_script;
914 struct e1000_dev_spec_82542 {
918 struct e1000_dev_spec_82543 {
919 u32 tbi_compatibility;
921 bool init_phy_disabled;
924 struct e1000_dev_spec_82571 {
927 E1000_MUTEX swflag_mutex;
930 struct e1000_dev_spec_80003es2lan {
934 struct e1000_shadow_ram {
939 #define E1000_SHADOW_RAM_WORDS 2048
941 /* I218 PHY Ultra Low Power (ULP) states */
942 enum e1000_ulp_state {
943 e1000_ulp_state_unknown,
948 struct e1000_dev_spec_ich8lan {
949 bool kmrn_lock_loss_workaround_enabled;
950 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
951 E1000_MUTEX nvm_mutex;
952 E1000_MUTEX swflag_mutex;
956 enum e1000_ulp_state ulp_state;
959 struct e1000_dev_spec_82575 {
961 bool global_device_reset;
964 bool clear_semaphore_once;
966 struct sfp_e1000_flags eth_flags;
971 struct e1000_dev_spec_vf {
981 unsigned long io_base;
983 struct e1000_mac_info mac;
984 struct e1000_fc_info fc;
985 struct e1000_phy_info phy;
986 struct e1000_nvm_info nvm;
987 struct e1000_bus_info bus;
988 struct e1000_mbx_info mbx;
989 struct e1000_host_mng_dhcp_cookie mng_cookie;
992 struct e1000_dev_spec_82541 _82541;
993 struct e1000_dev_spec_82542 _82542;
994 struct e1000_dev_spec_82543 _82543;
995 struct e1000_dev_spec_82571 _82571;
996 struct e1000_dev_spec_80003es2lan _80003es2lan;
997 struct e1000_dev_spec_ich8lan ich8lan;
998 struct e1000_dev_spec_82575 _82575;
999 struct e1000_dev_spec_vf vf;
1003 u16 subsystem_vendor_id;
1004 u16 subsystem_device_id;
1010 #include "e1000_82541.h"
1011 #include "e1000_82543.h"
1012 #include "e1000_82571.h"
1013 #include "e1000_80003es2lan.h"
1014 #include "e1000_ich8lan.h"
1015 #include "e1000_82575.h"
1016 #include "e1000_i210.h"
1018 /* These functions must be implemented by drivers */
1019 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1020 void e1000_pci_set_mwi(struct e1000_hw *hw);
1021 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1022 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1023 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1024 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);