1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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32 ******************************************************************************/
36 * 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection
42 * 82566DC-2 Gigabit Network Connection
43 * 82566DC Gigabit Network Connection
44 * 82566DM-2 Gigabit Network Connection
45 * 82566DM Gigabit Network Connection
46 * 82566MC Gigabit Network Connection
47 * 82566MM Gigabit Network Connection
48 * 82567LM Gigabit Network Connection
49 * 82567LF Gigabit Network Connection
50 * 82567V Gigabit Network Connection
51 * 82567LM-2 Gigabit Network Connection
52 * 82567LF-2 Gigabit Network Connection
53 * 82567V-2 Gigabit Network Connection
54 * 82567LF-3 Gigabit Network Connection
55 * 82567LM-3 Gigabit Network Connection
56 * 82567LM-4 Gigabit Network Connection
57 * 82577LM Gigabit Network Connection
58 * 82577LC Gigabit Network Connection
59 * 82578DM Gigabit Network Connection
60 * 82578DC Gigabit Network Connection
63 #include "e1000_api.h"
65 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
66 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
67 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
68 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
69 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
70 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
71 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
72 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
73 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
74 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
75 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
77 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
79 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
80 u16 words, u16 *data);
81 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
82 u16 words, u16 *data);
83 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
84 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
85 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
87 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
88 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
90 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
91 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
92 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
93 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
94 u16 *speed, u16 *duplex);
95 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
96 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
97 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
98 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
99 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
100 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
101 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
102 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
103 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
104 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
105 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
106 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
107 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
110 u32 offset, u8 *data);
111 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
113 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
114 u32 offset, u16 *data);
115 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
116 u32 offset, u8 byte);
117 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
118 u32 offset, u8 data);
119 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
121 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
122 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
124 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
125 /* Offset 04h HSFSTS */
126 union ich8_hws_flash_status {
128 u16 flcdone :1; /* bit 0 Flash Cycle Done */
129 u16 flcerr :1; /* bit 1 Flash Cycle Error */
130 u16 dael :1; /* bit 2 Direct Access error Log */
131 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
132 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
133 u16 reserved1 :2; /* bit 13:6 Reserved */
134 u16 reserved2 :6; /* bit 13:6 Reserved */
135 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
136 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
141 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
142 /* Offset 06h FLCTL */
143 union ich8_hws_flash_ctrl {
144 struct ich8_hsflctl {
145 u16 flcgo :1; /* 0 Flash Cycle Go */
146 u16 flcycle :2; /* 2:1 Flash Cycle */
147 u16 reserved :5; /* 7:3 Reserved */
148 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
149 u16 flockdn :6; /* 15:10 Reserved */
154 /* ICH Flash Region Access Permissions */
155 union ich8_hws_flash_regacc {
157 u32 grra :8; /* 0:7 GbE region Read Access */
158 u32 grwa :8; /* 8:15 GbE region Write Access */
159 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
160 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
166 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
167 * @hw: pointer to the HW structure
169 * Initialize family-specific PHY parameters and function pointers.
171 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
173 struct e1000_phy_info *phy = &hw->phy;
174 s32 ret_val = E1000_SUCCESS;
176 DEBUGFUNC("e1000_init_phy_params_pchlan");
179 phy->reset_delay_us = 100;
181 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
182 phy->ops.check_polarity = e1000_check_polarity_ife;
183 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
184 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
185 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
186 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
187 phy->ops.get_info = e1000_get_phy_info_ich8lan;
188 phy->ops.read_reg = e1000_read_phy_reg_hv;
189 phy->ops.release = e1000_release_swflag_ich8lan;
190 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
191 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
192 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
193 phy->ops.write_reg = e1000_write_phy_reg_hv;
194 phy->ops.power_up = e1000_power_up_phy_copper;
195 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
196 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
198 phy->id = e1000_phy_unknown;
199 e1000_get_phy_id(hw);
200 phy->type = e1000_get_phy_type_from_id(phy->id);
202 if (phy->type == e1000_phy_82577) {
203 phy->ops.check_polarity = e1000_check_polarity_82577;
204 phy->ops.force_speed_duplex =
205 e1000_phy_force_speed_duplex_82577;
206 phy->ops.get_cable_length = e1000_get_cable_length_82577;
207 phy->ops.get_info = e1000_get_phy_info_82577;
208 phy->ops.commit = e1000_phy_sw_reset_generic;
215 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
216 * @hw: pointer to the HW structure
218 * Initialize family-specific PHY parameters and function pointers.
220 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
222 struct e1000_phy_info *phy = &hw->phy;
223 s32 ret_val = E1000_SUCCESS;
226 DEBUGFUNC("e1000_init_phy_params_ich8lan");
229 phy->reset_delay_us = 100;
231 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
232 phy->ops.check_polarity = e1000_check_polarity_ife;
233 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
234 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
235 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
236 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
237 phy->ops.get_info = e1000_get_phy_info_ich8lan;
238 phy->ops.read_reg = e1000_read_phy_reg_igp;
239 phy->ops.release = e1000_release_swflag_ich8lan;
240 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
241 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
242 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
243 phy->ops.write_reg = e1000_write_phy_reg_igp;
244 phy->ops.power_up = e1000_power_up_phy_copper;
245 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
248 * We may need to do this twice - once for IGP and if that fails,
249 * we'll set BM func pointers and try again
251 ret_val = e1000_determine_phy_address(hw);
253 phy->ops.write_reg = e1000_write_phy_reg_bm;
254 phy->ops.read_reg = e1000_read_phy_reg_bm;
255 ret_val = e1000_determine_phy_address(hw);
257 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
263 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
266 ret_val = e1000_get_phy_id(hw);
273 case IGP03E1000_E_PHY_ID:
274 phy->type = e1000_phy_igp_3;
275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
278 case IFE_PLUS_E_PHY_ID:
280 phy->type = e1000_phy_ife;
281 phy->autoneg_mask = E1000_ALL_NOT_GIG;
283 case BME1000_E_PHY_ID:
284 phy->type = e1000_phy_bm;
285 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
286 phy->ops.read_reg = e1000_read_phy_reg_bm;
287 phy->ops.write_reg = e1000_write_phy_reg_bm;
288 phy->ops.commit = e1000_phy_sw_reset_generic;
291 ret_val = -E1000_ERR_PHY;
300 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
301 * @hw: pointer to the HW structure
303 * Initialize family-specific NVM parameters and function
306 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
308 struct e1000_nvm_info *nvm = &hw->nvm;
309 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
310 u32 gfpreg, sector_base_addr, sector_end_addr;
311 s32 ret_val = E1000_SUCCESS;
314 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
316 /* Can't read flash registers if the register set isn't mapped. */
317 if (!hw->flash_address) {
318 DEBUGOUT("ERROR: Flash registers not mapped\n");
319 ret_val = -E1000_ERR_CONFIG;
323 nvm->type = e1000_nvm_flash_sw;
325 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
328 * sector_X_addr is a "sector"-aligned address (4096 bytes)
329 * Add 1 to sector_end_addr since this sector is included in
332 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
333 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
335 /* flash_base_addr is byte-aligned */
336 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
339 * find total size of the NVM, then cut in half since the total
340 * size represents two separate NVM banks.
342 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
343 << FLASH_SECTOR_ADDR_SHIFT;
344 nvm->flash_bank_size /= 2;
345 /* Adjust to word count */
346 nvm->flash_bank_size /= sizeof(u16);
348 nvm->word_size = E1000_SHADOW_RAM_WORDS;
350 /* Clear shadow ram */
351 for (i = 0; i < nvm->word_size; i++) {
352 dev_spec->shadow_ram[i].modified = FALSE;
353 dev_spec->shadow_ram[i].value = 0xFFFF;
356 /* Function Pointers */
357 nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
358 nvm->ops.read = e1000_read_nvm_ich8lan;
359 nvm->ops.release = e1000_release_swflag_ich8lan;
360 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
361 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
362 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
363 nvm->ops.write = e1000_write_nvm_ich8lan;
370 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
371 * @hw: pointer to the HW structure
373 * Initialize family-specific MAC parameters and function
376 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
378 struct e1000_mac_info *mac = &hw->mac;
381 DEBUGFUNC("e1000_init_mac_params_ich8lan");
383 /* Set media type function pointer */
384 hw->phy.media_type = e1000_media_type_copper;
386 /* Set mta register count */
387 mac->mta_reg_count = 32;
388 /* Set rar entry count */
389 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
390 if (mac->type == e1000_ich8lan)
391 mac->rar_entry_count--;
392 /* Set if part includes ASF firmware */
393 mac->asf_firmware_present = TRUE;
394 /* Set if manageability features are enabled. */
395 mac->arc_subsystem_valid = TRUE;
397 /* Function pointers */
399 /* bus type/speed/width */
400 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
402 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
404 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
405 /* hw initialization */
406 mac->ops.init_hw = e1000_init_hw_ich8lan;
408 mac->ops.setup_link = e1000_setup_link_ich8lan;
409 /* physical interface setup */
410 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
412 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
413 /* check management mode */
414 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
416 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
417 /* multicast address update */
418 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
420 mac->ops.mta_set = e1000_mta_set_generic;
421 /* clear hardware counters */
422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
430 mac->ops.id_led_init = e1000_id_led_init_generic;
432 mac->ops.blink_led = e1000_blink_led_generic;
434 mac->ops.setup_led = e1000_setup_led_generic;
436 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
437 /* turn on/off LED */
438 mac->ops.led_on = e1000_led_on_ich8lan;
439 mac->ops.led_off = e1000_led_off_ich8lan;
442 /* save PCH revision_id */
443 e1000_read_pci_cfg(hw, 0x2, &pci_cfg);
444 hw->revision_id = (u8)(pci_cfg &= 0x000F);
446 mac->ops.id_led_init = e1000_id_led_init_pchlan;
448 mac->ops.setup_led = e1000_setup_led_pchlan;
450 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
451 /* turn on/off LED */
452 mac->ops.led_on = e1000_led_on_pchlan;
453 mac->ops.led_off = e1000_led_off_pchlan;
459 /* Enable PCS Lock-loss workaround for ICH8 */
460 if (mac->type == e1000_ich8lan)
461 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
464 return E1000_SUCCESS;
468 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
469 * @hw: pointer to the HW structure
471 * Initialize family-specific function pointers for PHY, MAC, and NVM.
473 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
475 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
477 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
478 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
479 switch (hw->mac.type) {
483 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
486 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
494 * e1000_acquire_swflag_ich8lan - Acquire software control flag
495 * @hw: pointer to the HW structure
497 * Acquires the software control flag for performing NVM and PHY
498 * operations. This is a function pointer entry point only called by
499 * read/write routines for the PHY and NVM parts.
501 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
503 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
504 s32 ret_val = E1000_SUCCESS;
506 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
509 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
511 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
512 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
513 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
515 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
516 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
524 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
525 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
526 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
527 ret_val = -E1000_ERR_CONFIG;
536 * e1000_release_swflag_ich8lan - Release software control flag
537 * @hw: pointer to the HW structure
539 * Releases the software control flag for performing NVM and PHY operations.
540 * This is a function pointer entry point only called by read/write
541 * routines for the PHY and NVM parts.
543 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
547 DEBUGFUNC("e1000_release_swflag_ich8lan");
549 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
550 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
551 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
557 * e1000_check_mng_mode_ich8lan - Checks management mode
558 * @hw: pointer to the HW structure
560 * This checks if the adapter has manageability enabled.
561 * This is a function pointer entry point only called by read/write
562 * routines for the PHY and NVM parts.
564 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
568 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
570 fwsm = E1000_READ_REG(hw, E1000_FWSM);
572 return (fwsm & E1000_FWSM_MODE_MASK) ==
573 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
577 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
578 * @hw: pointer to the HW structure
580 * Checks if firmware is blocking the reset of the PHY.
581 * This is a function pointer entry point only called by
584 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
588 DEBUGFUNC("e1000_check_reset_block_ich8lan");
590 fwsm = E1000_READ_REG(hw, E1000_FWSM);
592 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
593 : E1000_BLK_PHY_RESET;
597 * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
598 * @hw: pointer to the HW structure
600 s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
602 if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
603 return E1000_SUCCESS;
605 return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444);
609 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
610 * done after every PHY reset.
612 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
614 s32 ret_val = E1000_SUCCESS;
616 if (hw->mac.type != e1000_pchlan)
619 /* Hanksville M Phy init for IEEE. */
620 if ((hw->revision_id == 2) &&
621 (hw->phy.type == e1000_phy_82577) &&
622 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
623 hw->phy.ops.write_reg(hw, 0x10, 0x8823);
624 hw->phy.ops.write_reg(hw, 0x11, 0x0018);
625 hw->phy.ops.write_reg(hw, 0x10, 0x8824);
626 hw->phy.ops.write_reg(hw, 0x11, 0x0016);
627 hw->phy.ops.write_reg(hw, 0x10, 0x8825);
628 hw->phy.ops.write_reg(hw, 0x11, 0x001A);
629 hw->phy.ops.write_reg(hw, 0x10, 0x888C);
630 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
631 hw->phy.ops.write_reg(hw, 0x10, 0x888D);
632 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
633 hw->phy.ops.write_reg(hw, 0x10, 0x888E);
634 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
635 hw->phy.ops.write_reg(hw, 0x10, 0x8827);
636 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
637 hw->phy.ops.write_reg(hw, 0x10, 0x8835);
638 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
639 hw->phy.ops.write_reg(hw, 0x10, 0x8834);
640 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
641 hw->phy.ops.write_reg(hw, 0x10, 0x8833);
642 hw->phy.ops.write_reg(hw, 0x11, 0x0002);
645 if (((hw->phy.type == e1000_phy_82577) &&
646 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
647 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
648 /* Disable generation of early preamble */
649 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
653 /* Preamble tuning for SSC */
654 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
659 if (hw->phy.type == e1000_phy_82578) {
660 if (hw->revision_id < 3) {
662 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
668 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
675 * Return registers to default by doing a soft reset then
676 * writing 0x3140 to the control register.
678 if (hw->phy.revision < 2) {
679 e1000_phy_sw_reset_generic(hw);
680 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
685 if ((hw->revision_id == 2) &&
686 (hw->phy.type == e1000_phy_82577) &&
687 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
689 * Workaround for OEM (GbE) not operating after reset -
692 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
695 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
701 ret_val = hw->phy.ops.acquire(hw);
705 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
706 hw->phy.ops.release(hw);
712 * e1000_lan_init_done_ich8lan - Check for PHY config completion
713 * @hw: pointer to the HW structure
715 * Check the appropriate indication the MAC has finished configuring the
716 * PHY after a software reset.
718 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
720 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
722 DEBUGFUNC("e1000_lan_init_done_ich8lan");
724 /* Wait for basic configuration completes before proceeding */
726 data = E1000_READ_REG(hw, E1000_STATUS);
727 data &= E1000_STATUS_LAN_INIT_DONE;
729 } while ((!data) && --loop);
732 * If basic configuration is incomplete before the above loop
733 * count reaches 0, loading the configuration from NVM will
734 * leave the PHY in a bad state possibly resulting in no link.
737 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
739 /* Clear the Init Done bit for the next init event */
740 data = E1000_READ_REG(hw, E1000_STATUS);
741 data &= ~E1000_STATUS_LAN_INIT_DONE;
742 E1000_WRITE_REG(hw, E1000_STATUS, data);
746 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
747 * @hw: pointer to the HW structure
750 * This is a function pointer entry point called by drivers
751 * or other shared routines.
753 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
755 struct e1000_phy_info *phy = &hw->phy;
756 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
758 u16 word_addr, reg_data, reg_addr, phy_page = 0;
760 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
762 ret_val = e1000_phy_hw_reset_generic(hw);
766 /* Allow time for h/w to get to a quiescent state after reset */
769 if (hw->mac.type == e1000_pchlan) {
770 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
776 * Initialize the PHY from the NVM on ICH platforms. This
777 * is needed due to an issue where the NVM configuration is
778 * not properly autoloaded after power transitions.
779 * Therefore, after each PHY reset, we will load the
780 * configuration data out of the NVM manually.
782 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
783 /* Check if SW needs configure the PHY */
784 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
785 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
786 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
788 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
790 data = E1000_READ_REG(hw, E1000_FEXTNVM);
791 if (!(data & sw_cfg_mask))
794 /* Wait for basic configuration completes before proceeding */
795 e1000_lan_init_done_ich8lan(hw);
798 * Make sure HW does not configure LCD from PHY
799 * extended configuration before SW configuration
801 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
802 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
805 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
806 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
807 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
811 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
812 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
814 /* Configure LCD from extended configuration region. */
816 /* cnf_base_addr is in DWORD */
817 word_addr = (u16)(cnf_base_addr << 1);
819 for (i = 0; i < cnf_size; i++) {
820 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
825 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
830 /* Save off the PHY page for future writes. */
831 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
836 reg_addr |= phy_page;
838 ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data);
849 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
850 * @hw: pointer to the HW structure
852 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
854 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
856 s32 ret_val = -E1000_ERR_PHY_TYPE;
858 DEBUGFUNC("e1000_get_phy_info_ich8lan");
860 switch (hw->phy.type) {
862 ret_val = e1000_get_phy_info_ife_ich8lan(hw);
864 case e1000_phy_igp_3:
866 case e1000_phy_82578:
867 case e1000_phy_82577:
868 ret_val = e1000_get_phy_info_igp(hw);
878 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
879 * @hw: pointer to the HW structure
881 * Populates "phy" structure with various feature states.
882 * This function is only called by other family-specific
885 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
887 struct e1000_phy_info *phy = &hw->phy;
892 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
894 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
899 DEBUGOUT("Phy info is only valid if link is up\n");
900 ret_val = -E1000_ERR_CONFIG;
904 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
907 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
910 if (phy->polarity_correction) {
911 ret_val = e1000_check_polarity_ife(hw);
915 /* Polarity is forced */
916 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
917 ? e1000_rev_polarity_reversed
918 : e1000_rev_polarity_normal;
921 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
925 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
927 /* The following parameters are undefined for 10/100 operation. */
928 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
929 phy->local_rx = e1000_1000t_rx_status_undefined;
930 phy->remote_rx = e1000_1000t_rx_status_undefined;
937 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
938 * @hw: pointer to the HW structure
939 * @active: TRUE to enable LPLU, FALSE to disable
941 * Sets the LPLU D0 state according to the active flag. When
942 * activating LPLU this function also disables smart speed
943 * and vice versa. LPLU will not be activated unless the
944 * device autonegotiation advertisement meets standards of
945 * either 10 or 10/100 or 10/100/1000 at all duplexes.
946 * This is a function pointer entry point only called by
947 * PHY setup routines.
949 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
951 struct e1000_phy_info *phy = &hw->phy;
953 s32 ret_val = E1000_SUCCESS;
956 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
958 if (phy->type == e1000_phy_ife)
961 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
964 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
965 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
967 if (phy->type != e1000_phy_igp_3)
971 * Call gig speed drop workaround on LPLU before accessing
974 if (hw->mac.type == e1000_ich8lan)
975 e1000_gig_downshift_workaround_ich8lan(hw);
977 /* When LPLU is enabled, we should disable SmartSpeed */
978 ret_val = phy->ops.read_reg(hw,
979 IGP01E1000_PHY_PORT_CONFIG,
981 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
982 ret_val = phy->ops.write_reg(hw,
983 IGP01E1000_PHY_PORT_CONFIG,
988 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
989 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
991 if (phy->type != e1000_phy_igp_3)
995 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
996 * during Dx states where the power conservation is most
997 * important. During driver activity we should enable
998 * SmartSpeed, so performance is maintained.
1000 if (phy->smart_speed == e1000_smart_speed_on) {
1001 ret_val = phy->ops.read_reg(hw,
1002 IGP01E1000_PHY_PORT_CONFIG,
1007 data |= IGP01E1000_PSCFR_SMART_SPEED;
1008 ret_val = phy->ops.write_reg(hw,
1009 IGP01E1000_PHY_PORT_CONFIG,
1013 } else if (phy->smart_speed == e1000_smart_speed_off) {
1014 ret_val = phy->ops.read_reg(hw,
1015 IGP01E1000_PHY_PORT_CONFIG,
1020 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1021 ret_val = phy->ops.write_reg(hw,
1022 IGP01E1000_PHY_PORT_CONFIG,
1034 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1035 * @hw: pointer to the HW structure
1036 * @active: TRUE to enable LPLU, FALSE to disable
1038 * Sets the LPLU D3 state according to the active flag. When
1039 * activating LPLU this function also disables smart speed
1040 * and vice versa. LPLU will not be activated unless the
1041 * device autonegotiation advertisement meets standards of
1042 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1043 * This is a function pointer entry point only called by
1044 * PHY setup routines.
1046 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1048 struct e1000_phy_info *phy = &hw->phy;
1050 s32 ret_val = E1000_SUCCESS;
1053 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
1055 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
1058 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1059 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1061 if (phy->type != e1000_phy_igp_3)
1065 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1066 * during Dx states where the power conservation is most
1067 * important. During driver activity we should enable
1068 * SmartSpeed, so performance is maintained.
1070 if (phy->smart_speed == e1000_smart_speed_on) {
1071 ret_val = phy->ops.read_reg(hw,
1072 IGP01E1000_PHY_PORT_CONFIG,
1077 data |= IGP01E1000_PSCFR_SMART_SPEED;
1078 ret_val = phy->ops.write_reg(hw,
1079 IGP01E1000_PHY_PORT_CONFIG,
1083 } else if (phy->smart_speed == e1000_smart_speed_off) {
1084 ret_val = phy->ops.read_reg(hw,
1085 IGP01E1000_PHY_PORT_CONFIG,
1090 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1091 ret_val = phy->ops.write_reg(hw,
1092 IGP01E1000_PHY_PORT_CONFIG,
1097 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1098 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1099 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1100 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1101 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
1103 if (phy->type != e1000_phy_igp_3)
1107 * Call gig speed drop workaround on LPLU before accessing
1110 if (hw->mac.type == e1000_ich8lan)
1111 e1000_gig_downshift_workaround_ich8lan(hw);
1113 /* When LPLU is enabled, we should disable SmartSpeed */
1114 ret_val = phy->ops.read_reg(hw,
1115 IGP01E1000_PHY_PORT_CONFIG,
1120 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1121 ret_val = phy->ops.write_reg(hw,
1122 IGP01E1000_PHY_PORT_CONFIG,
1131 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1132 * @hw: pointer to the HW structure
1133 * @bank: pointer to the variable that returns the active bank
1135 * Reads signature byte from the NVM using the flash access registers.
1136 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1138 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1141 struct e1000_nvm_info *nvm = &hw->nvm;
1142 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1143 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1145 s32 ret_val = E1000_SUCCESS;
1147 switch (hw->mac.type) {
1150 eecd = E1000_READ_REG(hw, E1000_EECD);
1151 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1152 E1000_EECD_SEC1VAL_VALID_MASK) {
1153 if (eecd & E1000_EECD_SEC1VAL)
1160 DEBUGOUT("Unable to determine valid NVM bank via EEC - "
1161 "reading flash signature\n");
1164 /* set bank to 0 in case flash read fails */
1168 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1172 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1173 E1000_ICH_NVM_SIG_VALUE) {
1179 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1184 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1185 E1000_ICH_NVM_SIG_VALUE) {
1190 DEBUGOUT("ERROR: No valid NVM bank present\n");
1191 ret_val = -E1000_ERR_NVM;
1199 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1200 * @hw: pointer to the HW structure
1201 * @offset: The offset (in bytes) of the word(s) to read.
1202 * @words: Size of data to read in words
1203 * @data: Pointer to the word(s) to read at offset.
1205 * Reads a word(s) from the NVM using the flash access registers.
1207 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1210 struct e1000_nvm_info *nvm = &hw->nvm;
1211 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1213 s32 ret_val = E1000_SUCCESS;
1217 DEBUGFUNC("e1000_read_nvm_ich8lan");
1219 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1221 DEBUGOUT("nvm parameter(s) out of bounds\n");
1222 ret_val = -E1000_ERR_NVM;
1226 ret_val = nvm->ops.acquire(hw);
1230 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1231 if (ret_val != E1000_SUCCESS)
1234 act_offset = (bank) ? nvm->flash_bank_size : 0;
1235 act_offset += offset;
1237 for (i = 0; i < words; i++) {
1238 if ((dev_spec->shadow_ram) &&
1239 (dev_spec->shadow_ram[offset+i].modified)) {
1240 data[i] = dev_spec->shadow_ram[offset+i].value;
1242 ret_val = e1000_read_flash_word_ich8lan(hw,
1252 nvm->ops.release(hw);
1256 DEBUGOUT1("NVM read error: %d\n", ret_val);
1262 * e1000_flash_cycle_init_ich8lan - Initialize flash
1263 * @hw: pointer to the HW structure
1265 * This function does initial flash setup so that a new read/write/erase cycle
1268 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1270 union ich8_hws_flash_status hsfsts;
1271 s32 ret_val = -E1000_ERR_NVM;
1274 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1276 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1278 /* Check if the flash descriptor is valid */
1279 if (hsfsts.hsf_status.fldesvalid == 0) {
1280 DEBUGOUT("Flash descriptor invalid. "
1281 "SW Sequencing must be used.");
1285 /* Clear FCERR and DAEL in hw status by writing 1 */
1286 hsfsts.hsf_status.flcerr = 1;
1287 hsfsts.hsf_status.dael = 1;
1289 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1292 * Either we should have a hardware SPI cycle in progress
1293 * bit to check against, in order to start a new cycle or
1294 * FDONE bit should be changed in the hardware so that it
1295 * is 1 after hardware reset, which can then be used as an
1296 * indication whether a cycle is in progress or has been
1300 if (hsfsts.hsf_status.flcinprog == 0) {
1302 * There is no cycle running at present,
1303 * so we can start a cycle.
1304 * Begin by setting Flash Cycle Done.
1306 hsfsts.hsf_status.flcdone = 1;
1307 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1308 ret_val = E1000_SUCCESS;
1311 * Otherwise poll for sometime so the current
1312 * cycle has a chance to end before giving up.
1314 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1315 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1317 if (hsfsts.hsf_status.flcinprog == 0) {
1318 ret_val = E1000_SUCCESS;
1323 if (ret_val == E1000_SUCCESS) {
1325 * Successful in waiting for previous cycle to timeout,
1326 * now set the Flash Cycle Done.
1328 hsfsts.hsf_status.flcdone = 1;
1329 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
1332 DEBUGOUT("Flash controller busy, cannot get access");
1341 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1342 * @hw: pointer to the HW structure
1343 * @timeout: maximum time to wait for completion
1345 * This function starts a flash cycle and waits for its completion.
1347 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1349 union ich8_hws_flash_ctrl hsflctl;
1350 union ich8_hws_flash_status hsfsts;
1351 s32 ret_val = -E1000_ERR_NVM;
1354 DEBUGFUNC("e1000_flash_cycle_ich8lan");
1356 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1357 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1358 hsflctl.hsf_ctrl.flcgo = 1;
1359 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1361 /* wait till FDONE bit is set to 1 */
1363 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1364 if (hsfsts.hsf_status.flcdone == 1)
1367 } while (i++ < timeout);
1369 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1370 ret_val = E1000_SUCCESS;
1376 * e1000_read_flash_word_ich8lan - Read word from flash
1377 * @hw: pointer to the HW structure
1378 * @offset: offset to data location
1379 * @data: pointer to the location for storing the data
1381 * Reads the flash word at offset into data. Offset is converted
1382 * to bytes before read.
1384 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1389 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1392 ret_val = -E1000_ERR_NVM;
1396 /* Must convert offset into bytes. */
1399 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1406 * e1000_read_flash_byte_ich8lan - Read byte from flash
1407 * @hw: pointer to the HW structure
1408 * @offset: The offset of the byte to read.
1409 * @data: Pointer to a byte to store the value read.
1411 * Reads a single byte from the NVM using the flash access registers.
1413 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1416 s32 ret_val = E1000_SUCCESS;
1419 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1430 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1431 * @hw: pointer to the HW structure
1432 * @offset: The offset (in bytes) of the byte or word to read.
1433 * @size: Size of data to read, 1=byte 2=word
1434 * @data: Pointer to the word to store the value read.
1436 * Reads a byte or word from the NVM using the flash access registers.
1438 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1441 union ich8_hws_flash_status hsfsts;
1442 union ich8_hws_flash_ctrl hsflctl;
1443 u32 flash_linear_addr;
1445 s32 ret_val = -E1000_ERR_NVM;
1448 DEBUGFUNC("e1000_read_flash_data_ich8lan");
1450 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1453 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1454 hw->nvm.flash_base_addr;
1459 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1460 if (ret_val != E1000_SUCCESS)
1463 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1464 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1465 hsflctl.hsf_ctrl.fldbcount = size - 1;
1466 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1467 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1469 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1471 ret_val = e1000_flash_cycle_ich8lan(hw,
1472 ICH_FLASH_READ_COMMAND_TIMEOUT);
1475 * Check if FCERR is set to 1, if set to 1, clear it
1476 * and try the whole sequence a few more times, else
1477 * read in (shift in) the Flash Data0, the order is
1478 * least significant byte first msb to lsb
1480 if (ret_val == E1000_SUCCESS) {
1481 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1483 *data = (u8)(flash_data & 0x000000FF);
1485 *data = (u16)(flash_data & 0x0000FFFF);
1489 * If we've gotten here, then things are probably
1490 * completely hosed, but if the error condition is
1491 * detected, it won't hurt to give it another try...
1492 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1494 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1496 if (hsfsts.hsf_status.flcerr == 1) {
1497 /* Repeat for some time before giving up. */
1499 } else if (hsfsts.hsf_status.flcdone == 0) {
1500 DEBUGOUT("Timeout error - flash cycle "
1501 "did not complete.");
1505 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1512 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1513 * @hw: pointer to the HW structure
1514 * @offset: The offset (in bytes) of the word(s) to write.
1515 * @words: Size of data to write in words
1516 * @data: Pointer to the word(s) to write at offset.
1518 * Writes a byte or word to the NVM using the flash access registers.
1520 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1523 struct e1000_nvm_info *nvm = &hw->nvm;
1524 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1525 s32 ret_val = E1000_SUCCESS;
1528 DEBUGFUNC("e1000_write_nvm_ich8lan");
1530 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1532 DEBUGOUT("nvm parameter(s) out of bounds\n");
1533 ret_val = -E1000_ERR_NVM;
1537 ret_val = nvm->ops.acquire(hw);
1541 for (i = 0; i < words; i++) {
1542 dev_spec->shadow_ram[offset+i].modified = TRUE;
1543 dev_spec->shadow_ram[offset+i].value = data[i];
1546 nvm->ops.release(hw);
1553 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1554 * @hw: pointer to the HW structure
1556 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1557 * which writes the checksum to the shadow ram. The changes in the shadow
1558 * ram are then committed to the EEPROM by processing each bank at a time
1559 * checking for the modified bit and writing only the pending changes.
1560 * After a successful commit, the shadow ram is cleared and is ready for
1563 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1565 struct e1000_nvm_info *nvm = &hw->nvm;
1566 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1567 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1571 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1573 ret_val = e1000_update_nvm_checksum_generic(hw);
1577 if (nvm->type != e1000_nvm_flash_sw)
1580 ret_val = nvm->ops.acquire(hw);
1585 * We're writing to the opposite bank so if we're on bank 1,
1586 * write to bank 0 etc. We also need to erase the segment that
1587 * is going to be written
1589 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1590 if (ret_val != E1000_SUCCESS) {
1591 nvm->ops.release(hw);
1596 new_bank_offset = nvm->flash_bank_size;
1597 old_bank_offset = 0;
1598 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1600 nvm->ops.release(hw);
1604 old_bank_offset = nvm->flash_bank_size;
1605 new_bank_offset = 0;
1606 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1608 nvm->ops.release(hw);
1613 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1615 * Determine whether to write the value stored
1616 * in the other NVM bank or a modified value stored
1619 if (dev_spec->shadow_ram[i].modified) {
1620 data = dev_spec->shadow_ram[i].value;
1622 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1630 * If the word is 0x13, then make sure the signature bits
1631 * (15:14) are 11b until the commit has completed.
1632 * This will allow us to write 10b which indicates the
1633 * signature is valid. We want to do this after the write
1634 * has completed so that we don't mark the segment valid
1635 * while the write is still in progress
1637 if (i == E1000_ICH_NVM_SIG_WORD)
1638 data |= E1000_ICH_NVM_SIG_MASK;
1640 /* Convert offset to bytes. */
1641 act_offset = (i + new_bank_offset) << 1;
1644 /* Write the bytes to the new bank. */
1645 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1652 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1660 * Don't bother writing the segment valid bits if sector
1661 * programming failed.
1664 DEBUGOUT("Flash commit failed.\n");
1665 nvm->ops.release(hw);
1670 * Finally validate the new segment by setting bit 15:14
1671 * to 10b in word 0x13 , this can be done without an
1672 * erase as well since these bits are 11 to start with
1673 * and we need to change bit 14 to 0b
1675 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1676 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1678 nvm->ops.release(hw);
1682 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1686 nvm->ops.release(hw);
1691 * And invalidate the previously valid segment by setting
1692 * its signature word (0x13) high_byte to 0b. This can be
1693 * done without an erase because flash erase sets all bits
1694 * to 1's. We can write 1's to 0's without an erase
1696 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1697 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1699 nvm->ops.release(hw);
1703 /* Great! Everything worked, we can now clear the cached entries. */
1704 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1705 dev_spec->shadow_ram[i].modified = FALSE;
1706 dev_spec->shadow_ram[i].value = 0xFFFF;
1709 nvm->ops.release(hw);
1712 * Reload the EEPROM, or else modifications will not appear
1713 * until after the next adapter reset.
1715 nvm->ops.reload(hw);
1720 DEBUGOUT1("NVM update error: %d\n", ret_val);
1726 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1727 * @hw: pointer to the HW structure
1729 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1730 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1731 * calculated, in which case we need to calculate the checksum and set bit 6.
1733 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1735 s32 ret_val = E1000_SUCCESS;
1738 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1741 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1742 * needs to be fixed. This bit is an indication that the NVM
1743 * was prepared by OEM software and did not calculate the
1744 * checksum...a likely scenario.
1746 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
1750 if ((data & 0x40) == 0) {
1752 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
1755 ret_val = hw->nvm.ops.update(hw);
1760 ret_val = e1000_validate_nvm_checksum_generic(hw);
1767 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1768 * @hw: pointer to the HW structure
1769 * @offset: The offset (in bytes) of the byte/word to read.
1770 * @size: Size of data to read, 1=byte 2=word
1771 * @data: The byte(s) to write to the NVM.
1773 * Writes one/two bytes to the NVM using the flash access registers.
1775 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1778 union ich8_hws_flash_status hsfsts;
1779 union ich8_hws_flash_ctrl hsflctl;
1780 u32 flash_linear_addr;
1782 s32 ret_val = -E1000_ERR_NVM;
1785 DEBUGFUNC("e1000_write_ich8_data");
1787 if (size < 1 || size > 2 || data > size * 0xff ||
1788 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1791 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1792 hw->nvm.flash_base_addr;
1797 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1798 if (ret_val != E1000_SUCCESS)
1801 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1802 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1803 hsflctl.hsf_ctrl.fldbcount = size - 1;
1804 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1805 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1807 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1810 flash_data = (u32)data & 0x00FF;
1812 flash_data = (u32)data;
1814 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
1817 * check if FCERR is set to 1 , if set to 1, clear it
1818 * and try the whole sequence a few more times else done
1820 ret_val = e1000_flash_cycle_ich8lan(hw,
1821 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1822 if (ret_val == E1000_SUCCESS)
1826 * If we're here, then things are most likely
1827 * completely hosed, but if the error condition
1828 * is detected, it won't hurt to give it another
1829 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1831 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1832 if (hsfsts.hsf_status.flcerr == 1) {
1833 /* Repeat for some time before giving up. */
1835 } else if (hsfsts.hsf_status.flcdone == 0) {
1836 DEBUGOUT("Timeout error - flash cycle "
1837 "did not complete.");
1840 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1847 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1848 * @hw: pointer to the HW structure
1849 * @offset: The index of the byte to read.
1850 * @data: The byte to write to the NVM.
1852 * Writes a single byte to the NVM using the flash access registers.
1854 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1857 u16 word = (u16)data;
1859 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1861 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1865 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1866 * @hw: pointer to the HW structure
1867 * @offset: The offset of the byte to write.
1868 * @byte: The byte to write to the NVM.
1870 * Writes a single byte to the NVM using the flash access registers.
1871 * Goes through a retry algorithm before giving up.
1873 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1874 u32 offset, u8 byte)
1877 u16 program_retries;
1879 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
1881 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1882 if (ret_val == E1000_SUCCESS)
1885 for (program_retries = 0; program_retries < 100; program_retries++) {
1886 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
1888 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1889 if (ret_val == E1000_SUCCESS)
1892 if (program_retries == 100) {
1893 ret_val = -E1000_ERR_NVM;
1902 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1903 * @hw: pointer to the HW structure
1904 * @bank: 0 for first bank, 1 for second bank, etc.
1906 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1907 * bank N is 4096 * N + flash_reg_addr.
1909 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1911 struct e1000_nvm_info *nvm = &hw->nvm;
1912 union ich8_hws_flash_status hsfsts;
1913 union ich8_hws_flash_ctrl hsflctl;
1914 u32 flash_linear_addr;
1915 /* bank size is in 16bit words - adjust to bytes */
1916 u32 flash_bank_size = nvm->flash_bank_size * 2;
1917 s32 ret_val = E1000_SUCCESS;
1919 s32 j, iteration, sector_size;
1921 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
1923 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1926 * Determine HW Sector size: Read BERASE bits of hw flash status
1928 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1929 * consecutive sectors. The start index for the nth Hw sector
1930 * can be calculated as = bank * 4096 + n * 256
1931 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1932 * The start index for the nth Hw sector can be calculated
1934 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1935 * (ich9 only, otherwise error condition)
1936 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1938 switch (hsfsts.hsf_status.berasesz) {
1940 /* Hw sector size 256 */
1941 sector_size = ICH_FLASH_SEG_SIZE_256;
1942 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1945 sector_size = ICH_FLASH_SEG_SIZE_4K;
1949 sector_size = ICH_FLASH_SEG_SIZE_8K;
1953 sector_size = ICH_FLASH_SEG_SIZE_64K;
1957 ret_val = -E1000_ERR_NVM;
1961 /* Start with the base address, then add the sector offset. */
1962 flash_linear_addr = hw->nvm.flash_base_addr;
1963 flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1965 for (j = 0; j < iteration ; j++) {
1968 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1973 * Write a value 11 (block Erase) in Flash
1974 * Cycle field in hw flash control
1976 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
1978 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1979 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
1983 * Write the last 24 bits of an index within the
1984 * block into Flash Linear address field in Flash
1987 flash_linear_addr += (j * sector_size);
1988 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
1991 ret_val = e1000_flash_cycle_ich8lan(hw,
1992 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1993 if (ret_val == E1000_SUCCESS)
1997 * Check if FCERR is set to 1. If 1,
1998 * clear it and try the whole sequence
1999 * a few more times else Done
2001 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2003 if (hsfsts.hsf_status.flcerr == 1)
2004 /* repeat for some time before giving up */
2006 else if (hsfsts.hsf_status.flcdone == 0)
2008 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2016 * e1000_valid_led_default_ich8lan - Set the default LED settings
2017 * @hw: pointer to the HW structure
2018 * @data: Pointer to the LED settings
2020 * Reads the LED default settings from the NVM to data. If the NVM LED
2021 * settings is all 0's or F's, set the LED default to a valid LED default
2024 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2028 DEBUGFUNC("e1000_valid_led_default_ich8lan");
2030 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
2032 DEBUGOUT("NVM Read Error\n");
2036 if (*data == ID_LED_RESERVED_0000 ||
2037 *data == ID_LED_RESERVED_FFFF)
2038 *data = ID_LED_DEFAULT_ICH8LAN;
2045 * e1000_id_led_init_pchlan - store LED configurations
2046 * @hw: pointer to the HW structure
2048 * PCH does not control LEDs via the LEDCTL register, rather it uses
2049 * the PHY LED configuration register.
2051 * PCH also does not have an "always on" or "always off" mode which
2052 * complicates the ID feature. Instead of using the "on" mode to indicate
2053 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
2054 * use "link_up" mode. The LEDs will still ID on request if there is no
2055 * link based on logic in e1000_led_[on|off]_pchlan().
2057 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2059 struct e1000_mac_info *mac = &hw->mac;
2061 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2062 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2063 u16 data, i, temp, shift;
2065 DEBUGFUNC("e1000_id_led_init_pchlan");
2067 /* Get default ID LED modes */
2068 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2072 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
2073 mac->ledctl_mode1 = mac->ledctl_default;
2074 mac->ledctl_mode2 = mac->ledctl_default;
2076 for (i = 0; i < 4; i++) {
2077 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2080 case ID_LED_ON1_DEF2:
2081 case ID_LED_ON1_ON2:
2082 case ID_LED_ON1_OFF2:
2083 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2084 mac->ledctl_mode1 |= (ledctl_on << shift);
2086 case ID_LED_OFF1_DEF2:
2087 case ID_LED_OFF1_ON2:
2088 case ID_LED_OFF1_OFF2:
2089 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2090 mac->ledctl_mode1 |= (ledctl_off << shift);
2097 case ID_LED_DEF1_ON2:
2098 case ID_LED_ON1_ON2:
2099 case ID_LED_OFF1_ON2:
2100 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2101 mac->ledctl_mode2 |= (ledctl_on << shift);
2103 case ID_LED_DEF1_OFF2:
2104 case ID_LED_ON1_OFF2:
2105 case ID_LED_OFF1_OFF2:
2106 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2107 mac->ledctl_mode2 |= (ledctl_off << shift);
2120 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2121 * @hw: pointer to the HW structure
2123 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2124 * register, so the the bus width is hard coded.
2126 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2128 struct e1000_bus_info *bus = &hw->bus;
2131 DEBUGFUNC("e1000_get_bus_info_ich8lan");
2133 ret_val = e1000_get_bus_info_pcie_generic(hw);
2136 * ICH devices are "PCI Express"-ish. They have
2137 * a configuration space, but do not contain
2138 * PCI Express Capability registers, so bus width
2139 * must be hardcoded.
2141 if (bus->width == e1000_bus_width_unknown)
2142 bus->width = e1000_bus_width_pcie_x1;
2148 * e1000_reset_hw_ich8lan - Reset the hardware
2149 * @hw: pointer to the HW structure
2151 * Does a full reset of the hardware which includes a reset of the PHY and
2154 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2159 DEBUGFUNC("e1000_reset_hw_ich8lan");
2162 * Prevent the PCI-E bus from sticking if there is no TLP connection
2163 * on the last TLP read/write transaction when MAC is reset.
2165 ret_val = e1000_disable_pcie_master_generic(hw);
2167 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2169 DEBUGOUT("Masking off all interrupts\n");
2170 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2173 * Disable the Transmit and Receive units. Then delay to allow
2174 * any pending transactions to complete before we hit the MAC
2175 * with the global reset.
2177 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2178 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2179 E1000_WRITE_FLUSH(hw);
2183 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2184 if (hw->mac.type == e1000_ich8lan) {
2185 /* Set Tx and Rx buffer allocation to 8k apiece. */
2186 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
2187 /* Set Packet Buffer Size to 16k. */
2188 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
2191 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2193 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
2194 /* Clear PHY Reset Asserted bit */
2195 if (hw->mac.type >= e1000_pchlan) {
2196 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2197 E1000_WRITE_REG(hw, E1000_STATUS, status &
2198 ~E1000_STATUS_PHYRA);
2202 * PHY HW reset requires MAC CORE reset at the same
2203 * time to make sure the interface between MAC and the
2204 * external PHY is reset.
2206 ctrl |= E1000_CTRL_PHY_RST;
2208 ret_val = e1000_acquire_swflag_ich8lan(hw);
2209 DEBUGOUT("Issuing a global reset to ich8lan\n");
2210 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
2214 e1000_release_swflag_ich8lan(hw);
2216 if (ctrl & E1000_CTRL_PHY_RST)
2217 ret_val = hw->phy.ops.get_cfg_done(hw);
2219 if (hw->mac.type >= e1000_ich10lan) {
2220 e1000_lan_init_done_ich8lan(hw);
2222 ret_val = e1000_get_auto_rd_done_generic(hw);
2225 * When auto config read does not complete, do not
2226 * return with an error. This can happen in situations
2227 * where there is no eeprom and prevents getting link.
2229 DEBUGOUT("Auto Read Done did not complete\n");
2233 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2234 icr = E1000_READ_REG(hw, E1000_ICR);
2236 kab = E1000_READ_REG(hw, E1000_KABGTXD);
2237 kab |= E1000_KABGTXD_BGSQLBIAS;
2238 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
2240 if (hw->mac.type == e1000_pchlan)
2241 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2247 * e1000_init_hw_ich8lan - Initialize the hardware
2248 * @hw: pointer to the HW structure
2250 * Prepares the hardware for transmit and receive by doing the following:
2251 * - initialize hardware bits
2252 * - initialize LED identification
2253 * - setup receive address registers
2254 * - setup flow control
2255 * - setup transmit descriptors
2256 * - clear statistics
2258 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2260 struct e1000_mac_info *mac = &hw->mac;
2261 u32 ctrl_ext, txdctl, snoop;
2265 DEBUGFUNC("e1000_init_hw_ich8lan");
2267 e1000_initialize_hw_bits_ich8lan(hw);
2269 /* Initialize identification LED */
2270 ret_val = mac->ops.id_led_init(hw);
2272 /* This is not fatal and we should not stop init due to this */
2273 DEBUGOUT("Error initializing identification LED\n");
2275 /* Setup the receive address. */
2276 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2278 /* Zero out the Multicast HASH table */
2279 DEBUGOUT("Zeroing the MTA\n");
2280 for (i = 0; i < mac->mta_reg_count; i++)
2281 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2284 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2285 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2286 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2288 if (hw->phy.type == e1000_phy_82578) {
2289 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2290 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2295 /* Setup link and flow control */
2296 ret_val = mac->ops.setup_link(hw);
2298 /* Set the transmit descriptor write-back policy for both queues */
2299 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2300 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2301 E1000_TXDCTL_FULL_TX_DESC_WB;
2302 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2303 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2304 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
2305 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
2306 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2307 E1000_TXDCTL_FULL_TX_DESC_WB;
2308 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2309 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2310 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
2313 * ICH8 has opposite polarity of no_snoop bits.
2314 * By default, we should use snoop behavior.
2316 if (mac->type == e1000_ich8lan)
2317 snoop = PCIE_ICH8_SNOOP_ALL;
2319 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2320 e1000_set_pcie_no_snoop_generic(hw, snoop);
2322 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2323 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2324 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2327 * Clear all of the statistics registers (clear on read). It is
2328 * important that we do this after we have tried to establish link
2329 * because the symbol error count will increment wildly if there
2332 e1000_clear_hw_cntrs_ich8lan(hw);
2337 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2338 * @hw: pointer to the HW structure
2340 * Sets/Clears required hardware bits necessary for correctly setting up the
2341 * hardware for transmit and receive.
2343 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2347 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
2349 /* Extended Device Control */
2350 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2352 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2353 if (hw->mac.type >= e1000_pchlan)
2354 reg |= E1000_CTRL_EXT_PHYPDEN;
2355 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2357 /* Transmit Descriptor Control 0 */
2358 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
2360 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
2362 /* Transmit Descriptor Control 1 */
2363 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2365 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2367 /* Transmit Arbitration Control 0 */
2368 reg = E1000_READ_REG(hw, E1000_TARC(0));
2369 if (hw->mac.type == e1000_ich8lan)
2370 reg |= (1 << 28) | (1 << 29);
2371 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2372 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2374 /* Transmit Arbitration Control 1 */
2375 reg = E1000_READ_REG(hw, E1000_TARC(1));
2376 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2380 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2381 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2384 if (hw->mac.type == e1000_ich8lan) {
2385 reg = E1000_READ_REG(hw, E1000_STATUS);
2387 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2394 * e1000_setup_link_ich8lan - Setup flow control and link settings
2395 * @hw: pointer to the HW structure
2397 * Determines which flow control settings to use, then configures flow
2398 * control. Calls the appropriate media-specific link configuration
2399 * function. Assuming the adapter has a valid link partner, a valid link
2400 * should be established. Assumes the hardware has previously been reset
2401 * and the transmitter and receiver are not enabled.
2403 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2405 s32 ret_val = E1000_SUCCESS;
2407 DEBUGFUNC("e1000_setup_link_ich8lan");
2409 if (hw->phy.ops.check_reset_block(hw))
2413 * ICH parts do not have a word in the NVM to determine
2414 * the default flow control setting, so we explicitly
2417 if (hw->fc.requested_mode == e1000_fc_default)
2418 hw->fc.requested_mode = e1000_fc_full;
2421 * Save off the requested flow control mode for use later. Depending
2422 * on the link partner's capabilities, we may or may not use this mode.
2424 hw->fc.current_mode = hw->fc.requested_mode;
2426 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
2427 hw->fc.current_mode);
2429 /* Continue to configure the copper link. */
2430 ret_val = hw->mac.ops.setup_physical_interface(hw);
2434 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2435 if ((hw->phy.type == e1000_phy_82578) ||
2436 (hw->phy.type == e1000_phy_82577)) {
2437 ret_val = hw->phy.ops.write_reg(hw,
2438 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2444 ret_val = e1000_set_fc_watermarks_generic(hw);
2451 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2452 * @hw: pointer to the HW structure
2454 * Configures the kumeran interface to the PHY to wait the appropriate time
2455 * when polling the PHY, then call the generic setup_copper_link to finish
2456 * configuring the copper link.
2458 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2464 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2466 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2467 ctrl |= E1000_CTRL_SLU;
2468 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2469 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2472 * Set the mac to wait the maximum time between each iteration
2473 * and increase the max iterations when polling the phy;
2474 * this fixes erroneous timeouts at 10Mbps.
2476 ret_val = e1000_write_kmrn_reg_generic(hw,
2477 E1000_KMRNCTRLSTA_TIMEOUTS,
2481 ret_val = e1000_read_kmrn_reg_generic(hw,
2482 E1000_KMRNCTRLSTA_INBAND_PARAM,
2487 ret_val = e1000_write_kmrn_reg_generic(hw,
2488 E1000_KMRNCTRLSTA_INBAND_PARAM,
2493 switch (hw->phy.type) {
2494 case e1000_phy_igp_3:
2495 ret_val = e1000_copper_link_setup_igp(hw);
2500 case e1000_phy_82578:
2501 ret_val = e1000_copper_link_setup_m88(hw);
2505 case e1000_phy_82577:
2506 ret_val = e1000_copper_link_setup_82577(hw);
2511 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2516 reg_data &= ~IFE_PMC_AUTO_MDIX;
2518 switch (hw->phy.mdix) {
2520 reg_data &= ~IFE_PMC_FORCE_MDIX;
2523 reg_data |= IFE_PMC_FORCE_MDIX;
2527 reg_data |= IFE_PMC_AUTO_MDIX;
2530 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2538 ret_val = e1000_setup_copper_link_generic(hw);
2545 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2546 * @hw: pointer to the HW structure
2547 * @speed: pointer to store current link speed
2548 * @duplex: pointer to store the current link duplex
2550 * Calls the generic get_speed_and_duplex to retrieve the current link
2551 * information and then calls the Kumeran lock loss workaround for links at
2554 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2559 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2561 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2565 if ((hw->mac.type == e1000_ich8lan) &&
2566 (hw->phy.type == e1000_phy_igp_3) &&
2567 (*speed == SPEED_1000)) {
2568 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2576 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2577 * @hw: pointer to the HW structure
2579 * Work-around for 82566 Kumeran PCS lock loss:
2580 * On link status change (i.e. PCI reset, speed change) and link is up and
2582 * 0) if workaround is optionally disabled do nothing
2583 * 1) wait 1ms for Kumeran link to come up
2584 * 2) check Kumeran Diagnostic register PCS lock loss bit
2585 * 3) if not set the link is locked (all is good), otherwise...
2587 * 5) repeat up to 10 times
2588 * Note: this is only called for IGP3 copper when speed is 1gb.
2590 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2592 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2594 s32 ret_val = E1000_SUCCESS;
2598 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
2600 if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
2604 * Make sure link is up before proceeding. If not just return.
2605 * Attempting this while link is negotiating fouled up link
2608 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2610 ret_val = E1000_SUCCESS;
2614 for (i = 0; i < 10; i++) {
2615 /* read once to clear */
2616 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2619 /* and again to get new status */
2620 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2624 /* check for PCS lock */
2625 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2626 ret_val = E1000_SUCCESS;
2630 /* Issue PHY reset */
2631 hw->phy.ops.reset(hw);
2634 /* Disable GigE link negotiation */
2635 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2636 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2637 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2638 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2641 * Call gig speed drop workaround on Gig disable before accessing
2644 e1000_gig_downshift_workaround_ich8lan(hw);
2646 /* unable to acquire PCS lock */
2647 ret_val = -E1000_ERR_PHY;
2654 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2655 * @hw: pointer to the HW structure
2656 * @state: boolean value used to set the current Kumeran workaround state
2658 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2659 * /disabled - FALSE).
2661 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2664 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2666 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
2668 if (hw->mac.type != e1000_ich8lan) {
2669 DEBUGOUT("Workaround applies to ICH8 only.\n");
2673 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2679 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2680 * @hw: pointer to the HW structure
2682 * Workaround for 82566 power-down on D3 entry:
2683 * 1) disable gigabit link
2684 * 2) write VR power-down enable
2686 * Continue if successful, else issue LCD reset and repeat
2688 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2694 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
2696 if (hw->phy.type != e1000_phy_igp_3)
2699 /* Try the workaround twice (if needed) */
2702 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2703 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2704 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2705 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
2708 * Call gig speed drop workaround on Gig disable before
2709 * accessing any PHY registers
2711 if (hw->mac.type == e1000_ich8lan)
2712 e1000_gig_downshift_workaround_ich8lan(hw);
2714 /* Write VR power-down enable */
2715 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2716 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2717 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
2718 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2720 /* Read it back and test */
2721 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2722 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2723 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2726 /* Issue PHY reset and repeat at most one more time */
2727 reg = E1000_READ_REG(hw, E1000_CTRL);
2728 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2737 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2738 * @hw: pointer to the HW structure
2740 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2741 * LPLU, Gig disable, MDIC PHY reset):
2742 * 1) Set Kumeran Near-end loopback
2743 * 2) Clear Kumeran Near-end loopback
2744 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2746 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2748 s32 ret_val = E1000_SUCCESS;
2751 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
2753 if ((hw->mac.type != e1000_ich8lan) ||
2754 (hw->phy.type != e1000_phy_igp_3))
2757 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2761 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2762 ret_val = e1000_write_kmrn_reg_generic(hw,
2763 E1000_KMRNCTRLSTA_DIAG_OFFSET,
2767 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2768 ret_val = e1000_write_kmrn_reg_generic(hw,
2769 E1000_KMRNCTRLSTA_DIAG_OFFSET,
2776 * e1000_disable_gig_wol_ich8lan - disable gig during WoL
2777 * @hw: pointer to the HW structure
2779 * During S0 to Sx transition, it is possible the link remains at gig
2780 * instead of negotiating to a lower speed. Before going to Sx, set
2781 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2784 * Should only be called for applicable parts.
2786 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2790 switch (hw->mac.type) {
2792 case e1000_ich10lan:
2794 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2795 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2796 E1000_PHY_CTRL_GBE_DISABLE;
2797 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2799 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2800 if (hw->mac.type == e1000_pchlan)
2810 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2811 * @hw: pointer to the HW structure
2813 * Return the LED back to the default configuration.
2815 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2817 s32 ret_val = E1000_SUCCESS;
2819 DEBUGFUNC("e1000_cleanup_led_ich8lan");
2821 if (hw->phy.type == e1000_phy_ife)
2822 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2825 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2831 * e1000_led_on_ich8lan - Turn LEDs on
2832 * @hw: pointer to the HW structure
2836 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2838 s32 ret_val = E1000_SUCCESS;
2840 DEBUGFUNC("e1000_led_on_ich8lan");
2842 if (hw->phy.type == e1000_phy_ife)
2843 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2844 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2846 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2852 * e1000_led_off_ich8lan - Turn LEDs off
2853 * @hw: pointer to the HW structure
2855 * Turn off the LEDs.
2857 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2859 s32 ret_val = E1000_SUCCESS;
2861 DEBUGFUNC("e1000_led_off_ich8lan");
2863 if (hw->phy.type == e1000_phy_ife)
2864 ret_val = hw->phy.ops.write_reg(hw,
2865 IFE_PHY_SPECIAL_CONTROL_LED,
2866 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2868 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2874 * e1000_setup_led_pchlan - Configures SW controllable LED
2875 * @hw: pointer to the HW structure
2877 * This prepares the SW controllable LED for use.
2879 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2881 DEBUGFUNC("e1000_setup_led_pchlan");
2883 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
2884 (u16)hw->mac.ledctl_mode1);
2888 * e1000_cleanup_led_pchlan - Restore the default LED operation
2889 * @hw: pointer to the HW structure
2891 * Return the LED back to the default configuration.
2893 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2895 DEBUGFUNC("e1000_cleanup_led_pchlan");
2897 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
2898 (u16)hw->mac.ledctl_default);
2902 * e1000_led_on_pchlan - Turn LEDs on
2903 * @hw: pointer to the HW structure
2907 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2909 u16 data = (u16)hw->mac.ledctl_mode2;
2912 DEBUGFUNC("e1000_led_on_pchlan");
2915 * If no link, then turn LED on by setting the invert bit
2916 * for each LED that's mode is "link_up" in ledctl_mode2.
2918 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2919 for (i = 0; i < 3; i++) {
2920 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2921 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2922 E1000_LEDCTL_MODE_LINK_UP)
2924 if (led & E1000_PHY_LED0_IVRT)
2925 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2927 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2931 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
2935 * e1000_led_off_pchlan - Turn LEDs off
2936 * @hw: pointer to the HW structure
2938 * Turn off the LEDs.
2940 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2942 u16 data = (u16)hw->mac.ledctl_mode1;
2945 DEBUGFUNC("e1000_led_off_pchlan");
2948 * If no link, then turn LED off by clearing the invert bit
2949 * for each LED that's mode is "link_up" in ledctl_mode1.
2951 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2952 for (i = 0; i < 3; i++) {
2953 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2954 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2955 E1000_LEDCTL_MODE_LINK_UP)
2957 if (led & E1000_PHY_LED0_IVRT)
2958 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2960 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2964 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
2968 * e1000_get_cfg_done_ich8lan - Read config done bit
2969 * @hw: pointer to the HW structure
2971 * Read the management control register for the config done bit for
2972 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2973 * to read the config done bit, so an error is *ONLY* logged and returns
2974 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2975 * would not be able to be reset or change link.
2977 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2979 s32 ret_val = E1000_SUCCESS;
2982 if (hw->mac.type >= e1000_pchlan) {
2983 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2985 if (status & E1000_STATUS_PHYRA) {
2986 E1000_WRITE_REG(hw, E1000_STATUS, status &
2987 ~E1000_STATUS_PHYRA);
2989 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
2992 e1000_get_cfg_done_generic(hw);
2994 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2995 if ((hw->mac.type != e1000_ich10lan) &&
2996 (hw->mac.type != e1000_pchlan)) {
2997 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2998 (hw->phy.type == e1000_phy_igp_3)) {
2999 e1000_phy_init_script_igp3(hw);
3002 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3003 /* Maybe we should do a basic PHY config */
3004 DEBUGOUT("EEPROM not present\n");
3005 ret_val = -E1000_ERR_CONFIG;
3013 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3014 * @hw: pointer to the HW structure
3016 * In the case of a PHY power down to save power, or to turn off link during a
3017 * driver unload, or wake on lan is not enabled, remove the link.
3019 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3021 /* If the management interface is not enabled, then power down */
3022 if (!(hw->mac.ops.check_mng_mode(hw) ||
3023 hw->phy.ops.check_reset_block(hw)))
3024 e1000_power_down_phy_copper(hw);
3030 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3031 * @hw: pointer to the HW structure
3033 * Clears hardware counters specific to the silicon family and calls
3034 * clear_hw_cntrs_generic to clear all general purpose counters.
3036 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3040 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
3042 e1000_clear_hw_cntrs_base_generic(hw);
3044 E1000_READ_REG(hw, E1000_ALGNERRC);
3045 E1000_READ_REG(hw, E1000_RXERRC);
3046 E1000_READ_REG(hw, E1000_TNCRS);
3047 E1000_READ_REG(hw, E1000_CEXTERR);
3048 E1000_READ_REG(hw, E1000_TSCTC);
3049 E1000_READ_REG(hw, E1000_TSCTFC);
3051 E1000_READ_REG(hw, E1000_MGTPRC);
3052 E1000_READ_REG(hw, E1000_MGTPDC);
3053 E1000_READ_REG(hw, E1000_MGTPTC);
3055 E1000_READ_REG(hw, E1000_IAC);
3056 E1000_READ_REG(hw, E1000_ICRXOC);
3058 /* Clear PHY statistics registers */
3059 if ((hw->phy.type == e1000_phy_82578) ||
3060 (hw->phy.type == e1000_phy_82577)) {
3061 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3062 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3063 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3064 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3065 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3066 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3067 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3068 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3069 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3070 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3071 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3072 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3073 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3074 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);