2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: 1. Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer. 2. The name
8 * of the author may not be used to endorse or promote products derived from
9 * this software without specific prior written permission
11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * DELAY_MULTIPLE: How much to boost "base" delays, except
27 * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this.
29 #define DELAY_MULTIPLE 10
30 #define BIT_DELAY_MULTIPLE 10
33 * Some global constants
35 #define TX_INIT_RATE 16
36 #define TX_INIT_MAX_RATE 64
37 #define RX_INIT_LATENCY 64
38 #define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */
39 #define RX_NEXT_EARLY_THRESH 500
41 #define EEPROMSIZE 0x40
42 #define MAX_EEPROMBUSY 1000
43 #define EP_LAST_TAG 0xd7
44 #define EP_MAX_BOARDS 16
45 #define EP_IOSIZE 16 /* 16 bytes of I/O space used. */
48 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
51 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
52 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
53 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
54 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
56 #define EEPROM_BUSY (1<<15)
57 #define EEPROM_TST_MODE (1<<14)
60 * Some short functions, worth to let them be a macro
62 #define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
63 #define GO_WINDOW(sc, x) CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT|(x))
65 /**************************************************************************
67 * These define the EEPROM data structure. They are used in the probe
68 * function to verify the existence of the adapter after having sent
71 **************************************************************************/
73 #define EEPROM_NODE_ADDR_0 0x0 /* Word */
74 #define EEPROM_NODE_ADDR_1 0x1 /* Word */
75 #define EEPROM_NODE_ADDR_2 0x2 /* Word */
76 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
77 #define EEPROM_MFG_DATE 0x4 /* Manufacturing date */
78 #define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */
79 #define EEPROM_MFG_PRODUCT 0x6 /* Product code */
80 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */
81 #define EEPROM_ADDR_CFG 0x8 /* Base addr */
82 #define ADDR_CFG_EISA 0x1f
83 #define ADDR_CFG_MASK 0x1f
84 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
85 #define EEPROM_OEM_ADDR0 0xa
86 #define EEPROM_OEM_ADDR1 0xb
87 #define EEPROM_OEM_ADDR2 0xc
88 #define EEPROM_SOFTINFO 0xd
89 #define EEPROM_COMPAT 0xe
90 #define EEPROM_SOFTINFO2 0xf
91 #define EEPROM_CAP 0x10
92 #define CAP_ISA 0x2083
93 #define CAP_PCMCIA 0x2082
94 #define EEPROM_INT_CONFIG_0 0x12
95 #define EEPROM_INT_CONFIG_1 0x13
96 /* RAM Partition TX FIFO/RX FIFO */
97 #define ICW1_RAM_PART_MASK 0x03
98 #define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b
99 * default power-up/reset */
100 #define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size ==
102 #define ICW1_RAM_PART_11 0x10 /* 1:1 */
103 #define ICW1_RAM_PART_RESV 0x11 /* Reserved */
104 /* ISA Adapter Selection */
105 #define ICW1_IAS_MASK 0x0c
106 #define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */
107 #define ICW1_IAS_ISA 0x04 /* ISA contention only */
108 #define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */
109 #define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */
111 #define EEPROM_CHECKSUM_EL3 0x17
113 /**************************************************************************
115 * These are the registers for the 3Com 3c509 and their bit patterns when *
116 * applicable. They have been taken out the "EtherLink III Parallel *
117 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
120 **************************************************************************/
122 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
124 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status
126 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window
129 * Window 0 registers. Setup.
132 #define EP_W0_EEPROM_DATA 0x0c
133 #define EP_W0_EEPROM_COMMAND 0x0a
134 #define EP_W0_RESOURCE_CFG 0x08
135 #define EP_W0_ADDRESS_CFG 0x06
136 #define EP_W0_CONFIG_CTRL 0x04
138 #define EP_W0_PRODUCT_ID 0x02
139 #define EP_W0_MFG_ID 0x00
142 * Window 1 registers. Operating Set.
145 #define EP_W1_TX_PIO_WR_2 0x02
146 #define EP_W1_TX_PIO_WR_1 0x00
148 #define EP_W1_FREE_TX 0x0c
149 #define EP_W1_TX_STATUS 0x0b /* byte */
150 #define EP_W1_TIMER 0x0a /* byte */
151 #define EP_W1_RX_STATUS 0x08
152 #define EP_W1_RX_PIO_RD_2 0x02
153 #define EP_W1_RX_PIO_RD_1 0x00
156 * Window 2 registers. Station Address Setup/Read
159 #define EP_W2_PHY_MGMT 0x0c
160 #define EP_W2_ALT_EEPROM 0x0a
161 #define EP_W2_ADDR_5 0x05
162 #define EP_W2_ADDR_4 0x04
163 #define EP_W2_ADDR_3 0x03
164 #define EP_W2_ADDR_2 0x02
165 #define EP_W2_ADDR_1 0x01
166 #define EP_W2_ADDR_0 0x00
169 * Window 3 registers. FIFO Management.
172 #define EP_W3_FREE_TX 0x0c
173 #define EP_W3_FREE_RX 0x0a
174 #define EP_W3_OPTIONS 0x08
177 * Window 4 registers. Diagnostics.
180 #define EP_W4_MEDIA_TYPE 0x0a
181 #define EP_W4_CTRLR_STATUS 0x08
182 #define EP_W4_NET_DIAG 0x06
183 #define EP_W4_FIFO_DIAG 0x04
184 #define EP_W4_HOST_DIAG 0x02
185 #define EP_W4_TX_DIAG 0x00
188 * Window 5 Registers. Results and Internal status.
191 #define EP_W5_READ_0_MASK 0x0c
192 #define EP_W5_INTR_MASK 0x0a
193 #define EP_W5_RX_FILTER 0x08
194 #define EP_W5_RX_EARLY_THRESH 0x06
195 #define EP_W5_TX_AVAIL_THRESH 0x02
196 #define EP_W5_TX_START_THRESH 0x00
199 * Window 6 registers. Statistics.
202 #define TX_TOTAL_OK 0x0c
203 #define RX_TOTAL_OK 0x0a
204 #define TX_DEFERRALS 0x08
205 #define RX_FRAMES_OK 0x07
206 #define TX_FRAMES_OK 0x06
207 #define RX_OVERRUNS 0x05
208 #define TX_COLLISIONS 0x04
209 #define TX_AFTER_1_COLLISION 0x03
210 #define TX_AFTER_X_COLLISIONS 0x02
211 #define TX_NO_SQE 0x01
212 #define TX_CD_LOST 0x00
214 /****************************************
216 * Register definitions.
218 ****************************************/
221 * Command parameter that disables threshold interrupts
222 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work.
223 * "busmastering" cards need 8188.
224 * The implicit two-bit upshift done by busmastering cards means
225 * a value of 2047 disables threshold interrupts on both.
227 #define EP_THRESH_DISABLE 2047
230 * Command register. All windows.
233 * 15-11: 5-bit code for command to be executed.
234 * 10-0: 11-bit arg if any. For commands with no args;
235 * this can be set to anything.
237 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
239 #define WINDOW_SELECT (u_short) (0x1<<11)
240 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
244 * before using trans-
246 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
248 #define RX_ENABLE (u_short) (0x4<<11)
249 #define RX_RESET (u_short) (0x5<<11)
250 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
251 #define TX_ENABLE (u_short) (0x9<<11)
252 #define TX_DISABLE (u_short) (0xa<<11)
253 #define TX_RESET (u_short) (0xb<<11)
254 #define REQ_INTR (u_short) (0xc<<11)
256 * The following C_* acknowledge the various interrupts. Some of them don't
257 * do anything. See the manual.
259 #define ACK_INTR (u_short) (0x6800)
260 # define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
261 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
262 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
263 # define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
264 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
265 # define C_RX_EARLY (u_short) (ACK_INTR|0x20)
266 # define C_INT_RQD (u_short) (ACK_INTR|0x40)
267 # define C_UPD_STATS (u_short) (ACK_INTR|0x80)
268 #define SET_INTR_MASK (u_short) (0xe<<11)
269 #define SET_RD_0_MASK (u_short) (0xf<<11)
270 #define SET_RX_FILTER (u_short) (0x10<<11)
271 # define FIL_INDIVIDUAL (u_short) (0x1)
272 # define FIL_MULTICAST (u_short) (0x02)
273 # define FIL_BRDCST (u_short) (0x04)
274 # define FIL_PROMISC (u_short) (0x08)
275 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
276 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
277 #define SET_TX_START_THRESH (u_short) (0x13<<11)
278 #define STATS_ENABLE (u_short) (0x15<<11)
279 #define STATS_DISABLE (u_short) (0x16<<11)
280 #define STOP_TRANSCEIVER (u_short) (0x17<<11)
281 #define TX_PLL_ENABLE (u_short) (0x18<<11)
282 #define TX_PLL_DISABLE (u_short) (0x19<<11)
283 #define POWER_UP (u_short) (0x1b<<11)
284 #define POWER_DOWN (u_short) (0x1b<<11)
285 #define POWER_AUTO (u_short) (0x1b<<11)
288 * Status register. All windows.
290 * 15-13: Window number(0-7).
291 * 12: Command_in_progress.
296 * 7: Update Statistics.
297 * 6: Interrupt Requested.
302 * 1: Adapter Failure.
303 * 0: Interrupt Latch.
305 #define S_INTR_LATCH (u_short) (0x1)
306 #define S_CARD_FAILURE (u_short) (0x2)
307 #define S_TX_COMPLETE (u_short) (0x4)
308 #define S_TX_AVAIL (u_short) (0x8)
309 #define S_RX_COMPLETE (u_short) (0x10)
310 #define S_RX_EARLY (u_short) (0x20)
311 #define S_INT_RQD (u_short) (0x40)
312 #define S_UPD_STATS (u_short) (0x80)
313 #define S_MASK (u_short) 0xFF /* mask of S_* */
314 #define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
315 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
316 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
318 #define EP_BUSY_WAIT(sc) while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS)
320 /* Address Config. Register.
324 #define ACF_CONNECTOR_BITS 14
325 #define ACF_CONNECTOR_UTP 0
326 #define ACF_CONNECTOR_AUI 1
327 #define ACF_CONNECTOR_BNC 3
329 /* Resource configuration register.
334 #define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \
335 ((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) | \
336 ((u_short)(irq)<<12)) ) /* set IRQ i */
340 * RX Status. Window 1/Port 08
342 * 15: Incomplete or FIFO empty.
343 * 14: 1: Error in RX Packet 0: Incomplete or no error.
344 * 13-11: Type of error.
346 * 1011 = Run Packet Error.
347 * 1100 = Alignment Error.
349 * 1001 = Oversize Packet Error (>1514 bytes)
350 * 0010 = Dribble Bits.
351 * (all other error codes, no errors.)
353 * 10-0: RX Bytes (0-1514)
355 #define ERR_RX_INCOMPLETE (u_short) (0x1<<15)
356 #define ERR_RX (u_short) (0x1<<14)
357 #define ERR_RX_OVERRUN (u_short) (0x8<<11)
358 #define ERR_RX_RUN_PKT (u_short) (0xb<<11)
359 #define ERR_RX_ALIGN (u_short) (0xc<<11)
360 #define ERR_RX_CRC (u_short) (0xd<<11)
361 #define ERR_RX_OVERSIZE (u_short) (0x9<<11)
362 #define ERR_RX_DRIBBLE (u_short) (0x2<<11)
366 * TX Status. Window 1/Port 0B
368 * Reports the transmit status of a completed transmission. Writing this
369 * register pops the transmit completion stack.
371 * Window 1/Port 0x0b.
374 * 6: Interrupt on successful transmission requested.
375 * 5: Jabber Error (TP Only, TX Reset required. )
376 * 4: Underrun (TX Reset required. )
377 * 3: Maximum Collisions.
378 * 2: TX Status Overflow.
382 #define TXS_COMPLETE 0x80
383 #define TXS_SUCCES_INTR_REQ 0x40
384 #define TXS_JABBER 0x20
385 #define TXS_UNDERRUN 0x10
386 #define TXS_MAX_COLLISION 0x8
387 #define TXS_STATUS_OVERFLOW 0x4
390 * Configuration control register.
394 #define IS_AUI (1<<13)
395 #define IS_BNC (1<<12)
396 #define IS_UTP (1<<9)
398 #define ENABLE_DRQ_IRQ 0x0001
399 #define W0_P4_CMD_RESET_ADAPTER 0x4
400 #define W0_P4_CMD_ENABLE_ADAPTER 0x1
403 * Media type and status.
406 #define JABBER_GUARD_ENABLE 0x40
407 #define LINKBEAT_ENABLE 0x80
408 #define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
409 #define DISABLE_UTP 0x0
410 #define MT_CSD 0x0004 /* CRC Strip disable */
411 #define MT_SQE 0x0008 /* SQE Enable */
412 #define MT_C0 0x0010 /* Collison */
413 #define MT_CS 0x0020 /* Carrier Sense */
414 #define MT_J 0x0200 /* Jabber detected */
415 #define MT_PL 0x0400 /* Plarity Inverted */
416 #define MT_LB 0x0800 /* Link Beat detected */
417 #define MT_SQ 0x1000 /* SQE Present */
418 #define MT_IN 0x2000 /* Reserved */
419 #define MT_CE 0x4000 /* Coax */
420 #define MT_TPE 0x8000
423 * Misc defines for various things.
425 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
426 #define MFG_ID 0x6d50 /* in EEPROM and W0
428 #define PROD_ID 0x9150
434 #define RX_BYTES_MASK (u_short) (0x07ff)