2 * Copyright (c) 1996, Javier MartÃn Rueda (jmrueda@diatel.upm.es)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * MAINTAINER: Matthew N. Dodd <winter@jurai.net>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Intel EtherExpress Pro/10, Pro/10+ Ethernet driver
40 * dd-mmm-yyyy: Multicast support ported from NetBSD's if_iy driver.
41 * 30-Oct-1996: first beta version. Inet and BPF supported, but no multicast.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/sockio.h>
49 #include <sys/socket.h>
51 #include <sys/module.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_types.h>
63 #include <net/ethernet.h>
66 #include <netinet/in.h>
67 #include <netinet/if_ether.h>
70 #include <isa/isavar.h>
71 #include <isa/pnpvar.h>
73 #include <dev/ex/if_exreg.h>
74 #include <dev/ex/if_exvar.h>
81 static int debug_mask = 0;
82 # define DODEBUG(level, action) if (level & debug_mask) action
84 # define DODEBUG(level, action)
87 devclass_t ex_devclass;
90 { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 };
92 { 9, 3, 5, 10, 11, 0, 0, 0 };
94 char plus_irq2eemap[] =
95 { -1, -1, -1, 0, 1, 2, -1, 3, -1, 4, 5, 6, 7, -1, -1, -1 };
96 u_char plus_ee2irqmap[] =
97 { 3, 4, 5, 7, 9, 10, 11, 12 };
99 /* Network Interface Functions */
100 static void ex_init(void *);
101 static void ex_init_locked(struct ex_softc *);
102 static void ex_start(struct ifnet *);
103 static void ex_start_locked(struct ifnet *);
104 static int ex_ioctl(struct ifnet *, u_long, caddr_t);
105 static void ex_watchdog(void *);
107 /* ifmedia Functions */
108 static int ex_ifmedia_upd(struct ifnet *);
109 static void ex_ifmedia_sts(struct ifnet *, struct ifmediareq *);
111 static int ex_get_media(struct ex_softc *);
113 static void ex_reset(struct ex_softc *);
114 static void ex_setmulti(struct ex_softc *);
116 static void ex_tx_intr(struct ex_softc *);
117 static void ex_rx_intr(struct ex_softc *);
120 ex_get_address(struct ex_softc *sc, u_char *enaddr)
124 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Lo);
125 enaddr[5] = eaddr_tmp & 0xff;
126 enaddr[4] = eaddr_tmp >> 8;
127 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Mid);
128 enaddr[3] = eaddr_tmp & 0xff;
129 enaddr[2] = eaddr_tmp >> 8;
130 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Hi);
131 enaddr[1] = eaddr_tmp & 0xff;
132 enaddr[0] = eaddr_tmp >> 8;
138 ex_card_type(u_char *enaddr)
140 if ((enaddr[0] == 0x00) && (enaddr[1] == 0xA0) && (enaddr[2] == 0xC9))
141 return (CARD_TYPE_EX_10_PLUS);
143 return (CARD_TYPE_EX_10);
147 * Caller is responsible for eventually calling
148 * ex_release_resources() on failure.
151 ex_alloc_resources(device_t dev)
153 struct ex_softc * sc = device_get_softc(dev);
156 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
157 &sc->ioport_rid, RF_ACTIVE);
159 device_printf(dev, "No I/O space?!\n");
164 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
168 device_printf(dev, "No IRQ?!\n");
178 ex_release_resources(device_t dev)
180 struct ex_softc * sc = device_get_softc(dev);
183 bus_teardown_intr(dev, sc->irq, sc->ih);
188 bus_release_resource(dev, SYS_RES_IOPORT,
189 sc->ioport_rid, sc->ioport);
194 bus_release_resource(dev, SYS_RES_IRQ,
195 sc->irq_rid, sc->irq);
206 ex_attach(device_t dev)
208 struct ex_softc * sc = device_get_softc(dev);
210 struct ifmedia * ifm;
214 ifp = sc->ifp = if_alloc(IFT_ETHER);
216 device_printf(dev, "can not if_alloc()\n");
219 /* work out which set of irq <-> internal tables to use */
220 if (ex_card_type(sc->enaddr) == CARD_TYPE_EX_10_PLUS) {
221 sc->irq2ee = plus_irq2eemap;
222 sc->ee2irq = plus_ee2irqmap;
224 sc->irq2ee = irq2eemap;
225 sc->ee2irq = ee2irqmap;
228 sc->mem_size = CARD_RAM_SIZE; /* XXX This should be read from the card itself. */
231 * Initialize the ifnet structure.
234 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
235 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
236 ifp->if_start = ex_start;
237 ifp->if_ioctl = ex_ioctl;
238 ifp->if_init = ex_init;
239 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
241 ifmedia_init(&sc->ifmedia, 0, ex_ifmedia_upd, ex_ifmedia_sts);
242 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
244 callout_init_mtx(&sc->timer, &sc->lock, 0);
246 temp = ex_eeprom_read(sc, EE_W5);
247 if (temp & EE_W5_PORT_TPE)
248 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
249 if (temp & EE_W5_PORT_BNC)
250 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
251 if (temp & EE_W5_PORT_AUI)
252 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
254 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
255 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_NONE, 0, NULL);
256 ifmedia_set(&sc->ifmedia, ex_get_media(sc));
259 ifm->ifm_media = ifm->ifm_cur->ifm_media;
263 * Attach the interface.
265 ether_ifattach(ifp, sc->enaddr);
267 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
268 NULL, ex_intr, (void *)sc, &sc->ih);
270 device_printf(dev, "bus_setup_intr() failed!\n");
272 mtx_destroy(&sc->lock);
280 ex_detach(device_t dev)
285 sc = device_get_softc(dev);
293 callout_drain(&sc->timer);
295 ex_release_resources(dev);
296 mtx_destroy(&sc->lock);
304 struct ex_softc * sc = (struct ex_softc *) xsc;
312 ex_init_locked(struct ex_softc *sc)
314 struct ifnet * ifp = sc->ifp;
316 unsigned short temp_reg;
318 DODEBUG(Start_End, printf("%s: ex_init: start\n", ifp->if_xname););
323 * Load the ethernet address into the card.
325 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
326 temp_reg = CSR_READ_1(sc, EEPROM_REG);
327 if (temp_reg & Trnoff_Enable)
328 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
329 for (i = 0; i < ETHER_ADDR_LEN; i++)
330 CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
333 * - Setup transmit chaining and discard bad received frames.
336 * - Set receiving mode.
338 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
339 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
340 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
342 * - Set IRQ number, if this part has it. ISA devices have this,
343 * while PC Card devices don't seem to. Either way, we have to
344 * switch to Bank1 as the rest of this code relies on that.
346 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
347 if (sc->flags & HAS_INT_NO_REG)
348 CSR_WRITE_1(sc, INT_NO_REG,
349 (CSR_READ_1(sc, INT_NO_REG) & 0xf8) |
350 sc->irq2ee[sc->irq_no]);
353 * Divide the available memory in the card into rcv and xmt buffers.
354 * By default, I use the first 3/4 of the memory for the rcv buffer,
355 * and the remaining 1/4 of the memory for the xmt buffer.
357 sc->rx_mem_size = sc->mem_size * 3 / 4;
358 sc->tx_mem_size = sc->mem_size - sc->rx_mem_size;
359 sc->rx_lower_limit = 0x0000;
360 sc->rx_upper_limit = sc->rx_mem_size - 2;
361 sc->tx_lower_limit = sc->rx_mem_size;
362 sc->tx_upper_limit = sc->mem_size - 2;
363 CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
364 CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8);
365 CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8);
366 CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8);
369 * Enable receive and transmit interrupts, and clear any pending int.
371 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
372 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
373 CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
374 CSR_WRITE_1(sc, STATUS_REG, All_Int);
377 * Initialize receive and transmit ring buffers.
379 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
380 sc->rx_head = sc->rx_lower_limit;
381 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
382 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
383 sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
385 ifp->if_drv_flags |= IFF_DRV_RUNNING;
386 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
387 DODEBUG(Status, printf("OIDLE init\n"););
388 callout_reset(&sc->timer, hz, ex_watchdog, sc);
393 * Final reset of the board, and enable operation.
395 CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD);
397 CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD);
399 ex_start_locked(ifp);
401 DODEBUG(Start_End, printf("%s: ex_init: finish\n", ifp->if_xname););
405 ex_start(struct ifnet *ifp)
407 struct ex_softc * sc = ifp->if_softc;
410 ex_start_locked(ifp);
415 ex_start_locked(struct ifnet *ifp)
417 struct ex_softc * sc = ifp->if_softc;
418 int i, len, data_len, avail, dest, next;
419 unsigned char tmp16[2];
423 DODEBUG(Start_End, printf("ex_start%d: start\n", unit););
426 * Main loop: send outgoing packets to network card until there are no
427 * more packets left, or the card cannot accept any more yet.
429 while (((opkt = ifp->if_snd.ifq_head) != NULL) &&
430 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
433 * Ensure there is enough free transmit buffer space for
434 * this packet, including its header. Note: the header
435 * cannot wrap around the end of the transmit buffer and
436 * must be kept together, so we allow space for twice the
437 * length of the header, just in case.
440 for (len = 0, m = opkt; m != NULL; m = m->m_next) {
446 DODEBUG(Sent_Pkts, printf("1. Sending packet with %d data bytes. ", data_len););
449 len += XMT_HEADER_LEN + 1;
451 len += XMT_HEADER_LEN;
454 if ((i = sc->tx_tail - sc->tx_head) >= 0) {
455 avail = sc->tx_mem_size - i;
460 DODEBUG(Sent_Pkts, printf("i=%d, avail=%d\n", i, avail););
462 if (avail >= len + XMT_HEADER_LEN) {
463 IF_DEQUEUE(&ifp->if_snd, opkt);
467 * Disable rx and tx interrupts, to avoid corruption
468 * of the host address register by interrupt service
470 * XXX Is this necessary with splimp() enabled?
472 CSR_WRITE_1(sc, MASK_REG, All_Int);
476 * Compute the start and end addresses of this
477 * frame in the tx buffer.
482 if (next > sc->tx_upper_limit) {
483 if ((sc->tx_upper_limit + 2 - sc->tx_tail) <=
485 dest = sc->tx_lower_limit;
488 next = sc->tx_lower_limit +
489 next - sc->tx_upper_limit - 2;
494 * Build the packet frame in the card's ring buffer.
496 DODEBUG(Sent_Pkts, printf("2. dest=%d, next=%d. ", dest, next););
498 CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
499 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
500 CSR_WRITE_2(sc, IO_PORT_REG, 0);
501 CSR_WRITE_2(sc, IO_PORT_REG, next);
502 CSR_WRITE_2(sc, IO_PORT_REG, data_len);
505 * Output the packet data to the card. Ensure all
506 * transfers are 16-bit wide, even if individual
507 * mbufs have odd length.
509 for (m = opkt, i = 0; m != NULL; m = m->m_next) {
510 DODEBUG(Sent_Pkts, printf("[%d]", m->m_len););
512 tmp16[1] = *(mtod(m, caddr_t));
513 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
514 (uint16_t *) tmp16, 1);
516 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
517 (uint16_t *) (mtod(m, caddr_t) + i),
519 if ((i = (m->m_len - i) & 1) != 0) {
520 tmp16[0] = *(mtod(m, caddr_t) +
525 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
526 (uint16_t *) tmp16, 1);
528 * If there were other frames chained, update the
529 * chain in the last one.
531 if (sc->tx_head != sc->tx_tail) {
532 if (sc->tx_tail != dest) {
533 CSR_WRITE_2(sc, HOST_ADDR_REG,
534 sc->tx_last + XMT_Chain_Point);
535 CSR_WRITE_2(sc, IO_PORT_REG, dest);
537 CSR_WRITE_2(sc, HOST_ADDR_REG,
538 sc->tx_last + XMT_Byte_Count);
539 i = CSR_READ_2(sc, IO_PORT_REG);
540 CSR_WRITE_2(sc, HOST_ADDR_REG,
541 sc->tx_last + XMT_Byte_Count);
542 CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit);
546 * Resume normal operation of the card:
547 * - Make a dummy read to flush the DRAM write
549 * - Enable receive and transmit interrupts.
550 * - Send Transmit or Resume_XMT command, as
553 CSR_READ_2(sc, IO_PORT_REG);
555 CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
557 if (sc->tx_head == sc->tx_tail) {
558 CSR_WRITE_2(sc, XMT_BAR, dest);
559 CSR_WRITE_1(sc, CMD_REG, Transmit_CMD);
561 DODEBUG(Sent_Pkts, printf("Transmit\n"););
563 CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD);
564 DODEBUG(Sent_Pkts, printf("Resume\n"););
576 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
577 DODEBUG(Status, printf("OACTIVE start\n"););
581 DODEBUG(Start_End, printf("ex_start%d: finish\n", unit););
585 ex_stop(struct ex_softc *sc)
588 DODEBUG(Start_End, printf("ex_stop%d: start\n", unit););
590 EX_ASSERT_LOCKED(sc);
592 * Disable card operation:
593 * - Disable the interrupt line.
594 * - Flush transmission and disable reception.
595 * - Mask and clear all interrupts.
598 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
599 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
600 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
601 CSR_WRITE_1(sc, CMD_REG, Rcv_Stop);
602 sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
603 sc->tx_last = 0; /* XXX I think these two lines are not necessary, because ex_init will always be called again to reinit the interface. */
604 CSR_WRITE_1(sc, MASK_REG, All_Int);
605 CSR_WRITE_1(sc, STATUS_REG, All_Int);
606 CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
608 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
610 callout_stop(&sc->timer);
612 DODEBUG(Start_End, printf("ex_stop%d: finish\n", unit););
620 struct ex_softc *sc = (struct ex_softc *)arg;
621 struct ifnet *ifp = sc->ifp;
622 int int_status, send_pkts;
625 DODEBUG(Start_End, printf("ex_intr%d: start\n", unit););
629 while (loops-- > 0 &&
630 (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
631 /* don't loop forever */
632 if (int_status == 0xff)
634 if (int_status & Rx_Int) {
635 CSR_WRITE_1(sc, STATUS_REG, Rx_Int);
637 } else if (int_status & Tx_Int) {
638 CSR_WRITE_1(sc, STATUS_REG, Tx_Int);
644 printf("100 loops are not enough\n");
647 * If any packet has been transmitted, and there are queued packets to
648 * be sent, attempt to send more packets to the network card.
650 if (send_pkts && (ifp->if_snd.ifq_head != NULL))
651 ex_start_locked(ifp);
654 DODEBUG(Start_End, printf("ex_intr%d: finish\n", unit););
660 ex_tx_intr(struct ex_softc *sc)
662 struct ifnet * ifp = sc->ifp;
665 DODEBUG(Start_End, printf("ex_tx_intr%d: start\n", unit););
668 * - Cancel the watchdog.
669 * For all packets transmitted since last transmit interrupt:
670 * - Advance chain pointer to next queued packet.
671 * - Update statistics.
676 while (sc->tx_head != sc->tx_tail) {
677 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head);
679 if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit))
682 tx_status = CSR_READ_2(sc, IO_PORT_REG);
683 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);
685 if (tx_status & TX_OK_bit) {
691 ifp->if_collisions += tx_status & No_Collisions_bits;
695 * The card should be ready to accept more packets now.
698 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
700 DODEBUG(Status, printf("OIDLE tx_intr\n"););
701 DODEBUG(Start_End, printf("ex_tx_intr%d: finish\n", unit););
707 ex_rx_intr(struct ex_softc *sc)
709 struct ifnet * ifp = sc->ifp;
715 struct ether_header * eh;
717 DODEBUG(Start_End, printf("ex_rx_intr%d: start\n", unit););
720 * For all packets received since last receive interrupt:
721 * - If packet ok, read it into a new mbuf and queue it to interface,
722 * updating statistics.
723 * - If packet bad, just discard it, and update statistics.
724 * Finally, advance receive stop limit in card's memory to new location.
727 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
729 while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {
731 rx_status = CSR_READ_2(sc, IO_PORT_REG);
732 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);
733 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);
735 if (rx_status & RCV_OK_bit) {
736 MGETHDR(m, M_NOWAIT, MT_DATA);
741 ipkt->m_pkthdr.rcvif = ifp;
742 ipkt->m_pkthdr.len = pkt_len;
745 while (pkt_len > 0) {
746 if (pkt_len >= MINCLSIZE) {
748 if (m->m_flags & M_EXT) {
756 m->m_len = min(m->m_len, pkt_len);
759 * NOTE: I'm assuming that all mbufs allocated are of even length,
760 * except for the last one in an odd-length packet.
763 CSR_READ_MULTI_2(sc, IO_PORT_REG,
764 mtod(m, uint16_t *), m->m_len / 2);
767 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG);
772 MGET(m->m_next, M_NOWAIT, MT_DATA);
773 if (m->m_next == NULL) {
782 eh = mtod(ipkt, struct ether_header *);
784 if (debug_mask & Rcvd_Pkts) {
785 if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) {
786 printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":");
787 printf("%6D\n", eh->ether_dhost, ":");
792 (*ifp->if_input)(ifp, ipkt);
799 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
803 if (sc->rx_head < sc->rx_lower_limit + 2)
804 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit);
806 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2);
808 DODEBUG(Start_End, printf("ex_rx_intr%d: finish\n", unit););
815 ex_ioctl(register struct ifnet *ifp, u_long cmd, caddr_t data)
817 struct ex_softc * sc = ifp->if_softc;
818 struct ifreq * ifr = (struct ifreq *)data;
821 DODEBUG(Start_End, printf("%s: ex_ioctl: start ", ifp->if_xname););
827 error = ether_ioctl(ifp, cmd, data);
831 DODEBUG(Start_End, printf("SIOCSIFFLAGS"););
833 if ((ifp->if_flags & IFF_UP) == 0 &&
834 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
848 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd);
851 DODEBUG(Start_End, printf("unknown"););
855 DODEBUG(Start_End, printf("\n%s: ex_ioctl: finish\n", ifp->if_xname););
861 ex_setmulti(struct ex_softc *sc)
864 struct ifmultiaddr *maddr;
873 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
874 if (maddr->ifma_addr->sa_family != AF_LINK)
878 if_maddr_runlock(ifp);
880 if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI)
882 /* Interface is in promiscuous mode or there are too many
883 * multicast addresses for the card to handle */
884 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
885 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);
886 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
887 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
889 else if ((ifp->if_flags & IFF_MULTICAST) && (count > 0)) {
890 /* Program multicast addresses plus our MAC address
892 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
893 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);
894 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
895 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
897 /* Borrow space from TX buffer; this should be safe
898 * as this is only called from ex_init */
900 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit);
901 CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD);
902 CSR_WRITE_2(sc, IO_PORT_REG, 0);
903 CSR_WRITE_2(sc, IO_PORT_REG, 0);
904 CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6);
907 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
908 if (maddr->ifma_addr->sa_family != AF_LINK)
911 addr = (uint16_t*)LLADDR((struct sockaddr_dl *)
913 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
914 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
915 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
917 if_maddr_runlock(ifp);
919 /* Program our MAC address as well */
920 /* XXX: Is this necessary? The Linux driver does this
921 * but the NetBSD driver does not */
922 addr = (uint16_t*)IF_LLADDR(sc->ifp);
923 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
924 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
925 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
927 CSR_READ_2(sc, IO_PORT_REG);
928 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
929 CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD);
931 sc->tx_head = sc->tx_lower_limit;
932 sc->tx_tail = sc->tx_head + XMT_HEADER_LEN + (count + 1) * 6;
934 for (timeout=0; timeout<100; timeout++) {
936 if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0)
939 status = CSR_READ_1(sc, CMD_REG);
940 CSR_WRITE_1(sc, STATUS_REG, Exec_Int);
944 sc->tx_head = sc->tx_tail;
948 /* No multicast or promiscuous mode */
949 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
950 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);
951 /* ~(Multi_IA | Promisc_Mode) */
952 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
953 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
958 ex_reset(struct ex_softc *sc)
961 DODEBUG(Start_End, printf("ex_reset%d: start\n", unit););
963 EX_ASSERT_LOCKED(sc);
967 DODEBUG(Start_End, printf("ex_reset%d: finish\n", unit););
973 ex_watchdog(void *arg)
975 struct ex_softc * sc = arg;
976 struct ifnet *ifp = sc->ifp;
978 if (sc->tx_timeout && --sc->tx_timeout == 0) {
979 DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: start\n"););
981 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
983 DODEBUG(Status, printf("OIDLE watchdog\n"););
987 ex_start_locked(ifp);
989 DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: finish\n"););
992 callout_reset(&sc->timer, hz, ex_watchdog, sc);
996 ex_get_media(struct ex_softc *sc)
1001 media = ex_eeprom_read(sc, EE_W5);
1003 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1004 current = CSR_READ_1(sc, REG3);
1005 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
1007 if ((current & TPE_bit) && (media & EE_W5_PORT_TPE))
1008 return(IFM_ETHER|IFM_10_T);
1009 if ((current & BNC_bit) && (media & EE_W5_PORT_BNC))
1010 return(IFM_ETHER|IFM_10_2);
1012 if (media & EE_W5_PORT_AUI)
1013 return (IFM_ETHER|IFM_10_5);
1015 return (IFM_ETHER|IFM_AUTO);
1022 struct ex_softc * sc = ifp->if_softc;
1024 if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER)
1031 ex_ifmedia_sts(ifp, ifmr)
1033 struct ifmediareq * ifmr;
1035 struct ex_softc * sc = ifp->if_softc;
1038 ifmr->ifm_active = ex_get_media(sc);
1039 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1046 ex_eeprom_read(struct ex_softc *sc, int location)
1050 int read_cmd = location | EE_READ_CMD;
1051 short ctrl_val = EECS;
1053 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1054 CSR_WRITE_1(sc, EEPROM_REG, EECS);
1055 for (i = 8; i >= 0; i--) {
1056 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
1057 CSR_WRITE_1(sc, EEPROM_REG, outval);
1058 CSR_WRITE_1(sc, EEPROM_REG, outval | EESK);
1060 CSR_WRITE_1(sc, EEPROM_REG, outval);
1063 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1065 for (i = 16; i > 0; i--) {
1066 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1068 data = (data << 1) |
1069 ((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0);
1070 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1075 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1077 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1079 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);