2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
62 struct fw_asybindreq {
72 #define MAXREC(x) (2 << (x))
73 #define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */
74 #define FWMAXQUEUE 128
76 #define FWLOCALBUS 0xffc0
78 #define FWTCODE_WREQQ 0
79 #define FWTCODE_WREQB 1
80 #define FWTCODE_WRES 2
81 #define FWTCODE_RREQQ 4
82 #define FWTCODE_RREQB 5
83 #define FWTCODE_RRESQ 6
84 #define FWTCODE_RRESB 7
85 #define FWTCODE_CYCS 8
86 #define FWTCODE_LREQ 9
87 #define FWTCODE_STREAM 0xa
88 #define FWTCODE_LRES 0xb
89 #define FWTCODE_PHY 0xe
96 #define FWRCODE_COMPLETE 0
97 #define FWRCODE_ER_CONFL 4
98 #define FWRCODE_ER_DATA 5
99 #define FWRCODE_ER_TYPE 6
100 #define FWRCODE_ER_ADDR 7
110 #define FWSPD_S1600 4
111 #define FWSPD_S3200 5
113 #define FWP_TL_VALID (1 << 7)
123 #if BYTE_ORDER == BIG_ENDIAN
124 #define BIT4x2(x,y) uint8_t x:4, y:4
125 #define BIT16x2(x,y) uint32_t x:16, y:16
127 #define BIT4x2(x,y) uint8_t y:4, x:4
128 #define BIT16x2(x,y) uint32_t y:16, x:16
132 #if BYTE_ORDER == BIG_ENDIAN
133 #define COMMON_HDR(a,b,c,d) uint32_t a:16,b:8,c:4,d:4
134 #define COMMON_RES(a,b,c,d) uint32_t a:16,b:4,c:4,d:8
136 #define COMMON_HDR(a,b,c,d) uint32_t d:4,c:4,b:8,a:16
137 #define COMMON_RES(a,b,c,d) uint32_t d:8,c:4,b:4,a:16
144 COMMON_HDR(, , tcode, );
147 COMMON_HDR(len, chtag, tcode, sy);
151 COMMON_HDR(dst, tlrt, tcode, pri);
155 COMMON_HDR(dst, tlrt, tcode, pri);
156 BIT16x2(src, dest_hi);
160 COMMON_HDR(dst, tlrt, tcode, pri);
161 COMMON_RES(src, rtcode, , );
165 COMMON_HDR(dst, tlrt, tcode, pri);
166 BIT16x2(src, dest_hi);
168 BIT16x2(len, extcode);
171 COMMON_HDR(dst, tlrt, tcode, pri);
172 BIT16x2(src, dest_hi);
177 COMMON_HDR(dst, tlrt, tcode, pri);
178 BIT16x2(src, dest_hi);
183 COMMON_HDR(dst, tlrt, tcode, pri);
184 COMMON_RES(src, rtcode, , );
189 COMMON_HDR(dst, tlrt, tcode, pri);
190 BIT16x2(src, dest_hi);
192 BIT16x2(len, extcode);
196 COMMON_HDR(dst, tlrt, tcode, pri);
197 BIT16x2(src, dest_hi);
199 BIT16x2(len, extcode);
203 COMMON_HDR(dst, tlrt, tcode, pri);
204 COMMON_RES(src, rtcode, , );
206 BIT16x2(len, extcode);
210 COMMON_HDR(dst, tlrt, tcode, pri);
211 COMMON_RES(src, rtcode, , );
213 BIT16x2(len, extcode);
220 * Response code (rtcode)
222 /* The node has successfully completed the command. */
224 /* A resource conflict was detected. The request may be retried. */
225 #define RESP_CONFLICT_ERROR 4
226 /* Hardware error, data is unavailable. */
227 #define RESP_DATA_ERROR 5
228 /* A field in the request packet header was set to an unsupported or incorrect
229 * value, or an invalid transaction was attempted (e.g., a write to a read-only
231 #define RESP_TYPE_ERROR 6
232 /* The destination offset field in the request was set to an address not
233 * accessible in the destination node. */
234 #define RESP_ADDRESS_ERROR 7
237 * Extended transaction code (extcode)
239 #define EXTCODE_MASK_SWAP 1
240 #define EXTCODE_CMP_SWAP 2
241 #define EXTCODE_FETCH_ADD 3
242 #define EXTCODE_LITTLE_ADD 4
243 #define EXTCODE_BOUNDED_ADD 5
244 #define EXTCODE_WRAP_ADD 6
249 #define FW_EUI64_BYTE(eui, x) \
251 ((eui)->hi >> (8*(3-(x)))): \
252 ((eui)->lo >> (8*(7-(x)))) \
254 #define FW_EUI64_EQUAL(x, y) \
255 ((x).hi == (y).hi && (x).lo == (y).lo)
261 #define FWASREQNODE 0
264 #define FWASREQSTREAM 3
280 #define FW_MAX_DEVLST 70
281 struct fw_devlstreq {
284 struct fw_devinfo dev[FW_MAX_DEVLST];
288 * Defined in IEEE 1394a-2000
291 #define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
292 #define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
293 #define FW_SELF_ID_PORT_NOT_CONNECTED 1
294 #define FW_SELF_ID_PORT_NOT_EXISTS 0
296 #define FW_SELF_ID_PAGE0 0
297 #define FW_SELF_ID_PAGE1 1
299 #if BYTE_ORDER == BIG_ENDIAN
353 uint32_t more_packets:1,
369 uint32_t more_packets:1,
403 struct fw_topology_map {
407 uint32_t self_id_count:16,
409 union fw_self_id self_id[4*64];
412 struct fw_speed_map {
416 uint8_t speed[64][64];
426 * FireWire specific system requests.
428 #define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq)
429 #define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq)
430 #define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq)
431 #define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq)
432 #define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq)
433 #define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq)
435 #define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq)
436 #define FW_IBUSRST _IOR('S', 1, unsigned int)
437 #define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq)
438 #define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq)
439 #define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq)
440 #define FW_GTPMAP _IOR('S', 5, struct fw_topology_map)
441 #define FW_GCROM _IOWR('S', 7, struct fw_crom_buf)
443 #define FW_SDEUI64 _IOW('S', 20, struct fw_eui64)
444 #define FW_GDEUI64 _IOR('S', 21, struct fw_eui64)
446 #define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t)
447 #define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t)
448 #define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t)
449 #define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t)
451 #define DUMPDMA _IOWR('S', 82, uint32_t)
455 #define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
457 #if defined(__DragonFly__) || __FreeBSD_version < 500000
458 #define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8))
459 #define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff))
462 #define MAKEMINOR(f, u, s) \
463 ((f) | (((u) & 0xff) << 8) | (s & 0xff))
464 #define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8)
465 #define DEV2SUB(x) (dev2unit(x) & 0xff)
467 #define FWMEM_FLAG 0x10000
468 #define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG)