2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
72 #include <machine/resource.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <dev/fxp/if_fxpreg.h>
81 #include <dev/fxp/if_fxpvar.h>
82 #include <dev/fxp/rcvbundl.h>
84 MODULE_DEPEND(fxp, pci, 1, 1, 1);
85 MODULE_DEPEND(fxp, ether, 1, 1, 1);
86 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
87 #include "miibus_if.h"
90 * NOTE! On !x86 we typically have an alignment constraint. The
91 * card DMAs the packet immediately following the RFA. However,
92 * the first thing in the packet is a 14-byte Ethernet header.
93 * This means that the packet is misaligned. To compensate,
94 * we actually offset the RFA 2 bytes into the cluster. This
95 * alignes the packet after the Ethernet header at a 32-bit
96 * boundary. HOWEVER! This means that the RFA is misaligned!
98 #define RFA_ALIGNMENT_FUDGE 2
101 * Set initial transmit threshold at 64 (512 bytes). This is
102 * increased by 64 (512 bytes) at a time, to maximum of 192
103 * (1536 bytes), if an underrun occurs.
105 static int tx_threshold = 64;
108 * The configuration byte map has several undefined fields which
109 * must be one or must be zero. Set up a template for these bits.
110 * The actual configuration is performed in fxp_init_body.
112 * See struct fxp_cb_config for the bit definitions.
114 static const u_char const fxp_cb_config_template[] = {
115 0x0, 0x0, /* cb_status */
116 0x0, 0x0, /* cb_command */
117 0x0, 0x0, 0x0, 0x0, /* link_addr */
153 * Claim various Intel PCI device identifiers for this driver. The
154 * sub-vendor and sub-device field are extensively used to identify
155 * particular variants, but we don't currently differentiate between
158 static const struct fxp_ident const fxp_ident_table[] = {
159 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
160 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
161 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
162 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
163 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
164 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
170 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
171 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
172 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
175 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
176 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
177 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
178 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
179 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
180 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
181 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
182 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
183 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
184 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
185 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
186 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
187 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
188 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
189 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
191 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
192 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
193 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
194 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
196 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
197 { 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" },
198 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
199 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
200 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
201 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
202 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
203 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
207 #ifdef FXP_IP_CSUM_WAR
208 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
210 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
213 static int fxp_probe(device_t dev);
214 static int fxp_attach(device_t dev);
215 static int fxp_detach(device_t dev);
216 static int fxp_shutdown(device_t dev);
217 static int fxp_suspend(device_t dev);
218 static int fxp_resume(device_t dev);
220 static const struct fxp_ident *fxp_find_ident(device_t dev);
221 static void fxp_intr(void *xsc);
222 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
223 struct mbuf *m, uint16_t status, int pos);
224 static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
225 uint8_t statack, int count);
226 static void fxp_init(void *xsc);
227 static void fxp_init_body(struct fxp_softc *sc, int);
228 static void fxp_tick(void *xsc);
229 static void fxp_start(struct ifnet *ifp);
230 static void fxp_start_body(struct ifnet *ifp);
231 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
232 static void fxp_txeof(struct fxp_softc *sc);
233 static void fxp_stop(struct fxp_softc *sc);
234 static void fxp_release(struct fxp_softc *sc);
235 static int fxp_ioctl(struct ifnet *ifp, u_long command,
237 static void fxp_watchdog(struct fxp_softc *sc);
238 static void fxp_add_rfabuf(struct fxp_softc *sc,
240 static void fxp_discard_rfabuf(struct fxp_softc *sc,
242 static int fxp_new_rfabuf(struct fxp_softc *sc,
244 static int fxp_mc_addrs(struct fxp_softc *sc);
245 static void fxp_mc_setup(struct fxp_softc *sc);
246 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
248 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
250 static void fxp_autosize_eeprom(struct fxp_softc *sc);
251 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
252 int offset, int words);
253 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
254 int offset, int words);
255 static int fxp_ifmedia_upd(struct ifnet *ifp);
256 static void fxp_ifmedia_sts(struct ifnet *ifp,
257 struct ifmediareq *ifmr);
258 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
259 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
260 struct ifmediareq *ifmr);
261 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
262 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
264 static void fxp_miibus_statchg(device_t dev);
265 static void fxp_load_ucode(struct fxp_softc *sc);
266 static void fxp_update_stats(struct fxp_softc *sc);
267 static void fxp_sysctl_node(struct fxp_softc *sc);
268 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
270 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
271 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
272 static void fxp_scb_wait(struct fxp_softc *sc);
273 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
274 static void fxp_dma_wait(struct fxp_softc *sc,
275 volatile uint16_t *status, bus_dma_tag_t dmat,
278 static device_method_t fxp_methods[] = {
279 /* Device interface */
280 DEVMETHOD(device_probe, fxp_probe),
281 DEVMETHOD(device_attach, fxp_attach),
282 DEVMETHOD(device_detach, fxp_detach),
283 DEVMETHOD(device_shutdown, fxp_shutdown),
284 DEVMETHOD(device_suspend, fxp_suspend),
285 DEVMETHOD(device_resume, fxp_resume),
288 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
289 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
290 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
295 static driver_t fxp_driver = {
298 sizeof(struct fxp_softc),
301 static devclass_t fxp_devclass;
303 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
304 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
306 static struct resource_spec fxp_res_spec_mem[] = {
307 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
308 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
312 static struct resource_spec fxp_res_spec_io[] = {
313 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
314 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
319 * Wait for the previous command to be accepted (but not necessarily
323 fxp_scb_wait(struct fxp_softc *sc)
331 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
334 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
335 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
336 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
337 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
338 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
339 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
344 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
347 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
348 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
355 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
356 bus_dma_tag_t dmat, bus_dmamap_t map)
360 for (i = 10000; i > 0; i--) {
362 bus_dmamap_sync(dmat, map,
363 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
364 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
368 device_printf(sc->dev, "DMA timeout\n");
371 static const struct fxp_ident *
372 fxp_find_ident(device_t dev)
376 const struct fxp_ident *ident;
378 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
379 devid = pci_get_device(dev);
380 revid = pci_get_revid(dev);
381 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
382 if (ident->devid == devid &&
383 (ident->revid == revid || ident->revid == -1)) {
392 * Return identification string if this device is ours.
395 fxp_probe(device_t dev)
397 const struct fxp_ident *ident;
399 ident = fxp_find_ident(dev);
401 device_set_desc(dev, ident->name);
402 return (BUS_PROBE_DEFAULT);
408 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
415 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
417 *addr = segs->ds_addr;
421 fxp_attach(device_t dev)
423 struct fxp_softc *sc;
424 struct fxp_cb_tx *tcbp;
429 uint16_t data, myea[ETHER_ADDR_LEN / 2];
430 u_char eaddr[ETHER_ADDR_LEN];
431 int error, flags, i, pmc, prefer_iomap;
434 sc = device_get_softc(dev);
436 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
438 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
439 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
440 fxp_serial_ifmedia_sts);
442 ifp = sc->ifp = if_alloc(IFT_ETHER);
444 device_printf(dev, "can not if_alloc()\n");
450 * Enable bus mastering.
452 pci_enable_busmaster(dev);
453 val = pci_read_config(dev, PCIR_COMMAND, 2);
456 * Figure out which we should try first - memory mapping or i/o mapping?
457 * We default to memory mapping. Then we accept an override from the
458 * command line. Then we check to see which one is enabled.
461 resource_int_value(device_get_name(dev), device_get_unit(dev),
462 "prefer_iomap", &prefer_iomap);
464 sc->fxp_spec = fxp_res_spec_io;
466 sc->fxp_spec = fxp_res_spec_mem;
468 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
470 if (sc->fxp_spec == fxp_res_spec_mem)
471 sc->fxp_spec = fxp_res_spec_io;
473 sc->fxp_spec = fxp_res_spec_mem;
474 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
477 device_printf(dev, "could not allocate resources\n");
483 device_printf(dev, "using %s space register mapping\n",
484 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
488 * Put CU/RU idle state and prepare full reset.
490 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
492 /* Full reset and disable interrupts. */
493 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
495 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
498 * Find out how large of an SEEPROM we have.
500 fxp_autosize_eeprom(sc);
503 * Find out the chip revision; lump all 82557 revs together.
505 sc->ident = fxp_find_ident(dev);
506 if (sc->ident->ich > 0) {
507 /* Assume ICH controllers are 82559. */
508 sc->revision = FXP_REV_82559_A0;
510 fxp_read_eeprom(sc, &data, 5, 1);
511 if ((data >> 8) == 1)
512 sc->revision = FXP_REV_82557;
514 sc->revision = pci_get_revid(dev);
518 * Check availability of WOL. 82559ER does not support WOL.
520 if (sc->revision >= FXP_REV_82558_A4 &&
521 sc->revision != FXP_REV_82559S_A) {
522 fxp_read_eeprom(sc, &data, 10, 1);
523 if ((data & 0x20) != 0 &&
524 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
525 sc->flags |= FXP_FLAG_WOLCAP;
528 /* Receiver lock-up workaround detection. */
529 if (sc->revision < FXP_REV_82558_A4) {
530 fxp_read_eeprom(sc, &data, 3, 1);
531 if ((data & 0x03) != 0x03) {
532 sc->flags |= FXP_FLAG_RXBUG;
533 device_printf(dev, "Enabling Rx lock-up workaround\n");
538 * Determine whether we must use the 503 serial interface.
540 fxp_read_eeprom(sc, &data, 6, 1);
541 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
542 && (data & FXP_PHY_SERIAL_ONLY))
543 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
547 * Enable workarounds for certain chip revision deficiencies.
549 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
550 * some systems based a normal 82559 design, have a defect where
551 * the chip can cause a PCI protocol violation if it receives
552 * a CU_RESUME command when it is entering the IDLE state. The
553 * workaround is to disable Dynamic Standby Mode, so the chip never
554 * deasserts CLKRUN#, and always remains in an active state.
556 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
558 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
559 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
560 fxp_read_eeprom(sc, &data, 10, 1);
561 if (data & 0x02) { /* STB enable */
566 "Disabling dynamic standby mode in EEPROM\n");
568 fxp_write_eeprom(sc, &data, 10, 1);
569 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
571 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
572 fxp_read_eeprom(sc, &data, i, 1);
575 i = (1 << sc->eeprom_size) - 1;
576 cksum = 0xBABA - cksum;
577 fxp_read_eeprom(sc, &data, i, 1);
578 fxp_write_eeprom(sc, &cksum, i, 1);
580 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
584 * If the user elects to continue, try the software
585 * workaround, as it is better than nothing.
587 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
593 * If we are not a 82557 chip, we can enable extended features.
595 if (sc->revision != FXP_REV_82557) {
597 * If MWI is enabled in the PCI configuration, and there
598 * is a valid cacheline size (8 or 16 dwords), then tell
599 * the board to turn on MWI.
601 if (val & PCIM_CMD_MWRICEN &&
602 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
603 sc->flags |= FXP_FLAG_MWI_ENABLE;
605 /* turn on the extended TxCB feature */
606 sc->flags |= FXP_FLAG_EXT_TXCB;
608 /* enable reception of long frames for VLAN */
609 sc->flags |= FXP_FLAG_LONG_PKT_EN;
611 /* a hack to get long VLAN frames on a 82557 */
612 sc->flags |= FXP_FLAG_SAVE_BAD;
615 /* For 82559 or later chips, Rx checksum offload is supported. */
616 if (sc->revision >= FXP_REV_82559_A0) {
617 /* 82559ER does not support Rx checksum offloading. */
618 if (sc->ident->devid != 0x1209)
619 sc->flags |= FXP_FLAG_82559_RXCSUM;
622 * Enable use of extended RFDs and TCBs for 82550
623 * and later chips. Note: we need extended TXCB support
624 * too, but that's already enabled by the code above.
625 * Be careful to do this only on the right devices.
627 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
628 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
629 || sc->revision == FXP_REV_82551_10) {
630 sc->rfa_size = sizeof (struct fxp_rfa);
631 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
632 sc->flags |= FXP_FLAG_EXT_RFA;
633 /* Use extended RFA instead of 82559 checksum mode. */
634 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
636 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
637 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
641 * Allocate DMA tags and DMA safe memory.
643 sc->maxtxseg = FXP_NTXSEG;
644 sc->maxsegsize = MCLBYTES;
645 if (sc->flags & FXP_FLAG_EXT_RFA) {
647 sc->maxsegsize = FXP_TSO_SEGSIZE;
649 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
650 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
651 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
652 sc->maxtxseg, sc->maxsegsize, 0,
653 busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
655 device_printf(dev, "could not create TX DMA tag\n");
659 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
660 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
661 MCLBYTES, 1, MCLBYTES, 0,
662 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
664 device_printf(dev, "could not create RX DMA tag\n");
668 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
669 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
670 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
671 busdma_lock_mutex, &Giant, &sc->fxp_stag);
673 device_printf(dev, "could not create stats DMA tag\n");
677 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
678 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
680 device_printf(dev, "could not allocate stats DMA memory\n");
683 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
684 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
686 device_printf(dev, "could not load the stats DMA buffer\n");
690 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
691 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
692 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
693 busdma_lock_mutex, &Giant, &sc->cbl_tag);
695 device_printf(dev, "could not create TxCB DMA tag\n");
699 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
700 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
702 device_printf(dev, "could not allocate TxCB DMA memory\n");
706 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
707 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
708 &sc->fxp_desc.cbl_addr, 0);
710 device_printf(dev, "could not load TxCB DMA buffer\n");
714 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
715 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
716 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
717 busdma_lock_mutex, &Giant, &sc->mcs_tag);
720 "could not create multicast setup DMA tag\n");
724 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
725 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
728 "could not allocate multicast setup DMA memory\n");
731 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
732 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
735 "can't load the multicast setup DMA buffer\n");
740 * Pre-allocate the TX DMA maps and setup the pointers to
741 * the TX command blocks.
743 txp = sc->fxp_desc.tx_list;
744 tcbp = sc->fxp_desc.cbl_list;
745 for (i = 0; i < FXP_NTXCB; i++) {
746 txp[i].tx_cb = tcbp + i;
747 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
749 device_printf(dev, "can't create DMA map for TX\n");
753 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
755 device_printf(dev, "can't create spare DMA map\n");
760 * Pre-allocate our receive buffers.
762 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
763 for (i = 0; i < FXP_NRFABUFS; i++) {
764 rxp = &sc->fxp_desc.rx_list[i];
765 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
767 device_printf(dev, "can't create DMA map for RX\n");
770 if (fxp_new_rfabuf(sc, rxp) != 0) {
774 fxp_add_rfabuf(sc, rxp);
780 fxp_read_eeprom(sc, myea, 0, 3);
781 eaddr[0] = myea[0] & 0xff;
782 eaddr[1] = myea[0] >> 8;
783 eaddr[2] = myea[1] & 0xff;
784 eaddr[3] = myea[1] >> 8;
785 eaddr[4] = myea[2] & 0xff;
786 eaddr[5] = myea[2] >> 8;
788 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
789 pci_get_vendor(dev), pci_get_device(dev),
790 pci_get_subvendor(dev), pci_get_subdevice(dev),
792 fxp_read_eeprom(sc, &data, 10, 1);
793 device_printf(dev, "Dynamic Standby mode is %s\n",
794 data & 0x02 ? "enabled" : "disabled");
798 * If this is only a 10Mbps device, then there is no MII, and
799 * the PHY will use a serial interface instead.
801 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
802 * doesn't have a programming interface of any sort. The
803 * media is sensed automatically based on how the link partner
804 * is configured. This is, in essence, manual configuration.
806 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
807 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
808 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
811 * i82557 wedge when isolating all of their PHYs.
813 flags = MIIF_NOISOLATE;
814 if (sc->revision >= FXP_REV_82558_A4)
815 flags |= MIIF_DOPAUSE;
816 error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd,
817 fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
818 MII_OFFSET_ANY, flags);
820 device_printf(dev, "attaching PHYs failed\n");
825 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
826 ifp->if_init = fxp_init;
828 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
829 ifp->if_ioctl = fxp_ioctl;
830 ifp->if_start = fxp_start;
832 ifp->if_capabilities = ifp->if_capenable = 0;
834 /* Enable checksum offload/TSO for 82550 or better chips */
835 if (sc->flags & FXP_FLAG_EXT_RFA) {
836 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
837 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
838 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
841 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
842 ifp->if_capabilities |= IFCAP_RXCSUM;
843 ifp->if_capenable |= IFCAP_RXCSUM;
846 if (sc->flags & FXP_FLAG_WOLCAP) {
847 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
848 ifp->if_capenable |= IFCAP_WOL_MAGIC;
851 #ifdef DEVICE_POLLING
852 /* Inform the world we support polling. */
853 ifp->if_capabilities |= IFCAP_POLLING;
857 * Attach the interface.
859 ether_ifattach(ifp, eaddr);
862 * Tell the upper layer(s) we support long frames.
863 * Must appear after the call to ether_ifattach() because
864 * ether_ifattach() sets ifi_hdrlen to the default value.
866 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
867 ifp->if_capabilities |= IFCAP_VLAN_MTU;
868 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
869 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
870 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
871 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
872 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
873 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
877 * Let the system queue as many packets as we have available
880 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
881 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
882 IFQ_SET_READY(&ifp->if_snd);
885 * Hook our interrupt after all initialization is complete.
887 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
888 NULL, fxp_intr, sc, &sc->ih);
890 device_printf(dev, "could not setup irq\n");
891 ether_ifdetach(sc->ifp);
896 * Configure hardware to reject magic frames otherwise
897 * system will hang on recipt of magic frames.
899 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
901 /* Clear wakeup events. */
902 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
903 fxp_init_body(sc, 1);
915 * Release all resources. The softc lock should not be held and the
916 * interrupt should already be torn down.
919 fxp_release(struct fxp_softc *sc)
925 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
926 KASSERT(sc->ih == NULL,
927 ("fxp_release() called with intr handle still active"));
929 device_delete_child(sc->dev, sc->miibus);
930 bus_generic_detach(sc->dev);
931 ifmedia_removeall(&sc->sc_media);
932 if (sc->fxp_desc.cbl_list) {
933 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
934 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
938 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
939 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
942 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
943 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
945 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
946 if (sc->fxp_rxmtag) {
947 for (i = 0; i < FXP_NRFABUFS; i++) {
948 rxp = &sc->fxp_desc.rx_list[i];
949 if (rxp->rx_mbuf != NULL) {
950 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
951 BUS_DMASYNC_POSTREAD);
952 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
953 m_freem(rxp->rx_mbuf);
955 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
957 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
958 bus_dma_tag_destroy(sc->fxp_rxmtag);
960 if (sc->fxp_txmtag) {
961 for (i = 0; i < FXP_NTXCB; i++) {
962 txp = &sc->fxp_desc.tx_list[i];
963 if (txp->tx_mbuf != NULL) {
964 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
965 BUS_DMASYNC_POSTWRITE);
966 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
967 m_freem(txp->tx_mbuf);
969 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
971 bus_dma_tag_destroy(sc->fxp_txmtag);
974 bus_dma_tag_destroy(sc->fxp_stag);
976 bus_dma_tag_destroy(sc->cbl_tag);
978 bus_dma_tag_destroy(sc->mcs_tag);
982 mtx_destroy(&sc->sc_mtx);
989 fxp_detach(device_t dev)
991 struct fxp_softc *sc = device_get_softc(dev);
993 #ifdef DEVICE_POLLING
994 if (sc->ifp->if_capenable & IFCAP_POLLING)
995 ether_poll_deregister(sc->ifp);
1000 * Stop DMA and drop transmit queue, but disable interrupts first.
1002 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1005 callout_drain(&sc->stat_ch);
1008 * Close down routes etc.
1010 ether_ifdetach(sc->ifp);
1013 * Unhook interrupt before dropping lock. This is to prevent
1014 * races with fxp_intr().
1016 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1019 /* Release our allocated resources. */
1025 * Device shutdown routine. Called at system shutdown after sync. The
1026 * main purpose of this routine is to shut off receiver DMA so that
1027 * kernel memory doesn't get clobbered during warmboot.
1030 fxp_shutdown(device_t dev)
1034 * Make sure that DMA is disabled prior to reboot. Not doing
1035 * do could allow DMA to corrupt kernel memory during the
1036 * reboot before the driver initializes.
1038 return (fxp_suspend(dev));
1042 * Device suspend routine. Stop the interface and save some PCI
1043 * settings in case the BIOS doesn't restore them properly on
1047 fxp_suspend(device_t dev)
1049 struct fxp_softc *sc = device_get_softc(dev);
1057 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1058 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1059 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1060 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1062 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1063 sc->flags |= FXP_FLAG_WOL;
1064 /* Reconfigure hardware to accept magic frames. */
1065 fxp_init_body(sc, 1);
1067 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1078 * Device resume routine. re-enable busmastering, and restart the interface if
1082 fxp_resume(device_t dev)
1084 struct fxp_softc *sc = device_get_softc(dev);
1085 struct ifnet *ifp = sc->ifp;
1091 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1092 sc->flags &= ~FXP_FLAG_WOL;
1093 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1094 /* Disable PME and clear PME status. */
1095 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1096 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1097 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1098 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1099 CSR_READ_1(sc, FXP_CSR_PMDR));
1102 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1105 /* reinitialize interface if necessary */
1106 if (ifp->if_flags & IFF_UP)
1107 fxp_init_body(sc, 1);
1116 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1124 for (x = 1 << (length - 1); x; x >>= 1) {
1126 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1128 reg = FXP_EEPROM_EECS;
1129 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1131 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1133 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1139 * Read from the serial EEPROM. Basically, you manually shift in
1140 * the read opcode (one bit at a time) and then shift in the address,
1141 * and then you shift out the data (all of this one bit at a time).
1142 * The word size is 16 bits, so you have to provide the address for
1143 * every 16 bits of data.
1146 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1153 * Shift in read opcode.
1155 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1160 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1162 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1164 reg = FXP_EEPROM_EECS;
1165 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1167 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1169 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1171 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1173 if (autosize && reg == 0) {
1174 sc->eeprom_size = data;
1182 reg = FXP_EEPROM_EECS;
1183 for (x = 1 << 15; x; x >>= 1) {
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1186 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1188 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1198 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1203 * Erase/write enable.
1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1206 fxp_eeprom_shiftin(sc, 0x4, 3);
1207 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1208 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1211 * Shift in write opcode, address, data.
1213 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1214 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1215 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1216 fxp_eeprom_shiftin(sc, data, 16);
1217 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1220 * Wait for EEPROM to finish up.
1222 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1224 for (i = 0; i < 1000; i++) {
1225 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1229 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1232 * Erase/write disable.
1234 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1235 fxp_eeprom_shiftin(sc, 0x4, 3);
1236 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1237 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1244 * Figure out EEPROM size.
1246 * 559's can have either 64-word or 256-word EEPROMs, the 558
1247 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1248 * talks about the existance of 16 to 256 word EEPROMs.
1250 * The only known sizes are 64 and 256, where the 256 version is used
1251 * by CardBus cards to store CIS information.
1253 * The address is shifted in msb-to-lsb, and after the last
1254 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1255 * after which follows the actual data. We try to detect this zero, by
1256 * probing the data-out bit in the EEPROM control register just after
1257 * having shifted in a bit. If the bit is zero, we assume we've
1258 * shifted enough address bits. The data-out should be tri-state,
1259 * before this, which should translate to a logical one.
1262 fxp_autosize_eeprom(struct fxp_softc *sc)
1265 /* guess maximum size of 256 words */
1266 sc->eeprom_size = 8;
1269 (void) fxp_eeprom_getword(sc, 0, 1);
1273 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1277 for (i = 0; i < words; i++)
1278 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1282 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1286 for (i = 0; i < words; i++)
1287 fxp_eeprom_putword(sc, offset + i, data[i]);
1291 * Grab the softc lock and call the real fxp_start_body() routine
1294 fxp_start(struct ifnet *ifp)
1296 struct fxp_softc *sc = ifp->if_softc;
1299 fxp_start_body(ifp);
1304 * Start packet transmission on the interface.
1305 * This routine must be called with the softc lock held, and is an
1306 * internal entry point only.
1309 fxp_start_body(struct ifnet *ifp)
1311 struct fxp_softc *sc = ifp->if_softc;
1312 struct mbuf *mb_head;
1315 FXP_LOCK_ASSERT(sc, MA_OWNED);
1317 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1321 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1324 * We're finished if there is nothing more to add to the list or if
1325 * we're all filled up with buffers to transmit.
1326 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1327 * a NOP command when needed.
1330 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1331 sc->tx_queued < FXP_NTXCB - 1) {
1334 * Grab a packet to transmit.
1336 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1337 if (mb_head == NULL)
1340 if (fxp_encap(sc, &mb_head)) {
1341 if (mb_head == NULL)
1343 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1344 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1348 * Pass packet to bpf if there is a listener.
1350 BPF_MTAP(ifp, mb_head);
1354 * We're finished. If we added to the list, issue a RESUME to get DMA
1355 * going again if suspended.
1358 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1361 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1363 * Set a 5 second timer just in case we don't hear
1364 * from the card again.
1366 sc->watchdog_timer = 5;
1371 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1376 struct fxp_cb_tx *cbp;
1378 bus_dma_segment_t segs[FXP_NTXSEG];
1379 int error, i, nseg, tcp_payload;
1381 FXP_LOCK_ASSERT(sc, MA_OWNED);
1387 * Get pointer to next available tx desc.
1389 txp = sc->fxp_desc.tx_last->tx_next;
1392 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1393 * Ethernet Controller Family Open Source Software
1394 * Developer Manual says:
1395 * Using software parsing is only allowed with legal
1396 * TCP/IP or UDP/IP packets.
1398 * For all other datagrams, hardware parsing must
1400 * Software parsing appears to truncate ICMP and
1401 * fragmented UDP packets that contain one to three
1402 * bytes in the second (and final) mbuf of the packet.
1404 if (sc->flags & FXP_FLAG_EXT_RFA)
1405 txp->tx_cb->ipcb_ip_activation_high =
1406 FXP_IPCB_HARDWAREPARSING_ENABLE;
1409 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1411 * 82550/82551 requires ethernet/IP/TCP headers must be
1412 * contained in the first active transmit buffer.
1414 struct ether_header *eh;
1416 uint32_t ip_off, poff;
1418 if (M_WRITABLE(*m_head) == 0) {
1419 /* Get a writable copy. */
1420 m = m_dup(*m_head, M_DONTWAIT);
1428 ip_off = sizeof(struct ether_header);
1429 m = m_pullup(*m_head, ip_off);
1434 eh = mtod(m, struct ether_header *);
1435 /* Check the existence of VLAN tag. */
1436 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1437 ip_off = sizeof(struct ether_vlan_header);
1438 m = m_pullup(m, ip_off);
1444 m = m_pullup(m, ip_off + sizeof(struct ip));
1449 ip = (struct ip *)(mtod(m, char *) + ip_off);
1450 poff = ip_off + (ip->ip_hl << 2);
1451 m = m_pullup(m, poff + sizeof(struct tcphdr));
1456 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1457 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
1464 * Since 82550/82551 doesn't modify IP length and pseudo
1465 * checksum in the first frame driver should compute it.
1467 ip = (struct ip *)(mtod(m, char *) + ip_off);
1468 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1470 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1471 (tcp->th_off << 2));
1472 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1473 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1474 m->m_pkthdr.tso_segsz));
1475 /* Compute total TCP payload. */
1476 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1477 tcp_payload -= tcp->th_off << 2;
1479 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1481 * Deal with TCP/IP checksum offload. Note that
1482 * in order for TCP checksum offload to work,
1483 * the pseudo header checksum must have already
1484 * been computed and stored in the checksum field
1485 * in the TCP header. The stack should have
1486 * already done this for us.
1488 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1489 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1490 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1492 #ifdef FXP_IP_CSUM_WAR
1494 * XXX The 82550 chip appears to have trouble
1495 * dealing with IP header checksums in very small
1496 * datagrams, namely fragments from 1 to 3 bytes
1497 * in size. For example, say you want to transmit
1498 * a UDP packet of 1473 bytes. The packet will be
1499 * fragmented over two IP datagrams, the latter
1500 * containing only one byte of data. The 82550 will
1501 * botch the header checksum on the 1-byte fragment.
1502 * As long as the datagram contains 4 or more bytes
1503 * of data, you're ok.
1505 * The following code attempts to work around this
1506 * problem: if the datagram is less than 38 bytes
1507 * in size (14 bytes ether header, 20 bytes IP header,
1508 * plus 4 bytes of data), we punt and compute the IP
1509 * header checksum by hand. This workaround doesn't
1510 * work very well, however, since it can be fooled
1511 * by things like VLAN tags and IP options that make
1512 * the header sizes/offsets vary.
1515 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1516 if (m->m_pkthdr.len < 38) {
1518 m->m_data += ETHER_HDR_LEN;
1519 ip = mtod(m, struct ip *);
1520 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1521 m->m_data -= ETHER_HDR_LEN;
1522 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1524 txp->tx_cb->ipcb_ip_activation_high =
1525 FXP_IPCB_HARDWAREPARSING_ENABLE;
1526 txp->tx_cb->ipcb_ip_schedule |=
1527 FXP_IPCB_IP_CHECKSUM_ENABLE;
1533 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1535 if (error == EFBIG) {
1536 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg);
1543 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1544 *m_head, segs, &nseg, 0);
1550 } else if (error != 0)
1558 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1559 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1562 for (i = 0; i < nseg; i++) {
1564 * If this is an 82550/82551, then we're using extended
1565 * TxCBs _and_ we're using checksum offload. This means
1566 * that the TxCB is really an IPCB. One major difference
1567 * between the two is that with plain extended TxCBs,
1568 * the bottom half of the TxCB contains two entries from
1569 * the TBD array, whereas IPCBs contain just one entry:
1570 * one entry (8 bytes) has been sacrificed for the TCP/IP
1571 * checksum offload control bits. So to make things work
1572 * right, we have to start filling in the TBD array
1573 * starting from a different place depending on whether
1574 * the chip is an 82550/82551 or not.
1576 if (sc->flags & FXP_FLAG_EXT_RFA) {
1577 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1578 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1580 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1581 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1584 if (sc->flags & FXP_FLAG_EXT_RFA) {
1585 /* Configure dynamic TBD for 82550/82551. */
1586 cbp->tbd_number = 0xFF;
1587 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1589 cbp->tbd_number = nseg;
1590 /* Configure TSO. */
1591 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1592 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1593 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1594 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1595 FXP_IPCB_IP_CHECKSUM_ENABLE |
1596 FXP_IPCB_TCP_PACKET |
1597 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1599 /* Configure VLAN hardware tag insertion. */
1600 if ((m->m_flags & M_VLANTAG) != 0) {
1601 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1602 txp->tx_cb->ipcb_ip_activation_high |=
1603 FXP_IPCB_INSERTVLAN_ENABLE;
1607 txp->tx_cb->cb_status = 0;
1608 txp->tx_cb->byte_count = 0;
1609 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1610 txp->tx_cb->cb_command =
1611 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1614 txp->tx_cb->cb_command =
1615 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1616 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1617 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1618 txp->tx_cb->tx_threshold = tx_threshold;
1621 * Advance the end of list forward.
1623 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1624 sc->fxp_desc.tx_last = txp;
1627 * Advance the beginning of the list forward if there are
1628 * no other packets queued (when nothing is queued, tx_first
1629 * sits on the last TxCB that was sent out).
1631 if (sc->tx_queued == 0)
1632 sc->fxp_desc.tx_first = txp;
1639 #ifdef DEVICE_POLLING
1640 static poll_handler_t fxp_poll;
1643 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1645 struct fxp_softc *sc = ifp->if_softc;
1650 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1655 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1657 if (cmd == POLL_AND_CHECK_STATUS) {
1660 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1661 if (tmp == 0xff || tmp == 0) {
1663 return (rx_npkts); /* nothing to do */
1666 /* ack what we can */
1668 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1671 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1675 #endif /* DEVICE_POLLING */
1678 * Process interface interrupts.
1683 struct fxp_softc *sc = xsc;
1684 struct ifnet *ifp = sc->ifp;
1688 if (sc->suspended) {
1693 #ifdef DEVICE_POLLING
1694 if (ifp->if_capenable & IFCAP_POLLING) {
1699 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1701 * It should not be possible to have all bits set; the
1702 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1703 * all bits are set, this may indicate that the card has
1704 * been physically ejected, so ignore it.
1706 if (statack == 0xff) {
1712 * First ACK all the interrupts in this pass.
1714 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1715 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1716 fxp_intr_body(sc, ifp, statack, -1);
1722 fxp_txeof(struct fxp_softc *sc)
1728 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1729 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1730 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1731 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1732 txp = txp->tx_next) {
1733 if (txp->tx_mbuf != NULL) {
1734 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1735 BUS_DMASYNC_POSTWRITE);
1736 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1737 m_freem(txp->tx_mbuf);
1738 txp->tx_mbuf = NULL;
1739 /* clear this to reset csum offload bits */
1740 txp->tx_cb->tbd[0].tb_addr = 0;
1743 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1745 sc->fxp_desc.tx_first = txp;
1746 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1748 if (sc->tx_queued == 0)
1749 sc->watchdog_timer = 0;
1753 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1754 uint16_t status, int pos)
1756 struct ether_header *eh;
1759 int32_t hlen, len, pktlen, temp32;
1760 uint16_t csum, *opts;
1762 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1763 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1764 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1765 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1766 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1767 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1768 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1769 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1770 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1772 m->m_pkthdr.csum_data = 0xffff;
1778 pktlen = m->m_pkthdr.len;
1779 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1781 eh = mtod(m, struct ether_header *);
1782 if (eh->ether_type != htons(ETHERTYPE_IP))
1784 ip = (struct ip *)(eh + 1);
1785 if (ip->ip_v != IPVERSION)
1788 hlen = ip->ip_hl << 2;
1789 pktlen -= sizeof(struct ether_header);
1790 if (hlen < sizeof(struct ip))
1792 if (ntohs(ip->ip_len) < hlen)
1794 if (ntohs(ip->ip_len) != pktlen)
1796 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1797 return; /* can't handle fragmented packet */
1801 if (pktlen < (hlen + sizeof(struct tcphdr)))
1805 if (pktlen < (hlen + sizeof(struct udphdr)))
1807 uh = (struct udphdr *)((caddr_t)ip + hlen);
1808 if (uh->uh_sum == 0)
1809 return; /* no checksum */
1814 /* Extract computed checksum. */
1815 csum = be16dec(mtod(m, char *) + pos);
1816 /* checksum fixup for IP options */
1817 len = hlen - sizeof(struct ip);
1819 opts = (uint16_t *)(ip + 1);
1820 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1821 temp32 = csum - *opts;
1822 temp32 = (temp32 >> 16) + (temp32 & 65535);
1823 csum = temp32 & 65535;
1826 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1827 m->m_pkthdr.csum_data = csum;
1831 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1836 struct fxp_rfa *rfa;
1837 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1842 FXP_LOCK_ASSERT(sc, MA_OWNED);
1846 #ifdef DEVICE_POLLING
1847 /* Pick up a deferred RNR condition if `count' ran out last time. */
1848 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1849 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1855 * Free any finished transmit mbuf chains.
1857 * Handle the CNA event likt a CXTNO event. It used to
1858 * be that this event (control unit not ready) was not
1859 * encountered, but it is now with the SMPng modifications.
1860 * The exact sequence of events that occur when the interface
1861 * is brought up are different now, and if this event
1862 * goes unhandled, the configuration/rxfilter setup sequence
1863 * can stall for several seconds. The result is that no
1864 * packets go out onto the wire for about 5 to 10 seconds
1865 * after the interface is ifconfig'ed for the first time.
1867 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1871 * Try to start more packets transmitting.
1873 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1874 fxp_start_body(ifp);
1877 * Just return if nothing happened on the receive side.
1879 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1883 * Process receiver interrupts. If a no-resource (RNR)
1884 * condition exists, get whatever packets we can and
1885 * re-start the receiver.
1887 * When using polling, we do not process the list to completion,
1888 * so when we get an RNR interrupt we must defer the restart
1889 * until we hit the last buffer with the C bit set.
1890 * If we run out of cycles and rfa_headm has the C bit set,
1891 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1892 * that the info will be used in the subsequent polling cycle.
1895 rxp = sc->fxp_desc.rx_head;
1897 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1898 RFA_ALIGNMENT_FUDGE);
1899 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1900 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1902 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1903 if (count >= 0 && count-- == 0) {
1905 /* Defer RNR processing until the next time. */
1906 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1911 #endif /* DEVICE_POLLING */
1913 status = le16toh(rfa->rfa_status);
1914 if ((status & FXP_RFA_STATUS_C) == 0)
1917 if ((status & FXP_RFA_STATUS_RNR) != 0)
1920 * Advance head forward.
1922 sc->fxp_desc.rx_head = rxp->rx_next;
1925 * Add a new buffer to the receive chain.
1926 * If this fails, the old buffer is recycled
1929 if (fxp_new_rfabuf(sc, rxp) == 0) {
1933 * Fetch packet length (the top 2 bits of
1934 * actual_size are flags set by the controller
1935 * upon completion), and drop the packet in case
1936 * of bogus length or CRC errors.
1938 total_len = le16toh(rfa->actual_size) & 0x3fff;
1939 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1940 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1941 /* Adjust for appended checksum bytes. */
1944 if (total_len < (int)sizeof(struct ether_header) ||
1945 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1947 status & (FXP_RFA_STATUS_CRC |
1948 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1950 fxp_add_rfabuf(sc, rxp);
1954 m->m_pkthdr.len = m->m_len = total_len;
1955 m->m_pkthdr.rcvif = ifp;
1957 /* Do IP checksum checking. */
1958 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1959 fxp_rxcsum(sc, ifp, m, status, total_len);
1960 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1961 (status & FXP_RFA_STATUS_VLAN) != 0) {
1962 m->m_pkthdr.ether_vtag =
1963 ntohs(rfa->rfax_vlan_id);
1964 m->m_flags |= M_VLANTAG;
1967 * Drop locks before calling if_input() since it
1968 * may re-enter fxp_start() in the netisr case.
1969 * This would result in a lock reversal. Better
1970 * performance might be obtained by chaining all
1971 * packets received, dropping the lock, and then
1972 * calling if_input() on each one.
1975 (*ifp->if_input)(ifp, m);
1978 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1981 /* Reuse RFA and loaded DMA map. */
1983 fxp_discard_rfabuf(sc, rxp);
1985 fxp_add_rfabuf(sc, rxp);
1989 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1990 sc->fxp_desc.rx_head->rx_addr);
1991 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1997 fxp_update_stats(struct fxp_softc *sc)
1999 struct ifnet *ifp = sc->ifp;
2000 struct fxp_stats *sp = sc->fxp_stats;
2001 struct fxp_hwstats *hsp;
2004 FXP_LOCK_ASSERT(sc, MA_OWNED);
2006 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2007 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2008 /* Update statistical counters. */
2009 if (sc->revision >= FXP_REV_82559_A0)
2010 status = &sp->completion_status;
2011 else if (sc->revision >= FXP_REV_82558_A4)
2012 status = (uint32_t *)&sp->tx_tco;
2014 status = &sp->tx_pause;
2015 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2016 hsp = &sc->fxp_hwstats;
2017 hsp->tx_good += le32toh(sp->tx_good);
2018 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2019 hsp->tx_latecols += le32toh(sp->tx_latecols);
2020 hsp->tx_underruns += le32toh(sp->tx_underruns);
2021 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2022 hsp->tx_deffered += le32toh(sp->tx_deffered);
2023 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2024 hsp->tx_multiple_collisions +=
2025 le32toh(sp->tx_multiple_collisions);
2026 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2027 hsp->rx_good += le32toh(sp->rx_good);
2028 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2029 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2030 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2031 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2032 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2033 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2034 hsp->tx_pause += le32toh(sp->tx_pause);
2035 hsp->rx_pause += le32toh(sp->rx_pause);
2036 hsp->rx_controls += le32toh(sp->rx_controls);
2037 hsp->tx_tco += le16toh(sp->tx_tco);
2038 hsp->rx_tco += le16toh(sp->rx_tco);
2040 ifp->if_opackets += le32toh(sp->tx_good);
2041 ifp->if_collisions += le32toh(sp->tx_total_collisions);
2043 ifp->if_ipackets += le32toh(sp->rx_good);
2044 sc->rx_idle_secs = 0;
2045 } else if (sc->flags & FXP_FLAG_RXBUG) {
2047 * Receiver's been idle for another second.
2052 le32toh(sp->rx_crc_errors) +
2053 le32toh(sp->rx_alignment_errors) +
2054 le32toh(sp->rx_rnr_errors) +
2055 le32toh(sp->rx_overrun_errors);
2057 * If any transmit underruns occured, bump up the transmit
2058 * threshold by another 512 bytes (64 * 8).
2060 if (sp->tx_underruns) {
2061 ifp->if_oerrors += le32toh(sp->tx_underruns);
2062 if (tx_threshold < 192)
2066 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2072 * Update packet in/out/collision statistics. The i82557 doesn't
2073 * allow you to access these counters without doing a fairly
2074 * expensive DMA to get _all_ of the statistics it maintains, so
2075 * we do this operation here only once per second. The statistics
2076 * counters in the kernel are updated from the previous dump-stats
2077 * DMA and then a new dump-stats DMA is started. The on-chip
2078 * counters are zeroed when the DMA completes. If we can't start
2079 * the DMA immediately, we don't wait - we just prepare to read
2080 * them again next time.
2085 struct fxp_softc *sc = xsc;
2086 struct ifnet *ifp = sc->ifp;
2088 FXP_LOCK_ASSERT(sc, MA_OWNED);
2090 /* Update statistical counters. */
2091 fxp_update_stats(sc);
2094 * Release any xmit buffers that have completed DMA. This isn't
2095 * strictly necessary to do here, but it's advantagous for mbufs
2096 * with external storage to be released in a timely manner rather
2097 * than being defered for a potentially long time. This limits
2098 * the delay to a maximum of one second.
2103 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2104 * then assume the receiver has locked up and attempt to clear
2105 * the condition by reprogramming the multicast filter. This is
2106 * a work-around for a bug in the 82557 where the receiver locks
2107 * up if it gets certain types of garbage in the syncronization
2108 * bits prior to the packet header. This bug is supposed to only
2109 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2110 * mode as well (perhaps due to a 10/100 speed transition).
2112 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2113 sc->rx_idle_secs = 0;
2114 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2115 fxp_init_body(sc, 1);
2119 * If there is no pending command, start another stats
2120 * dump. Otherwise punt for now.
2122 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2124 * Start another stats dump.
2126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2128 if (sc->miibus != NULL)
2129 mii_tick(device_get_softc(sc->miibus));
2132 * Check that chip hasn't hung.
2137 * Schedule another timeout one second from now.
2139 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2143 * Stop the interface. Cancels the statistics updater and resets
2147 fxp_stop(struct fxp_softc *sc)
2149 struct ifnet *ifp = sc->ifp;
2153 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2154 sc->watchdog_timer = 0;
2157 * Cancel stats updater.
2159 callout_stop(&sc->stat_ch);
2162 * Preserve PCI configuration, configure, IA/multicast
2163 * setup and put RU and CU into idle state.
2165 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2167 /* Disable interrupts. */
2168 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2170 fxp_update_stats(sc);
2173 * Release any xmit buffers.
2175 txp = sc->fxp_desc.tx_list;
2177 for (i = 0; i < FXP_NTXCB; i++) {
2178 if (txp[i].tx_mbuf != NULL) {
2179 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2180 BUS_DMASYNC_POSTWRITE);
2181 bus_dmamap_unload(sc->fxp_txmtag,
2183 m_freem(txp[i].tx_mbuf);
2184 txp[i].tx_mbuf = NULL;
2185 /* clear this to reset csum offload bits */
2186 txp[i].tx_cb->tbd[0].tb_addr = 0;
2190 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2191 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2196 * Watchdog/transmission transmit timeout handler. Called when a
2197 * transmission is started on the interface, but no interrupt is
2198 * received before the timeout. This usually indicates that the
2199 * card has wedged for some reason.
2202 fxp_watchdog(struct fxp_softc *sc)
2205 FXP_LOCK_ASSERT(sc, MA_OWNED);
2207 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2210 device_printf(sc->dev, "device timeout\n");
2211 sc->ifp->if_oerrors++;
2213 fxp_init_body(sc, 1);
2217 * Acquire locks and then call the real initialization function. This
2218 * is necessary because ether_ioctl() calls if_init() and this would
2219 * result in mutex recursion if the mutex was held.
2224 struct fxp_softc *sc = xsc;
2227 fxp_init_body(sc, 1);
2232 * Perform device initialization. This routine must be called with the
2236 fxp_init_body(struct fxp_softc *sc, int setmedia)
2238 struct ifnet *ifp = sc->ifp;
2239 struct mii_data *mii;
2240 struct fxp_cb_config *cbp;
2241 struct fxp_cb_ias *cb_ias;
2242 struct fxp_cb_tx *tcbp;
2246 FXP_LOCK_ASSERT(sc, MA_OWNED);
2248 * Cancel any pending I/O
2253 * Issue software reset, which also unloads the microcode.
2255 sc->flags &= ~FXP_FLAG_UCODE;
2256 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2259 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2262 * Initialize base of CBL and RFA memory. Loading with zero
2263 * sets it up for regular linear addressing.
2265 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2266 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2269 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2272 * Initialize base of dump-stats buffer.
2275 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2276 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2277 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2278 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2279 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2282 * Attempt to load microcode if requested.
2283 * For ICH based controllers do not load microcode.
2285 if (sc->ident->ich == 0) {
2286 if (ifp->if_flags & IFF_LINK0 &&
2287 (sc->flags & FXP_FLAG_UCODE) == 0)
2292 * Set IFF_ALLMULTI status. It's needed in configure action
2298 * We temporarily use memory that contains the TxCB list to
2299 * construct the config CB. The TxCB list memory is rebuilt
2302 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2305 * This bcopy is kind of disgusting, but there are a bunch of must be
2306 * zero and must be one bits in this structure and this is the easiest
2307 * way to initialize them all to proper values.
2309 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2312 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2314 cbp->link_addr = 0xffffffff; /* (no) next command */
2315 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2316 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2317 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2318 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2319 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2320 cbp->type_enable = 0; /* actually reserved */
2321 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2322 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2323 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2324 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2325 cbp->dma_mbce = 0; /* (disable) dma max counters */
2326 cbp->late_scb = 0; /* (don't) defer SCB update */
2327 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2328 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2329 cbp->ci_int = 1; /* interrupt on CU idle */
2330 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2331 cbp->ext_stats_dis = 1; /* disable extended counters */
2332 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2333 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2334 cbp->disc_short_rx = !prm; /* discard short packets */
2335 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2336 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2337 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2338 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2339 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2340 cbp->csma_dis = 0; /* (don't) disable link */
2341 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2342 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2343 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2344 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2345 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2346 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2347 cbp->nsai = 1; /* (don't) disable source addr insert */
2348 cbp->preamble_length = 2; /* (7 byte) preamble */
2349 cbp->loopback = 0; /* (don't) loopback */
2350 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2351 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2352 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2353 cbp->promiscuous = prm; /* promiscuous mode */
2354 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2355 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2356 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2357 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2358 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2360 cbp->stripping = !prm; /* truncate rx packet to byte count */
2361 cbp->padding = 1; /* (do) pad short tx packets */
2362 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2363 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2364 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2365 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2366 cbp->force_fdx = 0; /* (don't) force full duplex */
2367 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2368 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2369 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm;
2370 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2371 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2372 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2374 if (sc->revision == FXP_REV_82557) {
2376 * The 82557 has no hardware flow control, the values
2377 * below are the defaults for the chip.
2379 cbp->fc_delay_lsb = 0;
2380 cbp->fc_delay_msb = 0x40;
2381 cbp->pri_fc_thresh = 3;
2383 cbp->rx_fc_restop = 0;
2384 cbp->rx_fc_restart = 0;
2386 cbp->pri_fc_loc = 1;
2388 /* Set pause RX FIFO threshold to 1KB. */
2389 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2390 /* Set pause time. */
2391 cbp->fc_delay_lsb = 0xff;
2392 cbp->fc_delay_msb = 0xff;
2393 cbp->pri_fc_thresh = 3;
2394 mii = device_get_softc(sc->miibus);
2395 if ((IFM_OPTIONS(mii->mii_media_active) &
2396 IFM_ETH_TXPAUSE) != 0)
2397 /* enable transmit FC */
2400 /* disable transmit FC */
2402 if ((IFM_OPTIONS(mii->mii_media_active) &
2403 IFM_ETH_RXPAUSE) != 0) {
2404 /* enable FC restart/restop frames */
2405 cbp->rx_fc_restart = 1;
2406 cbp->rx_fc_restop = 1;
2408 /* disable FC restart/restop frames */
2409 cbp->rx_fc_restart = 0;
2410 cbp->rx_fc_restop = 0;
2412 cbp->fc_filter = !prm; /* drop FC frames to host */
2413 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2416 /* Enable 82558 and 82559 extended statistics functionality. */
2417 if (sc->revision >= FXP_REV_82558_A4) {
2418 if (sc->revision >= FXP_REV_82559_A0) {
2420 * Extend configuration table size to 32
2421 * to include TCO configuration.
2423 cbp->byte_count = 32;
2424 cbp->ext_stats_dis = 1;
2425 /* Enable TCO stats. */
2426 cbp->tno_int_or_tco_en = 1;
2429 cbp->ext_stats_dis = 0;
2433 * Start the config command/DMA.
2436 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2437 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2438 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2439 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2440 /* ...and wait for it to complete. */
2441 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2444 * Now initialize the station address. Temporarily use the TxCB
2445 * memory area like we did above for the config CB.
2447 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2448 cb_ias->cb_status = 0;
2449 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2450 cb_ias->link_addr = 0xffffffff;
2451 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2454 * Start the IAS (Individual Address Setup) command/DMA.
2457 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2458 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2459 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2460 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2461 /* ...and wait for it to complete. */
2462 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2465 * Initialize the multicast address list.
2470 * Initialize transmit control block (TxCB) list.
2472 txp = sc->fxp_desc.tx_list;
2473 tcbp = sc->fxp_desc.cbl_list;
2474 bzero(tcbp, FXP_TXCB_SZ);
2475 for (i = 0; i < FXP_NTXCB; i++) {
2476 txp[i].tx_mbuf = NULL;
2477 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2478 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2479 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2480 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2481 if (sc->flags & FXP_FLAG_EXT_TXCB)
2482 tcbp[i].tbd_array_addr =
2483 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2485 tcbp[i].tbd_array_addr =
2486 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2487 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2490 * Set the suspend flag on the first TxCB and start the control
2491 * unit. It will execute the NOP and then suspend.
2493 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2494 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2496 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2500 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2501 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2504 * Initialize receiver buffer area - RFA.
2507 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2508 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2510 if (sc->miibus != NULL && setmedia != 0)
2511 mii_mediachg(device_get_softc(sc->miibus));
2513 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2514 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2517 * Enable interrupts.
2519 #ifdef DEVICE_POLLING
2521 * ... but only do that if we are not polling. And because (presumably)
2522 * the default is interrupts on, we need to disable them explicitly!
2524 if (ifp->if_capenable & IFCAP_POLLING )
2525 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2527 #endif /* DEVICE_POLLING */
2528 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2531 * Start stats updater.
2533 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2537 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2544 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2547 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2551 * Change media according to request.
2554 fxp_ifmedia_upd(struct ifnet *ifp)
2556 struct fxp_softc *sc = ifp->if_softc;
2557 struct mii_data *mii;
2558 struct mii_softc *miisc;
2560 mii = device_get_softc(sc->miibus);
2562 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2563 mii_phy_reset(miisc);
2570 * Notify the world which media we're using.
2573 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2575 struct fxp_softc *sc = ifp->if_softc;
2576 struct mii_data *mii;
2578 mii = device_get_softc(sc->miibus);
2581 ifmr->ifm_active = mii->mii_media_active;
2582 ifmr->ifm_status = mii->mii_media_status;
2584 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2585 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2586 sc->cu_resume_bug = 1;
2588 sc->cu_resume_bug = 0;
2593 * Add a buffer to the end of the RFA buffer list.
2594 * Return 0 if successful, 1 for failure. A failure results in
2595 * reusing the RFA buffer.
2596 * The RFA struct is stuck at the beginning of mbuf cluster and the
2597 * data pointer is fixed up to point just past it.
2600 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2603 struct fxp_rfa *rfa;
2604 bus_dmamap_t tmp_map;
2607 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2612 * Move the data pointer up so that the incoming data packet
2613 * will be 32-bit aligned.
2615 m->m_data += RFA_ALIGNMENT_FUDGE;
2618 * Get a pointer to the base of the mbuf cluster and move
2619 * data start past it.
2621 rfa = mtod(m, struct fxp_rfa *);
2622 m->m_data += sc->rfa_size;
2623 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2625 rfa->rfa_status = 0;
2626 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2627 rfa->actual_size = 0;
2628 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2632 * Initialize the rest of the RFA. Note that since the RFA
2633 * is misaligned, we cannot store values directly. We're thus
2634 * using the le32enc() function which handles endianness and
2635 * is also alignment-safe.
2637 le32enc(&rfa->link_addr, 0xffffffff);
2638 le32enc(&rfa->rbd_addr, 0xffffffff);
2640 /* Map the RFA into DMA memory. */
2641 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2642 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2643 &rxp->rx_addr, BUS_DMA_NOWAIT);
2649 if (rxp->rx_mbuf != NULL)
2650 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2651 tmp_map = sc->spare_map;
2652 sc->spare_map = rxp->rx_map;
2653 rxp->rx_map = tmp_map;
2656 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2657 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2662 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2664 struct fxp_rfa *p_rfa;
2665 struct fxp_rx *p_rx;
2668 * If there are other buffers already on the list, attach this
2669 * one to the end by fixing up the tail to point to this one.
2671 if (sc->fxp_desc.rx_head != NULL) {
2672 p_rx = sc->fxp_desc.rx_tail;
2673 p_rfa = (struct fxp_rfa *)
2674 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2675 p_rx->rx_next = rxp;
2676 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2677 p_rfa->rfa_control = 0;
2678 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2681 rxp->rx_next = NULL;
2682 sc->fxp_desc.rx_head = rxp;
2684 sc->fxp_desc.rx_tail = rxp;
2688 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2691 struct fxp_rfa *rfa;
2694 m->m_data = m->m_ext.ext_buf;
2696 * Move the data pointer up so that the incoming data packet
2697 * will be 32-bit aligned.
2699 m->m_data += RFA_ALIGNMENT_FUDGE;
2702 * Get a pointer to the base of the mbuf cluster and move
2703 * data start past it.
2705 rfa = mtod(m, struct fxp_rfa *);
2706 m->m_data += sc->rfa_size;
2707 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2709 rfa->rfa_status = 0;
2710 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2711 rfa->actual_size = 0;
2714 * Initialize the rest of the RFA. Note that since the RFA
2715 * is misaligned, we cannot store values directly. We're thus
2716 * using the le32enc() function which handles endianness and
2717 * is also alignment-safe.
2719 le32enc(&rfa->link_addr, 0xffffffff);
2720 le32enc(&rfa->rbd_addr, 0xffffffff);
2722 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2723 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2727 fxp_miibus_readreg(device_t dev, int phy, int reg)
2729 struct fxp_softc *sc = device_get_softc(dev);
2733 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2734 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2736 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2741 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2743 return (value & 0xffff);
2747 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2749 struct fxp_softc *sc = device_get_softc(dev);
2752 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2753 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2756 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2761 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2766 fxp_miibus_statchg(device_t dev)
2768 struct fxp_softc *sc;
2769 struct mii_data *mii;
2772 sc = device_get_softc(dev);
2773 mii = device_get_softc(sc->miibus);
2775 if (mii == NULL || ifp == NULL ||
2776 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
2777 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2778 (IFM_AVALID | IFM_ACTIVE))
2782 * Call fxp_init_body in order to adjust the flow control settings.
2783 * Note that the 82557 doesn't support hardware flow control.
2785 if (sc->revision == FXP_REV_82557)
2787 fxp_init_body(sc, 0);
2791 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2793 struct fxp_softc *sc = ifp->if_softc;
2794 struct ifreq *ifr = (struct ifreq *)data;
2795 struct mii_data *mii;
2796 int flag, mask, error = 0, reinit;
2802 * If interface is marked up and not running, then start it.
2803 * If it is marked down and running, stop it.
2804 * XXX If it's up then re-initialize it. This is so flags
2805 * such as IFF_PROMISC are handled.
2807 if (ifp->if_flags & IFF_UP) {
2808 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2809 ((ifp->if_flags ^ sc->if_flags) &
2810 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0)
2811 fxp_init_body(sc, 1);
2812 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2813 fxp_init_body(sc, 1);
2815 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2818 sc->if_flags = ifp->if_flags;
2825 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2826 fxp_init_body(sc, 0);
2832 if (sc->miibus != NULL) {
2833 mii = device_get_softc(sc->miibus);
2834 error = ifmedia_ioctl(ifp, ifr,
2835 &mii->mii_media, command);
2837 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2843 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2844 #ifdef DEVICE_POLLING
2845 if (mask & IFCAP_POLLING) {
2846 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2847 error = ether_poll_register(fxp_poll, ifp);
2851 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2852 FXP_SCB_INTR_DISABLE);
2853 ifp->if_capenable |= IFCAP_POLLING;
2856 error = ether_poll_deregister(ifp);
2857 /* Enable interrupts in any case */
2859 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2860 ifp->if_capenable &= ~IFCAP_POLLING;
2866 if ((mask & IFCAP_TXCSUM) != 0 &&
2867 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2868 ifp->if_capenable ^= IFCAP_TXCSUM;
2869 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2870 ifp->if_hwassist |= FXP_CSUM_FEATURES;
2872 ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2874 if ((mask & IFCAP_RXCSUM) != 0 &&
2875 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2876 ifp->if_capenable ^= IFCAP_RXCSUM;
2877 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2880 if ((mask & IFCAP_TSO4) != 0 &&
2881 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2882 ifp->if_capenable ^= IFCAP_TSO4;
2883 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2884 ifp->if_hwassist |= CSUM_TSO;
2886 ifp->if_hwassist &= ~CSUM_TSO;
2888 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2889 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2890 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2891 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2892 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2893 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2894 if (sc->revision != FXP_REV_82557)
2895 flag = FXP_FLAG_LONG_PKT_EN;
2896 else /* a hack to get long frames on the old chip */
2897 flag = FXP_FLAG_SAVE_BAD;
2899 if (ifp->if_flags & IFF_UP)
2902 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2903 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2904 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2905 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2906 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2907 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2908 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2909 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2910 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2911 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2912 ifp->if_capenable &=
2913 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
2916 if (reinit > 0 && ifp->if_flags & IFF_UP)
2917 fxp_init_body(sc, 1);
2919 VLAN_CAPABILITIES(ifp);
2923 error = ether_ioctl(ifp, command, data);
2929 * Fill in the multicast address list and return number of entries.
2932 fxp_mc_addrs(struct fxp_softc *sc)
2934 struct fxp_cb_mcs *mcsp = sc->mcsp;
2935 struct ifnet *ifp = sc->ifp;
2936 struct ifmultiaddr *ifma;
2940 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2941 if_maddr_rlock(ifp);
2942 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2943 if (ifma->ifma_addr->sa_family != AF_LINK)
2945 if (nmcasts >= MAXMCADDR) {
2946 ifp->if_flags |= IFF_ALLMULTI;
2950 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2951 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2954 if_maddr_runlock(ifp);
2956 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2961 * Program the multicast filter.
2963 * We have an artificial restriction that the multicast setup command
2964 * must be the first command in the chain, so we take steps to ensure
2965 * this. By requiring this, it allows us to keep up the performance of
2966 * the pre-initialized command ring (esp. link pointers) by not actually
2967 * inserting the mcsetup command in the ring - i.e. its link pointer
2968 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2969 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2970 * lead into the regular TxCB ring when it completes.
2973 fxp_mc_setup(struct fxp_softc *sc)
2975 struct fxp_cb_mcs *mcsp;
2978 FXP_LOCK_ASSERT(sc, MA_OWNED);
2981 mcsp->cb_status = 0;
2982 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2983 mcsp->link_addr = 0xffffffff;
2987 * Wait until command unit is idle. This should never be the
2988 * case when nothing is queued, but make sure anyway.
2991 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
2992 FXP_SCB_CUS_IDLE && --count)
2995 device_printf(sc->dev, "command queue timeout\n");
3000 * Start the multicast setup command.
3003 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3005 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3006 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3007 /* ...and wait for it to complete. */
3008 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3011 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3012 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3013 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3014 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3016 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3017 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3019 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3021 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3023 static const struct ucode {
3027 u_short int_delay_offset;
3028 u_short bundle_max_offset;
3029 } const ucode_table[] = {
3030 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3031 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3032 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3033 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3034 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3035 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3037 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3038 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3039 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3040 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3042 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3043 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3044 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3045 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3046 { 0, NULL, 0, 0, 0 }
3050 fxp_load_ucode(struct fxp_softc *sc)
3052 const struct ucode *uc;
3053 struct fxp_cb_ucode *cbp;
3056 for (uc = ucode_table; uc->ucode != NULL; uc++)
3057 if (sc->revision == uc->revision)
3059 if (uc->ucode == NULL)
3061 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3063 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3064 cbp->link_addr = 0xffffffff; /* (no) next command */
3065 for (i = 0; i < uc->length; i++)
3066 cbp->ucode[i] = htole32(uc->ucode[i]);
3067 if (uc->int_delay_offset)
3068 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3069 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3070 if (uc->bundle_max_offset)
3071 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3072 htole16(sc->tunable_bundle_max);
3074 * Download the ucode to the chip.
3077 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3079 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3080 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3081 /* ...and wait for it to complete. */
3082 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3083 device_printf(sc->dev,
3084 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3085 sc->tunable_int_delay,
3086 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3087 sc->flags |= FXP_FLAG_UCODE;
3090 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3091 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3094 fxp_sysctl_node(struct fxp_softc *sc)
3096 struct sysctl_ctx_list *ctx;
3097 struct sysctl_oid_list *child, *parent;
3098 struct sysctl_oid *tree;
3099 struct fxp_hwstats *hsp;
3101 ctx = device_get_sysctl_ctx(sc->dev);
3102 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3104 SYSCTL_ADD_PROC(ctx, child,
3105 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3106 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3107 "FXP driver receive interrupt microcode bundling delay");
3108 SYSCTL_ADD_PROC(ctx, child,
3109 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3110 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3111 "FXP driver receive interrupt microcode bundle size limit");
3112 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3116 * Pull in device tunables.
3118 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3119 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3120 (void) resource_int_value(device_get_name(sc->dev),
3121 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3122 (void) resource_int_value(device_get_name(sc->dev),
3123 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3126 hsp = &sc->fxp_hwstats;
3127 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3128 NULL, "FXP statistics");
3129 parent = SYSCTL_CHILDREN(tree);
3131 /* Rx MAC statistics. */
3132 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3133 NULL, "Rx MAC statistics");
3134 child = SYSCTL_CHILDREN(tree);
3135 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3136 &hsp->rx_good, "Good frames");
3137 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3138 &hsp->rx_crc_errors, "CRC errors");
3139 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3140 &hsp->rx_alignment_errors, "Alignment errors");
3141 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3142 &hsp->rx_rnr_errors, "RNR errors");
3143 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3144 &hsp->rx_overrun_errors, "Overrun errors");
3145 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3146 &hsp->rx_cdt_errors, "Collision detect errors");
3147 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3148 &hsp->rx_shortframes, "Short frame errors");
3149 if (sc->revision >= FXP_REV_82558_A4) {
3150 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3151 &hsp->rx_pause, "Pause frames");
3152 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3153 &hsp->rx_controls, "Unsupported control frames");
3155 if (sc->revision >= FXP_REV_82559_A0)
3156 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3157 &hsp->rx_tco, "TCO frames");
3159 /* Tx MAC statistics. */
3160 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3161 NULL, "Tx MAC statistics");
3162 child = SYSCTL_CHILDREN(tree);
3163 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3164 &hsp->tx_good, "Good frames");
3165 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3166 &hsp->tx_maxcols, "Maximum collisions errors");
3167 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3168 &hsp->tx_latecols, "Late collisions errors");
3169 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3170 &hsp->tx_underruns, "Underrun errors");
3171 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3172 &hsp->tx_lostcrs, "Lost carrier sense");
3173 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3174 &hsp->tx_deffered, "Deferred");
3175 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3176 &hsp->tx_single_collisions, "Single collisions");
3177 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3178 &hsp->tx_multiple_collisions, "Multiple collisions");
3179 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3180 &hsp->tx_total_collisions, "Total collisions");
3181 if (sc->revision >= FXP_REV_82558_A4)
3182 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3183 &hsp->tx_pause, "Pause frames");
3184 if (sc->revision >= FXP_REV_82559_A0)
3185 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3186 &hsp->tx_tco, "TCO frames");
3189 #undef FXP_SYSCTL_STAT_ADD
3192 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3196 value = *(int *)arg1;
3197 error = sysctl_handle_int(oidp, &value, 0, req);
3198 if (error || !req->newptr)
3200 if (value < low || value > high)
3202 *(int *)arg1 = value;
3207 * Interrupt delay is expressed in microseconds, a multiplier is used
3208 * to convert this to the appropriate clock ticks before using.
3211 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3214 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3218 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3221 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));