2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 /***************************************************************************
35 * IDE IO Register File
36 ***************************************************************************/
39 * IDE IO Port definition
41 typedef struct _IDE_REGISTERS_1 {
42 USHORT Data; /* RW: Data port feature register */
43 UCHAR BlockCount; /* RW: Sector count */
44 UCHAR BlockNumber; /* RW: Sector number & LBA 0-7 */
45 UCHAR CylinderLow; /* RW: Cylinder low & LBA 8-15 */
46 UCHAR CylinderHigh; /* RW: Cylinder hign & LBA 16-23 */
47 UCHAR DriveSelect; /* RW: Drive/head & LBA 24-27 */
48 UCHAR Command; /* RO: Status WR:Command */
49 } IDE_REGISTERS_1, *PIDE_REGISTERS_1;
53 * IDE status definitions
55 #define IDE_STATUS_ERROR 0x01 /* Error Occurred in Execution */
56 #define IDE_STATUS_INDEX 0x02 /* is vendor specific */
57 #define IDE_STATUS_CORRECTED_ERROR 0x04 /* Corrected Data */
58 #define IDE_STATUS_DRQ 0x08 /* Ready to transfer data */
59 #define IDE_STATUS_DSC 0x10 /* not defined in ATA-2 */
60 #define IDE_STATUS_DWF 0x20 /* Device Fault has been detected */
61 #define IDE_STATUS_DRDY 0x40 /* Device Ready to accept command */
62 #define IDE_STATUS_IDLE 0x50 /* Device is OK */
63 #define IDE_STATUS_BUSY 0x80 /* Device Busy, must wait */
66 #define IDE_ERROR_BAD_BLOCK 0x80 /* Reserved now */
67 #define IDE_ERROR_DATA_ERROR 0x40 /* Uncorreectable Data Error */
68 #define IDE_ERROR_MEDIA_CHANGE 0x20 /* Media Changed */
69 #define IDE_ERROR_ID_NOT_FOUND 0x10 /* ID Not Found */
70 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08 /* Media Change Requested */
71 #define IDE_ERROR_COMMAND_ABORTED 0x04 /* Aborted Command */
72 #define IDE_ERROR_TRACK0_NOT_FOUND 0x02 /* Track 0 Not Found */
73 #define IDE_ERROR_ADDRESS_NOT_FOUND 0x01 /* Address Mark Not Found */
79 * IDE command definitions
82 #define IDE_COMMAND_RECALIBRATE 0x10 /* Recalibrate */
83 #define IDE_COMMAND_READ 0x20 /* Read Sectors with retry */
84 #define IDE_COMMAND_WRITE 0x30 /* Write Sectors with retry */
85 #define IDE_COMMAND_VERIFY 0x40 /* Read Verify Sectors with Retry */
86 #define IDE_COMMAND_SEEK 0x70 /* Seek */
87 #define IDE_COMMAND_SET_DRIVE_PARAMETER 0x91 /* Initialize Device Parmeters */
88 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
89 #define IDE_COMMAND_DOOR_LOCK 0xDE /* Door Lock */
90 #define IDE_COMMAND_DOOR_UNLOCK 0xDF /* Door Unlock */
91 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF /* Set Features */
92 #define IDE_COMMAND_IDENTIFY 0xEC /* Identify Device */
93 #define IDE_COMMAND_MEDIA_EJECT 0xED
94 #define IDE_COMMAND_SET_FEATURES 0xEF /* IDE set features command */
96 #define IDE_COMMAND_FLUSH_CACHE 0xE7
97 #define IDE_COMMAND_STANDBY_IMMEDIATE 0xE0
99 #ifndef NOT_SUPPORT_MULTIPLE
100 #define IDE_COMMAND_READ_MULTIPLE 0xC4 /* Read Multiple */
101 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5 /* Write Multiple */
102 #define IDE_COMMAND_SET_MULTIPLE 0xC6 /* Set Multiple Mode */
105 #ifndef NOT_SUPPORT_DMA
106 #define IDE_COMMAND_DMA_READ 0xc8 /* IDE DMA read command */
107 #define IDE_COMMAND_DMA_WRITE 0xca /* IDE DMA write command */
110 #define IDE_COMMAND_READ_DMA_QUEUE 0xc7 /* IDE read DMA queue command */
111 #define IDE_COMMAND_WRITE_DMA_QUEUE 0xcc /* IDE write DMA queue command */
112 #define IDE_COMMAND_SERVICE 0xA2 /* IDE service command command */
113 #define IDE_COMMAND_NOP 0x00 /* IDE NOP command */
114 #define IDE_STATUS_SRV 0x10
115 #define IDE_RELEASE_BUS 4
117 /*#define IDE_COMMAND_FLUSH_CACHE_EXT */
118 #define IDE_COMMAND_READ_DMA_EXT 0x25
119 #define IDE_COMMAND_READ_QUEUE_EXT 0x26
120 #define IDE_COMMAND_READ_MULTIPLE_EXT 0x29
121 #define IDE_COMMAND_READ_MAX_ADDR 0x27
122 #define IDE_COMMAND_READ_EXT 0x24
123 #define IDE_COMMAND_VERIFY_EXT 0x42
124 #define IDE_COMMAND_SET_MULTIPLE_EXT 0x37
125 #define IDE_COMMAND_WRITE_DMA_EXT 0x35
126 #define IDE_COMMAND_WRITE_QUEUE_EXT 0x36
127 #define IDE_COMMAND_WRITE_EXT 0x34
128 #define IDE_COMMAND_WRITE_MULTIPLE_EXT 0x39
131 * IDE_COMMAND_SET_FEATURES
133 #define FT_USE_ULTRA 0x40 /* Set feature for Ultra DMA */
134 #define FT_USE_MWDMA 0x20 /* Set feature for MW DMA */
135 #define FT_USE_SWDMA 0x10 /* Set feature for SW DMA */
136 #define FT_USE_PIO 0x8 /* Set feature for PIO */
137 #define FT_DISABLE_IORDY 0x10 /* Set feature for disabling IORDY */
140 * S.M.A.R.T. commands
142 #define IDE_COMMAND_SMART 0xB0
143 #define SMART_READ_VALUES 0xd0
144 #define SMART_READ_THRESHOLDS 0xd1
145 #define SMART_AUTOSAVE 0xd2
146 #define SMART_SAVE 0xd3
147 #define SMART_IMMEDIATE_OFFLINE 0xd4
148 #define SMART_READ_LOG_SECTOR 0xd5
149 #define SMART_WRITE_LOG_SECTOR 0xd6
150 #define SMART_ENABLE 0xd8
151 #define SMART_DISABLE 0xd9
152 #define SMART_STATUS 0xda
153 #define SMART_AUTO_OFFLINE 0xdb
155 /***************************************************************************
156 * IDE Control Register File
157 ***************************************************************************/
159 typedef struct _IDE_REGISTERS_2 {
160 UCHAR AlternateStatus; /* RW: device control port */
161 } IDE_REGISTERS_2, *PIDE_REGISTERS_2;
165 * IDE drive control definitions
167 #define IDE_DC_DISABLE_INTERRUPTS 0x02
168 #define IDE_DC_RESET_CONTROLLER 0x04
169 #define IDE_DC_REENABLE_CONTROLLER 0x00
171 /***************************************************************************
172 * MSNS: Removable device
173 ***************************************************************************/
177 #define MSNS_NO_MEDIA 2
178 #define MSNS_MEDIA_CHANGE_REQUEST 8
179 #define MSNS_MIDIA_CHANGE 0x20
180 #define MSNS_WRITE_PROTECT 0x40
181 #define MSNS_READ_PROTECT 0x80
186 typedef struct _IDENTIFY_DATA {
187 USHORT GeneralConfiguration; /* 00 00 */
188 USHORT NumberOfCylinders; /* 02 1 */
189 USHORT Reserved1; /* 04 2 */
190 USHORT NumberOfHeads; /* 06 3 */
191 USHORT UnformattedBytesPerTrack; /* 08 4 */
192 USHORT UnformattedBytesPerSector; /* 0A 5 */
193 USHORT SectorsPerTrack; /* 0C 6 */
194 USHORT VendorUnique1[3]; /* 0E 7-9 */
195 USHORT SerialNumber[10]; /* 14 10-19 */
196 USHORT BufferType; /* 28 20 */
197 USHORT BufferSectorSize; /* 2A 21 */
198 USHORT NumberOfEccBytes; /* 2C 22 */
199 USHORT FirmwareRevision[4]; /* 2E 23-26 */
200 USHORT ModelNumber[20]; /* 36 27-46 */
201 UCHAR MaximumBlockTransfer; /* 5E 47 */
202 UCHAR VendorUnique2; /* 5F */
203 USHORT DoubleWordIo; /* 60 48 */
204 USHORT Capabilities; /* 62 49 */
205 USHORT Reserved2; /* 64 50 */
206 UCHAR VendorUnique3; /* 66 51 */
207 UCHAR PioCycleTimingMode; /* 67 */
208 UCHAR VendorUnique4; /* 68 52 */
209 UCHAR DmaCycleTimingMode; /* 69 */
210 USHORT TranslationFieldsValid; /* 6A 53 */
211 USHORT NumberOfCurrentCylinders; /* 6C 54 */
212 USHORT NumberOfCurrentHeads; /* 6E 55 */
213 USHORT CurrentSectorsPerTrack; /* 70 56 */
214 ULONG CurrentSectorCapacity; /* 72 57-58 */
215 USHORT CurrentMultiSectorSetting; /* 76 59 */
216 ULONG UserAddressableSectors; /* 78 60-61 */
217 UCHAR SingleWordDMASupport; /* 7C 62 */
218 UCHAR SingleWordDMAActive; /* 7D */
219 UCHAR MultiWordDMASupport; /* 7E 63 */
220 UCHAR MultiWordDMAActive; /* 7F */
221 UCHAR AdvancedPIOModes; /* 80 64 */
222 UCHAR Reserved4; /* 81 */
223 USHORT MinimumMWXferCycleTime; /* 82 65 */
224 USHORT RecommendedMWXferCycleTime; /* 84 66 */
225 USHORT MinimumPIOCycleTime; /* 86 67 */
226 USHORT MinimumPIOCycleTimeIORDY; /* 88 68 */
227 USHORT Reserved5[2]; /* 8A 69-70 */
228 USHORT ReleaseTimeOverlapped; /* 8E 71 */
229 USHORT ReleaseTimeServiceCommand; /* 90 72 */
230 USHORT MajorRevision; /* 92 73 */
231 USHORT MinorRevision; /* 94 74 */
232 USHORT MaxQueueDepth; /* 96 75 */
233 USHORT SataCapability; /* 76 */
234 USHORT Reserved6[9]; /* 98 77-85 */
235 USHORT CommandSupport; /* 86 */
236 USHORT CommandEnable; /* 87 */
237 USHORT UtralDmaMode; /* 88 */
238 USHORT Reserved7[11]; /* 89-99 */
239 ULONG Lba48BitLow; /* 101-100 */
240 ULONG Lba48BitHigh; /* 103-102 */
241 USHORT Reserved8[23]; /* 104-126 */
242 USHORT SpecialFunctionsEnabled; /* 127 */
243 USHORT Reserved9[128]; /* 128-255 */
245 } IDENTIFY_DATA, *PIDENTIFY_DATA;
247 typedef struct _CONFIGURATION_IDENTIFY_DATA {
249 USHORT MWDMAModeSupported;
250 USHORT UDMAModeSupported;
252 ULONG MaximumLbaHigh;
253 USHORT CommandSupport;
254 USHORT Reserved[247];
255 UCHAR Signature; /* 0xA5 */
258 CONFIGURATION_IDENTIFY_DATA, *PCONFIGURATION_IDENTIFY_DATA;
261 /* Identify data without the Reserved4. */
263 typedef struct _IDENTIFY_DATA2 {
264 USHORT GeneralConfiguration; /* 00 00 */
265 USHORT NumberOfCylinders; /* 02 1 */
266 USHORT Reserved1; /* 04 2 */
267 USHORT NumberOfHeads; /* 06 3 */
268 USHORT UnformattedBytesPerTrack; /* 08 4 */
269 USHORT UnformattedBytesPerSector; /* 0A 5 */
270 USHORT SectorsPerTrack; /* 0C 6 */
271 USHORT VendorUnique1[3]; /* 0E 7-9 */
272 USHORT SerialNumber[10]; /* 14 10-19 */
273 USHORT BufferType; /* 28 20 */
274 USHORT BufferSectorSize; /* 2A 21 */
275 USHORT NumberOfEccBytes; /* 2C 22 */
276 USHORT FirmwareRevision[4]; /* 2E 23-26 */
277 USHORT ModelNumber[20]; /* 36 27-46 */
278 UCHAR MaximumBlockTransfer; /* 5E 47 */
279 UCHAR VendorUnique2; /* 5F */
280 USHORT DoubleWordIo; /* 60 48 */
281 USHORT Capabilities; /* 62 49 */
282 USHORT Reserved2; /* 64 50 */
283 UCHAR VendorUnique3; /* 66 51 */
284 UCHAR PioCycleTimingMode; /* 67 */
285 UCHAR VendorUnique4; /* 68 52 */
286 UCHAR DmaCycleTimingMode; /* 69 */
287 USHORT TranslationFieldsValid; /* 6A 53 */
288 USHORT NumberOfCurrentCylinders; /* 6C 54 */
289 USHORT NumberOfCurrentHeads; /* 6E 55 */
290 USHORT CurrentSectorsPerTrack; /* 70 56 */
291 ULONG CurrentSectorCapacity; /* 72 57-58 */
292 USHORT CurrentMultiSectorSetting; /* 59 */
293 ULONG UserAddressableSectors; /* 60-61 */
294 UCHAR SingleWordDMASupport; /* 62 */
295 UCHAR SingleWordDMAActive;
296 UCHAR MultiWordDMASupport; /* 63 */
297 UCHAR MultiWordDMAActive;
298 UCHAR AdvancedPIOModes; /* 64 */
300 USHORT MinimumMWXferCycleTime; /* 65 */
301 USHORT RecommendedMWXferCycleTime; /* 66 */
302 USHORT MinimumPIOCycleTime; /* 67 */
303 USHORT MinimumPIOCycleTimeIORDY; /* 68 */
304 USHORT Reserved5[2]; /* 69-70 */
305 USHORT ReleaseTimeOverlapped; /* 71 */
306 USHORT ReleaseTimeServiceCommand; /* 72 */
307 USHORT MajorRevision; /* 73 */
308 USHORT MinorRevision; /* 74 */
309 /* USHORT Reserved6[14]; // 75-88 */
310 } IDENTIFY_DATA2, *PIDENTIFY_DATA2;
312 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA2)
315 /* IDENTIFY DMA timing cycle modes. */
318 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00
319 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01
320 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02
325 typedef enum _DISK_MODE
345 /***************************************************************************
347 ***************************************************************************/
349 #define MAX_LBA_T ((LBA_T)-1)
352 #define SECTOR_TO_BYTE_SHIFT 9
353 #define SECTOR_TO_BYTE(x) ((ULONG)(x) << SECTOR_TO_BYTE_SHIFT)
355 #define mGetStatus(IOPort2) (UCHAR)InPort(&IOPort2->AlternateStatus)
356 #define mUnitControl(IOPort2, Value) OutPort(&IOPort2->AlternateStatus,(UCHAR)(Value))
358 #define mGetErrorCode(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->Data+1)
359 #define mSetFeaturePort(IOPort,x) OutPort((PUCHAR)&IOPort->Data+1, x)
360 #define mSetBlockCount(IOPort,x) OutPort(&IOPort->BlockCount, x)
361 #define mGetBlockCount(IOPort) (UCHAR)InPort(&IOPort->BlockCount)
362 #define mGetInterruptReason(IOPort) (UCHAR)InPort(&IOPort->BlockCount)
363 #define mSetBlockNumber(IOPort,x) OutPort(&IOPort->BlockNumber, x)
364 #define mGetBlockNumber(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->BlockNumber)
365 #define mGetByteLow(IOPort) (UCHAR)InPort(&IOPort->CylinderLow)
366 #define mSetCylinderLow(IOPort,x) OutPort(&IOPort->CylinderLow, x)
367 #define mGetByteHigh(IOPort) (UCHAR)InPort(&IOPort->CylinderHigh)
368 #define mSetCylinderHigh(IOPort,x) OutPort(&IOPort->CylinderHigh, x)
369 #define mGetBaseStatus(IOPort) (UCHAR)InPort(&IOPort->Command)
370 #ifdef SUPPORT_HPT601
371 #define mSelectUnit(IOPort,UnitId) do {\
372 OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\
373 OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\
376 #define mSelectUnit(IOPort,UnitId) OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId))
378 #define mGetUnitNumber(IOPort) InPort(&IOPort->DriveSelect)
379 #define mIssueCommand(IOPort,Cmd) OutPort(&IOPort->Command, (UCHAR)(Cmd))
382 * WDC old disk, don't care right now
384 #define WDC_MW1_FIX_FLAG_OFFSET 129
385 #define WDC_MW1_FIX_FLAG_VALUE 0x00005555