2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #if (__FreeBSD_version >= 1100000)
42 #include <x86/apicvar.h>
44 #include <machine/apicvar.h>
46 #include <machine/cpu.h>
47 #include <machine/cpufunc.h>
48 #include <machine/md_var.h>
49 #include <machine/specialreg.h>
51 #define CORE_CPUID_REQUEST 0xA
52 #define CORE_CPUID_REQUEST_SIZE 0x4
53 #define CORE_CPUID_EAX 0x0
54 #define CORE_CPUID_EBX 0x1
55 #define CORE_CPUID_ECX 0x2
56 #define CORE_CPUID_EDX 0x3
58 #define IAF_PMC_CAPS \
59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
60 PMC_CAP_USER | PMC_CAP_SYSTEM)
61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
67 #define EV_IS_NOTARCH 0
68 #define EV_IS_ARCH_SUPP 1
69 #define EV_IS_ARCH_NOTSUPP -1
72 * "Architectural" events defined by Intel. The values of these
73 * symbols correspond to positions in the bitmask returned by
74 * the CPUID.0AH instruction.
76 enum core_arch_events {
77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
78 CORE_AE_BRANCH_MISSES_RETIRED = 6,
79 CORE_AE_INSTRUCTION_RETIRED = 1,
80 CORE_AE_LLC_MISSES = 4,
81 CORE_AE_LLC_REFERENCE = 3,
82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
83 CORE_AE_UNHALTED_CORE_CYCLES = 0
86 static enum pmc_cputype core_cputype;
89 volatile uint32_t pc_resync;
90 volatile uint32_t pc_iafctrl; /* Fixed function control. */
91 volatile uint64_t pc_globalctrl; /* Global control register. */
92 struct pmc_hw pc_corepmcs[];
95 static struct core_cpu **core_pcpu;
97 static uint32_t core_architectural_events;
98 static uint64_t core_pmcmask;
100 static int core_iaf_ri; /* relative index of fixed counters */
101 static int core_iaf_width;
102 static int core_iaf_npmc;
104 static int core_iap_width;
105 static int core_iap_npmc;
108 core_pcpu_noop(struct pmc_mdep *md, int cpu)
116 core_pcpu_init(struct pmc_mdep *md, int cpu)
121 int core_ri, n, npmc;
123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
124 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
126 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu);
128 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
129 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
131 if (core_cputype != PMC_CPU_INTEL_CORE)
132 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
134 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
135 M_PMC, M_WAITOK | M_ZERO);
140 KASSERT(pc != NULL && cc != NULL,
141 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
143 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
144 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
145 PMC_PHW_CPU_TO_STATE(cpu) |
146 PMC_PHW_INDEX_TO_STATE(n + core_ri);
148 pc->pc_hwpmcs[n + core_ri] = phw;
155 core_pcpu_fini(struct pmc_mdep *md, int cpu)
157 int core_ri, n, npmc;
162 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
163 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
165 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
167 if ((cc = core_pcpu[cpu]) == NULL)
170 core_pcpu[cpu] = NULL;
174 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
177 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
178 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
180 for (n = 0; n < npmc; n++) {
181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
182 wrmsr(IAP_EVSEL0 + n, msr);
185 if (core_cputype != PMC_CPU_INTEL_CORE) {
186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
187 wrmsr(IAF_CTRL, msr);
188 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
191 for (n = 0; n < npmc; n++)
192 pc->pc_hwpmcs[n + core_ri] = NULL;
200 * Fixed function counters.
204 iaf_perfctr_value_to_reload_count(pmc_value_t v)
207 /* If the PMC has overflowed, return a reload count of zero. */
208 if ((v & (1ULL << (core_iaf_width - 1))) == 0)
210 v &= (1ULL << core_iaf_width) - 1;
211 return (1ULL << core_iaf_width) - v;
215 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
217 return (1ULL << core_iaf_width) - rlc;
221 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
222 const struct pmc_op_pmcallocate *a)
225 uint32_t caps, flags, validflags;
227 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
228 ("[core,%d] illegal CPU %d", __LINE__, cpu));
230 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
232 if (ri < 0 || ri > core_iaf_npmc)
237 if (a->pm_class != PMC_CLASS_IAF ||
238 (caps & IAF_PMC_CAPS) != caps)
242 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
245 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
247 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
249 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
252 flags = a->pm_md.pm_iaf.pm_iaf_flags;
254 validflags = IAF_MASK;
256 if (core_cputype != PMC_CPU_INTEL_ATOM &&
257 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT)
258 validflags &= ~IAF_ANY;
260 if ((flags & ~validflags) != 0)
263 if (caps & PMC_CAP_INTERRUPT)
265 if (caps & PMC_CAP_SYSTEM)
267 if (caps & PMC_CAP_USER)
269 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
270 flags |= (IAF_OS | IAF_USR);
272 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
274 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx",
275 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
281 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
283 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
284 ("[core,%d] illegal CPU %d", __LINE__, cpu));
286 KASSERT(ri >= 0 && ri < core_iaf_npmc,
287 ("[core,%d] illegal row-index %d", __LINE__, ri));
289 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
291 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
294 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
300 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
304 char iaf_name[PMC_NAME_MAX];
306 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
308 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
309 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
313 pi->pm_class = PMC_CLASS_IAF;
315 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
316 pi->pm_enabled = TRUE;
317 *ppmc = phw->phw_pmc;
319 pi->pm_enabled = FALSE;
327 iaf_get_config(int cpu, int ri, struct pmc **ppm)
329 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
335 iaf_get_msr(int ri, uint32_t *msr)
337 KASSERT(ri >= 0 && ri < core_iaf_npmc,
338 ("[iaf,%d] ri %d out of range", __LINE__, ri));
340 *msr = IAF_RI_TO_MSR(ri);
346 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
351 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
352 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
353 KASSERT(ri >= 0 && ri < core_iaf_npmc,
354 ("[core,%d] illegal row-index %d", __LINE__, ri));
356 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
359 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
360 ri, ri + core_iaf_ri));
362 tmp = rdpmc(IAF_RI_TO_MSR(ri));
364 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
365 *v = iaf_perfctr_value_to_reload_count(tmp);
369 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
370 IAF_RI_TO_MSR(ri), *v);
376 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
378 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
380 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
381 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
382 KASSERT(ri >= 0 && ri < core_iaf_npmc,
383 ("[core,%d] illegal row-index %d", __LINE__, ri));
385 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
386 ("[core,%d] PHW pmc non-NULL", __LINE__));
392 iaf_start_pmc(int cpu, int ri)
395 struct core_cpu *iafc;
398 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
399 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
400 KASSERT(ri >= 0 && ri < core_iaf_npmc,
401 ("[core,%d] illegal row-index %d", __LINE__, ri));
403 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
405 iafc = core_pcpu[cpu];
406 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
408 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
410 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
411 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
415 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
416 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
417 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
418 IAF_GLOBAL_CTRL_MASK));
419 } while (iafc->pc_resync != 0);
421 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
422 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
423 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
429 iaf_stop_pmc(int cpu, int ri)
432 struct core_cpu *iafc;
435 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
437 iafc = core_pcpu[cpu];
439 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
440 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
441 KASSERT(ri >= 0 && ri < core_iaf_npmc,
442 ("[core,%d] illegal row-index %d", __LINE__, ri));
444 fc = (IAF_MASK << (ri * 4));
446 if (core_cputype != PMC_CPU_INTEL_ATOM &&
447 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT)
450 iafc->pc_iafctrl &= ~fc;
452 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
453 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
454 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
458 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
459 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
460 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
461 IAF_GLOBAL_CTRL_MASK));
462 } while (iafc->pc_resync != 0);
464 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
465 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
466 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
472 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
478 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
479 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
480 KASSERT(ri >= 0 && ri < core_iaf_npmc,
481 ("[core,%d] illegal row-index %d", __LINE__, ri));
484 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
487 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
489 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
490 v = iaf_reload_count_to_perfctr_value(v);
492 /* Turn off fixed counters */
493 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
494 wrmsr(IAF_CTRL, msr);
496 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
498 /* Turn on fixed counters */
499 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
500 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
502 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
503 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
504 (uintmax_t) rdmsr(IAF_CTRL),
505 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
512 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
514 struct pmc_classdep *pcd;
516 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
518 PMCDBG0(MDP,INI,1, "iaf-initialize");
520 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
522 pcd->pcd_caps = IAF_PMC_CAPS;
523 pcd->pcd_class = PMC_CLASS_IAF;
525 pcd->pcd_ri = md->pmd_npmc;
526 pcd->pcd_width = pmcwidth;
528 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
529 pcd->pcd_config_pmc = iaf_config_pmc;
530 pcd->pcd_describe = iaf_describe;
531 pcd->pcd_get_config = iaf_get_config;
532 pcd->pcd_get_msr = iaf_get_msr;
533 pcd->pcd_pcpu_fini = core_pcpu_noop;
534 pcd->pcd_pcpu_init = core_pcpu_noop;
535 pcd->pcd_read_pmc = iaf_read_pmc;
536 pcd->pcd_release_pmc = iaf_release_pmc;
537 pcd->pcd_start_pmc = iaf_start_pmc;
538 pcd->pcd_stop_pmc = iaf_stop_pmc;
539 pcd->pcd_write_pmc = iaf_write_pmc;
541 md->pmd_npmc += npmc;
545 * Intel programmable PMCs.
549 * Event descriptor tables.
551 * For each event id, we track:
553 * 1. The CPUs that the event is valid for.
555 * 2. If the event uses a fixed UMASK, the value of the umask field.
556 * If the event doesn't use a fixed UMASK, a mask of legal bits
560 struct iap_event_descr {
561 enum pmc_event iap_ev;
562 unsigned char iap_evcode;
563 unsigned char iap_umask;
564 unsigned int iap_flags;
567 #define IAP_F_CC (1 << 0) /* CPU: Core */
568 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
569 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
570 #define IAP_F_CA (1 << 3) /* CPU: Atom */
571 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
572 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
573 #define IAP_F_WM (1 << 5) /* CPU: Westmere */
574 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */
575 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */
576 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */
577 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */
578 #define IAP_F_HW (1 << 10) /* CPU: Haswell */
579 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */
580 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */
581 #define IAP_F_FM (1 << 13) /* Fixed mask */
583 #define IAP_F_ALLCPUSCORE2 \
584 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
586 /* Sub fields of UMASK that this event supports. */
587 #define IAP_M_CORE (1 << 0) /* Core specificity */
588 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
589 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
590 #define IAP_M_MESI (1 << 3) /* MESI */
591 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
592 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
593 #define IAP_M_TRANSITION (1 << 6) /* Transition */
595 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
596 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
597 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
598 #define IAP_F_MESI (0xF << 8) /* MESI */
599 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
600 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
601 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
603 #define IAP_PREFETCH_RESERVED (0x2 << 12)
604 #define IAP_CORE_THIS (0x1 << 14)
605 #define IAP_CORE_ALL (0x3 << 14)
606 #define IAP_F_CMASK 0xFF000000
608 static struct iap_event_descr iap_events[] = {
610 #define IAPDESCR(N,EV,UM,FLAGS) { \
611 .iap_ev = PMC_EV_IAP_EVENT_##N, \
612 .iap_evcode = (EV), \
614 .iap_flags = (FLAGS) \
617 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
618 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
620 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
621 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
622 IAP_F_SBX | IAP_F_CAS),
623 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
624 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
625 IAP_F_CAS | IAP_F_HWX),
626 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O |
628 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
629 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
630 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB |
631 IAP_F_SBX | IAP_F_CAS),
632 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS),
633 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS),
634 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS),
636 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS),
637 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O |
639 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS),
640 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS),
641 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
642 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS),
643 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS),
644 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS),
645 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS),
646 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS),
648 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
649 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
650 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
651 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB |
652 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
653 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS),
655 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
656 IAP_F_CC2E | IAP_F_CA),
657 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
658 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
659 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
660 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
661 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
663 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
664 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
665 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
666 IAP_F_HW | IAP_F_HWX),
667 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
668 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
669 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
670 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB |
673 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
674 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX),
675 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
676 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX),
677 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
678 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX),
679 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
680 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
681 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
682 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
683 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
684 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
685 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
686 IAP_F_SBX | IAP_F_HW | IAP_F_HWX),
687 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | IAP_F_HWX),
688 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX),
689 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
690 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX),
691 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
692 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
693 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX),
694 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_IB | IAP_F_IBX),
696 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
697 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
698 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
699 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
701 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
702 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
703 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
705 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
707 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
708 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
710 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW |
711 IAP_F_IB | IAP_F_IBX | IAP_F_HWX),
712 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
714 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
715 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
716 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
717 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
718 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
719 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
721 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
722 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
723 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
724 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
725 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
726 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
728 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
729 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
730 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ),
731 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
732 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
735 IAP_F_SBX | IAP_F_IB | IAP_F_IBX),
736 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
737 IAP_F_SBX | IAP_F_IB | IAP_F_IBX),
738 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
739 IAP_F_SBX | IAP_F_IB | IAP_F_IBX),
740 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
741 IAP_F_SBX | IAP_F_IB | IAP_F_IBX),
742 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
744 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
745 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB |
746 IAP_F_SBX | IAP_F_IB | IAP_F_IBX),
747 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX),
748 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
750 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
751 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
752 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
753 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
754 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
755 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
756 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
757 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
758 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
760 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
761 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
762 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
763 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
764 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
765 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
767 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
768 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
769 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
770 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
772 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
775 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
776 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
778 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
779 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
780 IAP_F_I7 | IAP_F_WM),
781 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
783 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
784 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
785 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
787 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
789 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
790 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
791 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
792 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
794 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
795 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
796 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
797 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
798 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
800 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
802 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
803 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
804 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
805 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
806 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
807 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
808 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
809 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
810 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
811 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
812 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
813 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
814 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
815 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
816 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
817 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
818 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
819 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
820 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
821 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
822 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
823 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
824 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
825 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
826 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
827 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
828 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
829 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
830 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
831 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
832 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
833 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | IAP_F_HWX),
835 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
837 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
838 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
839 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
840 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
841 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
842 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
843 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
844 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
845 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
846 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
847 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
848 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
850 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
851 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
852 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
853 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
854 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB |
856 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
857 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
858 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
859 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
860 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
861 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
862 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
863 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
864 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
865 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
866 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
867 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
869 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
870 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
871 IAP_F_SBX | IAP_F_IBX),
872 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX),
873 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
874 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
875 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB |
876 IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
877 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
878 IAP_F_SBX | IAP_F_IBX),
880 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
881 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
882 IAP_F_CA | IAP_F_CC2),
883 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
884 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
886 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
888 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
889 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
890 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
891 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
892 IAP_F_CAS | IAP_F_HWX),
893 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
894 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
895 IAP_F_CAS | IAP_F_HWX),
897 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
899 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS),
900 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS),
901 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
902 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
904 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
905 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
907 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
909 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
910 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
911 IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
912 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
913 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
914 IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
915 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
917 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
919 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
920 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
921 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
922 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
923 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
924 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
925 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
927 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
928 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
929 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
930 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
931 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
932 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
933 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
935 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
936 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
937 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
938 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
939 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
940 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
942 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
944 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
945 IAP_F_CC2 | IAP_F_I7),
947 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
949 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
951 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
952 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
954 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
955 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
956 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
957 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
959 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
960 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
961 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
962 IAP_F_HW | IAP_F_HWX),
963 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
964 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX |
965 IAP_F_HW | IAP_F_HWX),
966 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB |
967 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
968 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
969 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
970 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
971 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX),
972 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX),
973 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
974 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX),
976 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
977 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
978 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
979 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
980 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
982 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
983 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
984 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
985 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
986 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
988 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
990 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
991 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
992 IAP_F_SB | IAP_F_SBX),
993 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
994 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
996 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
997 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
998 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
999 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
1000 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
1002 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1003 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1004 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1005 IAP_F_SB | IAP_F_SBX),
1006 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1007 IAP_F_SB | IAP_F_SBX),
1008 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1009 IAP_F_SB | IAP_F_SBX),
1011 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1013 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1015 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1016 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1017 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1018 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1020 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1021 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1022 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1024 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1025 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1026 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1027 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1029 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1030 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1031 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1032 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1034 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1035 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1037 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */
1038 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX | IAP_F_IB),
1040 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1041 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1042 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1043 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1044 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1045 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1046 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1047 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1048 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1050 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1051 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
1053 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
1054 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
1056 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
1057 IAP_F_CA | IAP_F_CC2),
1058 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
1059 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1060 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1061 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1062 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1064 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1065 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
1067 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
1068 IAP_F_CA | IAP_F_CC2),
1069 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
1071 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1073 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1074 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
1076 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1077 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1078 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1079 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1081 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1082 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1084 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1085 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
1087 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1088 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
1090 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1091 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
1093 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1094 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
1096 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
1097 IAP_F_CA | IAP_F_CC2),
1098 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
1100 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
1101 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
1103 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1104 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1105 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1106 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1107 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1108 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1109 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1110 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1112 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1114 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1115 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1117 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1119 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1120 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1122 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1124 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1126 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
1128 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1130 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1131 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
1133 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1135 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1136 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS),
1137 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1138 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
1139 IAP_F_CAS | IAP_F_HWX),
1140 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1141 IAP_F_WM | IAP_F_CAS),
1142 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX),
1144 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1145 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
1146 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
1148 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1149 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1150 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
1151 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1152 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
1153 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
1155 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
1156 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1158 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
1159 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1160 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1161 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1162 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1163 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1164 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1165 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1166 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB |
1167 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1168 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX),
1169 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX),
1170 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1171 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1173 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1175 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1176 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1177 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1178 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1179 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1180 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1181 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1182 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1184 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1185 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1186 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1187 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1188 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1189 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1190 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1191 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1192 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1193 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1194 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1195 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1196 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1197 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1198 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1199 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1200 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1201 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1202 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1203 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1204 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1205 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1207 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1208 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1209 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1210 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1211 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1212 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1213 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1214 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1215 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1216 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1217 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1218 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1219 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1220 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1221 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1222 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1223 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1224 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1225 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1226 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1227 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1229 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1230 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1231 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1232 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1233 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1234 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1236 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1237 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1238 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1239 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1240 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1242 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1243 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1245 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1246 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1248 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1250 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1251 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1252 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1253 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1254 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
1255 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1256 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
1257 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1258 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_IB | IAP_F_IBX),
1259 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
1260 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1261 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
1262 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1263 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1264 IAP_F_SBX | IAP_F_IBX),
1265 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1266 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1267 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1268 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1270 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1271 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1272 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1273 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1274 IAP_F_SB | IAP_F_SBX),
1275 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1276 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1277 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1278 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1279 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1280 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1281 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1282 IAP_F_SB | IAP_F_SBX),
1283 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1284 IAP_F_SB | IAP_F_SBX),
1285 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1286 IAP_F_SB | IAP_F_SBX),
1288 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX),
1289 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX),
1290 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB),
1291 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1292 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX),
1293 IAPDESCR(A3H_0CH, 0xA3, 0x08, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1295 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1296 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1297 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX |
1298 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX),
1300 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1301 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1302 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1303 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1305 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1306 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1307 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1308 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1310 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1311 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1312 IAP_F_SBX | IAP_F_IBX),
1313 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1315 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1316 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1318 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1319 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1320 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1321 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB |
1322 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1323 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1324 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1325 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1326 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1327 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1328 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1329 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1330 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1332 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1333 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1334 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1335 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1336 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1337 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1338 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1339 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1340 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1341 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1342 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1343 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1344 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1347 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1348 IAP_F_SB | IAP_F_SBX),
1350 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1351 IAP_F_WM | IAP_F_I7O),
1352 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1353 IAP_F_WM | IAP_F_I7O),
1354 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1355 IAP_F_WM | IAP_F_I7O),
1356 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1357 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1358 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1359 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1360 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1361 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1362 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1363 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1364 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1366 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1367 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1368 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1370 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1371 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS),
1373 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1374 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_CAS),
1375 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS),
1377 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1378 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1379 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1381 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1382 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1384 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1385 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1387 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1388 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1389 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1390 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1391 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1392 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1393 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1394 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1396 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1397 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1398 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1399 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1401 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1403 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1404 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
1405 IAP_F_CAS | IAP_F_HWX),
1406 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1407 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1408 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1409 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1410 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1411 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1412 IAP_F_I7 | IAP_F_WM),
1413 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1415 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1416 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1417 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1418 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1419 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1420 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1421 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1422 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1423 IAP_F_SBX | IAP_F_IBX),
1424 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1425 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_IB | IAP_F_IBX),
1426 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1428 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1429 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1430 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1431 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
1432 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1433 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1434 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1435 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1436 IAP_F_I7 | IAP_F_WM),
1437 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1438 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1439 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1440 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS),
1442 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1443 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1444 IAP_F_I7 | IAP_F_WM | IAP_F_CAS),
1445 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1446 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
1447 IAP_F_CAS | IAP_F_HWX),
1448 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1449 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1450 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
1451 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS),
1452 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1453 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1454 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1456 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1457 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1458 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
1459 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1460 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1461 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1462 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1463 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1464 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1465 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1466 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1467 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1468 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1469 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW |
1471 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1472 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1473 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1474 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1475 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1476 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1477 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1478 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1479 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS),
1480 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS),
1481 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS),
1482 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS),
1483 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS),
1484 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS),
1485 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS),
1486 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS),
1488 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1489 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX |
1490 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
1491 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1492 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1493 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1494 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1495 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1496 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1497 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1498 IAP_F_SBX | IAP_F_IBX),
1499 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1500 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1501 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS),
1502 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS),
1503 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS),
1504 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS),
1505 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS),
1506 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS),
1507 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS),
1508 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS),
1510 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1511 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1512 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1514 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1515 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1516 IAP_F_I7 | IAP_F_WM),
1517 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1518 IAP_F_I7 | IAP_F_WM),
1519 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1520 IAP_F_I7 | IAP_F_WM),
1521 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1522 IAP_F_I7 | IAP_F_WM),
1523 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1524 IAP_F_I7 | IAP_F_WM),
1525 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1527 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1528 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1530 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1532 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1533 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS),
1534 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1535 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1536 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1537 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1538 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1539 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1540 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1541 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1542 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1543 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1544 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS),
1545 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS),
1546 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS),
1548 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1549 IAP_F_I7 | IAP_F_WM | IAP_F_CAS),
1550 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1551 IAP_F_I7 | IAP_F_WM),
1552 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1553 IAP_F_I7 | IAP_F_WM),
1554 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1555 IAP_F_I7 | IAP_F_WM),
1556 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1558 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS),
1559 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1560 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1562 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1563 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1564 IAP_F_I7 | IAP_F_WM),
1565 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1566 IAP_F_I7 | IAP_F_WM),
1567 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1568 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1569 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1571 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1572 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1573 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX),
1574 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1575 IAP_F_SBX | IAP_F_IBX),
1577 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1578 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1580 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */
1581 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1582 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
1583 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1584 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
1586 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
1588 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1589 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1590 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
1592 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
1593 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
1595 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1596 IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */
1597 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1598 IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */
1599 IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
1601 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1602 IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */
1603 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1604 IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */
1605 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
1606 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1607 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1608 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1609 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1610 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1611 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
1612 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1613 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX),
1614 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB |
1615 IAP_F_HW | IAP_F_HWX),
1616 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1617 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1619 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1620 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1621 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1622 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1623 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1624 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1625 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1626 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1627 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1628 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1629 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1630 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1631 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1632 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
1633 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1635 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1637 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX |
1638 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1639 IAPDESCR(D3H_03H, 0xD0, 0x3, IAP_F_IBX ),
1640 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */
1641 IAPDESCR(D3H_0CH, 0xD0, 0x0, IAP_F_IBX ),
1642 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX ),
1643 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX ),
1645 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1646 IAP_F_I7 | IAP_F_WM),
1647 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1648 IAP_F_SB | IAP_F_SBX),
1649 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1650 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1651 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1653 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1654 IAP_F_I7 | IAP_F_WM),
1655 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1656 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1657 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1658 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1660 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1662 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1663 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1664 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1665 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1666 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1668 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1669 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1670 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1671 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1673 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1674 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1675 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1677 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1678 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1680 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1681 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1682 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1683 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1684 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1685 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1687 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1688 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1691 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1693 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1694 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1696 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1698 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1699 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1700 IAP_F_WM | IAP_F_SBX | IAP_F_CAS),
1701 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1702 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS),
1703 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS),
1704 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB |
1705 IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1707 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS),
1709 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1710 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1711 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O),
1713 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1715 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1716 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1717 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1718 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1719 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1720 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1721 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1722 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1723 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1724 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1725 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1726 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1727 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1728 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1729 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1730 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1731 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1733 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB |
1734 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1735 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1736 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1737 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1738 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1739 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1740 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
1742 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1743 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1744 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1745 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1746 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1747 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1748 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1749 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX),
1750 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1751 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX),
1752 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
1754 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1756 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1757 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1758 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1759 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1760 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1761 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1763 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1764 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1765 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1766 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1767 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1768 IAP_F_SB | IAP_F_SBX),
1770 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1772 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1773 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1774 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1776 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1777 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1779 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1780 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1781 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1782 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1783 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1784 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1785 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1788 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1791 iap_perfctr_value_to_reload_count(pmc_value_t v)
1794 /* If the PMC has overflowed, return a reload count of zero. */
1795 if ((v & (1ULL << (core_iap_width - 1))) == 0)
1797 v &= (1ULL << core_iap_width) - 1;
1798 return (1ULL << core_iap_width) - v;
1802 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1804 return (1ULL << core_iap_width) - rlc;
1808 iap_pmc_has_overflowed(int ri)
1813 * We treat a Core (i.e., Intel architecture v1) PMC as has
1814 * having overflowed if its MSB is zero.
1817 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1821 * Check an event against the set of supported architectural events.
1823 * If the event is not architectural EV_IS_NOTARCH is returned.
1824 * If the event is architectural and supported on this CPU, the correct
1825 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned.
1826 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP.
1830 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map)
1832 enum core_arch_events ae;
1835 case PMC_EV_IAP_ARCH_UNH_COR_CYC:
1836 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1837 *map = PMC_EV_IAP_EVENT_3CH_00H;
1839 case PMC_EV_IAP_ARCH_INS_RET:
1840 ae = CORE_AE_INSTRUCTION_RETIRED;
1841 *map = PMC_EV_IAP_EVENT_C0H_00H;
1843 case PMC_EV_IAP_ARCH_UNH_REF_CYC:
1844 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1845 *map = PMC_EV_IAP_EVENT_3CH_01H;
1847 case PMC_EV_IAP_ARCH_LLC_REF:
1848 ae = CORE_AE_LLC_REFERENCE;
1849 *map = PMC_EV_IAP_EVENT_2EH_4FH;
1851 case PMC_EV_IAP_ARCH_LLC_MIS:
1852 ae = CORE_AE_LLC_MISSES;
1853 *map = PMC_EV_IAP_EVENT_2EH_41H;
1855 case PMC_EV_IAP_ARCH_BR_INS_RET:
1856 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1857 *map = PMC_EV_IAP_EVENT_C4H_00H;
1859 case PMC_EV_IAP_ARCH_BR_MIS_RET:
1860 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1861 *map = PMC_EV_IAP_EVENT_C5H_00H;
1864 default: /* Non architectural event. */
1865 return (EV_IS_NOTARCH);
1868 return (((core_architectural_events & (1 << ae)) == 0) ?
1869 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP);
1873 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1879 * Events valid only on counter 0, 1.
1881 case PMC_EV_IAP_EVENT_40H_01H:
1882 case PMC_EV_IAP_EVENT_40H_02H:
1883 case PMC_EV_IAP_EVENT_40H_04H:
1884 case PMC_EV_IAP_EVENT_40H_08H:
1885 case PMC_EV_IAP_EVENT_40H_0FH:
1886 case PMC_EV_IAP_EVENT_41H_02H:
1887 case PMC_EV_IAP_EVENT_41H_04H:
1888 case PMC_EV_IAP_EVENT_41H_08H:
1889 case PMC_EV_IAP_EVENT_42H_01H:
1890 case PMC_EV_IAP_EVENT_42H_02H:
1891 case PMC_EV_IAP_EVENT_42H_04H:
1892 case PMC_EV_IAP_EVENT_42H_08H:
1893 case PMC_EV_IAP_EVENT_43H_01H:
1894 case PMC_EV_IAP_EVENT_43H_02H:
1895 case PMC_EV_IAP_EVENT_51H_01H:
1896 case PMC_EV_IAP_EVENT_51H_02H:
1897 case PMC_EV_IAP_EVENT_51H_04H:
1898 case PMC_EV_IAP_EVENT_51H_08H:
1899 case PMC_EV_IAP_EVENT_63H_01H:
1900 case PMC_EV_IAP_EVENT_63H_02H:
1905 mask = ~0; /* Any row index is ok. */
1908 return (mask & (1 << ri));
1912 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1918 * Events valid only on counter 0.
1920 case PMC_EV_IAP_EVENT_60H_01H:
1921 case PMC_EV_IAP_EVENT_60H_02H:
1922 case PMC_EV_IAP_EVENT_60H_04H:
1923 case PMC_EV_IAP_EVENT_60H_08H:
1924 case PMC_EV_IAP_EVENT_B3H_01H:
1925 case PMC_EV_IAP_EVENT_B3H_02H:
1926 case PMC_EV_IAP_EVENT_B3H_04H:
1931 * Events valid only on counter 0, 1.
1933 case PMC_EV_IAP_EVENT_4CH_01H:
1934 case PMC_EV_IAP_EVENT_4EH_01H:
1935 case PMC_EV_IAP_EVENT_4EH_02H:
1936 case PMC_EV_IAP_EVENT_4EH_04H:
1937 case PMC_EV_IAP_EVENT_51H_01H:
1938 case PMC_EV_IAP_EVENT_51H_02H:
1939 case PMC_EV_IAP_EVENT_51H_04H:
1940 case PMC_EV_IAP_EVENT_51H_08H:
1941 case PMC_EV_IAP_EVENT_63H_01H:
1942 case PMC_EV_IAP_EVENT_63H_02H:
1947 mask = ~0; /* Any row index is ok. */
1950 return (mask & (1 << ri));
1954 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri)
1959 /* Events valid only on counter 0. */
1960 case PMC_EV_IAP_EVENT_B7H_01H:
1963 /* Events valid only on counter 1. */
1964 case PMC_EV_IAP_EVENT_C0H_01H:
1967 /* Events valid only on counter 2. */
1968 case PMC_EV_IAP_EVENT_48H_01H:
1969 case PMC_EV_IAP_EVENT_A2H_02H:
1972 /* Events valid only on counter 3. */
1973 case PMC_EV_IAP_EVENT_A3H_08H:
1974 case PMC_EV_IAP_EVENT_BBH_01H:
1975 case PMC_EV_IAP_EVENT_CDH_01H:
1976 case PMC_EV_IAP_EVENT_CDH_02H:
1980 mask = ~0; /* Any row index is ok. */
1983 return (mask & (1 << ri));
1987 iap_event_ok_on_counter(enum pmc_event pe, int ri)
1993 * Events valid only on counter 0.
1995 case PMC_EV_IAP_EVENT_10H_00H:
1996 case PMC_EV_IAP_EVENT_14H_00H:
1997 case PMC_EV_IAP_EVENT_18H_00H:
1998 case PMC_EV_IAP_EVENT_B3H_01H:
1999 case PMC_EV_IAP_EVENT_B3H_02H:
2000 case PMC_EV_IAP_EVENT_B3H_04H:
2001 case PMC_EV_IAP_EVENT_C1H_00H:
2002 case PMC_EV_IAP_EVENT_CBH_01H:
2003 case PMC_EV_IAP_EVENT_CBH_02H:
2008 * Events valid only on counter 1.
2010 case PMC_EV_IAP_EVENT_11H_00H:
2011 case PMC_EV_IAP_EVENT_12H_00H:
2012 case PMC_EV_IAP_EVENT_13H_00H:
2017 mask = ~0; /* Any row index is ok. */
2020 return (mask & (1 << ri));
2024 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
2025 const struct pmc_op_pmcallocate *a)
2028 enum pmc_event ev, map;
2029 struct iap_event_descr *ie;
2030 uint32_t c, caps, config, cpuflag, evsel, mask;
2032 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2033 ("[core,%d] illegal CPU %d", __LINE__, cpu));
2034 KASSERT(ri >= 0 && ri < core_iap_npmc,
2035 ("[core,%d] illegal row-index value %d", __LINE__, ri));
2037 /* check requested capabilities */
2039 if ((IAP_PMC_CAPS & caps) != caps)
2041 map = 0; /* XXX: silent GCC warning */
2042 arch = iap_is_event_architectural(pm->pm_event, &map);
2043 if (arch == EV_IS_ARCH_NOTSUPP)
2044 return (EOPNOTSUPP);
2045 else if (arch == EV_IS_ARCH_SUPP)
2051 * A small number of events are not supported in all the
2052 * processors based on a given microarchitecture.
2054 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) {
2055 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
2056 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)
2060 switch (core_cputype) {
2061 case PMC_CPU_INTEL_COREI7:
2062 case PMC_CPU_INTEL_NEHALEM_EX:
2063 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
2066 case PMC_CPU_INTEL_SANDYBRIDGE:
2067 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2068 case PMC_CPU_INTEL_IVYBRIDGE:
2069 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2070 case PMC_CPU_INTEL_HASWELL:
2071 case PMC_CPU_INTEL_HASWELL_XEON:
2072 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
2075 case PMC_CPU_INTEL_WESTMERE:
2076 case PMC_CPU_INTEL_WESTMERE_EX:
2077 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
2081 if (iap_event_ok_on_counter(ev, ri) == 0)
2086 * Look for an event descriptor with matching CPU and event id
2090 switch (core_cputype) {
2092 case PMC_CPU_INTEL_ATOM:
2095 case PMC_CPU_INTEL_ATOM_SILVERMONT:
2096 cpuflag = IAP_F_CAS;
2098 case PMC_CPU_INTEL_CORE:
2101 case PMC_CPU_INTEL_CORE2:
2102 cpuflag = IAP_F_CC2;
2104 case PMC_CPU_INTEL_CORE2EXTREME:
2105 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
2107 case PMC_CPU_INTEL_COREI7:
2110 case PMC_CPU_INTEL_HASWELL:
2113 case PMC_CPU_INTEL_HASWELL_XEON:
2114 cpuflag = IAP_F_HWX;
2116 case PMC_CPU_INTEL_IVYBRIDGE:
2119 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2120 cpuflag = IAP_F_IBX;
2122 case PMC_CPU_INTEL_SANDYBRIDGE:
2125 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2126 cpuflag = IAP_F_SBX;
2128 case PMC_CPU_INTEL_WESTMERE:
2133 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
2134 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
2137 if (n == niap_events)
2141 * A matching event descriptor has been found, so start
2142 * assembling the contents of the event select register.
2144 evsel = ie->iap_evcode;
2146 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
2149 * If the event uses a fixed umask value, reject any umask
2150 * bits set by the user.
2152 if (ie->iap_flags & IAP_F_FM) {
2154 if (IAP_UMASK(config) != 0)
2157 evsel |= (ie->iap_umask << 8);
2162 * Otherwise, the UMASK value needs to be taken from
2163 * the MD fields of the allocation request. Reject
2164 * requests that specify reserved bits.
2169 if (ie->iap_umask & IAP_M_CORE) {
2170 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
2176 if (ie->iap_umask & IAP_M_AGENT)
2177 mask |= IAP_F_AGENT;
2179 if (ie->iap_umask & IAP_M_PREFETCH) {
2181 if ((c = (config & IAP_F_PREFETCH)) ==
2182 IAP_PREFETCH_RESERVED)
2185 mask |= IAP_F_PREFETCH;
2188 if (ie->iap_umask & IAP_M_MESI)
2191 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
2192 mask |= IAP_F_SNOOPRESPONSE;
2194 if (ie->iap_umask & IAP_M_SNOOPTYPE)
2195 mask |= IAP_F_SNOOPTYPE;
2197 if (ie->iap_umask & IAP_M_TRANSITION)
2198 mask |= IAP_F_TRANSITION;
2201 * If bits outside of the allowed set of umask bits
2202 * are set, reject the request.
2207 evsel |= (config & mask);
2212 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
2214 if (core_cputype == PMC_CPU_INTEL_ATOM ||
2215 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT ||
2216 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2217 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON)
2218 evsel |= (config & IAP_ANY);
2219 else if (config & IAP_ANY)
2223 * Check offcore response configuration.
2225 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
2226 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
2227 ev != PMC_EV_IAP_EVENT_BBH_01H)
2229 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
2230 ev == PMC_EV_IAP_EVENT_BBH_01H)
2232 if ((core_cputype == PMC_CPU_INTEL_COREI7 ||
2233 core_cputype == PMC_CPU_INTEL_WESTMERE ||
2234 core_cputype == PMC_CPU_INTEL_NEHALEM_EX ||
2235 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) &&
2236 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM)
2238 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
2239 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
2240 core_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
2241 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) &&
2242 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB)
2244 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp;
2247 if (caps & PMC_CAP_THRESHOLD)
2248 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
2249 if (caps & PMC_CAP_USER)
2251 if (caps & PMC_CAP_SYSTEM)
2253 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
2254 evsel |= (IAP_OS | IAP_USR);
2255 if (caps & PMC_CAP_EDGE)
2257 if (caps & PMC_CAP_INVERT)
2259 if (caps & PMC_CAP_INTERRUPT)
2262 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
2268 iap_config_pmc(int cpu, int ri, struct pmc *pm)
2270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2271 ("[core,%d] illegal CPU %d", __LINE__, cpu));
2273 KASSERT(ri >= 0 && ri < core_iap_npmc,
2274 ("[core,%d] illegal row-index %d", __LINE__, ri));
2276 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
2278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
2281 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
2287 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
2291 char iap_name[PMC_NAME_MAX];
2293 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
2295 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
2296 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
2300 pi->pm_class = PMC_CLASS_IAP;
2302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
2303 pi->pm_enabled = TRUE;
2304 *ppmc = phw->phw_pmc;
2306 pi->pm_enabled = FALSE;
2314 iap_get_config(int cpu, int ri, struct pmc **ppm)
2316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2322 iap_get_msr(int ri, uint32_t *msr)
2324 KASSERT(ri >= 0 && ri < core_iap_npmc,
2325 ("[iap,%d] ri %d out of range", __LINE__, ri));
2333 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
2338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2339 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2340 KASSERT(ri >= 0 && ri < core_iap_npmc,
2341 ("[core,%d] illegal row-index %d", __LINE__, ri));
2343 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2346 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
2350 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2351 *v = iap_perfctr_value_to_reload_count(tmp);
2353 *v = tmp & ((1ULL << core_iap_width) - 1);
2355 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
2362 iap_release_pmc(int cpu, int ri, struct pmc *pm)
2366 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
2369 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2370 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2371 KASSERT(ri >= 0 && ri < core_iap_npmc,
2372 ("[core,%d] illegal row-index %d", __LINE__, ri));
2374 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
2375 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
2381 iap_start_pmc(int cpu, int ri)
2385 struct core_cpu *cc;
2387 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2388 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2389 KASSERT(ri >= 0 && ri < core_iap_npmc,
2390 ("[core,%d] illegal row-index %d", __LINE__, ri));
2392 cc = core_pcpu[cpu];
2393 pm = cc->pc_corepmcs[ri].phw_pmc;
2396 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
2397 __LINE__, cpu, ri));
2399 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
2401 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
2403 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
2404 cpu, ri, IAP_EVSEL0 + ri, evsel);
2406 /* Event specific configuration. */
2407 switch (pm->pm_event) {
2408 case PMC_EV_IAP_EVENT_B7H_01H:
2409 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
2411 case PMC_EV_IAP_EVENT_BBH_01H:
2412 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
2418 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
2420 if (core_cputype == PMC_CPU_INTEL_CORE)
2425 cc->pc_globalctrl |= (1ULL << ri);
2426 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2427 } while (cc->pc_resync != 0);
2433 iap_stop_pmc(int cpu, int ri)
2436 struct core_cpu *cc;
2439 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2440 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2441 KASSERT(ri >= 0 && ri < core_iap_npmc,
2442 ("[core,%d] illegal row index %d", __LINE__, ri));
2444 cc = core_pcpu[cpu];
2445 pm = cc->pc_corepmcs[ri].phw_pmc;
2448 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2451 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
2453 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2454 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
2456 if (core_cputype == PMC_CPU_INTEL_CORE)
2462 cc->pc_globalctrl &= ~(1ULL << ri);
2463 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2464 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2465 } while (cc->pc_resync != 0);
2471 iap_write_pmc(int cpu, int ri, pmc_value_t v)
2474 struct core_cpu *cc;
2476 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2477 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2478 KASSERT(ri >= 0 && ri < core_iap_npmc,
2479 ("[core,%d] illegal row index %d", __LINE__, ri));
2481 cc = core_pcpu[cpu];
2482 pm = cc->pc_corepmcs[ri].phw_pmc;
2485 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2488 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
2491 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2492 v = iap_reload_count_to_perfctr_value(v);
2495 * Write the new value to the counter. The counter will be in
2496 * a stopped state when the pcd_write() entry point is called.
2499 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
2506 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
2509 struct pmc_classdep *pcd;
2511 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
2513 PMCDBG0(MDP,INI,1, "iap-initialize");
2515 /* Remember the set of architectural events supported. */
2516 core_architectural_events = ~flags;
2518 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
2520 pcd->pcd_caps = IAP_PMC_CAPS;
2521 pcd->pcd_class = PMC_CLASS_IAP;
2522 pcd->pcd_num = npmc;
2523 pcd->pcd_ri = md->pmd_npmc;
2524 pcd->pcd_width = pmcwidth;
2526 pcd->pcd_allocate_pmc = iap_allocate_pmc;
2527 pcd->pcd_config_pmc = iap_config_pmc;
2528 pcd->pcd_describe = iap_describe;
2529 pcd->pcd_get_config = iap_get_config;
2530 pcd->pcd_get_msr = iap_get_msr;
2531 pcd->pcd_pcpu_fini = core_pcpu_fini;
2532 pcd->pcd_pcpu_init = core_pcpu_init;
2533 pcd->pcd_read_pmc = iap_read_pmc;
2534 pcd->pcd_release_pmc = iap_release_pmc;
2535 pcd->pcd_start_pmc = iap_start_pmc;
2536 pcd->pcd_stop_pmc = iap_stop_pmc;
2537 pcd->pcd_write_pmc = iap_write_pmc;
2539 md->pmd_npmc += npmc;
2543 core_intr(int cpu, struct trapframe *tf)
2547 struct core_cpu *cc;
2548 int error, found_interrupt, ri;
2551 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2552 TRAPF_USERMODE(tf));
2554 found_interrupt = 0;
2555 cc = core_pcpu[cpu];
2557 for (ri = 0; ri < core_iap_npmc; ri++) {
2559 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2560 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2563 if (!iap_pmc_has_overflowed(ri))
2566 found_interrupt = 1;
2568 if (pm->pm_state != PMC_STATE_RUNNING)
2571 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2572 TRAPF_USERMODE(tf));
2574 v = pm->pm_sc.pm_reloadcount;
2575 v = iaf_reload_count_to_perfctr_value(v);
2578 * Stop the counter, reload it but only restart it if
2579 * the PMC is not stalled.
2581 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2582 wrmsr(IAP_EVSEL0 + ri, msr);
2583 wrmsr(IAP_PMC0 + ri, v);
2588 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2592 if (found_interrupt)
2593 lapic_reenable_pmc();
2595 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2596 &pmc_stats.pm_intr_ignored, 1);
2598 return (found_interrupt);
2602 core2_intr(int cpu, struct trapframe *tf)
2604 int error, found_interrupt, n;
2605 uint64_t flag, intrstatus, intrenable, msr;
2607 struct core_cpu *cc;
2610 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2611 TRAPF_USERMODE(tf));
2614 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2615 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2616 * the current set of interrupting PMCs and process these
2617 * after stopping them.
2619 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2620 intrenable = intrstatus & core_pmcmask;
2622 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2623 (uintmax_t) intrstatus);
2625 found_interrupt = 0;
2626 cc = core_pcpu[cpu];
2628 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2630 cc->pc_globalctrl &= ~intrenable;
2631 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2634 * Stop PMCs and clear overflow status bits.
2636 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2637 wrmsr(IA_GLOBAL_CTRL, msr);
2638 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2639 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2640 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2643 * Look for interrupts from fixed function PMCs.
2645 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2648 if ((intrstatus & flag) == 0)
2651 found_interrupt = 1;
2653 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2654 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2655 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2658 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2659 TRAPF_USERMODE(tf));
2661 intrenable &= ~flag;
2663 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2665 /* Reload sampling count. */
2666 wrmsr(IAF_CTR0 + n, v);
2668 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
2669 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2673 * Process interrupts from the programmable counters.
2675 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2676 if ((intrstatus & flag) == 0)
2679 found_interrupt = 1;
2681 pm = cc->pc_corepmcs[n].phw_pmc;
2682 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2683 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2686 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2687 TRAPF_USERMODE(tf));
2689 intrenable &= ~flag;
2691 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2693 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2696 /* Reload sampling count. */
2697 wrmsr(IAP_PMC0 + n, v);
2701 * Reenable all non-stalled PMCs.
2703 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2704 (uintmax_t) intrenable);
2706 cc->pc_globalctrl |= intrenable;
2708 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2710 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2711 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2712 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2713 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2714 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2716 if (found_interrupt)
2717 lapic_reenable_pmc();
2719 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2720 &pmc_stats.pm_intr_ignored, 1);
2722 return (found_interrupt);
2726 pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2728 int cpuid[CORE_CPUID_REQUEST_SIZE];
2729 int ipa_version, flags, nflags;
2731 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2733 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2735 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2736 md->pmd_cputype, maxcpu, ipa_version);
2738 if (ipa_version < 1 || ipa_version > 3) {
2739 /* Unknown PMC architecture. */
2740 printf("hwpc_core: unknown PMC architecture: %d\n",
2742 return (EPROGMISMATCH);
2745 core_cputype = md->pmd_cputype;
2750 * Initialize programmable counters.
2752 KASSERT(ipa_version >= 1,
2753 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2755 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2756 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2758 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2760 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2761 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2763 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2766 * Initialize fixed function counters, if present.
2768 if (core_cputype != PMC_CPU_INTEL_CORE) {
2769 KASSERT(ipa_version >= 2,
2770 ("[core,%d] ipa_version %d too small", __LINE__,
2773 core_iaf_ri = core_iap_npmc;
2774 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2775 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2777 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2778 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2781 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2784 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2788 * Choose the appropriate interrupt handler.
2790 if (ipa_version == 1)
2791 md->pmd_intr = core_intr;
2793 md->pmd_intr = core2_intr;
2795 md->pmd_pcpu_fini = NULL;
2796 md->pmd_pcpu_init = NULL;
2802 pmc_core_finalize(struct pmc_mdep *md)
2804 PMCDBG0(MDP,INI,1, "core-finalize");
2806 free(core_pcpu, M_PMC);