2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Intel Core, Core 2 and Atom PMCs.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/apicvar.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/md_var.h>
45 #include <machine/specialreg.h>
47 #define CORE_CPUID_REQUEST 0xA
48 #define CORE_CPUID_REQUEST_SIZE 0x4
49 #define CORE_CPUID_EAX 0x0
50 #define CORE_CPUID_EBX 0x1
51 #define CORE_CPUID_ECX 0x2
52 #define CORE_CPUID_EDX 0x3
54 #define IAF_PMC_CAPS \
55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT)
56 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
58 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
59 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
60 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
63 * "Architectural" events defined by Intel. The values of these
64 * symbols correspond to positions in the bitmask returned by
65 * the CPUID.0AH instruction.
67 enum core_arch_events {
68 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
69 CORE_AE_BRANCH_MISSES_RETIRED = 6,
70 CORE_AE_INSTRUCTION_RETIRED = 1,
71 CORE_AE_LLC_MISSES = 4,
72 CORE_AE_LLC_REFERENCE = 3,
73 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
74 CORE_AE_UNHALTED_CORE_CYCLES = 0
77 static enum pmc_cputype core_cputype;
80 volatile uint32_t pc_resync;
81 volatile uint32_t pc_iafctrl; /* Fixed function control. */
82 volatile uint64_t pc_globalctrl; /* Global control register. */
83 struct pmc_hw pc_corepmcs[];
86 static struct core_cpu **core_pcpu;
88 static uint32_t core_architectural_events;
89 static uint64_t core_pmcmask;
91 static int core_iaf_ri; /* relative index of fixed counters */
92 static int core_iaf_width;
93 static int core_iaf_npmc;
95 static int core_iap_width;
96 static int core_iap_npmc;
99 core_pcpu_noop(struct pmc_mdep *md, int cpu)
107 core_pcpu_init(struct pmc_mdep *md, int cpu)
112 int core_ri, n, npmc;
114 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
115 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
117 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
119 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
120 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
122 if (core_cputype != PMC_CPU_INTEL_CORE)
123 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
125 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
126 M_PMC, M_WAITOK | M_ZERO);
131 KASSERT(pc != NULL && cc != NULL,
132 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
134 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
135 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
136 PMC_PHW_CPU_TO_STATE(cpu) |
137 PMC_PHW_INDEX_TO_STATE(n + core_ri);
139 pc->pc_hwpmcs[n + core_ri] = phw;
146 core_pcpu_fini(struct pmc_mdep *md, int cpu)
148 int core_ri, n, npmc;
153 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
154 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
156 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
158 if ((cc = core_pcpu[cpu]) == NULL)
161 core_pcpu[cpu] = NULL;
165 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
168 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
169 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
171 for (n = 0; n < npmc; n++) {
172 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
173 wrmsr(IAP_EVSEL0 + n, msr);
176 if (core_cputype != PMC_CPU_INTEL_CORE) {
177 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
178 wrmsr(IAF_CTRL, msr);
179 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
182 for (n = 0; n < npmc; n++)
183 pc->pc_hwpmcs[n + core_ri] = NULL;
191 * Fixed function counters.
195 iaf_perfctr_value_to_reload_count(pmc_value_t v)
197 v &= (1ULL << core_iaf_width) - 1;
198 return (1ULL << core_iaf_width) - v;
202 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
204 return (1ULL << core_iaf_width) - rlc;
208 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
209 const struct pmc_op_pmcallocate *a)
212 uint32_t caps, flags, validflags;
214 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
215 ("[core,%d] illegal CPU %d", __LINE__, cpu));
217 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
219 if (ri < 0 || ri > core_iaf_npmc)
224 if (a->pm_class != PMC_CLASS_IAF ||
225 (caps & IAF_PMC_CAPS) != caps)
229 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
232 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
234 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
236 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
239 flags = a->pm_md.pm_iaf.pm_iaf_flags;
241 validflags = IAF_MASK;
243 if (core_cputype != PMC_CPU_INTEL_ATOM)
244 validflags &= ~IAF_ANY;
246 if ((flags & ~validflags) != 0)
249 if (caps & PMC_CAP_INTERRUPT)
251 if (caps & PMC_CAP_SYSTEM)
253 if (caps & PMC_CAP_USER)
255 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
256 flags |= (IAF_OS | IAF_USR);
258 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
260 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
261 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
267 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
269 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
270 ("[core,%d] illegal CPU %d", __LINE__, cpu));
272 KASSERT(ri >= 0 && ri < core_iaf_npmc,
273 ("[core,%d] illegal row-index %d", __LINE__, ri));
275 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
277 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
280 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
286 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
290 char iaf_name[PMC_NAME_MAX];
292 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
294 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
295 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
299 pi->pm_class = PMC_CLASS_IAF;
301 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
302 pi->pm_enabled = TRUE;
303 *ppmc = phw->phw_pmc;
305 pi->pm_enabled = FALSE;
313 iaf_get_config(int cpu, int ri, struct pmc **ppm)
315 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
321 iaf_get_msr(int ri, uint32_t *msr)
323 KASSERT(ri >= 0 && ri < core_iaf_npmc,
324 ("[iaf,%d] ri %d out of range", __LINE__, ri));
326 *msr = IAF_RI_TO_MSR(ri);
332 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
337 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
338 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
339 KASSERT(ri >= 0 && ri < core_iaf_npmc,
340 ("[core,%d] illegal row-index %d", __LINE__, ri));
342 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
345 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
346 ri, ri + core_iaf_ri));
348 tmp = rdpmc(IAF_RI_TO_MSR(ri));
350 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
351 *v = iaf_perfctr_value_to_reload_count(tmp);
355 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
356 IAF_RI_TO_MSR(ri), *v);
362 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
364 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
366 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
367 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
368 KASSERT(ri >= 0 && ri < core_iaf_npmc,
369 ("[core,%d] illegal row-index %d", __LINE__, ri));
371 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
372 ("[core,%d] PHW pmc non-NULL", __LINE__));
378 iaf_start_pmc(int cpu, int ri)
381 struct core_cpu *iafc;
384 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
385 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
386 KASSERT(ri >= 0 && ri < core_iaf_npmc,
387 ("[core,%d] illegal row-index %d", __LINE__, ri));
389 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
391 iafc = core_pcpu[cpu];
392 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
394 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
396 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
397 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
401 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
402 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
403 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
404 IAF_GLOBAL_CTRL_MASK));
405 } while (iafc->pc_resync != 0);
407 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
408 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
409 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
415 iaf_stop_pmc(int cpu, int ri)
418 struct core_cpu *iafc;
421 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
423 iafc = core_pcpu[cpu];
425 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
426 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
427 KASSERT(ri >= 0 && ri < core_iaf_npmc,
428 ("[core,%d] illegal row-index %d", __LINE__, ri));
430 fc = (IAF_MASK << (ri * 4));
432 if (core_cputype != PMC_CPU_INTEL_ATOM)
435 iafc->pc_iafctrl &= ~fc;
437 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
438 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
439 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
443 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
444 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
445 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
446 IAF_GLOBAL_CTRL_MASK));
447 } while (iafc->pc_resync != 0);
449 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
450 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
451 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
457 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
463 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
464 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
465 KASSERT(ri >= 0 && ri < core_iaf_npmc,
466 ("[core,%d] illegal row-index %d", __LINE__, ri));
469 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
472 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
474 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
475 v = iaf_reload_count_to_perfctr_value(v);
477 /* Turn off fixed counters */
478 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
479 wrmsr(IAF_CTRL, msr);
481 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
483 /* Turn on fixed counters */
484 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
485 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
487 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
488 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
489 (uintmax_t) rdmsr(IAF_CTRL),
490 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
497 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
499 struct pmc_classdep *pcd;
501 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
503 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
505 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
507 pcd->pcd_caps = IAF_PMC_CAPS;
508 pcd->pcd_class = PMC_CLASS_IAF;
510 pcd->pcd_ri = md->pmd_npmc;
511 pcd->pcd_width = pmcwidth;
513 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
514 pcd->pcd_config_pmc = iaf_config_pmc;
515 pcd->pcd_describe = iaf_describe;
516 pcd->pcd_get_config = iaf_get_config;
517 pcd->pcd_get_msr = iaf_get_msr;
518 pcd->pcd_pcpu_fini = core_pcpu_noop;
519 pcd->pcd_pcpu_init = core_pcpu_noop;
520 pcd->pcd_read_pmc = iaf_read_pmc;
521 pcd->pcd_release_pmc = iaf_release_pmc;
522 pcd->pcd_start_pmc = iaf_start_pmc;
523 pcd->pcd_stop_pmc = iaf_stop_pmc;
524 pcd->pcd_write_pmc = iaf_write_pmc;
526 md->pmd_npmc += npmc;
530 * Intel programmable PMCs.
534 * Event descriptor tables.
536 * For each event id, we track:
538 * 1. The CPUs that the event is valid for.
540 * 2. If the event uses a fixed UMASK, the value of the umask field.
541 * If the event doesn't use a fixed UMASK, a mask of legal bits
545 struct iap_event_descr {
546 enum pmc_event iap_ev;
547 unsigned char iap_evcode;
548 unsigned char iap_umask;
549 unsigned char iap_flags;
552 #define IAP_F_CC (1 << 0) /* CPU: Core */
553 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
554 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
555 #define IAP_F_CA (1 << 3) /* CPU: Atom */
556 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
557 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
558 #define IAP_F_WM (1 << 5) /* CPU: Westmere */
559 #define IAP_F_SB (1 << 6) /* CPU: Sandy Brdige */
560 #define IAP_F_FM (1 << 7) /* Fixed mask */
562 #define IAP_F_ALLCPUSCORE2 \
563 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
565 /* Sub fields of UMASK that this event supports. */
566 #define IAP_M_CORE (1 << 0) /* Core specificity */
567 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
568 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
569 #define IAP_M_MESI (1 << 3) /* MESI */
570 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
571 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
572 #define IAP_M_TRANSITION (1 << 6) /* Transition */
574 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
575 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
576 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
577 #define IAP_F_MESI (0xF << 8) /* MESI */
578 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
579 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
580 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
582 #define IAP_PREFETCH_RESERVED (0x2 << 12)
583 #define IAP_CORE_THIS (0x1 << 14)
584 #define IAP_CORE_ALL (0x3 << 14)
585 #define IAP_F_CMASK 0xFF000000
587 static struct iap_event_descr iap_events[] = {
589 #define IAPDESCR(N,EV,UM,FLAGS) { \
590 .iap_ev = PMC_EV_IAP_EVENT_##N, \
591 .iap_evcode = (EV), \
593 .iap_flags = (FLAGS) \
596 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
597 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
599 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
600 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
601 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
602 IAP_F_WM | IAP_F_SB),
603 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
604 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
605 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB),
606 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
608 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
609 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
610 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
611 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
612 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
614 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
615 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
616 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB),
617 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
619 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
620 IAP_F_CC2E | IAP_F_CA),
621 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
622 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
623 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
624 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
625 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
627 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
628 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
629 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
630 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
631 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
632 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
633 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB),
635 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
636 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
637 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
638 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
639 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
640 IAP_F_WM | IAP_F_SB),
641 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
642 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
643 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
644 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
645 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
646 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
647 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
648 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O),
649 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
651 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
652 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
653 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
654 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
656 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
657 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
658 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
660 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
662 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
663 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
665 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB),
666 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB),
668 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
669 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
671 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
672 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
673 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
674 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
675 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
676 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
678 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
679 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
680 IAP_F_WM | IAP_F_SB),
681 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
682 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
683 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
684 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
685 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
686 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
687 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
688 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
690 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
691 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB),
692 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB),
693 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
695 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
696 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
697 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
698 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
699 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
700 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
701 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
702 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
703 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
705 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
706 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
707 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
708 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
709 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
710 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
712 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
713 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
714 IAP_F_WM | IAP_F_SB),
715 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
717 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
719 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
720 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
722 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
723 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
724 IAP_F_I7 | IAP_F_WM),
725 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
727 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
728 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
729 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
731 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
735 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
736 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
738 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
739 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
740 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
741 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
742 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
743 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
744 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
745 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
746 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
747 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
748 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
749 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
750 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
751 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
752 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
754 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
756 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
757 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
758 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
759 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
760 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
761 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
762 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
763 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
764 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
765 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
766 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
767 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
769 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
770 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
771 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
772 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
773 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
774 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
775 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
776 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
777 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
778 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
779 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
780 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
781 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
783 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
784 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
785 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
786 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
787 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB),
788 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
790 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
791 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
792 IAP_F_CA | IAP_F_CC2),
793 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
794 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
796 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
798 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
799 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
800 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
802 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 |
805 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
807 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
808 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
810 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
811 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
813 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
815 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
816 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
817 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
818 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
819 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
821 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
823 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
824 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
825 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
826 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
827 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
828 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
829 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
831 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
832 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
833 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
834 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
835 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
836 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
837 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
839 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
840 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
841 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
842 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
843 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
844 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
846 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
848 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
849 IAP_F_CC2 | IAP_F_I7),
851 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
853 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
855 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
856 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
858 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
859 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB),
860 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O),
862 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
863 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
864 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
865 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
866 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
867 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB),
868 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
870 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7),
871 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
872 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7),
874 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
875 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
876 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
877 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
878 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
880 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
881 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
883 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB),
885 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
887 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
888 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
890 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
891 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
893 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
894 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
895 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
896 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
897 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
899 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
901 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
903 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
905 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
908 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
910 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
912 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB),
913 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB),
914 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB),
916 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB),
917 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB),
918 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB),
919 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB),
921 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB),
922 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB),
924 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB),
926 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
927 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
929 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
930 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
932 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
935 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
936 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
938 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
939 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
941 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
942 IAP_F_CA | IAP_F_CC2),
943 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
944 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
946 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
949 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
950 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
952 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
953 IAP_F_CA | IAP_F_CC2),
954 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
956 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
958 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
959 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
961 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
962 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
963 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
964 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
966 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
967 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
969 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
970 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
972 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
973 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
975 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
976 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
978 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
979 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
981 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
982 IAP_F_CA | IAP_F_CC2),
983 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
985 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
986 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
988 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB),
989 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB),
990 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB),
991 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB),
992 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB),
993 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB),
995 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
997 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
999 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
1001 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1002 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
1004 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
1006 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1007 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1008 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1009 IAP_F_WM | IAP_F_SB),
1010 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1012 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1014 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1015 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
1016 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
1018 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1019 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1020 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
1021 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1022 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
1023 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
1025 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
1026 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1028 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
1029 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1031 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1033 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1035 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB),
1036 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
1037 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
1038 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1040 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1042 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1043 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1045 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1046 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1048 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1049 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1051 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1052 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1054 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1056 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1058 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1059 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1061 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1063 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1065 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1066 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1068 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1069 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB),
1070 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB),
1072 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1073 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1075 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1076 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1078 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1079 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1081 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1083 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1085 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1086 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1088 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1089 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB),
1090 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB),
1092 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1093 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1094 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1095 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1096 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1097 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1099 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1100 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1101 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1102 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1103 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1105 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB),
1107 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1108 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1109 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1111 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1113 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1115 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1117 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1119 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB),
1120 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1122 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1124 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB),
1125 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB),
1126 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB),
1128 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1129 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1131 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1133 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1135 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1137 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1139 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1141 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1143 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1146 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1147 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1148 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1150 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1151 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1152 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1153 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1155 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1157 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1160 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB),
1161 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB),
1162 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB),
1164 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1167 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1168 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1170 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1171 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1173 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O |
1175 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1176 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1177 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1178 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1180 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1181 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1183 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1185 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1186 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1187 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1188 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1189 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1190 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1191 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1192 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1195 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1198 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1199 IAP_F_WM | IAP_F_I7O),
1200 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1201 IAP_F_WM | IAP_F_I7O),
1202 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1203 IAP_F_WM | IAP_F_I7O),
1204 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1205 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1206 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1207 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1208 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1209 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1210 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1211 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1212 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1214 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1215 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1216 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1218 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB),
1220 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1223 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1224 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1225 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1227 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1228 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1230 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1233 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB),
1234 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB),
1236 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB),
1238 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1240 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1241 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1242 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1243 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1244 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1245 IAP_F_I7 | IAP_F_WM),
1246 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1248 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1249 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1250 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB),
1251 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB),
1252 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB),
1253 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB),
1254 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1256 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1257 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1258 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1259 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1260 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1261 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1262 IAP_F_I7 | IAP_F_WM),
1263 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1264 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1265 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1266 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1268 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1269 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1270 IAP_F_I7 | IAP_F_WM),
1271 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1273 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1274 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1275 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1276 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB),
1278 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1279 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1280 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1281 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1282 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1283 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1284 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1285 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1286 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1288 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1289 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1290 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB),
1291 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB),
1292 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB),
1294 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1295 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1296 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB),
1297 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1299 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB),
1300 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB),
1301 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB),
1303 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1304 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1305 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1307 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1308 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1309 IAP_F_I7 | IAP_F_WM),
1310 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1311 IAP_F_I7 | IAP_F_WM),
1312 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1313 IAP_F_I7 | IAP_F_WM),
1314 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1315 IAP_F_I7 | IAP_F_WM),
1316 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1317 IAP_F_I7 | IAP_F_WM),
1318 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1320 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1321 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1323 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1325 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1326 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1327 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1329 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1331 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1333 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB),
1334 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB),
1336 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1337 IAP_F_I7 | IAP_F_WM),
1338 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1339 IAP_F_I7 | IAP_F_WM),
1340 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1341 IAP_F_I7 | IAP_F_WM),
1342 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1343 IAP_F_I7 | IAP_F_WM),
1344 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1346 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1347 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1349 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1350 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1351 IAP_F_I7 | IAP_F_WM),
1352 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1353 IAP_F_I7 | IAP_F_WM),
1354 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1355 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB),
1357 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1358 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB),
1359 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB),
1361 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1362 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1364 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1365 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1367 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB),
1368 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB),
1369 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB),
1370 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB),
1371 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB),
1373 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB),
1374 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1376 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1378 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1379 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB),
1381 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1382 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1383 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1384 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1385 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1386 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1387 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1388 IAP_F_I7 | IAP_F_WM | IAP_F_SB),
1389 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1390 IAP_F_I7 | IAP_F_WM),
1391 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1393 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1394 IAP_F_I7 | IAP_F_WM),
1395 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1397 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1398 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1399 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1401 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1402 IAP_F_I7 | IAP_F_WM),
1403 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1404 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1405 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1406 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1408 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1410 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1411 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1412 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1413 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1414 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1416 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1417 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1418 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1419 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1421 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1422 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1423 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1425 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1426 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1428 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1429 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1430 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1431 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1432 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1433 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1435 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1436 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1439 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1441 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1442 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1444 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1446 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1447 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1449 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1451 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1452 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1453 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O),
1455 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1457 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1458 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1460 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1462 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1464 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1466 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1468 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1470 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1472 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1475 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB),
1476 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1478 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1480 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1483 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1485 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1487 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1489 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1491 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB),
1492 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1494 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1495 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1496 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1497 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1498 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1499 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1501 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1502 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1503 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1504 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1505 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
1508 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1510 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1511 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1512 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1514 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1515 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1517 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1518 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1519 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1520 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1521 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1522 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1523 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1526 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1529 iap_perfctr_value_to_reload_count(pmc_value_t v)
1531 v &= (1ULL << core_iap_width) - 1;
1532 return (1ULL << core_iap_width) - v;
1536 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1538 return (1ULL << core_iap_width) - rlc;
1542 iap_pmc_has_overflowed(int ri)
1547 * We treat a Core (i.e., Intel architecture v1) PMC as has
1548 * having overflowed if its MSB is zero.
1551 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1555 * Check an event against the set of supported architectural events.
1557 * Returns 1 if the event is architectural and unsupported on this
1558 * CPU. Returns 0 otherwise.
1562 iap_architectural_event_is_unsupported(enum pmc_event pe)
1564 enum core_arch_events ae;
1567 case PMC_EV_IAP_EVENT_3CH_00H:
1568 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1570 case PMC_EV_IAP_EVENT_C0H_00H:
1571 ae = CORE_AE_INSTRUCTION_RETIRED;
1573 case PMC_EV_IAP_EVENT_3CH_01H:
1574 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1576 case PMC_EV_IAP_EVENT_2EH_4FH:
1577 ae = CORE_AE_LLC_REFERENCE;
1579 case PMC_EV_IAP_EVENT_2EH_41H:
1580 ae = CORE_AE_LLC_MISSES;
1582 case PMC_EV_IAP_EVENT_C4H_00H:
1583 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1585 case PMC_EV_IAP_EVENT_C5H_00H:
1586 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1589 default: /* Non architectural event. */
1593 return ((core_architectural_events & (1 << ae)) == 0);
1597 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1603 * Events valid only on counter 0, 1.
1605 case PMC_EV_IAP_EVENT_40H_01H:
1606 case PMC_EV_IAP_EVENT_40H_02H:
1607 case PMC_EV_IAP_EVENT_40H_04H:
1608 case PMC_EV_IAP_EVENT_40H_08H:
1609 case PMC_EV_IAP_EVENT_40H_0FH:
1610 case PMC_EV_IAP_EVENT_41H_02H:
1611 case PMC_EV_IAP_EVENT_41H_04H:
1612 case PMC_EV_IAP_EVENT_41H_08H:
1613 case PMC_EV_IAP_EVENT_42H_01H:
1614 case PMC_EV_IAP_EVENT_42H_02H:
1615 case PMC_EV_IAP_EVENT_42H_04H:
1616 case PMC_EV_IAP_EVENT_42H_08H:
1617 case PMC_EV_IAP_EVENT_43H_01H:
1618 case PMC_EV_IAP_EVENT_43H_02H:
1619 case PMC_EV_IAP_EVENT_51H_01H:
1620 case PMC_EV_IAP_EVENT_51H_02H:
1621 case PMC_EV_IAP_EVENT_51H_04H:
1622 case PMC_EV_IAP_EVENT_51H_08H:
1623 case PMC_EV_IAP_EVENT_63H_01H:
1624 case PMC_EV_IAP_EVENT_63H_02H:
1629 mask = ~0; /* Any row index is ok. */
1632 return (mask & (1 << ri));
1636 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1642 * Events valid only on counter 0.
1644 case PMC_EV_IAP_EVENT_60H_01H:
1645 case PMC_EV_IAP_EVENT_60H_02H:
1646 case PMC_EV_IAP_EVENT_60H_04H:
1647 case PMC_EV_IAP_EVENT_60H_08H:
1648 case PMC_EV_IAP_EVENT_B3H_01H:
1649 case PMC_EV_IAP_EVENT_B3H_02H:
1650 case PMC_EV_IAP_EVENT_B3H_04H:
1655 * Events valid only on counter 0, 1.
1657 case PMC_EV_IAP_EVENT_4CH_01H:
1658 case PMC_EV_IAP_EVENT_4EH_01H:
1659 case PMC_EV_IAP_EVENT_4EH_02H:
1660 case PMC_EV_IAP_EVENT_4EH_04H:
1661 case PMC_EV_IAP_EVENT_51H_01H:
1662 case PMC_EV_IAP_EVENT_51H_02H:
1663 case PMC_EV_IAP_EVENT_51H_04H:
1664 case PMC_EV_IAP_EVENT_51H_08H:
1665 case PMC_EV_IAP_EVENT_63H_01H:
1666 case PMC_EV_IAP_EVENT_63H_02H:
1671 mask = ~0; /* Any row index is ok. */
1674 return (mask & (1 << ri));
1678 iap_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri)
1684 * Events valid only on counter 2.
1686 case PMC_EV_IAP_EVENT_48H_01H:
1690 mask = ~0; /* Any row index is ok. */
1693 return (mask & (1 << ri));
1697 iap_event_ok_on_counter(enum pmc_event pe, int ri)
1703 * Events valid only on counter 0.
1705 case PMC_EV_IAP_EVENT_10H_00H:
1706 case PMC_EV_IAP_EVENT_14H_00H:
1707 case PMC_EV_IAP_EVENT_18H_00H:
1708 case PMC_EV_IAP_EVENT_B3H_01H:
1709 case PMC_EV_IAP_EVENT_B3H_02H:
1710 case PMC_EV_IAP_EVENT_B3H_04H:
1711 case PMC_EV_IAP_EVENT_C1H_00H:
1712 case PMC_EV_IAP_EVENT_CBH_01H:
1713 case PMC_EV_IAP_EVENT_CBH_02H:
1718 * Events valid only on counter 1.
1720 case PMC_EV_IAP_EVENT_11H_00H:
1721 case PMC_EV_IAP_EVENT_12H_00H:
1722 case PMC_EV_IAP_EVENT_13H_00H:
1727 mask = ~0; /* Any row index is ok. */
1730 return (mask & (1 << ri));
1734 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1735 const struct pmc_op_pmcallocate *a)
1739 struct iap_event_descr *ie;
1740 uint32_t c, caps, config, cpuflag, evsel, mask;
1742 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1743 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1744 KASSERT(ri >= 0 && ri < core_iap_npmc,
1745 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1747 /* check requested capabilities */
1749 if ((IAP_PMC_CAPS & caps) != caps)
1754 if (iap_architectural_event_is_unsupported(ev))
1755 return (EOPNOTSUPP);
1758 * A small number of events are not supported in all the
1759 * processors based on a given microarchitecture.
1761 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) {
1762 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
1763 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E)
1767 switch (core_cputype) {
1768 case PMC_CPU_INTEL_COREI7:
1769 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1772 case PMC_CPU_INTEL_SANDYBRIDGE:
1773 if (iap_event_sandybridge_ok_on_counter(ev, ri) == 0)
1776 case PMC_CPU_INTEL_WESTMERE:
1777 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1781 if (iap_event_ok_on_counter(ev, ri) == 0)
1786 * Look for an event descriptor with matching CPU and event id
1790 switch (core_cputype) {
1792 case PMC_CPU_INTEL_ATOM:
1795 case PMC_CPU_INTEL_CORE:
1798 case PMC_CPU_INTEL_CORE2:
1799 cpuflag = IAP_F_CC2;
1801 case PMC_CPU_INTEL_CORE2EXTREME:
1802 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
1804 case PMC_CPU_INTEL_COREI7:
1807 case PMC_CPU_INTEL_SANDYBRIDGE:
1810 case PMC_CPU_INTEL_WESTMERE:
1815 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
1816 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
1819 if (n == niap_events)
1823 * A matching event descriptor has been found, so start
1824 * assembling the contents of the event select register.
1826 evsel = ie->iap_evcode;
1828 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
1831 * If the event uses a fixed umask value, reject any umask
1832 * bits set by the user.
1834 if (ie->iap_flags & IAP_F_FM) {
1836 if (IAP_UMASK(config) != 0)
1839 evsel |= (ie->iap_umask << 8);
1844 * Otherwise, the UMASK value needs to be taken from
1845 * the MD fields of the allocation request. Reject
1846 * requests that specify reserved bits.
1851 if (ie->iap_umask & IAP_M_CORE) {
1852 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
1858 if (ie->iap_umask & IAP_M_AGENT)
1859 mask |= IAP_F_AGENT;
1861 if (ie->iap_umask & IAP_M_PREFETCH) {
1863 if ((c = (config & IAP_F_PREFETCH)) ==
1864 IAP_PREFETCH_RESERVED)
1867 mask |= IAP_F_PREFETCH;
1870 if (ie->iap_umask & IAP_M_MESI)
1873 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
1874 mask |= IAP_F_SNOOPRESPONSE;
1876 if (ie->iap_umask & IAP_M_SNOOPTYPE)
1877 mask |= IAP_F_SNOOPTYPE;
1879 if (ie->iap_umask & IAP_M_TRANSITION)
1880 mask |= IAP_F_TRANSITION;
1883 * If bits outside of the allowed set of umask bits
1884 * are set, reject the request.
1889 evsel |= (config & mask);
1894 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier.
1896 if (core_cputype == PMC_CPU_INTEL_ATOM ||
1897 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE)
1898 evsel |= (config & IAP_ANY);
1899 else if (config & IAP_ANY)
1903 * Check offcore response configuration.
1905 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
1906 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
1907 ev != PMC_EV_IAP_EVENT_BBH_01H)
1909 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
1910 ev == PMC_EV_IAP_EVENT_BBH_01H)
1912 if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
1914 pm->pm_md.pm_iap.pm_iap_rsp =
1915 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK;
1918 if (caps & PMC_CAP_THRESHOLD)
1919 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
1920 if (caps & PMC_CAP_USER)
1922 if (caps & PMC_CAP_SYSTEM)
1924 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
1925 evsel |= (IAP_OS | IAP_USR);
1926 if (caps & PMC_CAP_EDGE)
1928 if (caps & PMC_CAP_INVERT)
1930 if (caps & PMC_CAP_INTERRUPT)
1933 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
1939 iap_config_pmc(int cpu, int ri, struct pmc *pm)
1941 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1942 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1944 KASSERT(ri >= 0 && ri < core_iap_npmc,
1945 ("[core,%d] illegal row-index %d", __LINE__, ri));
1947 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
1949 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
1952 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
1958 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
1962 char iap_name[PMC_NAME_MAX];
1964 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
1966 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
1967 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
1971 pi->pm_class = PMC_CLASS_IAP;
1973 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
1974 pi->pm_enabled = TRUE;
1975 *ppmc = phw->phw_pmc;
1977 pi->pm_enabled = FALSE;
1985 iap_get_config(int cpu, int ri, struct pmc **ppm)
1987 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
1993 iap_get_msr(int ri, uint32_t *msr)
1995 KASSERT(ri >= 0 && ri < core_iap_npmc,
1996 ("[iap,%d] ri %d out of range", __LINE__, ri));
2004 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
2009 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2010 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2011 KASSERT(ri >= 0 && ri < core_iap_npmc,
2012 ("[core,%d] illegal row-index %d", __LINE__, ri));
2014 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
2017 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
2021 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2022 *v = iap_perfctr_value_to_reload_count(tmp);
2024 *v = tmp & ((1ULL << core_iap_width) - 1);
2026 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
2033 iap_release_pmc(int cpu, int ri, struct pmc *pm)
2037 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
2040 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2041 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2042 KASSERT(ri >= 0 && ri < core_iap_npmc,
2043 ("[core,%d] illegal row-index %d", __LINE__, ri));
2045 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
2046 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
2052 iap_start_pmc(int cpu, int ri)
2056 struct core_cpu *cc;
2058 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2059 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
2060 KASSERT(ri >= 0 && ri < core_iap_npmc,
2061 ("[core,%d] illegal row-index %d", __LINE__, ri));
2063 cc = core_pcpu[cpu];
2064 pm = cc->pc_corepmcs[ri].phw_pmc;
2067 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
2068 __LINE__, cpu, ri));
2070 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
2072 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
2074 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
2075 cpu, ri, IAP_EVSEL0 + ri, evsel);
2077 /* Event specific configuration. */
2078 switch (pm->pm_event) {
2079 case PMC_EV_IAP_EVENT_B7H_01H:
2080 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
2082 case PMC_EV_IAP_EVENT_BBH_01H:
2083 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
2089 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
2091 if (core_cputype == PMC_CPU_INTEL_CORE)
2096 cc->pc_globalctrl |= (1ULL << ri);
2097 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2098 } while (cc->pc_resync != 0);
2104 iap_stop_pmc(int cpu, int ri)
2107 struct core_cpu *cc;
2110 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2111 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2112 KASSERT(ri >= 0 && ri < core_iap_npmc,
2113 ("[core,%d] illegal row index %d", __LINE__, ri));
2115 cc = core_pcpu[cpu];
2116 pm = cc->pc_corepmcs[ri].phw_pmc;
2119 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2122 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
2124 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2125 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
2127 if (core_cputype == PMC_CPU_INTEL_CORE)
2133 cc->pc_globalctrl &= ~(1ULL << ri);
2134 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2135 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2136 } while (cc->pc_resync != 0);
2142 iap_write_pmc(int cpu, int ri, pmc_value_t v)
2145 struct core_cpu *cc;
2147 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
2148 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
2149 KASSERT(ri >= 0 && ri < core_iap_npmc,
2150 ("[core,%d] illegal row index %d", __LINE__, ri));
2152 cc = core_pcpu[cpu];
2153 pm = cc->pc_corepmcs[ri].phw_pmc;
2156 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
2159 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
2162 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2163 v = iap_reload_count_to_perfctr_value(v);
2166 * Write the new value to the counter. The counter will be in
2167 * a stopped state when the pcd_write() entry point is called.
2170 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
2177 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
2180 struct pmc_classdep *pcd;
2182 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
2184 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
2186 /* Remember the set of architectural events supported. */
2187 core_architectural_events = ~flags;
2189 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
2191 pcd->pcd_caps = IAP_PMC_CAPS;
2192 pcd->pcd_class = PMC_CLASS_IAP;
2193 pcd->pcd_num = npmc;
2194 pcd->pcd_ri = md->pmd_npmc;
2195 pcd->pcd_width = pmcwidth;
2197 pcd->pcd_allocate_pmc = iap_allocate_pmc;
2198 pcd->pcd_config_pmc = iap_config_pmc;
2199 pcd->pcd_describe = iap_describe;
2200 pcd->pcd_get_config = iap_get_config;
2201 pcd->pcd_get_msr = iap_get_msr;
2202 pcd->pcd_pcpu_fini = core_pcpu_fini;
2203 pcd->pcd_pcpu_init = core_pcpu_init;
2204 pcd->pcd_read_pmc = iap_read_pmc;
2205 pcd->pcd_release_pmc = iap_release_pmc;
2206 pcd->pcd_start_pmc = iap_start_pmc;
2207 pcd->pcd_stop_pmc = iap_stop_pmc;
2208 pcd->pcd_write_pmc = iap_write_pmc;
2210 md->pmd_npmc += npmc;
2214 core_intr(int cpu, struct trapframe *tf)
2218 struct core_cpu *cc;
2219 int error, found_interrupt, ri;
2222 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2223 TRAPF_USERMODE(tf));
2225 found_interrupt = 0;
2226 cc = core_pcpu[cpu];
2228 for (ri = 0; ri < core_iap_npmc; ri++) {
2230 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2231 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2234 if (!iap_pmc_has_overflowed(ri))
2237 found_interrupt = 1;
2239 if (pm->pm_state != PMC_STATE_RUNNING)
2242 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2243 TRAPF_USERMODE(tf));
2245 v = pm->pm_sc.pm_reloadcount;
2246 v = iaf_reload_count_to_perfctr_value(v);
2249 * Stop the counter, reload it but only restart it if
2250 * the PMC is not stalled.
2252 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2253 wrmsr(IAP_EVSEL0 + ri, msr);
2254 wrmsr(IAP_PMC0 + ri, v);
2259 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2263 if (found_interrupt)
2264 lapic_reenable_pmc();
2266 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2267 &pmc_stats.pm_intr_ignored, 1);
2269 return (found_interrupt);
2273 core2_intr(int cpu, struct trapframe *tf)
2275 int error, found_interrupt, n;
2276 uint64_t flag, intrstatus, intrenable, msr;
2278 struct core_cpu *cc;
2281 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2282 TRAPF_USERMODE(tf));
2285 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2286 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2287 * the current set of interrupting PMCs and process these
2288 * after stopping them.
2290 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2291 intrenable = intrstatus & core_pmcmask;
2293 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2294 (uintmax_t) intrstatus);
2296 found_interrupt = 0;
2297 cc = core_pcpu[cpu];
2299 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2301 cc->pc_globalctrl &= ~intrenable;
2302 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2305 * Stop PMCs and clear overflow status bits.
2307 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2308 wrmsr(IA_GLOBAL_CTRL, msr);
2309 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2310 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2311 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2314 * Look for interrupts from fixed function PMCs.
2316 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2319 if ((intrstatus & flag) == 0)
2322 found_interrupt = 1;
2324 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2325 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2326 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2329 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2330 TRAPF_USERMODE(tf));
2332 intrenable &= ~flag;
2334 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2336 /* Reload sampling count. */
2337 wrmsr(IAF_CTR0 + n, v);
2339 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error,
2340 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2344 * Process interrupts from the programmable counters.
2346 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2347 if ((intrstatus & flag) == 0)
2350 found_interrupt = 1;
2352 pm = cc->pc_corepmcs[n].phw_pmc;
2353 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2354 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2357 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
2358 TRAPF_USERMODE(tf));
2360 intrenable &= ~flag;
2362 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2364 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2367 /* Reload sampling count. */
2368 wrmsr(IAP_PMC0 + n, v);
2372 * Reenable all non-stalled PMCs.
2374 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2375 (uintmax_t) intrenable);
2377 cc->pc_globalctrl |= intrenable;
2379 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2381 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2382 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2383 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2384 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2385 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2387 if (found_interrupt)
2388 lapic_reenable_pmc();
2390 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2391 &pmc_stats.pm_intr_ignored, 1);
2393 return (found_interrupt);
2397 pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2399 int cpuid[CORE_CPUID_REQUEST_SIZE];
2400 int ipa_version, flags, nflags;
2402 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2404 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2406 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2407 md->pmd_cputype, maxcpu, ipa_version);
2409 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */
2410 return (EPROGMISMATCH);
2412 core_cputype = md->pmd_cputype;
2417 * Initialize programmable counters.
2419 KASSERT(ipa_version >= 1,
2420 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2422 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2423 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2425 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2427 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2428 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2430 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2433 * Initialize fixed function counters, if present.
2435 if (core_cputype != PMC_CPU_INTEL_CORE) {
2436 KASSERT(ipa_version >= 2,
2437 ("[core,%d] ipa_version %d too small", __LINE__,
2440 core_iaf_ri = core_iap_npmc;
2441 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2442 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2444 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2445 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2448 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2451 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2455 * Choose the appropriate interrupt handler.
2457 if (ipa_version == 1)
2458 md->pmd_intr = core_intr;
2460 md->pmd_intr = core2_intr;
2462 md->pmd_pcpu_fini = NULL;
2463 md->pmd_pcpu_init = NULL;
2469 pmc_core_finalize(struct pmc_mdep *md)
2471 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2473 free(core_pcpu, M_PMC);