2 * Copyright (c) 2005, Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* Machine dependent interfaces */
31 #ifndef _DEV_HWPMC_PIV_H_
32 #define _DEV_HWPMC_PIV_H_ 1
38 #define P4_INVALID_PMC_INDEX -1
39 #define P4_MAX_ESCR_PER_EVENT 2
40 #define P4_MAX_PMC_PER_ESCR 3
42 #define P4_CCCR_OVF (1 << 31)
43 #define P4_CCCR_CASCADE (1 << 30)
44 #define P4_CCCR_OVF_PMI_T1 (1 << 27)
45 #define P4_CCCR_OVF_PMI_T0 (1 << 26)
46 #define P4_CCCR_FORCE_OVF (1 << 25)
47 #define P4_CCCR_EDGE (1 << 24)
48 #define P4_CCCR_THRESHOLD_SHIFT 20
49 #define P4_CCCR_THRESHOLD_MASK 0x00F00000
50 #define P4_CCCR_TO_THRESHOLD(C) (((C) << P4_CCCR_THRESHOLD_SHIFT) & \
51 P4_CCCR_THRESHOLD_MASK)
52 #define P4_CCCR_COMPLEMENT (1 << 19)
53 #define P4_CCCR_COMPARE (1 << 18)
54 #define P4_CCCR_ACTIVE_THREAD_SHIFT 16
55 #define P4_CCCR_ACTIVE_THREAD_MASK 0x00030000
56 #define P4_CCCR_TO_ACTIVE_THREAD(T) (((T) << P4_CCCR_ACTIVE_THREAD_SHIFT) & \
57 P4_CCCR_ACTIVE_THREAD_MASK)
58 #define P4_CCCR_ESCR_SELECT_SHIFT 13
59 #define P4_CCCR_ESCR_SELECT_MASK 0x0000E000
60 #define P4_CCCR_TO_ESCR_SELECT(E) (((E) << P4_CCCR_ESCR_SELECT_SHIFT) & \
61 P4_CCCR_ESCR_SELECT_MASK)
62 #define P4_CCCR_ENABLE (1 << 12)
63 #define P4_CCCR_VALID_BITS (P4_CCCR_OVF | P4_CCCR_CASCADE | \
64 P4_CCCR_OVF_PMI_T1 | P4_CCCR_OVF_PMI_T0 | P4_CCCR_FORCE_OVF | \
65 P4_CCCR_EDGE | P4_CCCR_THRESHOLD_MASK | P4_CCCR_COMPLEMENT | \
66 P4_CCCR_COMPARE | P4_CCCR_ESCR_SELECT_MASK | P4_CCCR_ENABLE)
68 #define P4_ESCR_EVENT_SELECT_SHIFT 25
69 #define P4_ESCR_EVENT_SELECT_MASK 0x7E000000
70 #define P4_ESCR_TO_EVENT_SELECT(E) (((E) << P4_ESCR_EVENT_SELECT_SHIFT) & \
71 P4_ESCR_EVENT_SELECT_MASK)
72 #define P4_ESCR_EVENT_MASK_SHIFT 9
73 #define P4_ESCR_EVENT_MASK_MASK 0x01FFFE00
74 #define P4_ESCR_TO_EVENT_MASK(M) (((M) << P4_ESCR_EVENT_MASK_SHIFT) & \
75 P4_ESCR_EVENT_MASK_MASK)
76 #define P4_ESCR_TAG_VALUE_SHIFT 5
77 #define P4_ESCR_TAG_VALUE_MASK 0x000001E0
78 #define P4_ESCR_TO_TAG_VALUE(T) (((T) << P4_ESCR_TAG_VALUE_SHIFT) & \
79 P4_ESCR_TAG_VALUE_MASK)
80 #define P4_ESCR_TAG_ENABLE 0x00000010
81 #define P4_ESCR_T0_OS 0x00000008
82 #define P4_ESCR_T0_USR 0x00000004
83 #define P4_ESCR_T1_OS 0x00000002
84 #define P4_ESCR_T1_USR 0x00000001
85 #define P4_ESCR_OS P4_ESCR_T0_OS
86 #define P4_ESCR_USR P4_ESCR_T0_USR
87 #define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \
88 P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \
89 P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \
92 #define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */
93 #define P4_PERFCTR_OVERFLOWED(PMC) ((rdpmc(PMC) & (1LL << 39)) == 0)
95 #define P4_CCCR_MSR_FIRST 0x360 /* MSR_BPU_CCCR0 */
96 #define P4_PERFCTR_MSR_FIRST 0x300 /* MSR_BPU_COUNTER0 */
98 #define P4_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (1 - (V))
99 #define P4_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (1 - (P))
101 struct pmc_md_p4_op_pmcallocate {
102 uint32_t pm_p4_cccrconfig;
103 uint32_t pm_p4_escrconfig;
108 /* MD extension for 'struct pmc' */
109 struct pmc_md_p4_pmc {
110 uint32_t pm_p4_cccrvalue;
111 uint32_t pm_p4_escrvalue;
113 uint32_t pm_p4_escrmsr;
121 int pmc_p4_initialize(struct pmc_mdep *_md, int _ncpus);
122 void pmc_p4_finalize(struct pmc_mdep *md);
125 #endif /* _DEV_HWPMC_PIV_H_ */