2 * Copyright (c) 2010 Fabien Thomas
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/apicvar.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/specialreg.h>
46 #define UCF_PMC_CAPS \
47 (PMC_CAP_READ | PMC_CAP_WRITE)
49 #define UCP_PMC_CAPS \
50 (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
51 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
53 static enum pmc_cputype uncore_cputype;
56 volatile uint32_t pc_resync;
57 volatile uint32_t pc_ucfctrl; /* Fixed function control. */
58 volatile uint64_t pc_globalctrl; /* Global control register. */
59 struct pmc_hw pc_uncorepmcs[];
62 static struct uncore_cpu **uncore_pcpu;
64 static uint64_t uncore_pmcmask;
66 static int uncore_ucf_ri; /* relative index of fixed counters */
67 static int uncore_ucf_width;
68 static int uncore_ucf_npmc;
70 static int uncore_ucp_width;
71 static int uncore_ucp_npmc;
74 uncore_pcpu_noop(struct pmc_mdep *md, int cpu)
82 uncore_pcpu_init(struct pmc_mdep *md, int cpu)
85 struct uncore_cpu *cc;
87 int uncore_ri, n, npmc;
89 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
90 ("[ucf,%d] insane cpu number %d", __LINE__, cpu));
92 PMCDBG(MDP,INI,1,"uncore-init cpu=%d", cpu);
94 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
95 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
96 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
98 cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw),
99 M_PMC, M_WAITOK | M_ZERO);
101 uncore_pcpu[cpu] = cc;
104 KASSERT(pc != NULL && cc != NULL,
105 ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
107 for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) {
108 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
109 PMC_PHW_CPU_TO_STATE(cpu) |
110 PMC_PHW_INDEX_TO_STATE(n + uncore_ri);
112 pc->pc_hwpmcs[n + uncore_ri] = phw;
119 uncore_pcpu_fini(struct pmc_mdep *md, int cpu)
121 int uncore_ri, n, npmc;
123 struct uncore_cpu *cc;
125 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
126 ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu));
128 PMCDBG(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu);
130 if ((cc = uncore_pcpu[cpu]) == NULL)
133 uncore_pcpu[cpu] = NULL;
137 KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__,
140 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
141 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
143 for (n = 0; n < npmc; n++)
144 wrmsr(UCP_EVSEL0 + n, 0);
147 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
149 for (n = 0; n < npmc; n++)
150 pc->pc_hwpmcs[n + uncore_ri] = NULL;
158 * Fixed function counters.
162 ucf_perfctr_value_to_reload_count(pmc_value_t v)
164 v &= (1ULL << uncore_ucf_width) - 1;
165 return (1ULL << uncore_ucf_width) - v;
169 ucf_reload_count_to_perfctr_value(pmc_value_t rlc)
171 return (1ULL << uncore_ucf_width) - rlc;
175 ucf_allocate_pmc(int cpu, int ri, struct pmc *pm,
176 const struct pmc_op_pmcallocate *a)
179 uint32_t caps, flags;
181 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
182 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
184 PMCDBG(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
186 if (ri < 0 || ri > uncore_ucf_npmc)
191 if (a->pm_class != PMC_CLASS_UCF ||
192 (caps & UCF_PMC_CAPS) != caps)
196 if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST)
201 pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4));
203 PMCDBG(MDP,ALL,2, "ucf-allocate config=0x%jx",
204 (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl);
210 ucf_config_pmc(int cpu, int ri, struct pmc *pm)
212 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
213 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
215 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
216 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
218 PMCDBG(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
220 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
223 uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm;
229 ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
233 char ucf_name[PMC_NAME_MAX];
235 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri];
237 (void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri);
238 if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX,
242 pi->pm_class = PMC_CLASS_UCF;
244 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
245 pi->pm_enabled = TRUE;
246 *ppmc = phw->phw_pmc;
248 pi->pm_enabled = FALSE;
256 ucf_get_config(int cpu, int ri, struct pmc **ppm)
258 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
264 ucf_read_pmc(int cpu, int ri, pmc_value_t *v)
269 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
270 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
271 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
272 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
274 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
277 ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
278 ri, ri + uncore_ucf_ri));
280 tmp = rdmsr(UCF_CTR0 + ri);
282 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
283 *v = ucf_perfctr_value_to_reload_count(tmp);
287 PMCDBG(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v);
293 ucf_release_pmc(int cpu, int ri, struct pmc *pmc)
295 PMCDBG(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
297 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
298 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
299 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
300 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
302 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL,
303 ("[uncore,%d] PHW pmc non-NULL", __LINE__));
309 ucf_start_pmc(int cpu, int ri)
312 struct uncore_cpu *ucfc;
314 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
315 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
316 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
317 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
319 PMCDBG(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri);
321 ucfc = uncore_pcpu[cpu];
322 pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
324 ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl;
326 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
330 ucfc->pc_globalctrl |= (1ULL << (ri + UCF_OFFSET));
331 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
332 } while (ucfc->pc_resync != 0);
334 PMCDBG(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
335 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
336 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
342 ucf_stop_pmc(int cpu, int ri)
345 struct uncore_cpu *ucfc;
347 PMCDBG(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri);
349 ucfc = uncore_pcpu[cpu];
351 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
352 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
353 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
354 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
356 fc = (UCF_MASK << (ri * 4));
358 ucfc->pc_ucfctrl &= ~fc;
360 PMCDBG(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl);
361 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
365 ucfc->pc_globalctrl &= ~(1ULL << (ri + UCF_OFFSET));
366 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
367 } while (ucfc->pc_resync != 0);
369 PMCDBG(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
370 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
371 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
377 ucf_write_pmc(int cpu, int ri, pmc_value_t v)
379 struct uncore_cpu *cc;
382 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
383 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
384 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
385 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
387 cc = uncore_pcpu[cpu];
388 pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
391 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
393 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
394 v = ucf_reload_count_to_perfctr_value(v);
396 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */
397 wrmsr(UCF_CTR0 + ri, v);
398 wrmsr(UCF_CTRL, cc->pc_ucfctrl);
400 PMCDBG(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ",
401 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL));
408 ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
410 struct pmc_classdep *pcd;
412 KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__));
414 PMCDBG(MDP,INI,1, "%s", "ucf-initialize");
416 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF];
418 pcd->pcd_caps = UCF_PMC_CAPS;
419 pcd->pcd_class = PMC_CLASS_UCF;
421 pcd->pcd_ri = md->pmd_npmc;
422 pcd->pcd_width = pmcwidth;
424 pcd->pcd_allocate_pmc = ucf_allocate_pmc;
425 pcd->pcd_config_pmc = ucf_config_pmc;
426 pcd->pcd_describe = ucf_describe;
427 pcd->pcd_get_config = ucf_get_config;
428 pcd->pcd_get_msr = NULL;
429 pcd->pcd_pcpu_fini = uncore_pcpu_noop;
430 pcd->pcd_pcpu_init = uncore_pcpu_noop;
431 pcd->pcd_read_pmc = ucf_read_pmc;
432 pcd->pcd_release_pmc = ucf_release_pmc;
433 pcd->pcd_start_pmc = ucf_start_pmc;
434 pcd->pcd_stop_pmc = ucf_stop_pmc;
435 pcd->pcd_write_pmc = ucf_write_pmc;
437 md->pmd_npmc += npmc;
441 * Intel programmable PMCs.
445 * Event descriptor tables.
447 * For each event id, we track:
449 * 1. The CPUs that the event is valid for.
451 * 2. If the event uses a fixed UMASK, the value of the umask field.
452 * If the event doesn't use a fixed UMASK, a mask of legal bits
456 struct ucp_event_descr {
457 enum pmc_event ucp_ev;
458 unsigned char ucp_evcode;
459 unsigned char ucp_umask;
460 unsigned char ucp_flags;
463 #define UCP_F_I7 (1 << 0) /* CPU: Core i7 */
464 #define UCP_F_WM (1 << 1) /* CPU: Westmere */
465 #define UCP_F_FM (1 << 2) /* Fixed mask */
467 #define UCP_F_ALLCPUS \
468 (UCP_F_I7 | UCP_F_WM)
470 #define UCP_F_CMASK 0xFF000000
472 static struct ucp_event_descr ucp_events[] = {
474 #define UCPDESCR(N,EV,UM,FLAGS) { \
475 .ucp_ev = PMC_EV_UCP_EVENT_##N, \
476 .ucp_evcode = (EV), \
478 .ucp_flags = (FLAGS) \
481 UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
482 UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
483 UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
485 UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
486 UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
487 UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
489 UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
490 UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
491 UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
492 UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
493 UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
494 UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
495 UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
496 UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
498 UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
499 UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
500 UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
501 UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
502 UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
504 UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
505 UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
506 UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
508 UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
509 UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
510 UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
511 UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
512 UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
513 UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
515 UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
516 UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
517 UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
518 UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
519 UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
520 UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
521 UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
523 UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
524 UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
525 UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
526 UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
528 UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
529 UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
530 UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
531 UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
533 UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
534 UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
535 UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
536 UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
537 UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
539 UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
540 UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
541 UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
542 UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
543 UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
544 UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
546 UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM),
547 UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM),
548 UCPDESCR(0CH_04H_E, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
549 UCPDESCR(0CH_04H_F, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
550 UCPDESCR(0CH_04H_M, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
551 UCPDESCR(0CH_04H_S, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
552 UCPDESCR(0CH_08H_E, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
553 UCPDESCR(0CH_08H_F, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
554 UCPDESCR(0CH_08H_M, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
555 UCPDESCR(0CH_08H_S, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
557 UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
558 UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
559 UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
560 UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
561 UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
562 UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
564 UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
565 UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
566 UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
568 UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
569 UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
570 UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
572 UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
573 UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
574 UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
576 UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
577 UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
579 UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
580 UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
581 UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
583 UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
585 UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7),
586 UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7),
587 UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7),
588 UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7),
589 UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7),
590 UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7),
592 UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
593 UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
594 UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
595 UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
596 UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
597 UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
599 UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
600 UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
601 UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
602 UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
603 UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
604 UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
606 UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
607 UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
608 UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
609 UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM),
611 UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
612 UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
613 UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
614 UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
616 UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
617 UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
618 UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
619 UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
621 UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
622 UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
623 UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
624 UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
626 UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
627 UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
628 UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
629 UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
631 UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
632 UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
633 UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
634 UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
635 UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
636 UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
637 UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
638 UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
640 UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
641 UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
642 UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
643 UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
645 UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
646 UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
647 UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
648 UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
650 UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM),
651 UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM),
652 UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM),
653 UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM),
655 UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM),
656 UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM),
657 UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
658 UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM),
660 UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM),
661 UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM),
662 UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM),
663 UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM),
664 UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM),
665 UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM),
667 UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM),
668 UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM),
669 UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM),
671 UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
672 UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
673 UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
674 UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
675 UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
676 UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
677 UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
678 UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
680 UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
681 UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
682 UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
683 UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
684 UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
685 UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
686 UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
687 UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
689 UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM),
690 UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
691 UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM),
692 UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
694 UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
695 UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
697 UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
698 UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
699 UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
701 UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
702 UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
703 UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
705 UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
706 UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
707 UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
709 UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
710 UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
711 UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
712 UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
713 UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
714 UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
716 UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
717 UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
718 UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
719 UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
720 UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
721 UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
723 UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
724 UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
725 UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
727 UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
728 UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
729 UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
731 UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM),
732 UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM),
733 UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM),
734 UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM),
735 UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM),
736 UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM),
737 UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM),
738 UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM),
739 UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM),
740 UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM),
741 UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM),
742 UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM),
743 UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM),
744 UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM),
745 UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM),
746 UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM),
747 UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM),
748 UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM),
749 UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM),
750 UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM)
753 static const int nucp_events = sizeof(ucp_events) / sizeof(ucp_events[0]);
756 ucp_perfctr_value_to_reload_count(pmc_value_t v)
758 v &= (1ULL << uncore_ucp_width) - 1;
759 return (1ULL << uncore_ucp_width) - v;
763 ucp_reload_count_to_perfctr_value(pmc_value_t rlc)
765 return (1ULL << uncore_ucp_width) - rlc;
769 ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
770 const struct pmc_op_pmcallocate *a)
774 struct ucp_event_descr *ie;
775 uint32_t caps, config, cpuflag, evsel;
777 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
778 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
779 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
780 ("[uncore,%d] illegal row-index value %d", __LINE__, ri));
782 /* check requested capabilities */
784 if ((UCP_PMC_CAPS & caps) != caps)
790 * Look for an event descriptor with matching CPU and event id
794 switch (uncore_cputype) {
795 case PMC_CPU_INTEL_COREI7:
798 case PMC_CPU_INTEL_WESTMERE:
805 for (n = 0, ie = ucp_events; n < nucp_events; n++, ie++)
806 if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag)
809 if (n == nucp_events)
813 * A matching event descriptor has been found, so start
814 * assembling the contents of the event select register.
816 evsel = ie->ucp_evcode | UCP_EN;
818 config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK;
821 * If the event uses a fixed umask value, reject any umask
822 * bits set by the user.
824 if (ie->ucp_flags & UCP_F_FM) {
826 if (UCP_UMASK(config) != 0)
829 evsel |= (ie->ucp_umask << 8);
834 if (caps & PMC_CAP_THRESHOLD)
835 evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK);
836 if (caps & PMC_CAP_EDGE)
838 if (caps & PMC_CAP_INVERT)
841 pm->pm_md.pm_ucp.pm_ucp_evsel = evsel;
847 ucp_config_pmc(int cpu, int ri, struct pmc *pm)
849 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
850 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
852 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
853 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
855 PMCDBG(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
857 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
860 uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm;
866 ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
870 char ucp_name[PMC_NAME_MAX];
872 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri];
874 (void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri);
875 if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX,
879 pi->pm_class = PMC_CLASS_UCP;
881 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
882 pi->pm_enabled = TRUE;
883 *ppmc = phw->phw_pmc;
885 pi->pm_enabled = FALSE;
893 ucp_get_config(int cpu, int ri, struct pmc **ppm)
895 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
901 ucp_read_pmc(int cpu, int ri, pmc_value_t *v)
906 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
907 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
908 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
909 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
911 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
914 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
917 tmp = rdmsr(UCP_PMC0 + ri);
918 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
919 *v = ucp_perfctr_value_to_reload_count(tmp);
923 PMCDBG(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
930 ucp_release_pmc(int cpu, int ri, struct pmc *pm)
934 PMCDBG(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri,
937 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
938 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
939 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
940 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
942 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc
943 == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__));
949 ucp_start_pmc(int cpu, int ri)
953 struct uncore_cpu *cc;
955 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
956 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
957 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
958 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
960 cc = uncore_pcpu[cpu];
961 pm = cc->pc_uncorepmcs[ri].phw_pmc;
964 ("[uncore,%d] starting cpu%d,ri%d with no pmc configured",
967 PMCDBG(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri);
969 evsel = pm->pm_md.pm_ucp.pm_ucp_evsel;
971 PMCDBG(MDP,STA,2, "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
972 cpu, ri, UCP_EVSEL0 + ri, evsel);
974 /* Event specific configuration. */
975 switch (pm->pm_event) {
976 case PMC_EV_UCP_EVENT_0CH_04H_E:
977 case PMC_EV_UCP_EVENT_0CH_08H_E:
978 wrmsr(MSR_GQ_SNOOP_MESF,0x2);
980 case PMC_EV_UCP_EVENT_0CH_04H_F:
981 case PMC_EV_UCP_EVENT_0CH_08H_F:
982 wrmsr(MSR_GQ_SNOOP_MESF,0x8);
984 case PMC_EV_UCP_EVENT_0CH_04H_M:
985 case PMC_EV_UCP_EVENT_0CH_08H_M:
986 wrmsr(MSR_GQ_SNOOP_MESF,0x1);
988 case PMC_EV_UCP_EVENT_0CH_04H_S:
989 case PMC_EV_UCP_EVENT_0CH_08H_S:
990 wrmsr(MSR_GQ_SNOOP_MESF,0x4);
996 wrmsr(UCP_EVSEL0 + ri, evsel);
1000 cc->pc_globalctrl |= (1ULL << ri);
1001 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
1002 } while (cc->pc_resync != 0);
1008 ucp_stop_pmc(int cpu, int ri)
1011 struct uncore_cpu *cc;
1013 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1014 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
1015 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
1016 ("[uncore,%d] illegal row index %d", __LINE__, ri));
1018 cc = uncore_pcpu[cpu];
1019 pm = cc->pc_uncorepmcs[ri].phw_pmc;
1022 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1025 PMCDBG(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri);
1027 wrmsr(UCP_EVSEL0 + ri, 0); /* stop hw */
1031 cc->pc_globalctrl &= ~(1ULL << ri);
1032 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
1033 } while (cc->pc_resync != 0);
1039 ucp_write_pmc(int cpu, int ri, pmc_value_t v)
1042 struct uncore_cpu *cc;
1044 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1045 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
1046 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
1047 ("[uncore,%d] illegal row index %d", __LINE__, ri));
1049 cc = uncore_pcpu[cpu];
1050 pm = cc->pc_uncorepmcs[ri].phw_pmc;
1053 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1056 PMCDBG(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
1059 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1060 v = ucp_reload_count_to_perfctr_value(v);
1063 * Write the new value to the counter. The counter will be in
1064 * a stopped state when the pcd_write() entry point is called.
1067 wrmsr(UCP_PMC0 + ri, v);
1074 ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
1076 struct pmc_classdep *pcd;
1078 KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__));
1080 PMCDBG(MDP,INI,1, "%s", "ucp-initialize");
1082 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP];
1084 pcd->pcd_caps = UCP_PMC_CAPS;
1085 pcd->pcd_class = PMC_CLASS_UCP;
1086 pcd->pcd_num = npmc;
1087 pcd->pcd_ri = md->pmd_npmc;
1088 pcd->pcd_width = pmcwidth;
1090 pcd->pcd_allocate_pmc = ucp_allocate_pmc;
1091 pcd->pcd_config_pmc = ucp_config_pmc;
1092 pcd->pcd_describe = ucp_describe;
1093 pcd->pcd_get_config = ucp_get_config;
1094 pcd->pcd_get_msr = NULL;
1095 pcd->pcd_pcpu_fini = uncore_pcpu_fini;
1096 pcd->pcd_pcpu_init = uncore_pcpu_init;
1097 pcd->pcd_read_pmc = ucp_read_pmc;
1098 pcd->pcd_release_pmc = ucp_release_pmc;
1099 pcd->pcd_start_pmc = ucp_start_pmc;
1100 pcd->pcd_stop_pmc = ucp_stop_pmc;
1101 pcd->pcd_write_pmc = ucp_write_pmc;
1103 md->pmd_npmc += npmc;
1107 pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu)
1109 uncore_cputype = md->pmd_cputype;
1113 * Initialize programmable counters.
1116 uncore_ucp_npmc = 8;
1117 uncore_ucp_width = 48;
1119 uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1);
1121 ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width);
1124 * Initialize fixed function counters, if present.
1126 uncore_ucf_ri = uncore_ucp_npmc;
1127 uncore_ucf_npmc = 1;
1128 uncore_ucf_width = 48;
1130 ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width);
1131 uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << UCF_OFFSET;
1133 PMCDBG(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask,
1136 uncore_pcpu = malloc(sizeof(struct uncore_cpu **) * maxcpu, M_PMC,
1143 pmc_uncore_finalize(struct pmc_mdep *md)
1145 PMCDBG(MDP,INI,1, "%s", "uncore-finalize");
1147 free(uncore_pcpu, M_PMC);