2 * Copyright (c) 1999 FreeBSD Inc.
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30 * RSA Mode Driver Data Sheet
34 * Mode Select Register(Read/Write)
35 * bit4=interrupt type(1: level, 0: edge)
36 * bit3=Auto RTS-CTS Flow Control Enable
37 * bit2=External FIFO Enable
38 * bit1=Reserved(Default 0)Don't Change!!
39 * bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
42 * Interrupt Enable Register(Read/Write)
43 * bit4=Hardware Timer Interrupt Enable
44 * bit3=Character Time-Out Interrupt Enable
45 * bit2=Tx FIFO Empty Interrupt Enable
46 * bit1=Tx FIFO Half Full Interrupt Enable
47 * bit0=Rx FIFO Half Full Interrupt Enable
50 * Status Read Register(Read)
51 * bit7=Hardware Time Out Interrupt Status(1: True, 0: False)
52 * bit6=Character Time Out Interrupt Status
53 * bit5=Rx FIFO Full Flag(0: True, 1: False)
54 * bit4=Rx FIFO Half Full Flag
55 * bit3=Rx FIFO Empty Flag
56 * bit2=Tx FIFO Full Flag
57 * bit1=Tx FIFO Half Full Flag
58 * bit0=Tx FIFO Empty Flag
61 * FIFO Reset Register(Write)
65 * Timer Interval Value Set Register(Read/Write)
67 * Interval Value: n * 0.2ms
70 * Timer Control Register(Read/Write)
76 * Special Regisgter in RSA Mode
77 * UART Data Register(Base + 0x08)
78 * Data transfer between Extrnal FIFO
80 * UART MCR(Base + 0x0c)
81 * bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer
82 * bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer
84 * <<Intrrupt and Intrrupt Reset>>
85 * o Reciver Line Status(from UART16550)
88 * o Modem Status(from UART16550)
91 * o Rx FIFO Half Full(from Extrnal FIFO)
92 * Reset: Read Rx FIFO under Hall Full
94 * o Character Time Out(from Extrnal FIFO)
95 * Reset: Read Rx FIFO or SRR
97 * o Tx FIFO Empty(from Extrnal FIFO)
98 * Reset: Write Tx FIFO or Read SRR
100 * o Tx FIFO Half Full(from Extrnal FIFO)
101 * Reset: Write Tx FIFO until Hall Full or Read SRR
103 * o Hardware Timer(from Extrnal FIFO)
104 * Reset: Disable Timer in TCR
105 * Notes: If you want to use Timer for next intrrupt,
106 * you must enable Timer in TCR
109 * Auto RTS-CTS: Enable or Disable
110 * External FIFO: Enable
111 * Swap 8bytes: Disable
112 * Haredware Timer: Disable
113 * interrupt type: edge
122 /* I/O-DATA RSA Serise Exrension Register */
123 #define rsa_msr 0 /* Mode Status Register (R/W) */
124 #define rsa_ier 1 /* Interrupt Enable Register (R/W) */
125 #define rsa_srr 2 /* Status Read Register (R) */
126 #define rsa_frr 2 /* FIFO Reset Register (W) */
127 #define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */
128 #define rsa_tcr 4 /* Timer Control Register (W) */