2 * Copyright (c) 2004 Texas A&M University
5 * Developer: Wm. Daryl Hawkins
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel ICH Watchdog Timer (WDT) driver
32 * Originally developed by Wm. Daryl Hawkins of Texas A&M
33 * Heavily modified by <des@FreeBSD.org>
35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI
36 * device as it's actually an integrated function of the ICH LPC interface
37 * bridge. Detection is also awkward, because we can only infer the
38 * presence of the watchdog timer from the fact that the machine has an
39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
40 * ACPI table (although this driver does not support the ACPI detection
43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
44 * way of knowing if the WDT is permanently disabled (either by the BIOS
47 * The WDT is programmed through I/O registers in the ACPI I/O space.
48 * Intel swears it's always at offset 0x60, so we use that.
50 * For details about the ICH WDT, see Intel Application Note AP-725
51 * (document no. 292273-001). The WDT is also described in the individual
52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
53 * (document no. 252516-001) sections 9.10 and 9.11.
55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
61 #include <sys/param.h>
62 #include <sys/kernel.h>
63 #include <sys/module.h>
64 #include <sys/systm.h>
66 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <sys/watchdog.h>
71 #include <isa/isavar.h>
72 #include <dev/pci/pcivar.h>
74 #include <dev/ichwd/ichwd.h>
76 static struct ichwd_device ichwd_devices[] = {
77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 },
78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 },
79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 },
80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 },
81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 },
82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 },
83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 },
84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 },
85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 },
86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 },
87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 },
88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 },
89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 },
90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 },
91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 },
92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 },
93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 },
94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 },
95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 },
96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 },
97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 },
98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 },
99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 },
100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 },
101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 },
102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 },
103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 },
104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 },
105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 },
106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 },
107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 },
108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 },
109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 },
110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 },
114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 },
115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 },
116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 },
117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 },
118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 },
119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 },
120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 },
121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 },
122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 },
123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 },
124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 },
125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 },
126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 },
127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 },
128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 },
129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 },
130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 },
131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 },
132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 },
133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 },
134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 },
135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 },
136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 },
137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 },
138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 },
139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 },
140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 },
141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 },
142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 },
143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 },
144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 },
145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 },
146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 },
147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 },
148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 },
149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 },
150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 },
151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 },
154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 },
155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 },
156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 },
157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 },
158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 },
159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 },
160 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 },
161 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 },
162 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 },
163 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 },
164 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 },
165 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 },
166 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 },
167 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 },
168 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 },
169 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 },
170 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 },
171 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 },
172 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 },
173 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 },
174 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 },
175 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 },
176 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 },
177 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 },
178 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 },
179 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 },
180 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 },
181 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 },
182 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 },
183 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 },
184 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 },
185 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 },
186 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 },
187 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 },
188 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 },
189 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 },
190 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 },
191 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 },
192 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 },
193 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 },
194 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 },
195 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10 },
199 static devclass_t ichwd_devclass;
201 #define ichwd_read_tco_1(sc, off) \
202 bus_read_1((sc)->tco_res, (off))
203 #define ichwd_read_tco_2(sc, off) \
204 bus_read_2((sc)->tco_res, (off))
205 #define ichwd_read_tco_4(sc, off) \
206 bus_read_4((sc)->tco_res, (off))
207 #define ichwd_read_smi_4(sc, off) \
208 bus_read_4((sc)->smi_res, (off))
209 #define ichwd_read_gcs_4(sc, off) \
210 bus_read_4((sc)->gcs_res, (off))
212 #define ichwd_write_tco_1(sc, off, val) \
213 bus_write_1((sc)->tco_res, (off), (val))
214 #define ichwd_write_tco_2(sc, off, val) \
215 bus_write_2((sc)->tco_res, (off), (val))
216 #define ichwd_write_tco_4(sc, off, val) \
217 bus_write_4((sc)->tco_res, (off), (val))
218 #define ichwd_write_smi_4(sc, off, val) \
219 bus_write_4((sc)->smi_res, (off), (val))
220 #define ichwd_write_gcs_4(sc, off, val) \
221 bus_write_4((sc)->gcs_res, (off), (val))
223 #define ichwd_verbose_printf(dev, ...) \
226 device_printf(dev, __VA_ARGS__);\
230 * Disable the watchdog timeout SMI handler.
232 * Apparently, some BIOSes install handlers that reset or disable the
233 * watchdog timer instead of resetting the system, so we disable the SMI
234 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
238 ichwd_smi_disable(struct ichwd_softc *sc)
240 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
244 * Enable the watchdog timeout SMI handler. See above for details.
247 ichwd_smi_enable(struct ichwd_softc *sc)
249 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
253 * Check if the watchdog SMI triggering is enabled.
256 ichwd_smi_is_enabled(struct ichwd_softc *sc)
258 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0);
262 * Reset the watchdog status bits.
265 ichwd_sts_reset(struct ichwd_softc *sc)
268 * The watchdog status bits are set to 1 by the hardware to
269 * indicate various conditions. They can be cleared by software
270 * by writing a 1, not a 0.
272 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
274 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must
275 * be done in two separate operations.
277 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
278 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
282 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
283 * TCO1_CNT register. This is complicated by the need to preserve bit 9
284 * of that same register, and the requirement that all other bits must be
285 * written back as zero.
288 ichwd_tmr_enable(struct ichwd_softc *sc)
292 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
293 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
295 ichwd_verbose_printf(sc->device, "timer enabled\n");
299 * Disable the watchdog timer. See above for details.
302 ichwd_tmr_disable(struct ichwd_softc *sc)
306 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
307 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
309 ichwd_verbose_printf(sc->device, "timer disabled\n");
313 * Reload the watchdog timer: writing anything to any of the lower five
314 * bits of the TCO_RLD register reloads the timer from the last value
315 * written to TCO_TMR.
318 ichwd_tmr_reload(struct ichwd_softc *sc)
320 if (sc->ich_version <= 5)
321 ichwd_write_tco_1(sc, TCO_RLD, 1);
323 ichwd_write_tco_2(sc, TCO_RLD, 1);
325 ichwd_verbose_printf(sc->device, "timer reloaded\n");
329 * Set the initial timeout value. Note that this must always be followed
333 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
336 if (timeout < TCO_RLD_TMR_MIN)
337 timeout = TCO_RLD_TMR_MIN;
339 if (sc->ich_version <= 5) {
340 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
342 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
343 if (timeout > TCO_RLD1_TMR_MAX)
344 timeout = TCO_RLD1_TMR_MAX;
346 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
348 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
350 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
351 if (timeout > TCO_RLD2_TMR_MAX)
352 timeout = TCO_RLD2_TMR_MAX;
353 tmr_val16 |= timeout;
354 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
357 sc->timeout = timeout;
359 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
363 ichwd_clear_noreboot(struct ichwd_softc *sc)
368 /* try to clear the NO_REBOOT bit */
369 if (sc->ich_version <= 5) {
370 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
371 status &= ~ICH_GEN_STA_NO_REBOOT;
372 pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
373 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
374 if (status & ICH_GEN_STA_NO_REBOOT)
377 status = ichwd_read_gcs_4(sc, 0);
378 status &= ~ICH_GCS_NO_REBOOT;
379 ichwd_write_gcs_4(sc, 0, status);
380 status = ichwd_read_gcs_4(sc, 0);
381 if (status & ICH_GCS_NO_REBOOT)
386 device_printf(sc->device,
387 "ICH WDT present but disabled in BIOS or hardware\n");
393 * Watchdog event handler - called by the framework to enable or disable
394 * the watchdog or change the initial timeout value.
397 ichwd_event(void *arg, unsigned int cmd, int *error)
399 struct ichwd_softc *sc = arg;
400 unsigned int timeout;
402 /* convert from power-of-two-ns to WDT ticks */
404 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK;
407 ichwd_tmr_enable(sc);
408 if (timeout != sc->timeout)
409 ichwd_tmr_set(sc, timeout);
410 ichwd_tmr_reload(sc);
414 ichwd_tmr_disable(sc);
419 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
421 struct ichwd_device *id;
424 /* look for an ICH LPC interface bridge */
425 for (id = ichwd_devices; id->desc != NULL; ++id)
426 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL)
432 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
433 id->version, id->desc);
442 * Look for an ICH LPC interface bridge. If one is found, register an
443 * ichwd device. There can be only one.
446 ichwd_identify(driver_t *driver, device_t parent)
448 struct ichwd_device *id_p;
454 ich = ichwd_find_ich_lpc_bridge(&id_p);
458 /* good, add child to bus */
459 if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
460 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
465 device_set_desc_copy(dev, id_p->desc);
467 if (id_p->version >= 6) {
468 /* get RCBA (root complex base address) */
469 rcba = pci_read_config(ich, ICH_RCBA, 4);
470 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
471 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE);
473 ichwd_verbose_printf(dev,
474 "Can not set memory resource for RCBA\n");
479 ichwd_probe(device_t dev)
482 /* Do not claim some ISA PnP device by accident. */
483 if (isa_get_logicalid(dev) != 0)
489 ichwd_attach(device_t dev)
491 struct ichwd_softc *sc;
492 struct ichwd_device *id_p;
494 unsigned int pmbase = 0;
496 sc = device_get_softc(dev);
499 ich = ichwd_find_ich_lpc_bridge(&id_p);
501 device_printf(sc->device, "Can not find ICH device.\n");
505 sc->ich_version = id_p->version;
507 /* get ACPI base address */
508 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
510 device_printf(dev, "ICH PMBASE register is empty\n");
514 /* allocate I/O register space */
516 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
517 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
518 RF_ACTIVE | RF_SHAREABLE);
519 if (sc->smi_res == NULL) {
520 device_printf(dev, "unable to reserve SMI registers\n");
525 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
526 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
527 RF_ACTIVE | RF_SHAREABLE);
528 if (sc->tco_res == NULL) {
529 device_printf(dev, "unable to reserve TCO registers\n");
534 if (sc->ich_version >= 6) {
535 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
536 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
537 if (sc->gcs_res == NULL) {
538 device_printf(dev, "unable to reserve GCS registers\n");
543 if (ichwd_clear_noreboot(sc) != 0)
546 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n",
547 device_get_desc(dev), sc->ich_version);
550 * Determine if we are coming up after a watchdog-induced reset. Some
551 * BIOSes may clear this bit at bootup, preventing us from reporting
552 * this case on such systems. We clear this bit in ichwd_sts_reset().
554 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0)
556 "resuming after hardware watchdog timeout\n");
558 /* reset the watchdog status registers */
561 /* make sure the WDT starts out inactive */
562 ichwd_tmr_disable(sc);
564 /* register the watchdog event handler */
565 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0);
567 /* disable the SMI handler */
568 sc->smi_enabled = ichwd_smi_is_enabled(sc);
569 ichwd_smi_disable(sc);
573 sc = device_get_softc(dev);
574 if (sc->tco_res != NULL)
575 bus_release_resource(dev, SYS_RES_IOPORT,
576 sc->tco_rid, sc->tco_res);
577 if (sc->smi_res != NULL)
578 bus_release_resource(dev, SYS_RES_IOPORT,
579 sc->smi_rid, sc->smi_res);
580 if (sc->gcs_res != NULL)
581 bus_release_resource(ich, SYS_RES_MEMORY,
582 sc->gcs_rid, sc->gcs_res);
588 ichwd_detach(device_t dev)
590 struct ichwd_softc *sc;
593 sc = device_get_softc(dev);
595 /* halt the watchdog timer */
597 ichwd_tmr_disable(sc);
599 /* enable the SMI handler */
600 if (sc->smi_enabled != 0)
601 ichwd_smi_enable(sc);
603 /* deregister event handler */
604 if (sc->ev_tag != NULL)
605 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
608 /* reset the watchdog status registers */
611 /* deallocate I/O register space */
612 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
613 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
615 /* deallocate memory resource */
616 ich = ichwd_find_ich_lpc_bridge(NULL);
617 if (sc->gcs_res && ich)
618 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res);
623 static device_method_t ichwd_methods[] = {
624 DEVMETHOD(device_identify, ichwd_identify),
625 DEVMETHOD(device_probe, ichwd_probe),
626 DEVMETHOD(device_attach, ichwd_attach),
627 DEVMETHOD(device_detach, ichwd_detach),
628 DEVMETHOD(device_shutdown, ichwd_detach),
632 static driver_t ichwd_driver = {
635 sizeof(struct ichwd_softc),
638 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL);