2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * High-level driver for µPD7210 based GPIB cards.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/limits.h>
43 #include <sys/module.h>
47 #include <sys/mutex.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <isa/isavar.h>
54 #define UPD7210_HW_DRIVER
55 #define UPD7210_SW_DRIVER
56 #include <dev/ieee488/upd7210.h>
57 #include <dev/ieee488/tnt4882.h>
59 static MALLOC_DEFINE(M_GPIB, "GPIB", "GPIB");
61 /* upd7210 generic stuff */
64 upd7210_print_isr(u_int isr1, u_int isr2)
66 printf("isr1=0x%b isr2=0x%b",
67 isr1, "\20\10CPT\7APT\6DET\5ENDRX\4DEC\3ERR\2DO\1DI",
68 isr2, "\20\10INT\7SRQI\6LOK\5REM\4CO\3LOKC\2REMC\1ADSC");
72 upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg)
76 r = bus_read_1(u->reg_res[reg], u->reg_offset[reg]);
82 upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val)
85 bus_write_1(u->reg_res[reg], u->reg_offset[reg], val);
88 u->wreg[8 + (val >> 5)] = val & 0x1f;
92 upd7210intr(void *arg)
94 u_int isr_1, isr_2, isr_3;
99 isr_1 = upd7210_rd(u, ISR1);
100 isr_2 = upd7210_rd(u, ISR2);
102 isr_3 = bus_read_1(u->reg_res[0], isr3);
106 if (isr_1 != 0 || isr_2 != 0 || isr_3 != 0) {
107 if (u->busy == 0 || u->irq == NULL || !u->irq(u, isr_3)) {
109 printf("upd7210intr [%02x %02x %02x",
110 upd7210_rd(u, DIR), isr1, isr2);
111 printf(" %02x %02x %02x %02x %02x] ",
116 upd7210_rd(u, ADR1));
117 upd7210_print_isr(isr1, isr2);
122 * "special interrupt handling"
124 * In order to implement shared IRQs, the original
125 * PCIIa uses IO locations 0x2f0 + (IRQ#) as an output
126 * location. If an ISR for a particular card has
127 * detected this card triggered the IRQ, it must reset
128 * the card's IRQ by writing (anything) to that IO
131 * Some clones apparently don't implement this
132 * feature, but National Instrument cards do.
134 if (u->irq_clear_res != NULL)
135 bus_write_1(u->irq_clear_res, 0, 42);
137 mtx_unlock(&u->mutex);
141 upd7210_take_ctrl_async(struct upd7210 *u)
145 upd7210_wr(u, AUXMR, AUXMR_TCA);
147 if (!(upd7210_rd(u, ADSR) & ADSR_ATN))
149 for (i = 0; i < 20; i++) {
151 if (!(upd7210_rd(u, ADSR) & ADSR_ATN))
158 upd7210_goto_standby(struct upd7210 *u)
162 upd7210_wr(u, AUXMR, AUXMR_GTS);
164 if (upd7210_rd(u, ADSR) & ADSR_ATN)
166 for (i = 0; i < 20; i++) {
168 if (upd7210_rd(u, ADSR) & ADSR_ATN)
174 /* Unaddressed Listen Only mode */
177 gpib_l_irq(struct upd7210 *u, int isr_3)
183 /* TNT5004 or TNT4882 in FIFO mode */
186 i = bus_read_1(u->reg_res[0], fifob);
188 bus_write_1(u->reg_res[0], cnt0, -1);
189 bus_write_1(u->reg_res[0], cnt1, (-1) >> 8);
190 bus_write_1(u->reg_res[0], cnt2, (-1) >> 16);
191 bus_write_1(u->reg_res[0], cnt3, (-1) >> 24);
192 bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
194 } else if (u->rreg[ISR1] & 1) {
195 i = upd7210_rd(u, DIR);
200 u->buf[u->buf_wp++] = i;
201 u->buf_wp &= (u->bufsize - 1);
202 i = (u->buf_rp + u->bufsize - u->buf_wp) & (u->bufsize - 1);
205 bus_write_1(u->reg_res[0], imr3, 0x00);
207 upd7210_wr(u, IMR1, 0);
216 gpib_l_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
224 mtx_unlock(&u->mutex);
229 mtx_unlock(&u->mutex);
231 u->buf = malloc(PAGE_SIZE, M_GPIB, M_WAITOK);
232 u->bufsize = PAGE_SIZE;
236 upd7210_wr(u, AUXMR, AUXMR_CRST); /* chip reset */
238 upd7210_wr(u, AUXMR, C_ICR | 8); /* 8 MHz clock */
240 upd7210_wr(u, ADR, 0x60); /* ADR0: disable listener and talker 0 */
241 upd7210_wr(u, ADR, 0xe0); /* ADR1: disable listener and talker 1 */
242 upd7210_wr(u, ADMR, 0x70); /* listen-only (lon) */
243 upd7210_wr(u, AUXMR, AUXMR_PON); /* immediate execute power-on (pon) */
245 /* TNT5004 or TNT4882 in FIFO mode */
246 bus_write_1(u->reg_res[0], cmdr, 0x10); /* reset FIFO */
247 bus_write_1(u->reg_res[0], cfg, 0x20); /* xfer IN, 8-bit FIFO */
248 bus_write_1(u->reg_res[0], cnt0, -1);
249 bus_write_1(u->reg_res[0], cnt1, (-1) >> 8);
250 bus_write_1(u->reg_res[0], cnt2, (-1) >> 16);
251 bus_write_1(u->reg_res[0], cnt3, (-1) >> 24);
252 bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
253 bus_write_1(u->reg_res[0], imr3, 0x04); /* NEF IE */
255 /* µPD7210/NAT7210, or TNT4882 in non-FIFO mode */
256 upd7210_wr(u, IMR1, 0x01); /* data in interrupt enable */
262 gpib_l_close(struct cdev *dev, int oflags, int devtype, struct thread *td)
271 /* TNT5004 or TNT4882 in FIFO mode */
272 bus_write_1(u->reg_res[0], cmdr, 0x22); /* soft RESET */
273 bus_write_1(u->reg_res[0], imr3, 0x00);
275 upd7210_wr(u, AUXMR, AUXMR_CRST);
277 upd7210_wr(u, IMR1, 0x00);
278 upd7210_wr(u, IMR2, 0x00);
279 free(u->buf, M_GPIB);
281 mtx_unlock(&u->mutex);
286 gpib_l_read(struct cdev *dev, struct uio *uio, int ioflag)
296 while (u->buf_wp == u->buf_rp) {
297 error = msleep(u->buf, &u->mutex, PZERO | PCATCH,
299 if (error && error != EWOULDBLOCK) {
300 mtx_unlock(&u->mutex);
304 while (uio->uio_resid > 0 && u->buf_wp != u->buf_rp) {
305 if (u->buf_wp < u->buf_rp)
306 z = u->bufsize - u->buf_rp;
308 z = u->buf_wp - u->buf_rp;
309 if (z > uio->uio_resid)
311 mtx_unlock(&u->mutex);
312 error = uiomove(u->buf + u->buf_rp, z, uio);
317 u->buf_rp &= (u->bufsize - 1);
320 bus_write_1(u->reg_res[0], imr3, 0x04); /* NFF IE */
322 if (u->wreg[IMR1] == 0)
323 upd7210_wr(u, IMR1, 0x01);
325 mtx_unlock(&u->mutex);
329 static struct cdevsw gpib_l_cdevsw = {
330 .d_version = D_VERSION,
332 .d_open = gpib_l_open,
333 .d_close = gpib_l_close,
334 .d_read = gpib_l_read,
339 static struct unrhdr *units;
342 upd7210attach(struct upd7210 *u)
347 units = new_unrhdr(0, INT_MAX, NULL);
348 u->unit = alloc_unr(units);
349 mtx_init(&u->mutex, "gpib", NULL, MTX_DEF);
350 u->cdev = make_dev(&gpib_l_cdevsw, u->unit,
351 UID_ROOT, GID_WHEEL, 0444,
353 u->cdev->si_drv1 = u;
355 dev = make_dev(&gpib_ib_cdevsw, u->unit,
356 UID_ROOT, GID_WHEEL, 0444,
357 "gpib%uib", u->unit);
359 dev_depends(u->cdev, dev);
363 upd7210detach(struct upd7210 *u)
366 destroy_dev(u->cdev);
367 mtx_destroy(&u->mutex);
368 free_unr(units, u->unit);