sys/dev/isp/isp_pci.c

   1 /*-
   2  * Copyright (c) 1997-2008 by Matthew Jacob
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice immediately at the beginning of the file, without modification,
  10  *    this list of conditions, and the following disclaimer.
  11  * 2. The name of the author may not be used to endorse or promote products
  12  *    derived from this software without specific prior written permission.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  18  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26 /*
  27  * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
  28  * FreeBSD Version.
  29  */
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/kernel.h>
  36 #include <sys/module.h>
  37 #include <sys/linker.h>
  38 #include <sys/firmware.h>
  39 #include <sys/bus.h>
  40 #include <sys/stdint.h>
  41 #include <dev/pci/pcireg.h>
  42 #include <dev/pci/pcivar.h>
  43 #include <machine/bus.h>
  44 #include <machine/resource.h>
  45 #include <sys/rman.h>
  46 #include <sys/malloc.h>
  47 #include <sys/uio.h>
  48
  49 #ifdef __sparc64__
  50 #include <dev/ofw/openfirm.h>
  51 #include <machine/ofw_machdep.h>
  52 #endif
  53
  54 #include <dev/isp/isp_freebsd.h>
  55
  56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int);
  57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t);
  58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
  59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
  60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
  61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
  62 static uint32_t isp_pci_rd_reg_2600(ispsoftc_t *, int);
  63 static void isp_pci_wr_reg_2600(ispsoftc_t *, int, uint32_t);
  64 static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
  65 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
  66 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
  67 static int isp_pci_mbxdma(ispsoftc_t *);
  68 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *);
  69
  70
  71 static void isp_pci_reset0(ispsoftc_t *);
  72 static void isp_pci_reset1(ispsoftc_t *);
  73 static void isp_pci_dumpregs(ispsoftc_t *, const char *);
  74
  75 static struct ispmdvec mdvec = {
  76         isp_pci_rd_isr,
  77         isp_pci_rd_reg,
  78         isp_pci_wr_reg,
  79         isp_pci_mbxdma,
  80         isp_pci_dmasetup,
  81         isp_common_dmateardown,
  82         isp_pci_reset0,
  83         isp_pci_reset1,
  84         isp_pci_dumpregs,
  85         NULL,
  86         BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
  87 };
  88
  89 static struct ispmdvec mdvec_1080 = {
  90         isp_pci_rd_isr,
  91         isp_pci_rd_reg_1080,
  92         isp_pci_wr_reg_1080,
  93         isp_pci_mbxdma,
  94         isp_pci_dmasetup,
  95         isp_common_dmateardown,
  96         isp_pci_reset0,
  97         isp_pci_reset1,
  98         isp_pci_dumpregs,
  99         NULL,
 100         BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
 101 };
 102
 103 static struct ispmdvec mdvec_12160 = {
 104         isp_pci_rd_isr,
 105         isp_pci_rd_reg_1080,
 106         isp_pci_wr_reg_1080,
 107         isp_pci_mbxdma,
 108         isp_pci_dmasetup,
 109         isp_common_dmateardown,
 110         isp_pci_reset0,
 111         isp_pci_reset1,
 112         isp_pci_dumpregs,
 113         NULL,
 114         BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
 115 };
 116
 117 static struct ispmdvec mdvec_2100 = {
 118         isp_pci_rd_isr,
 119         isp_pci_rd_reg,
 120         isp_pci_wr_reg,
 121         isp_pci_mbxdma,
 122         isp_pci_dmasetup,
 123         isp_common_dmateardown,
 124         isp_pci_reset0,
 125         isp_pci_reset1,
 126         isp_pci_dumpregs
 127 };
 128
 129 static struct ispmdvec mdvec_2200 = {
 130         isp_pci_rd_isr,
 131         isp_pci_rd_reg,
 132         isp_pci_wr_reg,
 133         isp_pci_mbxdma,
 134         isp_pci_dmasetup,
 135         isp_common_dmateardown,
 136         isp_pci_reset0,
 137         isp_pci_reset1,
 138         isp_pci_dumpregs
 139 };
 140
 141 static struct ispmdvec mdvec_2300 = {
 142         isp_pci_rd_isr_2300,
 143         isp_pci_rd_reg,
 144         isp_pci_wr_reg,
 145         isp_pci_mbxdma,
 146         isp_pci_dmasetup,
 147         isp_common_dmateardown,
 148         isp_pci_reset0,
 149         isp_pci_reset1,
 150         isp_pci_dumpregs
 151 };
 152
 153 static struct ispmdvec mdvec_2400 = {
 154         isp_pci_rd_isr_2400,
 155         isp_pci_rd_reg_2400,
 156         isp_pci_wr_reg_2400,
 157         isp_pci_mbxdma,
 158         isp_pci_dmasetup,
 159         isp_common_dmateardown,
 160         isp_pci_reset0,
 161         isp_pci_reset1,
 162         NULL
 163 };
 164
 165 static struct ispmdvec mdvec_2500 = {
 166         isp_pci_rd_isr_2400,
 167         isp_pci_rd_reg_2400,
 168         isp_pci_wr_reg_2400,
 169         isp_pci_mbxdma,
 170         isp_pci_dmasetup,
 171         isp_common_dmateardown,
 172         isp_pci_reset0,
 173         isp_pci_reset1,
 174         NULL
 175 };
 176
 177 static struct ispmdvec mdvec_2600 = {
 178         isp_pci_rd_isr_2400,
 179         isp_pci_rd_reg_2600,
 180         isp_pci_wr_reg_2600,
 181         isp_pci_mbxdma,
 182         isp_pci_dmasetup,
 183         isp_common_dmateardown,
 184         isp_pci_reset0,
 185         isp_pci_reset1,
 186         NULL
 187 };
 188
 189 #ifndef PCIM_CMD_INVEN
 190 #define PCIM_CMD_INVEN                  0x10
 191 #endif
 192 #ifndef PCIM_CMD_BUSMASTEREN
 193 #define PCIM_CMD_BUSMASTEREN            0x0004
 194 #endif
 195 #ifndef PCIM_CMD_PERRESPEN
 196 #define PCIM_CMD_PERRESPEN              0x0040
 197 #endif
 198 #ifndef PCIM_CMD_SEREN
 199 #define PCIM_CMD_SEREN                  0x0100
 200 #endif
 201 #ifndef PCIM_CMD_INTX_DISABLE
 202 #define PCIM_CMD_INTX_DISABLE           0x0400
 203 #endif
 204
 205 #ifndef PCIR_COMMAND
 206 #define PCIR_COMMAND                    0x04
 207 #endif
 208
 209 #ifndef PCIR_CACHELNSZ
 210 #define PCIR_CACHELNSZ                  0x0c
 211 #endif
 212
 213 #ifndef PCIR_LATTIMER
 214 #define PCIR_LATTIMER                   0x0d
 215 #endif
 216
 217 #ifndef PCIR_ROMADDR
 218 #define PCIR_ROMADDR                    0x30
 219 #endif
 220
 221 #ifndef PCI_VENDOR_QLOGIC
 222 #define PCI_VENDOR_QLOGIC               0x1077
 223 #endif
 224
 225 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
 226 #define PCI_PRODUCT_QLOGIC_ISP1020      0x1020
 227 #endif
 228
 229 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
 230 #define PCI_PRODUCT_QLOGIC_ISP1080      0x1080
 231 #endif
 232
 233 #ifndef PCI_PRODUCT_QLOGIC_ISP10160
 234 #define PCI_PRODUCT_QLOGIC_ISP10160     0x1016
 235 #endif
 236
 237 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
 238 #define PCI_PRODUCT_QLOGIC_ISP12160     0x1216
 239 #endif
 240
 241 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
 242 #define PCI_PRODUCT_QLOGIC_ISP1240      0x1240
 243 #endif
 244
 245 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
 246 #define PCI_PRODUCT_QLOGIC_ISP1280      0x1280
 247 #endif
 248
 249 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
 250 #define PCI_PRODUCT_QLOGIC_ISP2100      0x2100
 251 #endif
 252
 253 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
 254 #define PCI_PRODUCT_QLOGIC_ISP2200      0x2200
 255 #endif
 256
 257 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
 258 #define PCI_PRODUCT_QLOGIC_ISP2300      0x2300
 259 #endif
 260
 261 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
 262 #define PCI_PRODUCT_QLOGIC_ISP2312      0x2312
 263 #endif
 264
 265 #ifndef PCI_PRODUCT_QLOGIC_ISP2322
 266 #define PCI_PRODUCT_QLOGIC_ISP2322      0x2322
 267 #endif
 268
 269 #ifndef PCI_PRODUCT_QLOGIC_ISP2422
 270 #define PCI_PRODUCT_QLOGIC_ISP2422      0x2422
 271 #endif
 272
 273 #ifndef PCI_PRODUCT_QLOGIC_ISP2432
 274 #define PCI_PRODUCT_QLOGIC_ISP2432      0x2432
 275 #endif
 276
 277 #ifndef PCI_PRODUCT_QLOGIC_ISP2532
 278 #define PCI_PRODUCT_QLOGIC_ISP2532      0x2532
 279 #endif
 280
 281 #ifndef PCI_PRODUCT_QLOGIC_ISP6312
 282 #define PCI_PRODUCT_QLOGIC_ISP6312      0x6312
 283 #endif
 284
 285 #ifndef PCI_PRODUCT_QLOGIC_ISP6322
 286 #define PCI_PRODUCT_QLOGIC_ISP6322      0x6322
 287 #endif
 288
 289 #ifndef        PCI_PRODUCT_QLOGIC_ISP5432
 290 #define        PCI_PRODUCT_QLOGIC_ISP5432      0x5432
 291 #endif
 292
 293 #ifndef PCI_PRODUCT_QLOGIC_ISP2031
 294 #define PCI_PRODUCT_QLOGIC_ISP2031      0x2031
 295 #endif
 296
 297 #ifndef PCI_PRODUCT_QLOGIC_ISP8031
 298 #define PCI_PRODUCT_QLOGIC_ISP8031      0x8031
 299 #endif
 300
 301 #define        PCI_QLOGIC_ISP5432      \
 302        ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC)
 303
 304 #define PCI_QLOGIC_ISP1020      \
 305         ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
 306
 307 #define PCI_QLOGIC_ISP1080      \
 308         ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
 309
 310 #define PCI_QLOGIC_ISP10160     \
 311         ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
 312
 313 #define PCI_QLOGIC_ISP12160     \
 314         ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
 315
 316 #define PCI_QLOGIC_ISP1240      \
 317         ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
 318
 319 #define PCI_QLOGIC_ISP1280      \
 320         ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
 321
 322 #define PCI_QLOGIC_ISP2100      \
 323         ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
 324
 325 #define PCI_QLOGIC_ISP2200      \
 326         ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
 327
 328 #define PCI_QLOGIC_ISP2300      \
 329         ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
 330
 331 #define PCI_QLOGIC_ISP2312      \
 332         ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
 333
 334 #define PCI_QLOGIC_ISP2322      \
 335         ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
 336
 337 #define PCI_QLOGIC_ISP2422      \
 338         ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
 339
 340 #define PCI_QLOGIC_ISP2432      \
 341         ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
 342
 343 #define PCI_QLOGIC_ISP2532      \
 344         ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
 345
 346 #define PCI_QLOGIC_ISP6312      \
 347         ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
 348
 349 #define PCI_QLOGIC_ISP6322      \
 350         ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
 351
 352 #define PCI_QLOGIC_ISP2031      \
 353         ((PCI_PRODUCT_QLOGIC_ISP2031 << 16) | PCI_VENDOR_QLOGIC)
 354
 355 #define PCI_QLOGIC_ISP8031      \
 356         ((PCI_PRODUCT_QLOGIC_ISP8031 << 16) | PCI_VENDOR_QLOGIC)
 357
 358 /*
 359  * Odd case for some AMI raid cards... We need to *not* attach to this.
 360  */
 361 #define AMI_RAID_SUBVENDOR_ID   0x101e
 362
 363 #define PCI_DFLT_LTNCY  0x40
 364 #define PCI_DFLT_LNSZ   0x10
 365
 366 static int isp_pci_probe (device_t);
 367 static int isp_pci_attach (device_t);
 368 static int isp_pci_detach (device_t);
 369
 370
 371 #define ISP_PCD(isp)    ((struct isp_pcisoftc *)isp)->pci_dev
 372 struct isp_pcisoftc {
 373         ispsoftc_t                      pci_isp;
 374         device_t                        pci_dev;
 375         struct resource *               regs;
 376         struct resource *               regs1;
 377         struct resource *               regs2;
 378         void *                          irq;
 379         int                             iqd;
 380         int                             rtp;
 381         int                             rgd;
 382         int                             rtp1;
 383         int                             rgd1;
 384         int                             rtp2;
 385         int                             rgd2;
 386         void *                          ih;
 387         int16_t                         pci_poff[_NREG_BLKS];
 388         bus_dma_tag_t                   dmat;
 389         int                             msicount;
 390 };
 391
 392
 393 static device_method_t isp_pci_methods[] = {
 394         /* Device interface */
 395         DEVMETHOD(device_probe,         isp_pci_probe),
 396         DEVMETHOD(device_attach,        isp_pci_attach),
 397         DEVMETHOD(device_detach,        isp_pci_detach),
 398         { 0, 0 }
 399 };
 400
 401 static driver_t isp_pci_driver = {
 402         "isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
 403 };
 404 static devclass_t isp_devclass;
 405 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0);
 406 MODULE_DEPEND(isp, cam, 1, 1, 1);
 407 MODULE_DEPEND(isp, firmware, 1, 1, 1);
 408 static int isp_nvports = 0;
 409
 410 static int
 411 isp_pci_probe(device_t dev)
 412 {
 413         switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) {
 414         case PCI_QLOGIC_ISP1020:
 415                 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter");
 416                 break;
 417         case PCI_QLOGIC_ISP1080:
 418                 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter");
 419                 break;
 420         case PCI_QLOGIC_ISP1240:
 421                 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter");
 422                 break;
 423         case PCI_QLOGIC_ISP1280:
 424                 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter");
 425                 break;
 426         case PCI_QLOGIC_ISP10160:
 427                 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter");
 428                 break;
 429         case PCI_QLOGIC_ISP12160:
 430                 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) {
 431                         return (ENXIO);
 432                 }
 433                 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter");
 434                 break;
 435         case PCI_QLOGIC_ISP2100:
 436                 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter");
 437                 break;
 438         case PCI_QLOGIC_ISP2200:
 439                 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter");
 440                 break;
 441         case PCI_QLOGIC_ISP2300:
 442                 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
 443                 break;
 444         case PCI_QLOGIC_ISP2312:
 445                 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
 446                 break;
 447         case PCI_QLOGIC_ISP2322:
 448                 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
 449                 break;
 450         case PCI_QLOGIC_ISP2422:
 451                 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
 452                 break;
 453         case PCI_QLOGIC_ISP2432:
 454                 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter");
 455                 break;
 456         case PCI_QLOGIC_ISP2532:
 457                 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter");
 458                 break;
 459         case PCI_QLOGIC_ISP5432:
 460                 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter");
 461                 break;
 462         case PCI_QLOGIC_ISP6312:
 463                 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
 464                 break;
 465         case PCI_QLOGIC_ISP6322:
 466                 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
 467                 break;
 468         case PCI_QLOGIC_ISP2031:
 469                 device_set_desc(dev, "Qlogic ISP 2031 PCI FC-AL Adapter");
 470                 break;
 471         case PCI_QLOGIC_ISP8031:
 472                 device_set_desc(dev, "Qlogic ISP 8031 PCI FCoE Adapter");
 473                 break;
 474         default:
 475                 return (ENXIO);
 476         }
 477         if (isp_announced == 0 && bootverbose) {
 478                 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, "
 479                     "Core Version %d.%d\n",
 480                     ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
 481                     ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
 482                 isp_announced++;
 483         }
 484         /*
 485          * XXXX: Here is where we might load the f/w module
 486          * XXXX: (or increase a reference count to it).
 487          */
 488         return (BUS_PROBE_DEFAULT);
 489 }
 490
 491 static void
 492 isp_get_generic_options(device_t dev, ispsoftc_t *isp)
 493 {
 494         int tval;
 495
 496         tval = 0;
 497         if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) {
 498                 isp->isp_confopts |= ISP_CFG_NORELOAD;
 499         }
 500         tval = 0;
 501         if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) {
 502                 isp->isp_confopts |= ISP_CFG_NONVRAM;
 503         }
 504         tval = 0;
 505         (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval);
 506         if (tval) {
 507                 isp->isp_dblev = tval;
 508         } else {
 509                 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
 510         }
 511         if (bootverbose) {
 512                 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
 513         }
 514         tval = -1;
 515         (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval);
 516         if (tval > 0 && tval <= 254) {
 517                 isp_nvports = tval;
 518         }
 519         tval = 7;
 520         (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval);
 521         isp_quickboot_time = tval;
 522 }
 523
 524 static void
 525 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp)
 526 {
 527         const char *sptr;
 528         int tval = 0;
 529         char prefix[12], name[16];
 530
 531         if (chan == 0)
 532                 prefix[0] = 0;
 533         else
 534                 snprintf(prefix, sizeof(prefix), "chan%d.", chan);
 535         snprintf(name, sizeof(name), "%siid", prefix);
 536         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 537             name, &tval)) {
 538                 if (IS_FC(isp)) {
 539                         ISP_FC_PC(isp, chan)->default_id = 109 - chan;
 540                 } else {
 541 #ifdef __sparc64__
 542                         ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev);
 543 #else
 544                         ISP_SPI_PC(isp, chan)->iid = 7;
 545 #endif
 546                 }
 547         } else {
 548                 if (IS_FC(isp)) {
 549                         ISP_FC_PC(isp, chan)->default_id = tval - chan;
 550                 } else {
 551                         ISP_SPI_PC(isp, chan)->iid = tval;
 552                 }
 553                 isp->isp_confopts |= ISP_CFG_OWNLOOPID;
 554         }
 555
 556         if (IS_SCSI(isp))
 557                 return;
 558
 559         tval = -1;
 560         snprintf(name, sizeof(name), "%srole", prefix);
 561         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 562             name, &tval) == 0) {
 563                 switch (tval) {
 564                 case ISP_ROLE_NONE:
 565                 case ISP_ROLE_INITIATOR:
 566                 case ISP_ROLE_TARGET:
 567                 case ISP_ROLE_BOTH:
 568                         device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval);
 569                         break;
 570                 default:
 571                         tval = -1;
 572                         break;
 573                 }
 574         }
 575         if (tval == -1) {
 576                 tval = ISP_DEFAULT_ROLES;
 577         }
 578         ISP_FC_PC(isp, chan)->def_role = tval;
 579
 580         tval = 0;
 581         snprintf(name, sizeof(name), "%sfullduplex", prefix);
 582         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 583             name, &tval) == 0 && tval != 0) {
 584                 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX;
 585         }
 586         sptr = 0;
 587         snprintf(name, sizeof(name), "%stopology", prefix);
 588         if (resource_string_value(device_get_name(dev), device_get_unit(dev),
 589             name, (const char **) &sptr) == 0 && sptr != 0) {
 590                 if (strcmp(sptr, "lport") == 0) {
 591                         isp->isp_confopts |= ISP_CFG_LPORT;
 592                 } else if (strcmp(sptr, "nport") == 0) {
 593                         isp->isp_confopts |= ISP_CFG_NPORT;
 594                 } else if (strcmp(sptr, "lport-only") == 0) {
 595                         isp->isp_confopts |= ISP_CFG_LPORT_ONLY;
 596                 } else if (strcmp(sptr, "nport-only") == 0) {
 597                         isp->isp_confopts |= ISP_CFG_NPORT_ONLY;
 598                 }
 599         }
 600
 601 #ifdef ISP_FCTAPE_OFF
 602         isp->isp_confopts |= ISP_CFG_NOFCTAPE;
 603 #else
 604         isp->isp_confopts |= ISP_CFG_FCTAPE;
 605 #endif
 606
 607         tval = 0;
 608         snprintf(name, sizeof(name), "%snofctape", prefix);
 609         (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
 610             name, &tval);
 611         if (tval) {
 612                 isp->isp_confopts &= ~ISP_CFG_FCTAPE;
 613                 isp->isp_confopts |= ISP_CFG_NOFCTAPE;
 614         }
 615
 616         tval = 0;
 617         snprintf(name, sizeof(name), "%sfctape", prefix);
 618         (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
 619             name, &tval);
 620         if (tval) {
 621                 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE;
 622                 isp->isp_confopts |= ISP_CFG_FCTAPE;
 623         }
 624
 625
 626         /*
 627          * Because the resource_*_value functions can neither return
 628          * 64 bit integer values, nor can they be directly coerced
 629          * to interpret the right hand side of the assignment as
 630          * you want them to interpret it, we have to force WWN
 631          * hint replacement to specify WWN strings with a leading
 632          * 'w' (e..g w50000000aaaa0001). Sigh.
 633          */
 634         sptr = 0;
 635         snprintf(name, sizeof(name), "%sportwwn", prefix);
 636         tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
 637             name, (const char **) &sptr);
 638         if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
 639                 char *eptr = 0;
 640                 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16);
 641                 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) {
 642                         device_printf(dev, "mangled portwwn hint '%s'\n", sptr);
 643                         ISP_FC_PC(isp, chan)->def_wwpn = 0;
 644                 }
 645         }
 646
 647         sptr = 0;
 648         snprintf(name, sizeof(name), "%snodewwn", prefix);
 649         tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
 650             name, (const char **) &sptr);
 651         if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
 652                 char *eptr = 0;
 653                 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16);
 654                 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) {
 655                         device_printf(dev, "mangled nodewwn hint '%s'\n", sptr);
 656                         ISP_FC_PC(isp, chan)->def_wwnn = 0;
 657                 }
 658         }
 659
 660         tval = -1;
 661         snprintf(name, sizeof(name), "%sloop_down_limit", prefix);
 662         (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
 663             name, &tval);
 664         if (tval >= 0 && tval < 0xffff) {
 665                 ISP_FC_PC(isp, chan)->loop_down_limit = tval;
 666         } else {
 667                 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit;
 668         }
 669
 670         tval = -1;
 671         snprintf(name, sizeof(name), "%sgone_device_time", prefix);
 672         (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
 673             name, &tval);
 674         if (tval >= 0 && tval < 0xffff) {
 675                 ISP_FC_PC(isp, chan)->gone_device_time = tval;
 676         } else {
 677                 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time;
 678         }
 679 }
 680
 681 static int
 682 isp_pci_attach(device_t dev)
 683 {
 684         int i, locksetup = 0;
 685         uint32_t data, cmd, linesz, did;
 686         struct isp_pcisoftc *pcs;
 687         ispsoftc_t *isp;
 688         size_t psize, xsize;
 689         char fwname[32];
 690
 691         pcs = device_get_softc(dev);
 692         if (pcs == NULL) {
 693                 device_printf(dev, "cannot get softc\n");
 694                 return (ENOMEM);
 695         }
 696         memset(pcs, 0, sizeof (*pcs));
 697
 698         pcs->pci_dev = dev;
 699         isp = &pcs->pci_isp;
 700         isp->isp_dev = dev;
 701         isp->isp_nchan = 1;
 702         if (sizeof (bus_addr_t) > 4)
 703                 isp->isp_osinfo.sixtyfourbit = 1;
 704
 705         /*
 706          * Get Generic Options
 707          */
 708         isp_nvports = 0;
 709         isp_get_generic_options(dev, isp);
 710
 711         linesz = PCI_DFLT_LNSZ;
 712         pcs->irq = pcs->regs = pcs->regs2 = NULL;
 713         pcs->rgd = pcs->rtp = pcs->iqd = 0;
 714
 715         pcs->pci_dev = dev;
 716         pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
 717         pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
 718         pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
 719         pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
 720         pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
 721
 722         switch (pci_get_devid(dev)) {
 723         case PCI_QLOGIC_ISP1020:
 724                 did = 0x1040;
 725                 isp->isp_mdvec = &mdvec;
 726                 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
 727                 break;
 728         case PCI_QLOGIC_ISP1080:
 729                 did = 0x1080;
 730                 isp->isp_mdvec = &mdvec_1080;
 731                 isp->isp_type = ISP_HA_SCSI_1080;
 732                 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
 733                 break;
 734         case PCI_QLOGIC_ISP1240:
 735                 did = 0x1080;
 736                 isp->isp_mdvec = &mdvec_1080;
 737                 isp->isp_type = ISP_HA_SCSI_1240;
 738                 isp->isp_nchan = 2;
 739                 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
 740                 break;
 741         case PCI_QLOGIC_ISP1280:
 742                 did = 0x1080;
 743                 isp->isp_mdvec = &mdvec_1080;
 744                 isp->isp_type = ISP_HA_SCSI_1280;
 745                 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
 746                 break;
 747         case PCI_QLOGIC_ISP10160:
 748                 did = 0x12160;
 749                 isp->isp_mdvec = &mdvec_12160;
 750                 isp->isp_type = ISP_HA_SCSI_10160;
 751                 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
 752                 break;
 753         case PCI_QLOGIC_ISP12160:
 754                 did = 0x12160;
 755                 isp->isp_nchan = 2;
 756                 isp->isp_mdvec = &mdvec_12160;
 757                 isp->isp_type = ISP_HA_SCSI_12160;
 758                 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
 759                 break;
 760         case PCI_QLOGIC_ISP2100:
 761                 did = 0x2100;
 762                 isp->isp_mdvec = &mdvec_2100;
 763                 isp->isp_type = ISP_HA_FC_2100;
 764                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
 765                 if (pci_get_revid(dev) < 3) {
 766                         /*
 767                          * XXX: Need to get the actual revision
 768                          * XXX: number of the 2100 FB. At any rate,
 769                          * XXX: lower cache line size for early revision
 770                          * XXX; boards.
 771                          */
 772                         linesz = 1;
 773                 }
 774                 break;
 775         case PCI_QLOGIC_ISP2200:
 776                 did = 0x2200;
 777                 isp->isp_mdvec = &mdvec_2200;
 778                 isp->isp_type = ISP_HA_FC_2200;
 779                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
 780                 break;
 781         case PCI_QLOGIC_ISP2300:
 782                 did = 0x2300;
 783                 isp->isp_mdvec = &mdvec_2300;
 784                 isp->isp_type = ISP_HA_FC_2300;
 785                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
 786                 break;
 787         case PCI_QLOGIC_ISP2312:
 788         case PCI_QLOGIC_ISP6312:
 789                 did = 0x2300;
 790                 isp->isp_mdvec = &mdvec_2300;
 791                 isp->isp_type = ISP_HA_FC_2312;
 792                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
 793                 break;
 794         case PCI_QLOGIC_ISP2322:
 795         case PCI_QLOGIC_ISP6322:
 796                 did = 0x2322;
 797                 isp->isp_mdvec = &mdvec_2300;
 798                 isp->isp_type = ISP_HA_FC_2322;
 799                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
 800                 break;
 801         case PCI_QLOGIC_ISP2422:
 802         case PCI_QLOGIC_ISP2432:
 803                 did = 0x2400;
 804                 isp->isp_nchan += isp_nvports;
 805                 isp->isp_mdvec = &mdvec_2400;
 806                 isp->isp_type = ISP_HA_FC_2400;
 807                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
 808                 break;
 809         case PCI_QLOGIC_ISP2532:
 810                 did = 0x2500;
 811                 isp->isp_nchan += isp_nvports;
 812                 isp->isp_mdvec = &mdvec_2500;
 813                 isp->isp_type = ISP_HA_FC_2500;
 814                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
 815                 break;
 816         case PCI_QLOGIC_ISP5432:
 817                 did = 0x2500;
 818                 isp->isp_mdvec = &mdvec_2500;
 819                 isp->isp_type = ISP_HA_FC_2500;
 820                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
 821                 break;
 822         case PCI_QLOGIC_ISP2031:
 823         case PCI_QLOGIC_ISP8031:
 824                 did = 0x2600;
 825                 isp->isp_nchan += isp_nvports;
 826                 isp->isp_mdvec = &mdvec_2600;
 827                 isp->isp_type = ISP_HA_FC_2600;
 828                 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
 829                 break;
 830         default:
 831                 device_printf(dev, "unknown device type\n");
 832                 goto bad;
 833                 break;
 834         }
 835         isp->isp_revision = pci_get_revid(dev);
 836
 837         if (IS_26XX(isp)) {
 838                 pcs->rtp = SYS_RES_MEMORY;
 839                 pcs->rgd = PCIR_BAR(0);
 840                 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
 841                     RF_ACTIVE);
 842                 pcs->rtp1 = SYS_RES_MEMORY;
 843                 pcs->rgd1 = PCIR_BAR(2);
 844                 pcs->regs1 = bus_alloc_resource_any(dev, pcs->rtp1, &pcs->rgd1,
 845                     RF_ACTIVE);
 846                 pcs->rtp2 = SYS_RES_MEMORY;
 847                 pcs->rgd2 = PCIR_BAR(4);
 848                 pcs->regs2 = bus_alloc_resource_any(dev, pcs->rtp2, &pcs->rgd2,
 849                     RF_ACTIVE);
 850         } else {
 851                 pcs->rtp = SYS_RES_MEMORY;
 852                 pcs->rgd = PCIR_BAR(1);
 853                 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
 854                     RF_ACTIVE);
 855                 if (pcs->regs == NULL) {
 856                         pcs->rtp = SYS_RES_IOPORT;
 857                         pcs->rgd = PCIR_BAR(0);
 858                         pcs->regs = bus_alloc_resource_any(dev, pcs->rtp,
 859                             &pcs->rgd, RF_ACTIVE);
 860                 }
 861         }
 862         if (pcs->regs == NULL) {
 863                 device_printf(dev, "Unable to map any ports\n");
 864                 goto bad;
 865         }
 866         if (bootverbose) {
 867                 device_printf(dev, "Using %s space register mapping\n",
 868                     (pcs->rtp == SYS_RES_IOPORT)? "I/O" : "Memory");
 869         }
 870         isp->isp_regs = pcs->regs;
 871         isp->isp_regs2 = pcs->regs2;
 872
 873         if (IS_FC(isp)) {
 874                 psize = sizeof (fcparam);
 875                 xsize = sizeof (struct isp_fc);
 876         } else {
 877                 psize = sizeof (sdparam);
 878                 xsize = sizeof (struct isp_spi);
 879         }
 880         psize *= isp->isp_nchan;
 881         xsize *= isp->isp_nchan;
 882         isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
 883         if (isp->isp_param == NULL) {
 884                 device_printf(dev, "cannot allocate parameter data\n");
 885                 goto bad;
 886         }
 887         isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO);
 888         if (isp->isp_osinfo.pc.ptr == NULL) {
 889                 device_printf(dev, "cannot allocate parameter data\n");
 890                 goto bad;
 891         }
 892
 893         /*
 894          * Now that we know who we are (roughly) get/set specific options
 895          */
 896         for (i = 0; i < isp->isp_nchan; i++) {
 897                 isp_get_specific_options(dev, i, isp);
 898         }
 899
 900         isp->isp_osinfo.fw = NULL;
 901         if (isp->isp_osinfo.fw == NULL) {
 902                 snprintf(fwname, sizeof (fwname), "isp_%04x", did);
 903                 isp->isp_osinfo.fw = firmware_get(fwname);
 904         }
 905         if (isp->isp_osinfo.fw != NULL) {
 906                 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname);
 907                 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data;
 908         }
 909
 910         /*
 911          * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
 912          */
 913         cmd = pci_read_config(dev, PCIR_COMMAND, 2);
 914         cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
 915         if (IS_2300(isp)) {     /* per QLogic errata */
 916                 cmd &= ~PCIM_CMD_INVEN;
 917         }
 918         if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
 919                 cmd &= ~PCIM_CMD_INTX_DISABLE;
 920         }
 921         if (IS_24XX(isp)) {
 922                 cmd &= ~PCIM_CMD_INTX_DISABLE;
 923         }
 924         pci_write_config(dev, PCIR_COMMAND, cmd, 2);
 925
 926         /*
 927          * Make sure the Cache Line Size register is set sensibly.
 928          */
 929         data = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 930         if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) {
 931                 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data);
 932                 data = linesz;
 933                 pci_write_config(dev, PCIR_CACHELNSZ, data, 1);
 934         }
 935
 936         /*
 937          * Make sure the Latency Timer is sane.
 938          */
 939         data = pci_read_config(dev, PCIR_LATTIMER, 1);
 940         if (data < PCI_DFLT_LTNCY) {
 941                 data = PCI_DFLT_LTNCY;
 942                 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data);
 943                 pci_write_config(dev, PCIR_LATTIMER, data, 1);
 944         }
 945
 946         /*
 947          * Make sure we've disabled the ROM.
 948          */
 949         data = pci_read_config(dev, PCIR_ROMADDR, 4);
 950         data &= ~1;
 951         pci_write_config(dev, PCIR_ROMADDR, data, 4);
 952
 953         if (IS_26XX(isp)) {
 954                 /* 26XX chips support only MSI-X, so start from them. */
 955                 pcs->msicount = imin(pci_msix_count(dev), 1);
 956                 if (pcs->msicount > 0 &&
 957                     (i = pci_alloc_msix(dev, &pcs->msicount)) == 0) {
 958                         pcs->iqd = 1;
 959                 } else {
 960                         pcs->msicount = 0;
 961                 }
 962         }
 963         if (pcs->msicount == 0 && (IS_24XX(isp) || IS_2322(isp))) {
 964                 /*
 965                  * Older chips support both MSI and MSI-X, but I have
 966                  * feeling that older firmware may not support MSI-X,
 967                  * but we have no way to check the firmware flag here.
 968                  */
 969                 pcs->msicount = imin(pci_msi_count(dev), 1);
 970                 if (pcs->msicount > 0 &&
 971                     pci_alloc_msi(dev, &pcs->msicount) == 0) {
 972                         pcs->iqd = 1;
 973                 } else {
 974                         pcs->msicount = 0;
 975                 }
 976         }
 977         pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE);
 978         if (pcs->irq == NULL) {
 979                 device_printf(dev, "could not allocate interrupt\n");
 980                 goto bad;
 981         }
 982
 983         /* Make sure the lock is set up. */
 984         mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF);
 985         locksetup++;
 986
 987         if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) {
 988                 device_printf(dev, "could not setup interrupt\n");
 989                 goto bad;
 990         }
 991
 992         /*
 993          * Last minute checks...
 994          */
 995         if (IS_23XX(isp) || IS_24XX(isp)) {
 996                 isp->isp_port = pci_get_function(dev);
 997         }
 998
 999         /*
1000          * Make sure we're in reset state.
1001          */
1002         ISP_LOCK(isp);
1003         if (isp_reinit(isp, 1) != 0) {
1004                 ISP_UNLOCK(isp);
1005                 goto bad;
1006         }
1007         ISP_UNLOCK(isp);
1008         if (isp_attach(isp)) {
1009                 ISP_LOCK(isp);
1010                 isp_uninit(isp);
1011                 ISP_UNLOCK(isp);
1012                 goto bad;
1013         }
1014         return (0);
1015
1016 bad:
1017         if (pcs->ih) {
1018                 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1019         }
1020         if (locksetup) {
1021                 mtx_destroy(&isp->isp_osinfo.lock);
1022         }
1023         if (pcs->irq) {
1024                 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1025         }
1026         if (pcs->msicount) {
1027                 pci_release_msi(dev);
1028         }
1029         if (pcs->regs)
1030                 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1031         if (pcs->regs1)
1032                 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1);
1033         if (pcs->regs2)
1034                 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
1035         if (pcs->pci_isp.isp_param) {
1036                 free(pcs->pci_isp.isp_param, M_DEVBUF);
1037                 pcs->pci_isp.isp_param = NULL;
1038         }
1039         if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1040                 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1041                 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1042         }
1043         return (ENXIO);
1044 }
1045
1046 static int
1047 isp_pci_detach(device_t dev)
1048 {
1049         struct isp_pcisoftc *pcs;
1050         ispsoftc_t *isp;
1051         int status;
1052
1053         pcs = device_get_softc(dev);
1054         if (pcs == NULL) {
1055                 return (ENXIO);
1056         }
1057         isp = (ispsoftc_t *) pcs;
1058         status = isp_detach(isp);
1059         if (status)
1060                 return (status);
1061         ISP_LOCK(isp);
1062         isp_uninit(isp);
1063         if (pcs->ih) {
1064                 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1065         }
1066         ISP_UNLOCK(isp);
1067         mtx_destroy(&isp->isp_osinfo.lock);
1068         (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1069         if (pcs->msicount) {
1070                 pci_release_msi(dev);
1071         }
1072         (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1073         if (pcs->regs1)
1074                 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1);
1075         if (pcs->regs2)
1076                 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
1077         /*
1078          * XXX: THERE IS A LOT OF LEAKAGE HERE
1079          */
1080         if (pcs->pci_isp.isp_param) {
1081                 free(pcs->pci_isp.isp_param, M_DEVBUF);
1082                 pcs->pci_isp.isp_param = NULL;
1083         }
1084         if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1085                 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1086                 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1087         }
1088         return (0);
1089 }
1090
1091 #define IspVirt2Off(a, x)       \
1092         (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1093         _BLK_REG_SHFT] + ((x) & 0xfff))
1094
1095 #define BXR2(isp, off)          bus_read_2((isp)->isp_regs, (off))
1096 #define BXW2(isp, off, v)       bus_write_2((isp)->isp_regs, (off), (v))
1097 #define BXR4(isp, off)          bus_read_4((isp)->isp_regs, (off))
1098 #define BXW4(isp, off, v)       bus_write_4((isp)->isp_regs, (off), (v))
1099 #define B2R4(isp, off)          bus_read_4((isp)->isp_regs2, (off))
1100 #define B2W4(isp, off, v)       bus_write_4((isp)->isp_regs2, (off), (v))
1101
1102 static ISP_INLINE int
1103 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1104 {
1105         uint32_t val0, val1;
1106         int i = 0;
1107
1108         do {
1109                 val0 = BXR2(isp, IspVirt2Off(isp, off));
1110                 val1 = BXR2(isp, IspVirt2Off(isp, off));
1111         } while (val0 != val1 && ++i < 1000);
1112         if (val0 != val1) {
1113                 return (1);
1114         }
1115         *rp = val0;
1116         return (0);
1117 }
1118
1119 static int
1120 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1121 {
1122         uint16_t isr, sema;
1123
1124         if (IS_2100(isp)) {
1125                 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1126                     return (0);
1127                 }
1128                 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
1129                     return (0);
1130                 }
1131         } else {
1132                 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR));
1133                 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA));
1134         }
1135         isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
1136         isr &= INT_PENDING_MASK(isp);
1137         sema &= BIU_SEMA_LOCK;
1138         if (isr == 0 && sema == 0) {
1139                 return (0);
1140         }
1141         *isrp = isr;
1142         if ((*semap = sema) != 0) {
1143                 if (IS_2100(isp)) {
1144                         if (isp_pci_rd_debounced(isp, OUTMAILBOX0, info)) {
1145                                 return (0);
1146                         }
1147                 } else {
1148                         *info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0));
1149                 }
1150         }
1151         return (1);
1152 }
1153
1154 static int
1155 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1156 {
1157         uint32_t hccr, r2hisr;
1158
1159         if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1160                 *isrp = 0;
1161                 return (0);
1162         }
1163         r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO));
1164         isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1165         if ((r2hisr & BIU_R2HST_INTR) == 0) {
1166                 *isrp = 0;
1167                 return (0);
1168         }
1169         switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1170         case ISPR2HST_ROM_MBX_OK:
1171         case ISPR2HST_ROM_MBX_FAIL:
1172         case ISPR2HST_MBX_OK:
1173         case ISPR2HST_MBX_FAIL:
1174         case ISPR2HST_ASYNC_EVENT:
1175                 *semap = 1;
1176                 break;
1177         case ISPR2HST_RIO_16:
1178                 *info = ASYNC_RIO16_1;
1179                 *semap = 1;
1180                 return (1);
1181         case ISPR2HST_FPOST:
1182                 *info = ASYNC_CMD_CMPLT;
1183                 *semap = 1;
1184                 return (1);
1185         case ISPR2HST_FPOST_CTIO:
1186                 *info = ASYNC_CTIO_DONE;
1187                 *semap = 1;
1188                 return (1);
1189         case ISPR2HST_RSPQ_UPDATE:
1190                 *semap = 0;
1191                 break;
1192         default:
1193                 hccr = ISP_READ(isp, HCCR);
1194                 if (hccr & HCCR_PAUSE) {
1195                         ISP_WRITE(isp, HCCR, HCCR_RESET);
1196                         isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR));
1197                         ISP_WRITE(isp, BIU_ICR, 0);
1198                 } else {
1199                         isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1200                 }
1201                 return (0);
1202         }
1203         *info = (r2hisr >> 16);
1204         return (1);
1205 }
1206
1207 static int
1208 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1209 {
1210         uint32_t r2hisr;
1211
1212         r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO));
1213         isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1214         if ((r2hisr & BIU_R2HST_INTR) == 0) {
1215                 *isrp = 0;
1216                 return (0);
1217         }
1218         switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1219         case ISPR2HST_ROM_MBX_OK:
1220         case ISPR2HST_ROM_MBX_FAIL:
1221         case ISPR2HST_MBX_OK:
1222         case ISPR2HST_MBX_FAIL:
1223         case ISPR2HST_ASYNC_EVENT:
1224                 *semap = 1;
1225                 break;
1226         case ISPR2HST_RSPQ_UPDATE:
1227         case ISPR2HST_RSPQ_UPDATE2:
1228         case ISPR2HST_ATIO_UPDATE:
1229         case ISPR2HST_ATIO_RSPQ_UPDATE:
1230         case ISPR2HST_ATIO_UPDATE2:
1231                 *semap = 0;
1232                 break;
1233         default:
1234                 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
1235                 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1236                 return (0);
1237         }
1238         *info = (r2hisr >> 16);
1239         return (1);
1240 }
1241
1242 static uint32_t
1243 isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1244 {
1245         uint16_t rv;
1246         int oldconf = 0;
1247
1248         if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1249                 /*
1250                  * We will assume that someone has paused the RISC processor.
1251                  */
1252                 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1253                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP);
1254                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1255         }
1256         rv = BXR2(isp, IspVirt2Off(isp, regoff));
1257         if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1258                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1259                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1260         }
1261         return (rv);
1262 }
1263
1264 static void
1265 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val)
1266 {
1267         int oldconf = 0;
1268
1269         if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1270                 /*
1271                  * We will assume that someone has paused the RISC processor.
1272                  */
1273                 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1274                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1275                     oldconf | BIU_PCI_CONF1_SXP);
1276                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1277         }
1278         BXW2(isp, IspVirt2Off(isp, regoff), val);
1279         MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1280         if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1281                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1282                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1283         }
1284
1285 }
1286
1287 static uint32_t
1288 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1289 {
1290         uint32_t rv, oc = 0;
1291
1292         if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1293                 uint32_t tc;
1294                 /*
1295                  * We will assume that someone has paused the RISC processor.
1296                  */
1297                 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1298                 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1299                 if (regoff & SXP_BANK1_SELECT)
1300                         tc |= BIU_PCI1080_CONF1_SXP1;
1301                 else
1302                         tc |= BIU_PCI1080_CONF1_SXP0;
1303                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1304                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1305         } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1306                 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1307                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1308                     oc | BIU_PCI1080_CONF1_DMA);
1309                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1310         }
1311         rv = BXR2(isp, IspVirt2Off(isp, regoff));
1312         if (oc) {
1313                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1314                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1315         }
1316         return (rv);
1317 }
1318
1319 static void
1320 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val)
1321 {
1322         int oc = 0;
1323
1324         if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1325                 uint32_t tc;
1326                 /*
1327                  * We will assume that someone has paused the RISC processor.
1328                  */
1329                 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1330                 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1331                 if (regoff & SXP_BANK1_SELECT)
1332                         tc |= BIU_PCI1080_CONF1_SXP1;
1333                 else
1334                         tc |= BIU_PCI1080_CONF1_SXP0;
1335                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1336                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1337         } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1338                 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1339                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1340                     oc | BIU_PCI1080_CONF1_DMA);
1341                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1342         }
1343         BXW2(isp, IspVirt2Off(isp, regoff), val);
1344         MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1345         if (oc) {
1346                 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1347                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1348         }
1349 }
1350
1351 static uint32_t
1352 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
1353 {
1354         uint32_t rv;
1355         int block = regoff & _BLK_REG_MASK;
1356
1357         switch (block) {
1358         case BIU_BLOCK:
1359                 break;
1360         case MBOX_BLOCK:
1361                 return (BXR2(isp, IspVirt2Off(isp, regoff)));
1362         case SXP_BLOCK:
1363                 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK read at 0x%x", regoff);
1364                 return (0xffffffff);
1365         case RISC_BLOCK:
1366                 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK read at 0x%x", regoff);
1367                 return (0xffffffff);
1368         case DMA_BLOCK:
1369                 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK read at 0x%x", regoff);
1370                 return (0xffffffff);
1371         default:
1372                 isp_prt(isp, ISP_LOGERR, "unknown block read at 0x%x", regoff);
1373                 return (0xffffffff);
1374         }
1375
1376         switch (regoff) {
1377         case BIU2400_FLASH_ADDR:
1378         case BIU2400_FLASH_DATA:
1379         case BIU2400_ICR:
1380         case BIU2400_ISR:
1381         case BIU2400_CSR:
1382         case BIU2400_REQINP:
1383         case BIU2400_REQOUTP:
1384         case BIU2400_RSPINP:
1385         case BIU2400_RSPOUTP:
1386         case BIU2400_PRI_REQINP:
1387         case BIU2400_PRI_REQOUTP:
1388         case BIU2400_ATIO_RSPINP:
1389         case BIU2400_ATIO_RSPOUTP:
1390         case BIU2400_HCCR:
1391         case BIU2400_GPIOD:
1392         case BIU2400_GPIOE:
1393         case BIU2400_HSEMA:
1394                 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1395                 break;
1396         case BIU2400_R2HSTSLO:
1397                 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1398                 break;
1399         case BIU2400_R2HSTSHI:
1400                 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16;
1401                 break;
1402         default:
1403                 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
1404                     regoff);
1405                 rv = 0xffffffff;
1406                 break;
1407         }
1408         return (rv);
1409 }
1410
1411 static void
1412 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1413 {
1414         int block = regoff & _BLK_REG_MASK;
1415
1416         switch (block) {
1417         case BIU_BLOCK:
1418                 break;
1419         case MBOX_BLOCK:
1420                 BXW2(isp, IspVirt2Off(isp, regoff), val);
1421                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1422                 return;
1423         case SXP_BLOCK:
1424                 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK write at 0x%x", regoff);
1425                 return;
1426         case RISC_BLOCK:
1427                 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK write at 0x%x", regoff);
1428                 return;
1429         case DMA_BLOCK:
1430                 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK write at 0x%x", regoff);
1431                 return;
1432         default:
1433                 isp_prt(isp, ISP_LOGERR, "unknown block write at 0x%x", regoff);
1434                 break;
1435         }
1436
1437         switch (regoff) {
1438         case BIU2400_FLASH_ADDR:
1439         case BIU2400_FLASH_DATA:
1440         case BIU2400_ICR:
1441         case BIU2400_ISR:
1442         case BIU2400_CSR:
1443         case BIU2400_REQINP:
1444         case BIU2400_REQOUTP:
1445         case BIU2400_RSPINP:
1446         case BIU2400_RSPOUTP:
1447         case BIU2400_PRI_REQINP:
1448         case BIU2400_PRI_REQOUTP:
1449         case BIU2400_ATIO_RSPINP:
1450         case BIU2400_ATIO_RSPOUTP:
1451         case BIU2400_HCCR:
1452         case BIU2400_GPIOD:
1453         case BIU2400_GPIOE:
1454         case BIU2400_HSEMA:
1455                 BXW4(isp, IspVirt2Off(isp, regoff), val);
1456 #ifdef MEMORYBARRIERW
1457                 if (regoff == BIU2400_REQINP ||
1458                     regoff == BIU2400_RSPOUTP ||
1459                     regoff == BIU2400_PRI_REQINP ||
1460                     regoff == BIU2400_ATIO_RSPOUTP)
1461                         MEMORYBARRIERW(isp, SYNC_REG,
1462                             IspVirt2Off(isp, regoff), 4, -1)
1463                 else
1464 #endif
1465                 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
1466                 break;
1467         default:
1468                 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
1469                     regoff);
1470                 break;
1471         }
1472 }
1473
1474 static uint32_t
1475 isp_pci_rd_reg_2600(ispsoftc_t *isp, int regoff)
1476 {
1477         uint32_t rv;
1478
1479         switch (regoff) {
1480         case BIU2400_PRI_REQINP:
1481         case BIU2400_PRI_REQOUTP:
1482                 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
1483                     regoff);
1484                 rv = 0xffffffff;
1485                 break;
1486         case BIU2400_REQINP:
1487                 rv = B2R4(isp, 0x00);
1488                 break;
1489         case BIU2400_REQOUTP:
1490                 rv = B2R4(isp, 0x04);
1491                 break;
1492         case BIU2400_RSPINP:
1493                 rv = B2R4(isp, 0x08);
1494                 break;
1495         case BIU2400_RSPOUTP:
1496                 rv = B2R4(isp, 0x0c);
1497                 break;
1498         case BIU2400_ATIO_RSPINP:
1499                 rv = B2R4(isp, 0x10);
1500                 break;
1501         case BIU2400_ATIO_RSPOUTP:
1502                 rv = B2R4(isp, 0x14);
1503                 break;
1504         default:
1505                 rv = isp_pci_rd_reg_2400(isp, regoff);
1506                 break;
1507         }
1508         return (rv);
1509 }
1510
1511 static void
1512 isp_pci_wr_reg_2600(ispsoftc_t *isp, int regoff, uint32_t val)
1513 {
1514         int off;
1515
1516         switch (regoff) {
1517         case BIU2400_PRI_REQINP:
1518         case BIU2400_PRI_REQOUTP:
1519                 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
1520                     regoff);
1521                 return;
1522         case BIU2400_REQINP:
1523                 off = 0x00;
1524                 break;
1525         case BIU2400_REQOUTP:
1526                 off = 0x04;
1527                 break;
1528         case BIU2400_RSPINP:
1529                 off = 0x08;
1530                 break;
1531         case BIU2400_RSPOUTP:
1532                 off = 0x0c;
1533                 break;
1534         case BIU2400_ATIO_RSPINP:
1535                 off = 0x10;
1536                 break;
1537         case BIU2400_ATIO_RSPOUTP:
1538                 off = 0x14;
1539                 break;
1540         default:
1541                 isp_pci_wr_reg_2400(isp, regoff, val);
1542                 return;
1543         }
1544         B2W4(isp, off, val);
1545 }
1546
1547
1548 struct imush {
1549         bus_addr_t maddr;
1550         int error;
1551 };
1552
1553 static void
1554 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1555 {
1556         struct imush *imushp = (struct imush *) arg;
1557
1558         if (!(imushp->error = error))
1559                 imushp->maddr = segs[0].ds_addr;
1560 }
1561
1562 static int
1563 isp_pci_mbxdma(ispsoftc_t *isp)
1564 {
1565         caddr_t base;
1566         uint32_t len, nsegs;
1567         int i, error, cmap = 0;
1568         bus_size_t slim;        /* segment size */
1569         bus_addr_t llim;        /* low limit of unavailable dma */
1570         bus_addr_t hlim;        /* high limit of unavailable dma */
1571         struct imush im;
1572         isp_ecmd_t *ecmd;
1573
1574         /*
1575          * Already been here? If so, leave...
1576          */
1577         if (isp->isp_rquest) {
1578                 return (0);
1579         }
1580         ISP_UNLOCK(isp);
1581
1582         if (isp->isp_maxcmds == 0) {
1583                 isp_prt(isp, ISP_LOGERR, "maxcmds not set");
1584                 ISP_LOCK(isp);
1585                 return (1);
1586         }
1587
1588         hlim = BUS_SPACE_MAXADDR;
1589         if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1590                 if (sizeof (bus_size_t) > 4) {
1591                         slim = (bus_size_t) (1ULL << 32);
1592                 } else {
1593                         slim = (bus_size_t) (1UL << 31);
1594                 }
1595                 llim = BUS_SPACE_MAXADDR;
1596         } else {
1597                 llim = BUS_SPACE_MAXADDR_32BIT;
1598                 slim = (1UL << 24);
1599         }
1600
1601         len = isp->isp_maxcmds * sizeof (struct isp_pcmd);
1602         isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1603
1604         if (isp->isp_osinfo.sixtyfourbit) {
1605                 nsegs = ISP_NSEG64_MAX;
1606         } else {
1607                 nsegs = ISP_NSEG_MAX;
1608         }
1609
1610         if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) {
1611                 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1612                 ISP_LOCK(isp);
1613                 isp_prt(isp, ISP_LOGERR, "could not create master dma tag");
1614                 return (1);
1615         }
1616
1617         len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1618         isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1619         for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1620                 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1621         }
1622         isp->isp_xffree = isp->isp_xflist;
1623
1624         /*
1625          * Allocate and map the request queue and a region for external
1626          * DMA addressable command/status structures (22XX and later).
1627          */
1628         len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1629         if (isp->isp_type >= ISP_HA_FC_2200)
1630                 len += (N_XCMDS * XCMD_SIZE);
1631         if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim,
1632             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1633             len, 1, len, 0, &isp->isp_osinfo.reqdmat)) {
1634                 isp_prt(isp, ISP_LOGERR, "cannot create request DMA tag");
1635                 goto bad1;
1636         }
1637         if (bus_dmamem_alloc(isp->isp_osinfo.reqdmat, (void **)&base,
1638             BUS_DMA_COHERENT, &isp->isp_osinfo.reqmap) != 0) {
1639                 isp_prt(isp, ISP_LOGERR, "cannot allocate request DMA memory");
1640                 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat);
1641                 goto bad1;
1642         }
1643         isp->isp_rquest = base;
1644         im.error = 0;
1645         if (bus_dmamap_load(isp->isp_osinfo.reqdmat, isp->isp_osinfo.reqmap,
1646             base, len, imc, &im, 0) || im.error) {
1647                 isp_prt(isp, ISP_LOGERR, "error loading request DMA map %d", im.error);
1648                 goto bad1;
1649         }
1650         isp_prt(isp, ISP_LOGDEBUG0, "request area @ 0x%jx/0x%jx",
1651             (uintmax_t)im.maddr, (uintmax_t)len);
1652         isp->isp_rquest_dma = im.maddr;
1653         base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1654         im.maddr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1655         if (isp->isp_type >= ISP_HA_FC_2200) {
1656                 isp->isp_osinfo.ecmd_dma = im.maddr;
1657                 isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)base;
1658                 isp->isp_osinfo.ecmd_base = isp->isp_osinfo.ecmd_free;
1659                 for (ecmd = isp->isp_osinfo.ecmd_free;
1660                     ecmd < &isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) {
1661                         if (ecmd == &isp->isp_osinfo.ecmd_free[N_XCMDS - 1])
1662                                 ecmd->next = NULL;
1663                         else
1664                                 ecmd->next = ecmd + 1;
1665                 }
1666         }
1667
1668         /*
1669          * Allocate and map the result queue.
1670          */
1671         len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1672         if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim,
1673             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1674             len, 1, len, 0, &isp->isp_osinfo.respdmat)) {
1675                 isp_prt(isp, ISP_LOGERR, "cannot create response DMA tag");
1676                 goto bad1;
1677         }
1678         if (bus_dmamem_alloc(isp->isp_osinfo.respdmat, (void **)&base,
1679             BUS_DMA_COHERENT, &isp->isp_osinfo.respmap) != 0) {
1680                 isp_prt(isp, ISP_LOGERR, "cannot allocate response DMA memory");
1681                 bus_dma_tag_destroy(isp->isp_osinfo.respdmat);
1682                 goto bad1;
1683         }
1684         isp->isp_result = base;
1685         im.error = 0;
1686         if (bus_dmamap_load(isp->isp_osinfo.respdmat, isp->isp_osinfo.respmap,
1687             base, len, imc, &im, 0) || im.error) {
1688                 isp_prt(isp, ISP_LOGERR, "error loading response DMA map %d", im.error);
1689                 goto bad1;
1690         }
1691         isp_prt(isp, ISP_LOGDEBUG0, "response area @ 0x%jx/0x%jx",
1692             (uintmax_t)im.maddr, (uintmax_t)len);
1693         isp->isp_result_dma = im.maddr;
1694
1695 #ifdef  ISP_TARGET_MODE
1696         /*
1697          * Allocate and map ATIO queue on 24xx with target mode.
1698          */
1699         if (IS_24XX(isp)) {
1700                 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1701                 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim,
1702                     BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1703                     len, 1, len, 0, &isp->isp_osinfo.atiodmat)) {
1704                         isp_prt(isp, ISP_LOGERR, "cannot create ATIO DMA tag");
1705                         goto bad1;
1706                 }
1707                 if (bus_dmamem_alloc(isp->isp_osinfo.atiodmat, (void **)&base,
1708                     BUS_DMA_COHERENT, &isp->isp_osinfo.atiomap) != 0) {
1709                         isp_prt(isp, ISP_LOGERR, "cannot allocate ATIO DMA memory");
1710                         bus_dma_tag_destroy(isp->isp_osinfo.atiodmat);
1711                         goto bad1;
1712                 }
1713                 isp->isp_atioq = base;
1714                 im.error = 0;
1715                 if (bus_dmamap_load(isp->isp_osinfo.atiodmat, isp->isp_osinfo.atiomap,
1716                     base, len, imc, &im, 0) || im.error) {
1717                         isp_prt(isp, ISP_LOGERR, "error loading ATIO DMA map %d", im.error);
1718                         goto bad;
1719                 }
1720                 isp_prt(isp, ISP_LOGDEBUG0, "ATIO area @ 0x%jx/0x%jx",
1721                     (uintmax_t)im.maddr, (uintmax_t)len);
1722                 isp->isp_atioq_dma = im.maddr;
1723         }
1724 #endif
1725
1726         if (IS_FC(isp)) {
1727                 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim,
1728                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1729                     2*QENTRY_LEN, 1, 2*QENTRY_LEN, 0, &isp->isp_osinfo.iocbdmat)) {
1730                         goto bad;
1731                 }
1732                 if (bus_dmamem_alloc(isp->isp_osinfo.iocbdmat,
1733                     (void **)&base, BUS_DMA_COHERENT, &isp->isp_osinfo.iocbmap) != 0)
1734                         goto bad;
1735                 isp->isp_iocb = base;
1736                 im.error = 0;
1737                 if (bus_dmamap_load(isp->isp_osinfo.iocbdmat, isp->isp_osinfo.iocbmap,
1738                     base, 2*QENTRY_LEN, imc, &im, 0) || im.error)
1739                         goto bad;
1740                 isp->isp_iocb_dma = im.maddr;
1741
1742                 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim,
1743                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1744                     ISP_FC_SCRLEN, 1, ISP_FC_SCRLEN, 0, &isp->isp_osinfo.scdmat))
1745                         goto bad;
1746                 for (cmap = 0; cmap < isp->isp_nchan; cmap++) {
1747                         struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1748                         if (bus_dmamem_alloc(isp->isp_osinfo.scdmat,
1749                             (void **)&base, BUS_DMA_COHERENT, &fc->scmap) != 0)
1750                                 goto bad;
1751                         FCPARAM(isp, cmap)->isp_scratch = base;
1752                         im.error = 0;
1753                         if (bus_dmamap_load(isp->isp_osinfo.scdmat, fc->scmap,
1754                             base, ISP_FC_SCRLEN, imc, &im, 0) || im.error) {
1755                                 bus_dmamem_free(isp->isp_osinfo.scdmat,
1756                                     base, fc->scmap);
1757                                 goto bad;
1758                         }
1759                         FCPARAM(isp, cmap)->isp_scdma = im.maddr;
1760                         if (!IS_2100(isp)) {
1761                                 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) {
1762                                         struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO);
1763                                         if (n == NULL) {
1764                                                 while (fc->nexus_free_list) {
1765                                                         n = fc->nexus_free_list;
1766                                                         fc->nexus_free_list = n->next;
1767                                                         free(n, M_DEVBUF);
1768                                                 }
1769                                                 goto bad;
1770                                         }
1771                                         n->next = fc->nexus_free_list;
1772                                         fc->nexus_free_list = n;
1773                                 }
1774                         }
1775                 }
1776         }
1777
1778         for (i = 0; i < isp->isp_maxcmds; i++) {
1779                 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i];
1780                 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap);
1781                 if (error) {
1782                         isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error);
1783                         while (--i >= 0) {
1784                                 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap);
1785                         }
1786                         goto bad;
1787                 }
1788                 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0);
1789                 if (i == isp->isp_maxcmds-1) {
1790                         pcmd->next = NULL;
1791                 } else {
1792                         pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1];
1793                 }
1794         }
1795         isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0];
1796         ISP_LOCK(isp);
1797         return (0);
1798
1799 bad:
1800         if (IS_FC(isp)) {
1801                 while (--cmap >= 0) {
1802                         struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1803                         bus_dmamap_unload(isp->isp_osinfo.scdmat, fc->scmap);
1804                         bus_dmamem_free(isp->isp_osinfo.scdmat,
1805                             FCPARAM(isp, cmap)->isp_scratch, fc->scmap);
1806                         while (fc->nexus_free_list) {
1807                                 struct isp_nexus *n = fc->nexus_free_list;
1808                                 fc->nexus_free_list = n->next;
1809                                 free(n, M_DEVBUF);
1810                         }
1811                 }
1812                 bus_dma_tag_destroy(isp->isp_osinfo.scdmat);
1813                 bus_dmamap_unload(isp->isp_osinfo.iocbdmat, isp->isp_osinfo.iocbmap);
1814                 bus_dmamem_free(isp->isp_osinfo.iocbdmat, isp->isp_iocb,
1815                     isp->isp_osinfo.iocbmap);
1816                 bus_dma_tag_destroy(isp->isp_osinfo.iocbdmat);
1817         }
1818 bad1:
1819         if (isp->isp_rquest_dma != 0) {
1820                 bus_dmamap_unload(isp->isp_osinfo.reqdmat,
1821                     isp->isp_osinfo.reqmap);
1822         }
1823         if (isp->isp_rquest != NULL) {
1824                 bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_rquest,
1825                     isp->isp_osinfo.reqmap);
1826                 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat);
1827         }
1828         if (isp->isp_result_dma != 0) {
1829                 bus_dmamap_unload(isp->isp_osinfo.respdmat,
1830                     isp->isp_osinfo.respmap);
1831         }
1832         if (isp->isp_result != NULL) {
1833                 bus_dmamem_free(isp->isp_osinfo.respdmat, isp->isp_result,
1834                     isp->isp_osinfo.respmap);
1835                 bus_dma_tag_destroy(isp->isp_osinfo.respdmat);
1836         }
1837 #ifdef  ISP_TARGET_MODE
1838         if (IS_24XX(isp)) {
1839                 if (isp->isp_atioq_dma != 0) {
1840                         bus_dmamap_unload(isp->isp_osinfo.atiodmat,
1841                             isp->isp_osinfo.atiomap);
1842                 }
1843                 if (isp->isp_atioq != NULL) {
1844                         bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_atioq,
1845                             isp->isp_osinfo.atiomap);
1846                         bus_dma_tag_destroy(isp->isp_osinfo.atiodmat);
1847                 }
1848         }
1849 #endif
1850         free(isp->isp_xflist, M_DEVBUF);
1851         free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1852         isp->isp_rquest = NULL;
1853         ISP_LOCK(isp);
1854         return (1);
1855 }
1856
1857 typedef struct {
1858         ispsoftc_t *isp;
1859         void *cmd_token;
1860         void *rq;       /* original request */
1861         int error;
1862         bus_size_t mapsize;
1863 } mush_t;
1864
1865 #define MUSHERR_NOQENTRIES      -2
1866
1867 #ifdef  ISP_TARGET_MODE
1868 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1869 static void tdma2(void *, bus_dma_segment_t *, int, int);
1870
1871 static void
1872 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1873 {
1874         mush_t *mp;
1875         mp = (mush_t *)arg;
1876         mp->mapsize = mapsize;
1877         tdma2(arg, dm_segs, nseg, error);
1878 }
1879
1880 static void
1881 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1882 {
1883         mush_t *mp;
1884         ispsoftc_t *isp;
1885         struct ccb_scsiio *csio;
1886         isp_ddir_t ddir;
1887         ispreq_t *rq;
1888
1889         mp = (mush_t *) arg;
1890         if (error) {
1891                 mp->error = error;
1892                 return;
1893         }
1894         csio = mp->cmd_token;
1895         isp = mp->isp;
1896         rq = mp->rq;
1897         if (nseg) {
1898                 if (isp->isp_osinfo.sixtyfourbit) {
1899                         if (nseg >= ISP_NSEG64_MAX) {
1900                                 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1901                                 mp->error = EFAULT;
1902                                 return;
1903                         }
1904                         if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) {
1905                                 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3;
1906                         }
1907                 } else {
1908                         if (nseg >= ISP_NSEG_MAX) {
1909                                 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1910                                 mp->error = EFAULT;
1911                                 return;
1912                         }
1913                 }
1914                 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1915                         bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1916                         ddir = ISP_TO_DEVICE;
1917                 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1918                         bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1919                         ddir = ISP_FROM_DEVICE;
1920                 } else {
1921                         dm_segs = NULL;
1922                         nseg = 0;
1923                         ddir = ISP_NOXFR;
1924                 }
1925         } else {
1926                 dm_segs = NULL;
1927                 nseg = 0;
1928                 ddir = ISP_NOXFR;
1929         }
1930
1931         error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len);
1932         switch (error) {
1933         case CMD_EAGAIN:
1934                 mp->error = MUSHERR_NOQENTRIES;
1935         case CMD_QUEUED:
1936                 break;
1937         default:
1938                 mp->error = EIO;
1939         }
1940 }
1941 #endif
1942
1943 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1944 static void dma2(void *, bus_dma_segment_t *, int, int);
1945
1946 static void
1947 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1948 {
1949         mush_t *mp;
1950         mp = (mush_t *)arg;
1951         mp->mapsize = mapsize;
1952         dma2(arg, dm_segs, nseg, error);
1953 }
1954
1955 static void
1956 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1957 {
1958         mush_t *mp;
1959         ispsoftc_t *isp;
1960         struct ccb_scsiio *csio;
1961         isp_ddir_t ddir;
1962         ispreq_t *rq;
1963
1964         mp = (mush_t *) arg;
1965         if (error) {
1966                 mp->error = error;
1967                 return;
1968         }
1969         csio = mp->cmd_token;
1970         isp = mp->isp;
1971         rq = mp->rq;
1972         if (nseg) {
1973                 if (isp->isp_osinfo.sixtyfourbit) {
1974                         if (nseg >= ISP_NSEG64_MAX) {
1975                                 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1976                                 mp->error = EFAULT;
1977                                 return;
1978                         }
1979                         if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1980                                 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1981                         } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1982                                 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1983                         }
1984                 } else {
1985                         if (nseg >= ISP_NSEG_MAX) {
1986                                 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1987                                 mp->error = EFAULT;
1988                                 return;
1989                         }
1990                 }
1991                 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1992                         bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1993                         ddir = ISP_FROM_DEVICE;
1994                 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1995                         bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1996                         ddir = ISP_TO_DEVICE;
1997                 } else {
1998                         ddir = ISP_NOXFR;
1999                 }
2000         } else {
2001                 dm_segs = NULL;
2002                 nseg = 0;
2003                 ddir = ISP_NOXFR;
2004         }
2005
2006         error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map);
2007         switch (error) {
2008         case CMD_EAGAIN:
2009                 mp->error = MUSHERR_NOQENTRIES;
2010                 break;
2011         case CMD_QUEUED:
2012                 break;
2013         default:
2014                 mp->error = EIO;
2015                 break;
2016         }
2017 }
2018
2019 static int
2020 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff)
2021 {
2022         mush_t mush, *mp;
2023         void (*eptr)(void *, bus_dma_segment_t *, int, int);
2024         void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int);
2025         int error;
2026
2027         mp = &mush;
2028         mp->isp = isp;
2029         mp->cmd_token = csio;
2030         mp->rq = ff;
2031         mp->error = 0;
2032         mp->mapsize = 0;
2033
2034 #ifdef  ISP_TARGET_MODE
2035         if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) {
2036                 eptr = tdma2;
2037                 eptr2 = tdma2_2;
2038         } else
2039 #endif
2040         {
2041                 eptr = dma2;
2042                 eptr2 = dma2_2;
2043         }
2044
2045
2046         error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap,
2047             (union ccb *)csio, eptr, mp, 0);
2048         if (error == EINPROGRESS) {
2049                 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap);
2050                 mp->error = EINVAL;
2051                 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported");
2052         } else if (error && mp->error == 0) {
2053 #ifdef  DIAGNOSTIC
2054                 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error);
2055 #endif
2056                 mp->error = error;
2057         }
2058         if (mp->error) {
2059                 int retval = CMD_COMPLETE;
2060                 if (mp->error == MUSHERR_NOQENTRIES) {
2061                         retval = CMD_EAGAIN;
2062                 } else if (mp->error == EFBIG) {
2063                         csio->ccb_h.status = CAM_REQ_TOO_BIG;
2064                 } else if (mp->error == EINVAL) {
2065                         csio->ccb_h.status = CAM_REQ_INVALID;
2066                 } else {
2067                         csio->ccb_h.status = CAM_UNREC_HBA_ERROR;
2068                 }
2069                 return (retval);
2070         }
2071         return (CMD_QUEUED);
2072 }
2073
2074 static void
2075 isp_pci_reset0(ispsoftc_t *isp)
2076 {
2077         ISP_DISABLE_INTS(isp);
2078 }
2079
2080 static void
2081 isp_pci_reset1(ispsoftc_t *isp)
2082 {
2083         if (!IS_24XX(isp)) {
2084                 /* Make sure the BIOS is disabled */
2085                 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
2086         }
2087         /* and enable interrupts */
2088         ISP_ENABLE_INTS(isp);
2089 }
2090
2091 static void
2092 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
2093 {
2094         struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2095         if (msg)
2096                 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);
2097         else
2098                 printf("%s:\n", device_get_nameunit(isp->isp_dev));
2099         if (IS_SCSI(isp))
2100                 printf("    biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
2101         else
2102                 printf("    biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
2103         printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
2104             ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
2105         printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
2106
2107
2108         if (IS_SCSI(isp)) {
2109                 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
2110                 printf("    cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
2111                         ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
2112                         ISP_READ(isp, CDMA_FIFO_STS));
2113                 printf("    ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
2114                         ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
2115                         ISP_READ(isp, DDMA_FIFO_STS));
2116                 printf("    sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
2117                         ISP_READ(isp, SXP_INTERRUPT),
2118                         ISP_READ(isp, SXP_GROSS_ERR),
2119                         ISP_READ(isp, SXP_PINS_CTRL));
2120                 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
2121         }
2122         printf("    mbox regs: %x %x %x %x %x\n",
2123             ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
2124             ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
2125             ISP_READ(isp, OUTMAILBOX4));
2126         printf("    PCI Status Command/Status=%x\n",
2127             pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1));
2128 }