2 * Copyright (c) 1997-2008 by Matthew Jacob
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice immediately at the beginning of the file, without modification,
10 * this list of conditions, and the following disclaimer.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/linker.h>
38 #include <sys/firmware.h>
40 #include <sys/stdint.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
46 #include <sys/malloc.h>
50 #include <dev/ofw/openfirm.h>
51 #include <machine/ofw_machdep.h>
54 #include <dev/isp/isp_freebsd.h>
56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int);
57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t);
58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
62 static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
65 static int isp_pci_mbxdma(ispsoftc_t *);
66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *);
69 static void isp_pci_reset0(ispsoftc_t *);
70 static void isp_pci_reset1(ispsoftc_t *);
71 static void isp_pci_dumpregs(ispsoftc_t *, const char *);
73 static struct ispmdvec mdvec = {
79 isp_common_dmateardown,
84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
87 static struct ispmdvec mdvec_1080 = {
93 isp_common_dmateardown,
98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
101 static struct ispmdvec mdvec_12160 = {
107 isp_common_dmateardown,
112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
115 static struct ispmdvec mdvec_2100 = {
121 isp_common_dmateardown,
127 static struct ispmdvec mdvec_2200 = {
133 isp_common_dmateardown,
139 static struct ispmdvec mdvec_2300 = {
145 isp_common_dmateardown,
151 static struct ispmdvec mdvec_2400 = {
157 isp_common_dmateardown,
163 static struct ispmdvec mdvec_2500 = {
169 isp_common_dmateardown,
175 #ifndef PCIM_CMD_INVEN
176 #define PCIM_CMD_INVEN 0x10
178 #ifndef PCIM_CMD_BUSMASTEREN
179 #define PCIM_CMD_BUSMASTEREN 0x0004
181 #ifndef PCIM_CMD_PERRESPEN
182 #define PCIM_CMD_PERRESPEN 0x0040
184 #ifndef PCIM_CMD_SEREN
185 #define PCIM_CMD_SEREN 0x0100
187 #ifndef PCIM_CMD_INTX_DISABLE
188 #define PCIM_CMD_INTX_DISABLE 0x0400
192 #define PCIR_COMMAND 0x04
195 #ifndef PCIR_CACHELNSZ
196 #define PCIR_CACHELNSZ 0x0c
199 #ifndef PCIR_LATTIMER
200 #define PCIR_LATTIMER 0x0d
204 #define PCIR_ROMADDR 0x30
207 #ifndef PCI_VENDOR_QLOGIC
208 #define PCI_VENDOR_QLOGIC 0x1077
211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160
220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016
223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322
252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322
255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422
256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422
259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432
260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432
263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532
264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532
267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312
268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312
271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322
272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322
275 #ifndef PCI_PRODUCT_QLOGIC_ISP5432
276 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432
279 #define PCI_QLOGIC_ISP5432 \
280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC)
282 #define PCI_QLOGIC_ISP1020 \
283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
285 #define PCI_QLOGIC_ISP1080 \
286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
288 #define PCI_QLOGIC_ISP10160 \
289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
291 #define PCI_QLOGIC_ISP12160 \
292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
294 #define PCI_QLOGIC_ISP1240 \
295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
297 #define PCI_QLOGIC_ISP1280 \
298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
300 #define PCI_QLOGIC_ISP2100 \
301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
303 #define PCI_QLOGIC_ISP2200 \
304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
306 #define PCI_QLOGIC_ISP2300 \
307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
309 #define PCI_QLOGIC_ISP2312 \
310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
312 #define PCI_QLOGIC_ISP2322 \
313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
315 #define PCI_QLOGIC_ISP2422 \
316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
318 #define PCI_QLOGIC_ISP2432 \
319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
321 #define PCI_QLOGIC_ISP2532 \
322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
324 #define PCI_QLOGIC_ISP6312 \
325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
327 #define PCI_QLOGIC_ISP6322 \
328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
331 * Odd case for some AMI raid cards... We need to *not* attach to this.
333 #define AMI_RAID_SUBVENDOR_ID 0x101e
335 #define IO_MAP_REG 0x10
336 #define MEM_MAP_REG 0x14
338 #define PCI_DFLT_LTNCY 0x40
339 #define PCI_DFLT_LNSZ 0x10
341 static int isp_pci_probe (device_t);
342 static int isp_pci_attach (device_t);
343 static int isp_pci_detach (device_t);
346 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev
347 struct isp_pcisoftc {
350 struct resource * regs;
356 int16_t pci_poff[_NREG_BLKS];
362 static device_method_t isp_pci_methods[] = {
363 /* Device interface */
364 DEVMETHOD(device_probe, isp_pci_probe),
365 DEVMETHOD(device_attach, isp_pci_attach),
366 DEVMETHOD(device_detach, isp_pci_detach),
370 static driver_t isp_pci_driver = {
371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
373 static devclass_t isp_devclass;
374 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0);
375 MODULE_DEPEND(isp, cam, 1, 1, 1);
376 MODULE_DEPEND(isp, firmware, 1, 1, 1);
377 static int isp_nvports = 0;
380 isp_pci_probe(device_t dev)
382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) {
383 case PCI_QLOGIC_ISP1020:
384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter");
386 case PCI_QLOGIC_ISP1080:
387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter");
389 case PCI_QLOGIC_ISP1240:
390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter");
392 case PCI_QLOGIC_ISP1280:
393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter");
395 case PCI_QLOGIC_ISP10160:
396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter");
398 case PCI_QLOGIC_ISP12160:
399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) {
402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter");
404 case PCI_QLOGIC_ISP2100:
405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter");
407 case PCI_QLOGIC_ISP2200:
408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter");
410 case PCI_QLOGIC_ISP2300:
411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
413 case PCI_QLOGIC_ISP2312:
414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
416 case PCI_QLOGIC_ISP2322:
417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
419 case PCI_QLOGIC_ISP2422:
420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
422 case PCI_QLOGIC_ISP2432:
423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter");
425 case PCI_QLOGIC_ISP2532:
426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter");
428 case PCI_QLOGIC_ISP5432:
429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter");
431 case PCI_QLOGIC_ISP6312:
432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
434 case PCI_QLOGIC_ISP6322:
435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
440 if (isp_announced == 0 && bootverbose) {
441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, "
442 "Core Version %d.%d\n",
443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
448 * XXXX: Here is where we might load the f/w module
449 * XXXX: (or increase a reference count to it).
451 return (BUS_PROBE_DEFAULT);
455 isp_get_generic_options(device_t dev, ispsoftc_t *isp)
460 * Figure out if we're supposed to skip this one.
463 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) {
464 device_printf(dev, "disabled at user request\n");
465 isp->isp_osinfo.disabled = 1;
470 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) {
471 isp->isp_confopts |= ISP_CFG_NORELOAD;
474 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) {
475 isp->isp_confopts |= ISP_CFG_NONVRAM;
478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval);
480 isp->isp_dblev = tval;
482 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
485 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval);
489 if (tval > 0 && tval <= 254) {
493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval);
494 isp_quickboot_time = tval;
498 isp_get_pci_options(device_t dev, int *m1, int *m2)
502 * Which we should try first - memory mapping or i/o mapping?
504 * We used to try memory first followed by i/o on alpha, otherwise
505 * the reverse, but we should just try memory first all the time now.
507 *m1 = PCIM_CMD_MEMEN;
508 *m2 = PCIM_CMD_PORTEN;
511 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) {
512 *m1 = PCIM_CMD_PORTEN;
513 *m2 = PCIM_CMD_MEMEN;
516 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) {
517 *m1 = PCIM_CMD_MEMEN;
518 *m2 = PCIM_CMD_PORTEN;
523 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp)
527 char prefix[12], name[16];
532 snprintf(prefix, sizeof(prefix), "chan%d.", chan);
533 snprintf(name, sizeof(name), "%siid", prefix);
534 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
537 ISP_FC_PC(isp, chan)->default_id = 109 - chan;
540 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev);
542 ISP_SPI_PC(isp, chan)->iid = 7;
547 ISP_FC_PC(isp, chan)->default_id = tval - chan;
549 ISP_SPI_PC(isp, chan)->iid = tval;
551 isp->isp_confopts |= ISP_CFG_OWNLOOPID;
558 snprintf(name, sizeof(name), "%srole", prefix);
559 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
563 case ISP_ROLE_INITIATOR:
564 case ISP_ROLE_TARGET:
566 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval);
574 tval = ISP_DEFAULT_ROLES;
576 ISP_FC_PC(isp, chan)->def_role = tval;
579 snprintf(name, sizeof(name), "%sfullduplex", prefix);
580 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
581 name, &tval) == 0 && tval != 0) {
582 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX;
585 snprintf(name, sizeof(name), "%stopology", prefix);
586 if (resource_string_value(device_get_name(dev), device_get_unit(dev),
587 name, (const char **) &sptr) == 0 && sptr != 0) {
588 if (strcmp(sptr, "lport") == 0) {
589 isp->isp_confopts |= ISP_CFG_LPORT;
590 } else if (strcmp(sptr, "nport") == 0) {
591 isp->isp_confopts |= ISP_CFG_NPORT;
592 } else if (strcmp(sptr, "lport-only") == 0) {
593 isp->isp_confopts |= ISP_CFG_LPORT_ONLY;
594 } else if (strcmp(sptr, "nport-only") == 0) {
595 isp->isp_confopts |= ISP_CFG_NPORT_ONLY;
600 snprintf(name, sizeof(name), "%snofctape", prefix);
601 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
604 isp->isp_confopts |= ISP_CFG_NOFCTAPE;
608 snprintf(name, sizeof(name), "%sfctape", prefix);
609 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
612 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE;
613 isp->isp_confopts |= ISP_CFG_FCTAPE;
618 * Because the resource_*_value functions can neither return
619 * 64 bit integer values, nor can they be directly coerced
620 * to interpret the right hand side of the assignment as
621 * you want them to interpret it, we have to force WWN
622 * hint replacement to specify WWN strings with a leading
623 * 'w' (e..g w50000000aaaa0001). Sigh.
626 snprintf(name, sizeof(name), "%sportwwn", prefix);
627 tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
628 name, (const char **) &sptr);
629 if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
631 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16);
632 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) {
633 device_printf(dev, "mangled portwwn hint '%s'\n", sptr);
634 ISP_FC_PC(isp, chan)->def_wwpn = 0;
639 snprintf(name, sizeof(name), "%snodewwn", prefix);
640 tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
641 name, (const char **) &sptr);
642 if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
644 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16);
645 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) {
646 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr);
647 ISP_FC_PC(isp, chan)->def_wwnn = 0;
652 snprintf(name, sizeof(name), "%shysteresis", prefix);
653 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
655 if (tval >= 0 && tval < 256) {
656 ISP_FC_PC(isp, chan)->hysteresis = tval;
658 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis;
662 snprintf(name, sizeof(name), "%sloop_down_limit", prefix);
663 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
665 if (tval >= 0 && tval < 0xffff) {
666 ISP_FC_PC(isp, chan)->loop_down_limit = tval;
668 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit;
672 snprintf(name, sizeof(name), "%sgone_device_time", prefix);
673 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
675 if (tval >= 0 && tval < 0xffff) {
676 ISP_FC_PC(isp, chan)->gone_device_time = tval;
678 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time;
683 isp_pci_attach(device_t dev)
685 int i, m1, m2, locksetup = 0;
686 uint32_t data, cmd, linesz, did;
687 struct isp_pcisoftc *pcs;
692 pcs = device_get_softc(dev);
694 device_printf(dev, "cannot get softc\n");
697 memset(pcs, 0, sizeof (*pcs));
703 if (sizeof (bus_addr_t) > 4)
704 isp->isp_osinfo.sixtyfourbit = 1;
707 * Get Generic Options
710 isp_get_generic_options(dev, isp);
713 * Check to see if options have us disabled
715 if (isp->isp_osinfo.disabled) {
717 * But return zero to preserve unit numbering
723 * Get PCI options- which in this case are just mapping preferences.
725 isp_get_pci_options(dev, &m1, &m2);
727 linesz = PCI_DFLT_LNSZ;
728 pcs->irq = pcs->regs = NULL;
729 pcs->rgd = pcs->rtp = pcs->iqd = 0;
731 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
732 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
733 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
734 if (pcs->regs == NULL) {
735 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
736 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG;
737 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE);
739 if (pcs->regs == NULL) {
740 device_printf(dev, "unable to map any ports\n");
744 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory");
746 isp->isp_bus_tag = rman_get_bustag(pcs->regs);
747 isp->isp_bus_handle = rman_get_bushandle(pcs->regs);
750 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
751 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
752 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
753 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
754 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
756 switch (pci_get_devid(dev)) {
757 case PCI_QLOGIC_ISP1020:
759 isp->isp_mdvec = &mdvec;
760 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
762 case PCI_QLOGIC_ISP1080:
764 isp->isp_mdvec = &mdvec_1080;
765 isp->isp_type = ISP_HA_SCSI_1080;
766 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
768 case PCI_QLOGIC_ISP1240:
770 isp->isp_mdvec = &mdvec_1080;
771 isp->isp_type = ISP_HA_SCSI_1240;
773 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
775 case PCI_QLOGIC_ISP1280:
777 isp->isp_mdvec = &mdvec_1080;
778 isp->isp_type = ISP_HA_SCSI_1280;
779 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
781 case PCI_QLOGIC_ISP10160:
783 isp->isp_mdvec = &mdvec_12160;
784 isp->isp_type = ISP_HA_SCSI_10160;
785 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
787 case PCI_QLOGIC_ISP12160:
790 isp->isp_mdvec = &mdvec_12160;
791 isp->isp_type = ISP_HA_SCSI_12160;
792 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
794 case PCI_QLOGIC_ISP2100:
796 isp->isp_mdvec = &mdvec_2100;
797 isp->isp_type = ISP_HA_FC_2100;
798 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
799 if (pci_get_revid(dev) < 3) {
801 * XXX: Need to get the actual revision
802 * XXX: number of the 2100 FB. At any rate,
803 * XXX: lower cache line size for early revision
809 case PCI_QLOGIC_ISP2200:
811 isp->isp_mdvec = &mdvec_2200;
812 isp->isp_type = ISP_HA_FC_2200;
813 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
815 case PCI_QLOGIC_ISP2300:
817 isp->isp_mdvec = &mdvec_2300;
818 isp->isp_type = ISP_HA_FC_2300;
819 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
821 case PCI_QLOGIC_ISP2312:
822 case PCI_QLOGIC_ISP6312:
824 isp->isp_mdvec = &mdvec_2300;
825 isp->isp_type = ISP_HA_FC_2312;
826 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
828 case PCI_QLOGIC_ISP2322:
829 case PCI_QLOGIC_ISP6322:
831 isp->isp_mdvec = &mdvec_2300;
832 isp->isp_type = ISP_HA_FC_2322;
833 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
835 case PCI_QLOGIC_ISP2422:
836 case PCI_QLOGIC_ISP2432:
838 isp->isp_nchan += isp_nvports;
839 isp->isp_mdvec = &mdvec_2400;
840 isp->isp_type = ISP_HA_FC_2400;
841 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
843 case PCI_QLOGIC_ISP2532:
845 isp->isp_nchan += isp_nvports;
846 isp->isp_mdvec = &mdvec_2500;
847 isp->isp_type = ISP_HA_FC_2500;
848 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
850 case PCI_QLOGIC_ISP5432:
852 isp->isp_mdvec = &mdvec_2500;
853 isp->isp_type = ISP_HA_FC_2500;
854 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
857 device_printf(dev, "unknown device type\n");
861 isp->isp_revision = pci_get_revid(dev);
864 psize = sizeof (fcparam);
865 xsize = sizeof (struct isp_fc);
867 psize = sizeof (sdparam);
868 xsize = sizeof (struct isp_spi);
870 psize *= isp->isp_nchan;
871 xsize *= isp->isp_nchan;
872 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
873 if (isp->isp_param == NULL) {
874 device_printf(dev, "cannot allocate parameter data\n");
877 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO);
878 if (isp->isp_osinfo.pc.ptr == NULL) {
879 device_printf(dev, "cannot allocate parameter data\n");
884 * Now that we know who we are (roughly) get/set specific options
886 for (i = 0; i < isp->isp_nchan; i++) {
887 isp_get_specific_options(dev, i, isp);
890 isp->isp_osinfo.fw = NULL;
891 if (isp->isp_osinfo.fw == NULL) {
892 snprintf(fwname, sizeof (fwname), "isp_%04x", did);
893 isp->isp_osinfo.fw = firmware_get(fwname);
895 if (isp->isp_osinfo.fw != NULL) {
896 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname);
897 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data;
901 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
903 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
904 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
905 if (IS_2300(isp)) { /* per QLogic errata */
906 cmd &= ~PCIM_CMD_INVEN;
908 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
909 cmd &= ~PCIM_CMD_INTX_DISABLE;
912 cmd &= ~PCIM_CMD_INTX_DISABLE;
914 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
917 * Make sure the Cache Line Size register is set sensibly.
919 data = pci_read_config(dev, PCIR_CACHELNSZ, 1);
920 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) {
921 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data);
923 pci_write_config(dev, PCIR_CACHELNSZ, data, 1);
927 * Make sure the Latency Timer is sane.
929 data = pci_read_config(dev, PCIR_LATTIMER, 1);
930 if (data < PCI_DFLT_LTNCY) {
931 data = PCI_DFLT_LTNCY;
932 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data);
933 pci_write_config(dev, PCIR_LATTIMER, data, 1);
937 * Make sure we've disabled the ROM.
939 data = pci_read_config(dev, PCIR_ROMADDR, 4);
941 pci_write_config(dev, PCIR_ROMADDR, data, 4);
946 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express)
948 if (IS_24XX(isp) || IS_2322(isp)) {
949 pcs->msicount = pci_msi_count(dev);
950 if (pcs->msicount > 1) {
953 if (pci_alloc_msi(dev, &pcs->msicount) == 0) {
959 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE);
960 if (pcs->irq == NULL) {
961 device_printf(dev, "could not allocate interrupt\n");
965 /* Make sure the lock is set up. */
966 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF);
969 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) {
970 device_printf(dev, "could not setup interrupt\n");
975 * Last minute checks...
977 if (IS_23XX(isp) || IS_24XX(isp)) {
978 isp->isp_port = pci_get_function(dev);
982 * Make sure we're in reset state.
985 if (isp_reinit(isp, 1) != 0) {
990 if (isp_attach(isp)) {
1000 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1003 mtx_destroy(&isp->isp_osinfo.lock);
1006 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1008 if (pcs->msicount) {
1009 pci_release_msi(dev);
1012 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1014 if (pcs->pci_isp.isp_param) {
1015 free(pcs->pci_isp.isp_param, M_DEVBUF);
1016 pcs->pci_isp.isp_param = NULL;
1018 if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1019 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1020 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1026 isp_pci_detach(device_t dev)
1028 struct isp_pcisoftc *pcs;
1032 pcs = device_get_softc(dev);
1036 isp = (ispsoftc_t *) pcs;
1037 status = isp_detach(isp);
1043 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1046 mtx_destroy(&isp->isp_osinfo.lock);
1047 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1048 if (pcs->msicount) {
1049 pci_release_msi(dev);
1051 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1053 * XXX: THERE IS A LOT OF LEAKAGE HERE
1055 if (pcs->pci_isp.isp_param) {
1056 free(pcs->pci_isp.isp_param, M_DEVBUF);
1057 pcs->pci_isp.isp_param = NULL;
1059 if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1060 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1061 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1066 #define IspVirt2Off(a, x) \
1067 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1068 _BLK_REG_SHFT] + ((x) & 0xfff))
1070 #define BXR2(isp, off) \
1071 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off)
1072 #define BXW2(isp, off, v) \
1073 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v)
1074 #define BXR4(isp, off) \
1075 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off)
1076 #define BXW4(isp, off, v) \
1077 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v)
1080 static ISP_INLINE int
1081 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1083 uint32_t val0, val1;
1087 val0 = BXR2(isp, IspVirt2Off(isp, off));
1088 val1 = BXR2(isp, IspVirt2Off(isp, off));
1089 } while (val0 != val1 && ++i < 1000);
1098 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1103 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1106 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
1110 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR));
1111 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA));
1113 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
1114 isr &= INT_PENDING_MASK(isp);
1115 sema &= BIU_SEMA_LOCK;
1116 if (isr == 0 && sema == 0) {
1120 if ((*semap = sema) != 0) {
1122 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, info)) {
1126 *info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0));
1133 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1135 uint32_t hccr, r2hisr;
1137 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1141 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO));
1142 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1143 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1147 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1148 case ISPR2HST_ROM_MBX_OK:
1149 case ISPR2HST_ROM_MBX_FAIL:
1150 case ISPR2HST_MBX_OK:
1151 case ISPR2HST_MBX_FAIL:
1152 case ISPR2HST_ASYNC_EVENT:
1155 case ISPR2HST_RIO_16:
1156 *info = ASYNC_RIO16_1;
1159 case ISPR2HST_FPOST:
1160 *info = ASYNC_CMD_CMPLT;
1163 case ISPR2HST_FPOST_CTIO:
1164 *info = ASYNC_CTIO_DONE;
1167 case ISPR2HST_RSPQ_UPDATE:
1171 hccr = ISP_READ(isp, HCCR);
1172 if (hccr & HCCR_PAUSE) {
1173 ISP_WRITE(isp, HCCR, HCCR_RESET);
1174 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR));
1175 ISP_WRITE(isp, BIU_ICR, 0);
1177 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1181 *info = (r2hisr >> 16);
1186 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1190 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO));
1191 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1192 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1196 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1197 case ISPR2HST_ROM_MBX_OK:
1198 case ISPR2HST_ROM_MBX_FAIL:
1199 case ISPR2HST_MBX_OK:
1200 case ISPR2HST_MBX_FAIL:
1201 case ISPR2HST_ASYNC_EVENT:
1204 case ISPR2HST_RSPQ_UPDATE:
1205 case ISPR2HST_RSPQ_UPDATE2:
1206 case ISPR2HST_ATIO_UPDATE:
1207 case ISPR2HST_ATIO_RSPQ_UPDATE:
1208 case ISPR2HST_ATIO_UPDATE2:
1212 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
1213 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1216 *info = (r2hisr >> 16);
1221 isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1226 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1228 * We will assume that someone has paused the RISC processor.
1230 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1231 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP);
1232 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1234 rv = BXR2(isp, IspVirt2Off(isp, regoff));
1235 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1236 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1237 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1243 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val)
1247 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1249 * We will assume that someone has paused the RISC processor.
1251 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1252 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1253 oldconf | BIU_PCI_CONF1_SXP);
1254 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1256 BXW2(isp, IspVirt2Off(isp, regoff), val);
1257 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1258 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1259 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1260 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1266 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1268 uint32_t rv, oc = 0;
1270 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1273 * We will assume that someone has paused the RISC processor.
1275 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1276 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1277 if (regoff & SXP_BANK1_SELECT)
1278 tc |= BIU_PCI1080_CONF1_SXP1;
1280 tc |= BIU_PCI1080_CONF1_SXP0;
1281 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1282 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1283 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1284 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1285 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1286 oc | BIU_PCI1080_CONF1_DMA);
1287 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1289 rv = BXR2(isp, IspVirt2Off(isp, regoff));
1291 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1292 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1298 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val)
1302 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1305 * We will assume that someone has paused the RISC processor.
1307 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1308 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1309 if (regoff & SXP_BANK1_SELECT)
1310 tc |= BIU_PCI1080_CONF1_SXP1;
1312 tc |= BIU_PCI1080_CONF1_SXP0;
1313 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1314 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1315 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1316 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1317 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1318 oc | BIU_PCI1080_CONF1_DMA);
1319 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1321 BXW2(isp, IspVirt2Off(isp, regoff), val);
1322 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1324 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1325 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1330 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
1333 int block = regoff & _BLK_REG_MASK;
1339 return (BXR2(isp, IspVirt2Off(isp, regoff)));
1341 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
1342 return (0xffffffff);
1344 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
1345 return (0xffffffff);
1347 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
1348 return (0xffffffff);
1350 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
1351 return (0xffffffff);
1356 case BIU2400_FLASH_ADDR:
1357 case BIU2400_FLASH_DATA:
1361 case BIU2400_REQINP:
1362 case BIU2400_REQOUTP:
1363 case BIU2400_RSPINP:
1364 case BIU2400_RSPOUTP:
1365 case BIU2400_PRI_REQINP:
1366 case BIU2400_PRI_REQOUTP:
1367 case BIU2400_ATIO_RSPINP:
1368 case BIU2400_ATIO_RSPOUTP:
1373 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1375 case BIU2400_R2HSTSLO:
1376 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1378 case BIU2400_R2HSTSHI:
1379 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16;
1382 isp_prt(isp, ISP_LOGERR,
1383 "isp_pci_rd_reg_2400: unknown offset %x", regoff);
1391 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1393 int block = regoff & _BLK_REG_MASK;
1399 BXW2(isp, IspVirt2Off(isp, regoff), val);
1400 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1403 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
1406 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
1409 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
1412 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
1418 case BIU2400_FLASH_ADDR:
1419 case BIU2400_FLASH_DATA:
1423 case BIU2400_REQINP:
1424 case BIU2400_REQOUTP:
1425 case BIU2400_RSPINP:
1426 case BIU2400_RSPOUTP:
1427 case BIU2400_PRI_REQINP:
1428 case BIU2400_PRI_REQOUTP:
1429 case BIU2400_ATIO_RSPINP:
1430 case BIU2400_ATIO_RSPOUTP:
1435 BXW4(isp, IspVirt2Off(isp, regoff), val);
1436 #ifdef MEMORYBARRIERW
1437 if (regoff == BIU2400_REQINP ||
1438 regoff == BIU2400_RSPOUTP ||
1439 regoff == BIU2400_PRI_REQINP ||
1440 regoff == BIU2400_ATIO_RSPOUTP)
1441 MEMORYBARRIERW(isp, SYNC_REG,
1442 IspVirt2Off(isp, regoff), 4, -1)
1445 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
1448 isp_prt(isp, ISP_LOGERR,
1449 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
1462 static void imc(void *, bus_dma_segment_t *, int, int);
1463 static void imc1(void *, bus_dma_segment_t *, int, int);
1466 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1468 struct imush *imushp = (struct imush *) arg;
1472 imushp->error = error;
1476 imushp->error = EINVAL;
1479 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
1481 imushp->isp->isp_rquest = imushp->vbase;
1482 imushp->isp->isp_rquest_dma = segs->ds_addr;
1483 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
1484 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
1486 imushp->isp->isp_result_dma = segs->ds_addr;
1487 imushp->isp->isp_result = imushp->vbase;
1488 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp));
1489 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp));
1491 if (imushp->isp->isp_type >= ISP_HA_FC_2200) {
1492 imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr;
1493 imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase;
1494 imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free;
1495 for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) {
1496 if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) {
1499 ecmd->next = ecmd + 1;
1503 #ifdef ISP_TARGET_MODE
1504 segs->ds_addr += (N_XCMDS * XCMD_SIZE);
1505 imushp->vbase += (N_XCMDS * XCMD_SIZE);
1506 if (IS_24XX(imushp->isp)) {
1507 imushp->isp->isp_atioq_dma = segs->ds_addr;
1508 imushp->isp->isp_atioq = imushp->vbase;
1514 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1516 struct imush *imushp = (struct imush *) arg;
1518 imushp->error = error;
1522 imushp->error = EINVAL;
1525 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
1526 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr;
1527 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase;
1531 isp_pci_mbxdma(ispsoftc_t *isp)
1534 uint32_t len, nsegs;
1535 int i, error, cmap = 0;
1536 bus_size_t slim; /* segment size */
1537 bus_addr_t llim; /* low limit of unavailable dma */
1538 bus_addr_t hlim; /* high limit of unavailable dma */
1542 * Already been here? If so, leave...
1544 if (isp->isp_rquest) {
1549 if (isp->isp_maxcmds == 0) {
1550 isp_prt(isp, ISP_LOGERR, "maxcmds not set");
1555 hlim = BUS_SPACE_MAXADDR;
1556 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1557 if (sizeof (bus_size_t) > 4) {
1558 slim = (bus_size_t) (1ULL << 32);
1560 slim = (bus_size_t) (1UL << 31);
1562 llim = BUS_SPACE_MAXADDR;
1564 llim = BUS_SPACE_MAXADDR_32BIT;
1568 len = isp->isp_maxcmds * sizeof (struct isp_pcmd);
1569 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1570 if (isp->isp_osinfo.pcmd_pool == NULL) {
1571 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds");
1576 if (isp->isp_osinfo.sixtyfourbit) {
1577 nsegs = ISP_NSEG64_MAX;
1579 nsegs = ISP_NSEG_MAX;
1582 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) {
1583 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1585 isp_prt(isp, ISP_LOGERR, "could not create master dma tag");
1589 len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1590 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1591 if (isp->isp_xflist == NULL) {
1592 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1594 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array");
1597 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1598 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1600 isp->isp_xffree = isp->isp_xflist;
1601 #ifdef ISP_TARGET_MODE
1602 len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1603 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1604 if (isp->isp_tgtlist == NULL) {
1605 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1606 free(isp->isp_xflist, M_DEVBUF);
1608 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array");
1611 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1612 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1];
1614 isp->isp_tgtfree = isp->isp_tgtlist;
1618 * Allocate and map the request and result queues (and ATIO queue
1619 * if we're a 2400 supporting target mode), and a region for
1620 * external dma addressable command/status structures (23XX and
1623 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1624 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1625 #ifdef ISP_TARGET_MODE
1627 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1630 if (isp->isp_type >= ISP_HA_FC_2200) {
1631 len += (N_XCMDS * XCMD_SIZE);
1635 * Create a tag for the control spaces. We don't always need this
1636 * to be 32 bits, but we do this for simplicity and speed's sake.
1638 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, slim, 0, &isp->isp_osinfo.cdmat)) {
1639 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces");
1640 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1641 free(isp->isp_xflist, M_DEVBUF);
1642 #ifdef ISP_TARGET_MODE
1643 free(isp->isp_tgtlist, M_DEVBUF);
1649 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) {
1650 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len);
1651 bus_dma_tag_destroy(isp->isp_osinfo.cdmat);
1652 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1653 free(isp->isp_xflist, M_DEVBUF);
1654 #ifdef ISP_TARGET_MODE
1655 free(isp->isp_tgtlist, M_DEVBUF);
1666 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0);
1668 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error);
1673 for (cmap = 0; cmap < isp->isp_nchan; cmap++) {
1674 struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1675 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) {
1678 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) {
1679 bus_dma_tag_destroy(fc->tdmat);
1686 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0);
1688 bus_dmamem_free(fc->tdmat, base, fc->tdmap);
1689 bus_dma_tag_destroy(fc->tdmat);
1692 if (!IS_2100(isp)) {
1693 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) {
1694 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO);
1696 while (fc->nexus_free_list) {
1697 n = fc->nexus_free_list;
1698 fc->nexus_free_list = n->next;
1703 n->next = fc->nexus_free_list;
1704 fc->nexus_free_list = n;
1710 for (i = 0; i < isp->isp_maxcmds; i++) {
1711 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i];
1712 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap);
1714 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error);
1716 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap);
1720 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0);
1721 if (i == isp->isp_maxcmds-1) {
1724 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1];
1727 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0];
1732 while (--cmap >= 0) {
1733 struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1734 bus_dmamem_free(fc->tdmat, base, fc->tdmap);
1735 bus_dma_tag_destroy(fc->tdmat);
1736 while (fc->nexus_free_list) {
1737 struct isp_nexus *n = fc->nexus_free_list;
1738 fc->nexus_free_list = n->next;
1742 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap);
1743 bus_dma_tag_destroy(isp->isp_osinfo.cdmat);
1744 free(isp->isp_xflist, M_DEVBUF);
1745 #ifdef ISP_TARGET_MODE
1746 free(isp->isp_tgtlist, M_DEVBUF);
1748 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1749 isp->isp_rquest = NULL;
1757 void *rq; /* original request */
1762 #define MUSHERR_NOQENTRIES -2
1764 #ifdef ISP_TARGET_MODE
1765 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1766 static void tdma2(void *, bus_dma_segment_t *, int, int);
1769 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1773 mp->mapsize = mapsize;
1774 tdma2(arg, dm_segs, nseg, error);
1778 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1782 struct ccb_scsiio *csio;
1786 mp = (mush_t *) arg;
1791 csio = mp->cmd_token;
1795 if (isp->isp_osinfo.sixtyfourbit) {
1796 if (nseg >= ISP_NSEG64_MAX) {
1797 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1801 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) {
1802 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3;
1805 if (nseg >= ISP_NSEG_MAX) {
1806 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1811 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1812 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1813 ddir = ISP_TO_DEVICE;
1814 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1815 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1816 ddir = ISP_FROM_DEVICE;
1828 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len);
1831 mp->error = MUSHERR_NOQENTRIES;
1840 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1841 static void dma2(void *, bus_dma_segment_t *, int, int);
1844 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1848 mp->mapsize = mapsize;
1849 dma2(arg, dm_segs, nseg, error);
1853 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1857 struct ccb_scsiio *csio;
1861 mp = (mush_t *) arg;
1866 csio = mp->cmd_token;
1870 if (isp->isp_osinfo.sixtyfourbit) {
1871 if (nseg >= ISP_NSEG64_MAX) {
1872 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1876 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1877 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1878 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1879 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1882 if (nseg >= ISP_NSEG_MAX) {
1883 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1888 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1889 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1890 ddir = ISP_FROM_DEVICE;
1891 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1892 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1893 ddir = ISP_TO_DEVICE;
1903 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map);
1906 mp->error = MUSHERR_NOQENTRIES;
1917 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff)
1920 void (*eptr)(void *, bus_dma_segment_t *, int, int);
1921 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int);
1926 mp->cmd_token = csio;
1931 #ifdef ISP_TARGET_MODE
1932 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) {
1943 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap,
1944 (union ccb *)csio, eptr, mp, 0);
1945 if (error == EINPROGRESS) {
1946 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap);
1948 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported");
1949 } else if (error && mp->error == 0) {
1951 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error);
1956 int retval = CMD_COMPLETE;
1957 if (mp->error == MUSHERR_NOQENTRIES) {
1958 retval = CMD_EAGAIN;
1959 } else if (mp->error == EFBIG) {
1960 csio->ccb_h.status = CAM_REQ_TOO_BIG;
1961 } else if (mp->error == EINVAL) {
1962 csio->ccb_h.status = CAM_REQ_INVALID;
1964 csio->ccb_h.status = CAM_UNREC_HBA_ERROR;
1968 return (CMD_QUEUED);
1972 isp_pci_reset0(ispsoftc_t *isp)
1974 ISP_DISABLE_INTS(isp);
1978 isp_pci_reset1(ispsoftc_t *isp)
1980 if (!IS_24XX(isp)) {
1981 /* Make sure the BIOS is disabled */
1982 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
1984 /* and enable interrupts */
1985 ISP_ENABLE_INTS(isp);
1989 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
1991 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1993 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);
1995 printf("%s:\n", device_get_nameunit(isp->isp_dev));
1997 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
1999 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
2000 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
2001 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
2002 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
2006 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
2007 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
2008 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
2009 ISP_READ(isp, CDMA_FIFO_STS));
2010 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
2011 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
2012 ISP_READ(isp, DDMA_FIFO_STS));
2013 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
2014 ISP_READ(isp, SXP_INTERRUPT),
2015 ISP_READ(isp, SXP_GROSS_ERR),
2016 ISP_READ(isp, SXP_PINS_CTRL));
2017 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
2019 printf(" mbox regs: %x %x %x %x %x\n",
2020 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
2021 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
2022 ISP_READ(isp, OUTMAILBOX4));
2023 printf(" PCI Status Command/Status=%x\n",
2024 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1));