2 * Copyright (c) 2007-2009
3 * Damien Bergamini <damien.bergamini@free.fr>
5 * Benjamin Close <benjsc@FreeBSD.org>
6 * Copyright (c) 2008 Sam Leffler, Errno Consulting
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/sysctl.h>
33 #include <sys/kernel.h>
34 #include <sys/socket.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
39 #include <sys/endian.h>
40 #include <sys/firmware.h>
41 #include <sys/limits.h>
42 #include <sys/module.h>
43 #include <sys/queue.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/clock.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
55 #include <net/if_arp.h>
56 #include <net/ethernet.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/if_ether.h>
65 #include <netinet/ip.h>
67 #include <net80211/ieee80211_var.h>
68 #include <net80211/ieee80211_radiotap.h>
69 #include <net80211/ieee80211_regdomain.h>
70 #include <net80211/ieee80211_ratectl.h>
72 #include <dev/iwn/if_iwnreg.h>
73 #include <dev/iwn/if_iwnvar.h>
81 static const struct iwn_ident iwn_ident_table[] = {
82 { 0x8086, 0x0082, "Intel(R) Centrino(R) Advanced-N 6205" },
83 { 0x8086, 0x0083, "Intel(R) Centrino(R) Wireless-N 1000" },
84 { 0x8086, 0x0084, "Intel(R) Centrino(R) Wireless-N 1000" },
85 { 0x8086, 0x0085, "Intel(R) Centrino(R) Advanced-N 6205" },
86 { 0x8086, 0x0087, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" },
87 { 0x8086, 0x0089, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" },
88 { 0x8086, 0x008a, "Intel(R) Centrino(R) Wireless-N 1030" },
89 { 0x8086, 0x008b, "Intel(R) Centrino(R) Wireless-N 1030" },
90 { 0x8086, 0x0090, "Intel(R) Centrino(R) Advanced-N 6230" },
91 { 0x8086, 0x0091, "Intel(R) Centrino(R) Advanced-N 6230" },
92 { 0x8086, 0x4229, "Intel(R) Wireless WiFi Link 4965" },
93 { 0x8086, 0x422b, "Intel(R) Centrino(R) Ultimate-N 6300" },
94 { 0x8086, 0x422c, "Intel(R) Centrino(R) Advanced-N 6200" },
95 { 0x8086, 0x422d, "Intel(R) Wireless WiFi Link 4965" },
96 { 0x8086, 0x4230, "Intel(R) Wireless WiFi Link 4965" },
97 { 0x8086, 0x4232, "Intel(R) WiFi Link 5100" },
98 { 0x8086, 0x4233, "Intel(R) Wireless WiFi Link 4965" },
99 { 0x8086, 0x4235, "Intel(R) Ultimate N WiFi Link 5300" },
100 { 0x8086, 0x4236, "Intel(R) Ultimate N WiFi Link 5300" },
101 { 0x8086, 0x4237, "Intel(R) WiFi Link 5100" },
102 { 0x8086, 0x4238, "Intel(R) Centrino(R) Ultimate-N 6300" },
103 { 0x8086, 0x4239, "Intel(R) Centrino(R) Advanced-N 6200" },
104 { 0x8086, 0x423a, "Intel(R) WiMAX/WiFi Link 5350" },
105 { 0x8086, 0x423b, "Intel(R) WiMAX/WiFi Link 5350" },
106 { 0x8086, 0x423c, "Intel(R) WiMAX/WiFi Link 5150" },
107 { 0x8086, 0x423d, "Intel(R) WiMAX/WiFi Link 5150" },
111 static int iwn_probe(device_t);
112 static int iwn_attach(device_t);
113 static int iwn4965_attach(struct iwn_softc *, uint16_t);
114 static int iwn5000_attach(struct iwn_softc *, uint16_t);
115 static void iwn_radiotap_attach(struct iwn_softc *);
116 static void iwn_sysctlattach(struct iwn_softc *);
117 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
118 const char name[IFNAMSIZ], int unit, int opmode,
119 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
120 const uint8_t mac[IEEE80211_ADDR_LEN]);
121 static void iwn_vap_delete(struct ieee80211vap *);
122 static int iwn_detach(device_t);
123 static int iwn_shutdown(device_t);
124 static int iwn_suspend(device_t);
125 static int iwn_resume(device_t);
126 static int iwn_nic_lock(struct iwn_softc *);
127 static int iwn_eeprom_lock(struct iwn_softc *);
128 static int iwn_init_otprom(struct iwn_softc *);
129 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
130 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
131 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
132 void **, bus_size_t, bus_size_t);
133 static void iwn_dma_contig_free(struct iwn_dma_info *);
134 static int iwn_alloc_sched(struct iwn_softc *);
135 static void iwn_free_sched(struct iwn_softc *);
136 static int iwn_alloc_kw(struct iwn_softc *);
137 static void iwn_free_kw(struct iwn_softc *);
138 static int iwn_alloc_ict(struct iwn_softc *);
139 static void iwn_free_ict(struct iwn_softc *);
140 static int iwn_alloc_fwmem(struct iwn_softc *);
141 static void iwn_free_fwmem(struct iwn_softc *);
142 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
143 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
144 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
145 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
147 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
148 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
149 static void iwn5000_ict_reset(struct iwn_softc *);
150 static int iwn_read_eeprom(struct iwn_softc *,
151 uint8_t macaddr[IEEE80211_ADDR_LEN]);
152 static void iwn4965_read_eeprom(struct iwn_softc *);
153 static void iwn4965_print_power_group(struct iwn_softc *, int);
154 static void iwn5000_read_eeprom(struct iwn_softc *);
155 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
156 static void iwn_read_eeprom_band(struct iwn_softc *, int);
157 static void iwn_read_eeprom_ht40(struct iwn_softc *, int);
158 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
159 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
160 struct ieee80211_channel *);
161 static int iwn_setregdomain(struct ieee80211com *,
162 struct ieee80211_regdomain *, int,
163 struct ieee80211_channel[]);
164 static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
165 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
166 const uint8_t mac[IEEE80211_ADDR_LEN]);
167 static void iwn_newassoc(struct ieee80211_node *, int);
168 static int iwn_media_change(struct ifnet *);
169 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
170 static void iwn_calib_timeout(void *);
171 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
172 struct iwn_rx_data *);
173 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
174 struct iwn_rx_data *);
175 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
176 struct iwn_rx_data *);
177 static void iwn5000_rx_calib_results(struct iwn_softc *,
178 struct iwn_rx_desc *, struct iwn_rx_data *);
179 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
180 struct iwn_rx_data *);
181 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
182 struct iwn_rx_data *);
183 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
184 struct iwn_rx_data *);
185 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
187 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *);
188 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
189 static void iwn_notif_intr(struct iwn_softc *);
190 static void iwn_wakeup_intr(struct iwn_softc *);
191 static void iwn_rftoggle_intr(struct iwn_softc *);
192 static void iwn_fatal_intr(struct iwn_softc *);
193 static void iwn_intr(void *);
194 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
196 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
199 static void iwn5000_reset_sched(struct iwn_softc *, int, int);
201 static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
202 struct ieee80211_node *);
203 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *,
204 struct ieee80211_node *,
205 const struct ieee80211_bpf_params *params);
206 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
207 const struct ieee80211_bpf_params *);
208 static void iwn_start(struct ifnet *);
209 static void iwn_start_locked(struct ifnet *);
210 static void iwn_watchdog(void *);
211 static int iwn_ioctl(struct ifnet *, u_long, caddr_t);
212 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
213 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
215 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
217 static int iwn_set_link_quality(struct iwn_softc *,
218 struct ieee80211_node *);
219 static int iwn_add_broadcast_node(struct iwn_softc *, int);
220 static int iwn_updateedca(struct ieee80211com *);
221 static void iwn_update_mcast(struct ifnet *);
222 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
223 static int iwn_set_critical_temp(struct iwn_softc *);
224 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
225 static void iwn4965_power_calibration(struct iwn_softc *, int);
226 static int iwn4965_set_txpower(struct iwn_softc *,
227 struct ieee80211_channel *, int);
228 static int iwn5000_set_txpower(struct iwn_softc *,
229 struct ieee80211_channel *, int);
230 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
231 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
232 static int iwn_get_noise(const struct iwn_rx_general_stats *);
233 static int iwn4965_get_temperature(struct iwn_softc *);
234 static int iwn5000_get_temperature(struct iwn_softc *);
235 static int iwn_init_sensitivity(struct iwn_softc *);
236 static void iwn_collect_noise(struct iwn_softc *,
237 const struct iwn_rx_general_stats *);
238 static int iwn4965_init_gains(struct iwn_softc *);
239 static int iwn5000_init_gains(struct iwn_softc *);
240 static int iwn4965_set_gains(struct iwn_softc *);
241 static int iwn5000_set_gains(struct iwn_softc *);
242 static void iwn_tune_sensitivity(struct iwn_softc *,
243 const struct iwn_rx_stats *);
244 static int iwn_send_sensitivity(struct iwn_softc *);
245 static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
246 static int iwn_send_btcoex(struct iwn_softc *);
247 static int iwn_send_advanced_btcoex(struct iwn_softc *);
248 static int iwn_config(struct iwn_softc *);
249 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int);
250 static int iwn_scan(struct iwn_softc *);
251 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
252 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
253 static int iwn_ampdu_rx_start(struct ieee80211_node *,
254 struct ieee80211_rx_ampdu *, int, int, int);
255 static void iwn_ampdu_rx_stop(struct ieee80211_node *,
256 struct ieee80211_rx_ampdu *);
257 static int iwn_addba_request(struct ieee80211_node *,
258 struct ieee80211_tx_ampdu *, int, int, int);
259 static int iwn_addba_response(struct ieee80211_node *,
260 struct ieee80211_tx_ampdu *, int, int, int);
261 static int iwn_ampdu_tx_start(struct ieee80211com *,
262 struct ieee80211_node *, uint8_t);
263 static void iwn_ampdu_tx_stop(struct ieee80211_node *,
264 struct ieee80211_tx_ampdu *);
265 static void iwn4965_ampdu_tx_start(struct iwn_softc *,
266 struct ieee80211_node *, int, uint8_t, uint16_t);
267 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int,
269 static void iwn5000_ampdu_tx_start(struct iwn_softc *,
270 struct ieee80211_node *, int, uint8_t, uint16_t);
271 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int,
273 static int iwn5000_query_calibration(struct iwn_softc *);
274 static int iwn5000_send_calibration(struct iwn_softc *);
275 static int iwn5000_send_wimax_coex(struct iwn_softc *);
276 static int iwn5000_crystal_calib(struct iwn_softc *);
277 static int iwn5000_temp_offset_calib(struct iwn_softc *);
278 static int iwn4965_post_alive(struct iwn_softc *);
279 static int iwn5000_post_alive(struct iwn_softc *);
280 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
282 static int iwn4965_load_firmware(struct iwn_softc *);
283 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
284 const uint8_t *, int);
285 static int iwn5000_load_firmware(struct iwn_softc *);
286 static int iwn_read_firmware_leg(struct iwn_softc *,
287 struct iwn_fw_info *);
288 static int iwn_read_firmware_tlv(struct iwn_softc *,
289 struct iwn_fw_info *, uint16_t);
290 static int iwn_read_firmware(struct iwn_softc *);
291 static int iwn_clock_wait(struct iwn_softc *);
292 static int iwn_apm_init(struct iwn_softc *);
293 static void iwn_apm_stop_master(struct iwn_softc *);
294 static void iwn_apm_stop(struct iwn_softc *);
295 static int iwn4965_nic_config(struct iwn_softc *);
296 static int iwn5000_nic_config(struct iwn_softc *);
297 static int iwn_hw_prepare(struct iwn_softc *);
298 static int iwn_hw_init(struct iwn_softc *);
299 static void iwn_hw_stop(struct iwn_softc *);
300 static void iwn_radio_on(void *, int);
301 static void iwn_radio_off(void *, int);
302 static void iwn_init_locked(struct iwn_softc *);
303 static void iwn_init(void *);
304 static void iwn_stop_locked(struct iwn_softc *);
305 static void iwn_stop(struct iwn_softc *);
306 static void iwn_scan_start(struct ieee80211com *);
307 static void iwn_scan_end(struct ieee80211com *);
308 static void iwn_set_channel(struct ieee80211com *);
309 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
310 static void iwn_scan_mindwell(struct ieee80211_scan_state *);
311 static void iwn_hw_reset(void *, int);
316 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
317 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
318 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */
319 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */
320 IWN_DEBUG_RESET = 0x00000010, /* reset processing */
321 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */
322 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */
323 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */
324 IWN_DEBUG_INTR = 0x00000100, /* ISR */
325 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */
326 IWN_DEBUG_NODE = 0x00000400, /* node management */
327 IWN_DEBUG_LED = 0x00000800, /* led management */
328 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
329 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
330 IWN_DEBUG_ANY = 0xffffffff
333 #define DPRINTF(sc, m, fmt, ...) do { \
334 if (sc->sc_debug & (m)) \
335 printf(fmt, __VA_ARGS__); \
339 iwn_intr_str(uint8_t cmd)
343 case IWN_UC_READY: return "UC_READY";
344 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE";
345 case IWN_TX_DONE: return "TX_DONE";
346 case IWN_START_SCAN: return "START_SCAN";
347 case IWN_STOP_SCAN: return "STOP_SCAN";
348 case IWN_RX_STATISTICS: return "RX_STATS";
349 case IWN_BEACON_STATISTICS: return "BEACON_STATS";
350 case IWN_STATE_CHANGED: return "STATE_CHANGED";
351 case IWN_BEACON_MISSED: return "BEACON_MISSED";
352 case IWN_RX_PHY: return "RX_PHY";
353 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE";
354 case IWN_RX_DONE: return "RX_DONE";
356 /* Command Notifications */
357 case IWN_CMD_RXON: return "IWN_CMD_RXON";
358 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC";
359 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS";
360 case IWN_CMD_TIMING: return "IWN_CMD_TIMING";
361 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY";
362 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED";
363 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX";
364 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG";
365 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT";
366 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE";
367 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE";
368 case IWN_CMD_SCAN: return "IWN_CMD_SCAN";
369 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS";
370 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER";
371 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM";
372 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG";
373 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX";
374 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP";
375 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY";
376 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB";
378 return "UNKNOWN INTR NOTIF/CMD";
381 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0)
384 static device_method_t iwn_methods[] = {
385 /* Device interface */
386 DEVMETHOD(device_probe, iwn_probe),
387 DEVMETHOD(device_attach, iwn_attach),
388 DEVMETHOD(device_detach, iwn_detach),
389 DEVMETHOD(device_shutdown, iwn_shutdown),
390 DEVMETHOD(device_suspend, iwn_suspend),
391 DEVMETHOD(device_resume, iwn_resume),
395 static driver_t iwn_driver = {
398 sizeof(struct iwn_softc)
400 static devclass_t iwn_devclass;
402 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0);
404 MODULE_VERSION(iwn, 1);
406 MODULE_DEPEND(iwn, firmware, 1, 1, 1);
407 MODULE_DEPEND(iwn, pci, 1, 1, 1);
408 MODULE_DEPEND(iwn, wlan, 1, 1, 1);
411 iwn_probe(device_t dev)
413 const struct iwn_ident *ident;
415 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
416 if (pci_get_vendor(dev) == ident->vendor &&
417 pci_get_device(dev) == ident->device) {
418 device_set_desc(dev, ident->name);
426 iwn_attach(device_t dev)
428 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
429 struct ieee80211com *ic;
432 int i, error, result;
433 uint8_t macaddr[IEEE80211_ADDR_LEN];
438 * Get the offset of the PCI Express Capability Structure in PCI
439 * Configuration Space.
441 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
443 device_printf(dev, "PCIe capability structure not found!\n");
447 /* Clear device-specific "PCI retry timeout" register (41h). */
448 pci_write_config(dev, 0x41, 0, 1);
450 /* Hardware bug workaround. */
451 reg = pci_read_config(dev, PCIR_COMMAND, 1);
452 if (reg & PCIM_CMD_INTxDIS) {
453 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
455 reg &= ~PCIM_CMD_INTxDIS;
456 pci_write_config(dev, PCIR_COMMAND, reg, 1);
459 /* Enable bus-mastering. */
460 pci_enable_busmaster(dev);
462 sc->mem_rid = PCIR_BAR(0);
463 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
465 if (sc->mem == NULL) {
466 device_printf(dev, "can't map mem space\n");
470 sc->sc_st = rman_get_bustag(sc->mem);
471 sc->sc_sh = rman_get_bushandle(sc->mem);
474 if ((result = pci_msi_count(dev)) == 1 &&
475 pci_alloc_msi(dev, &result) == 0)
477 /* Install interrupt handler. */
478 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
479 RF_ACTIVE | RF_SHAREABLE);
480 if (sc->irq == NULL) {
481 device_printf(dev, "can't map interrupt\n");
488 /* Read hardware revision and attach. */
489 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf;
490 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
491 error = iwn4965_attach(sc, pci_get_device(dev));
493 error = iwn5000_attach(sc, pci_get_device(dev));
495 device_printf(dev, "could not attach device, error %d\n",
500 if ((error = iwn_hw_prepare(sc)) != 0) {
501 device_printf(dev, "hardware not ready, error %d\n", error);
505 /* Allocate DMA memory for firmware transfers. */
506 if ((error = iwn_alloc_fwmem(sc)) != 0) {
508 "could not allocate memory for firmware, error %d\n",
513 /* Allocate "Keep Warm" page. */
514 if ((error = iwn_alloc_kw(sc)) != 0) {
516 "could not allocate keep warm page, error %d\n", error);
520 /* Allocate ICT table for 5000 Series. */
521 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
522 (error = iwn_alloc_ict(sc)) != 0) {
523 device_printf(dev, "could not allocate ICT table, error %d\n",
528 /* Allocate TX scheduler "rings". */
529 if ((error = iwn_alloc_sched(sc)) != 0) {
531 "could not allocate TX scheduler rings, error %d\n", error);
535 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
536 for (i = 0; i < sc->ntxqs; i++) {
537 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
539 "could not allocate TX ring %d, error %d\n", i,
545 /* Allocate RX ring. */
546 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
547 device_printf(dev, "could not allocate RX ring, error %d\n",
552 /* Clear pending interrupts. */
553 IWN_WRITE(sc, IWN_INT, 0xffffffff);
555 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
557 device_printf(dev, "can not allocate ifnet structure\n");
563 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
564 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
566 /* Set device capabilities. */
568 IEEE80211_C_STA /* station mode supported */
569 | IEEE80211_C_MONITOR /* monitor mode supported */
570 | IEEE80211_C_BGSCAN /* background scanning */
571 | IEEE80211_C_TXPMGT /* tx power management */
572 | IEEE80211_C_SHSLOT /* short slot time supported */
574 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
576 | IEEE80211_C_IBSS /* ibss/adhoc mode */
578 | IEEE80211_C_WME /* WME */
581 /* Read MAC address, channels, etc from EEPROM. */
582 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) {
583 device_printf(dev, "could not read EEPROM, error %d\n",
588 /* Count the number of available chains. */
590 ((sc->txchainmask >> 2) & 1) +
591 ((sc->txchainmask >> 1) & 1) +
592 ((sc->txchainmask >> 0) & 1);
594 ((sc->rxchainmask >> 2) & 1) +
595 ((sc->rxchainmask >> 1) & 1) +
596 ((sc->rxchainmask >> 0) & 1);
598 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n",
599 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
603 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
604 ic->ic_rxstream = sc->nrxchains;
605 ic->ic_txstream = sc->ntxchains;
607 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */
608 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
609 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/
610 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
612 | IEEE80211_HTCAP_GREENFIELD
613 #if IWN_RBUF_SIZE == 8192
614 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */
616 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
619 /* s/w capabilities */
620 | IEEE80211_HTC_HT /* HT operation */
621 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
623 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
628 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
631 ifp->if_init = iwn_init;
632 ifp->if_ioctl = iwn_ioctl;
633 ifp->if_start = iwn_start;
634 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
635 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
636 IFQ_SET_READY(&ifp->if_snd);
638 ieee80211_ifattach(ic, macaddr);
639 ic->ic_vap_create = iwn_vap_create;
640 ic->ic_vap_delete = iwn_vap_delete;
641 ic->ic_raw_xmit = iwn_raw_xmit;
642 ic->ic_node_alloc = iwn_node_alloc;
643 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start;
644 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
645 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop;
646 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
647 sc->sc_addba_request = ic->ic_addba_request;
648 ic->ic_addba_request = iwn_addba_request;
649 sc->sc_addba_response = ic->ic_addba_response;
650 ic->ic_addba_response = iwn_addba_response;
651 sc->sc_addba_stop = ic->ic_addba_stop;
652 ic->ic_addba_stop = iwn_ampdu_tx_stop;
653 ic->ic_newassoc = iwn_newassoc;
654 ic->ic_wme.wme_update = iwn_updateedca;
655 ic->ic_update_mcast = iwn_update_mcast;
656 ic->ic_scan_start = iwn_scan_start;
657 ic->ic_scan_end = iwn_scan_end;
658 ic->ic_set_channel = iwn_set_channel;
659 ic->ic_scan_curchan = iwn_scan_curchan;
660 ic->ic_scan_mindwell = iwn_scan_mindwell;
661 ic->ic_setregdomain = iwn_setregdomain;
663 iwn_radiotap_attach(sc);
665 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
666 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
667 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc);
668 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc);
669 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc);
671 iwn_sysctlattach(sc);
674 * Hook our interrupt after all initialization is complete.
676 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
677 NULL, iwn_intr, sc, &sc->sc_ih);
679 device_printf(dev, "can't establish interrupt, error %d\n",
685 ieee80211_announce(ic);
693 iwn4965_attach(struct iwn_softc *sc, uint16_t pid)
695 struct iwn_ops *ops = &sc->ops;
697 ops->load_firmware = iwn4965_load_firmware;
698 ops->read_eeprom = iwn4965_read_eeprom;
699 ops->post_alive = iwn4965_post_alive;
700 ops->nic_config = iwn4965_nic_config;
701 ops->update_sched = iwn4965_update_sched;
702 ops->get_temperature = iwn4965_get_temperature;
703 ops->get_rssi = iwn4965_get_rssi;
704 ops->set_txpower = iwn4965_set_txpower;
705 ops->init_gains = iwn4965_init_gains;
706 ops->set_gains = iwn4965_set_gains;
707 ops->add_node = iwn4965_add_node;
708 ops->tx_done = iwn4965_tx_done;
709 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
710 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
711 sc->ntxqs = IWN4965_NTXQUEUES;
712 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE;
713 sc->ndmachnls = IWN4965_NDMACHNLS;
714 sc->broadcast_id = IWN4965_ID_BROADCAST;
715 sc->rxonsz = IWN4965_RXONSZ;
716 sc->schedsz = IWN4965_SCHEDSZ;
717 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
718 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
719 sc->fwsz = IWN4965_FWSZ;
720 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
721 sc->limits = &iwn4965_sensitivity_limits;
722 sc->fwname = "iwn4965fw";
723 /* Override chains masks, ROM is known to be broken. */
724 sc->txchainmask = IWN_ANT_AB;
725 sc->rxchainmask = IWN_ANT_ABC;
731 iwn5000_attach(struct iwn_softc *sc, uint16_t pid)
733 struct iwn_ops *ops = &sc->ops;
735 ops->load_firmware = iwn5000_load_firmware;
736 ops->read_eeprom = iwn5000_read_eeprom;
737 ops->post_alive = iwn5000_post_alive;
738 ops->nic_config = iwn5000_nic_config;
739 ops->update_sched = iwn5000_update_sched;
740 ops->get_temperature = iwn5000_get_temperature;
741 ops->get_rssi = iwn5000_get_rssi;
742 ops->set_txpower = iwn5000_set_txpower;
743 ops->init_gains = iwn5000_init_gains;
744 ops->set_gains = iwn5000_set_gains;
745 ops->add_node = iwn5000_add_node;
746 ops->tx_done = iwn5000_tx_done;
747 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
748 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
749 sc->ntxqs = IWN5000_NTXQUEUES;
750 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE;
751 sc->ndmachnls = IWN5000_NDMACHNLS;
752 sc->broadcast_id = IWN5000_ID_BROADCAST;
753 sc->rxonsz = IWN5000_RXONSZ;
754 sc->schedsz = IWN5000_SCHEDSZ;
755 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
756 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
757 sc->fwsz = IWN5000_FWSZ;
758 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
759 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
760 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
762 switch (sc->hw_type) {
763 case IWN_HW_REV_TYPE_5100:
764 sc->limits = &iwn5000_sensitivity_limits;
765 sc->fwname = "iwn5000fw";
766 /* Override chains masks, ROM is known to be broken. */
767 sc->txchainmask = IWN_ANT_B;
768 sc->rxchainmask = IWN_ANT_AB;
770 case IWN_HW_REV_TYPE_5150:
771 sc->limits = &iwn5150_sensitivity_limits;
772 sc->fwname = "iwn5150fw";
774 case IWN_HW_REV_TYPE_5300:
775 case IWN_HW_REV_TYPE_5350:
776 sc->limits = &iwn5000_sensitivity_limits;
777 sc->fwname = "iwn5000fw";
779 case IWN_HW_REV_TYPE_1000:
780 sc->limits = &iwn1000_sensitivity_limits;
781 sc->fwname = "iwn1000fw";
783 case IWN_HW_REV_TYPE_6000:
784 sc->limits = &iwn6000_sensitivity_limits;
785 sc->fwname = "iwn6000fw";
786 if (pid == 0x422c || pid == 0x4239) {
787 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
788 /* Override chains masks, ROM is known to be broken. */
789 sc->txchainmask = IWN_ANT_BC;
790 sc->rxchainmask = IWN_ANT_BC;
793 case IWN_HW_REV_TYPE_6050:
794 sc->limits = &iwn6000_sensitivity_limits;
795 sc->fwname = "iwn6050fw";
796 /* Override chains masks, ROM is known to be broken. */
797 sc->txchainmask = IWN_ANT_AB;
798 sc->rxchainmask = IWN_ANT_AB;
800 case IWN_HW_REV_TYPE_6005:
801 sc->limits = &iwn6000_sensitivity_limits;
802 if (pid != 0x0082 && pid != 0x0085) {
803 sc->fwname = "iwn6000g2bfw";
804 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX;
806 sc->fwname = "iwn6000g2afw";
809 device_printf(sc->sc_dev, "adapter type %d not supported\n",
817 * Attach the interface to 802.11 radiotap.
820 iwn_radiotap_attach(struct iwn_softc *sc)
822 struct ifnet *ifp = sc->sc_ifp;
823 struct ieee80211com *ic = ifp->if_l2com;
825 ieee80211_radiotap_attach(ic,
826 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
827 IWN_TX_RADIOTAP_PRESENT,
828 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
829 IWN_RX_RADIOTAP_PRESENT);
833 iwn_sysctlattach(struct iwn_softc *sc)
835 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
836 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
840 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
841 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
845 static struct ieee80211vap *
846 iwn_vap_create(struct ieee80211com *ic,
847 const char name[IFNAMSIZ], int unit, int opmode, int flags,
848 const uint8_t bssid[IEEE80211_ADDR_LEN],
849 const uint8_t mac[IEEE80211_ADDR_LEN])
852 struct ieee80211vap *vap;
854 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
856 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap),
857 M_80211_VAP, M_NOWAIT | M_ZERO);
861 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
862 vap->iv_bmissthreshold = 10; /* override default */
863 /* Override with driver methods. */
864 ivp->iv_newstate = vap->iv_newstate;
865 vap->iv_newstate = iwn_newstate;
867 ieee80211_ratectl_init(vap);
868 /* Complete setup. */
869 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
870 ic->ic_opmode = opmode;
875 iwn_vap_delete(struct ieee80211vap *vap)
877 struct iwn_vap *ivp = IWN_VAP(vap);
879 ieee80211_ratectl_deinit(vap);
880 ieee80211_vap_detach(vap);
881 free(ivp, M_80211_VAP);
885 iwn_detach(device_t dev)
887 struct iwn_softc *sc = device_get_softc(dev);
888 struct ifnet *ifp = sc->sc_ifp;
889 struct ieee80211com *ic;
895 ieee80211_draintask(ic, &sc->sc_reinit_task);
896 ieee80211_draintask(ic, &sc->sc_radioon_task);
897 ieee80211_draintask(ic, &sc->sc_radiooff_task);
900 callout_drain(&sc->watchdog_to);
901 callout_drain(&sc->calib_to);
902 ieee80211_ifdetach(ic);
905 /* Uninstall interrupt handler. */
906 if (sc->irq != NULL) {
907 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
908 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
909 if (sc->irq_rid == 1)
910 pci_release_msi(dev);
913 /* Free DMA resources. */
914 iwn_free_rx_ring(sc, &sc->rxq);
915 for (qid = 0; qid < sc->ntxqs; qid++)
916 iwn_free_tx_ring(sc, &sc->txq[qid]);
924 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
929 IWN_LOCK_DESTROY(sc);
934 iwn_shutdown(device_t dev)
936 struct iwn_softc *sc = device_get_softc(dev);
943 iwn_suspend(device_t dev)
945 struct iwn_softc *sc = device_get_softc(dev);
946 struct ifnet *ifp = sc->sc_ifp;
947 struct ieee80211com *ic = ifp->if_l2com;
948 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
957 iwn_resume(device_t dev)
959 struct iwn_softc *sc = device_get_softc(dev);
960 struct ifnet *ifp = sc->sc_ifp;
961 struct ieee80211com *ic = ifp->if_l2com;
962 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
964 /* Clear device-specific "PCI retry timeout" register (41h). */
965 pci_write_config(dev, 0x41, 0, 1);
967 if (ifp->if_flags & IFF_UP) {
971 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
978 iwn_nic_lock(struct iwn_softc *sc)
982 /* Request exclusive access to NIC. */
983 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
985 /* Spin until we actually get the lock. */
986 for (ntries = 0; ntries < 1000; ntries++) {
987 if ((IWN_READ(sc, IWN_GP_CNTRL) &
988 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
989 IWN_GP_CNTRL_MAC_ACCESS_ENA)
997 iwn_nic_unlock(struct iwn_softc *sc)
999 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
1002 static __inline uint32_t
1003 iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
1005 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
1006 IWN_BARRIER_READ_WRITE(sc);
1007 return IWN_READ(sc, IWN_PRPH_RDATA);
1010 static __inline void
1011 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1013 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
1014 IWN_BARRIER_WRITE(sc);
1015 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
1018 static __inline void
1019 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1021 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
1024 static __inline void
1025 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1027 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
1030 static __inline void
1031 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
1032 const uint32_t *data, int count)
1034 for (; count > 0; count--, data++, addr += 4)
1035 iwn_prph_write(sc, addr, *data);
1038 static __inline uint32_t
1039 iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
1041 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
1042 IWN_BARRIER_READ_WRITE(sc);
1043 return IWN_READ(sc, IWN_MEM_RDATA);
1046 static __inline void
1047 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1049 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
1050 IWN_BARRIER_WRITE(sc);
1051 IWN_WRITE(sc, IWN_MEM_WDATA, data);
1054 static __inline void
1055 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
1059 tmp = iwn_mem_read(sc, addr & ~3);
1061 tmp = (tmp & 0x0000ffff) | data << 16;
1063 tmp = (tmp & 0xffff0000) | data;
1064 iwn_mem_write(sc, addr & ~3, tmp);
1067 static __inline void
1068 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
1071 for (; count > 0; count--, addr += 4)
1072 *data++ = iwn_mem_read(sc, addr);
1075 static __inline void
1076 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
1079 for (; count > 0; count--, addr += 4)
1080 iwn_mem_write(sc, addr, val);
1084 iwn_eeprom_lock(struct iwn_softc *sc)
1088 for (i = 0; i < 100; i++) {
1089 /* Request exclusive access to EEPROM. */
1090 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1091 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1093 /* Spin until we actually get the lock. */
1094 for (ntries = 0; ntries < 100; ntries++) {
1095 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1096 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1104 static __inline void
1105 iwn_eeprom_unlock(struct iwn_softc *sc)
1107 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1111 * Initialize access by host to One Time Programmable ROM.
1112 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1115 iwn_init_otprom(struct iwn_softc *sc)
1117 uint16_t prev, base, next;
1120 /* Wait for clock stabilization before accessing prph. */
1121 if ((error = iwn_clock_wait(sc)) != 0)
1124 if ((error = iwn_nic_lock(sc)) != 0)
1126 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1128 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1131 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1132 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1133 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1134 IWN_RESET_LINK_PWR_MGMT_DIS);
1136 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1137 /* Clear ECC status. */
1138 IWN_SETBITS(sc, IWN_OTP_GP,
1139 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1142 * Find the block before last block (contains the EEPROM image)
1143 * for HW without OTP shadow RAM.
1145 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1146 /* Switch to absolute addressing mode. */
1147 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1149 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1150 error = iwn_read_prom_data(sc, base, &next, 2);
1153 if (next == 0) /* End of linked-list. */
1156 base = le16toh(next);
1158 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1160 /* Skip "next" word. */
1161 sc->prom_base = prev + 1;
1167 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1169 uint8_t *out = data;
1173 addr += sc->prom_base;
1174 for (; count > 0; count -= 2, addr++) {
1175 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1176 for (ntries = 0; ntries < 10; ntries++) {
1177 val = IWN_READ(sc, IWN_EEPROM);
1178 if (val & IWN_EEPROM_READ_VALID)
1183 device_printf(sc->sc_dev,
1184 "timeout reading ROM at 0x%x\n", addr);
1187 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1188 /* OTPROM, check for ECC errors. */
1189 tmp = IWN_READ(sc, IWN_OTP_GP);
1190 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1191 device_printf(sc->sc_dev,
1192 "OTPROM ECC error at 0x%x\n", addr);
1195 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1196 /* Correctable ECC error, clear bit. */
1197 IWN_SETBITS(sc, IWN_OTP_GP,
1198 IWN_OTP_GP_ECC_CORR_STTS);
1209 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1213 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1214 *(bus_addr_t *)arg = segs[0].ds_addr;
1218 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1219 void **kvap, bus_size_t size, bus_size_t alignment)
1226 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment,
1227 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
1228 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag);
1232 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1233 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map);
1237 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
1238 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT);
1242 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
1249 fail: iwn_dma_contig_free(dma);
1254 iwn_dma_contig_free(struct iwn_dma_info *dma)
1256 if (dma->map != NULL) {
1257 if (dma->vaddr != NULL) {
1258 bus_dmamap_sync(dma->tag, dma->map,
1259 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1260 bus_dmamap_unload(dma->tag, dma->map);
1261 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map);
1264 bus_dmamap_destroy(dma->tag, dma->map);
1267 if (dma->tag != NULL) {
1268 bus_dma_tag_destroy(dma->tag);
1274 iwn_alloc_sched(struct iwn_softc *sc)
1276 /* TX scheduler rings must be aligned on a 1KB boundary. */
1277 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched,
1282 iwn_free_sched(struct iwn_softc *sc)
1284 iwn_dma_contig_free(&sc->sched_dma);
1288 iwn_alloc_kw(struct iwn_softc *sc)
1290 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1291 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096);
1295 iwn_free_kw(struct iwn_softc *sc)
1297 iwn_dma_contig_free(&sc->kw_dma);
1301 iwn_alloc_ict(struct iwn_softc *sc)
1303 /* ICT table must be aligned on a 4KB boundary. */
1304 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict,
1305 IWN_ICT_SIZE, 4096);
1309 iwn_free_ict(struct iwn_softc *sc)
1311 iwn_dma_contig_free(&sc->ict_dma);
1315 iwn_alloc_fwmem(struct iwn_softc *sc)
1317 /* Must be aligned on a 16-byte boundary. */
1318 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16);
1322 iwn_free_fwmem(struct iwn_softc *sc)
1324 iwn_dma_contig_free(&sc->fw_dma);
1328 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1335 /* Allocate RX descriptors (256-byte aligned). */
1336 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1337 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1340 device_printf(sc->sc_dev,
1341 "%s: could not allocate RX ring DMA memory, error %d\n",
1346 /* Allocate RX status area (16-byte aligned). */
1347 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat,
1348 sizeof (struct iwn_rx_status), 16);
1350 device_printf(sc->sc_dev,
1351 "%s: could not allocate RX status DMA memory, error %d\n",
1356 /* Create RX buffer DMA tag. */
1357 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1358 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1359 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL,
1362 device_printf(sc->sc_dev,
1363 "%s: could not create RX buf DMA tag, error %d\n",
1369 * Allocate and map RX buffers.
1371 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1372 struct iwn_rx_data *data = &ring->data[i];
1375 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1377 device_printf(sc->sc_dev,
1378 "%s: could not create RX buf DMA map, error %d\n",
1383 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR,
1385 if (data->m == NULL) {
1386 device_printf(sc->sc_dev,
1387 "%s: could not allocate RX mbuf\n", __func__);
1392 error = bus_dmamap_load(ring->data_dmat, data->map,
1393 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
1394 &paddr, BUS_DMA_NOWAIT);
1395 if (error != 0 && error != EFBIG) {
1396 device_printf(sc->sc_dev,
1397 "%s: can't not map mbuf, error %d\n", __func__,
1402 /* Set physical address of RX buffer (256-byte aligned). */
1403 ring->desc[i] = htole32(paddr >> 8);
1406 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1407 BUS_DMASYNC_PREWRITE);
1411 fail: iwn_free_rx_ring(sc, ring);
1416 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1420 if (iwn_nic_lock(sc) == 0) {
1421 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1422 for (ntries = 0; ntries < 1000; ntries++) {
1423 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1424 IWN_FH_RX_STATUS_IDLE)
1431 sc->last_rx_valid = 0;
1435 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1439 iwn_dma_contig_free(&ring->desc_dma);
1440 iwn_dma_contig_free(&ring->stat_dma);
1442 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1443 struct iwn_rx_data *data = &ring->data[i];
1445 if (data->m != NULL) {
1446 bus_dmamap_sync(ring->data_dmat, data->map,
1447 BUS_DMASYNC_POSTREAD);
1448 bus_dmamap_unload(ring->data_dmat, data->map);
1452 if (data->map != NULL)
1453 bus_dmamap_destroy(ring->data_dmat, data->map);
1455 if (ring->data_dmat != NULL) {
1456 bus_dma_tag_destroy(ring->data_dmat);
1457 ring->data_dmat = NULL;
1462 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1472 /* Allocate TX descriptors (256-byte aligned). */
1473 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
1474 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1477 device_printf(sc->sc_dev,
1478 "%s: could not allocate TX ring DMA memory, error %d\n",
1483 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
1484 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
1487 device_printf(sc->sc_dev,
1488 "%s: could not allocate TX cmd DMA memory, error %d\n",
1493 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
1495 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL,
1498 device_printf(sc->sc_dev,
1499 "%s: could not create TX buf DMA tag, error %d\n",
1504 paddr = ring->cmd_dma.paddr;
1505 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1506 struct iwn_tx_data *data = &ring->data[i];
1508 data->cmd_paddr = paddr;
1509 data->scratch_paddr = paddr + 12;
1510 paddr += sizeof (struct iwn_tx_cmd);
1512 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1514 device_printf(sc->sc_dev,
1515 "%s: could not create TX buf DMA map, error %d\n",
1522 fail: iwn_free_tx_ring(sc, ring);
1527 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1531 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1532 struct iwn_tx_data *data = &ring->data[i];
1534 if (data->m != NULL) {
1535 bus_dmamap_sync(ring->data_dmat, data->map,
1536 BUS_DMASYNC_POSTWRITE);
1537 bus_dmamap_unload(ring->data_dmat, data->map);
1542 /* Clear TX descriptors. */
1543 memset(ring->desc, 0, ring->desc_dma.size);
1544 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1545 BUS_DMASYNC_PREWRITE);
1546 sc->qfullmsk &= ~(1 << ring->qid);
1552 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1556 iwn_dma_contig_free(&ring->desc_dma);
1557 iwn_dma_contig_free(&ring->cmd_dma);
1559 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1560 struct iwn_tx_data *data = &ring->data[i];
1562 if (data->m != NULL) {
1563 bus_dmamap_sync(ring->data_dmat, data->map,
1564 BUS_DMASYNC_POSTWRITE);
1565 bus_dmamap_unload(ring->data_dmat, data->map);
1568 if (data->map != NULL)
1569 bus_dmamap_destroy(ring->data_dmat, data->map);
1571 if (ring->data_dmat != NULL) {
1572 bus_dma_tag_destroy(ring->data_dmat);
1573 ring->data_dmat = NULL;
1578 iwn5000_ict_reset(struct iwn_softc *sc)
1580 /* Disable interrupts. */
1581 IWN_WRITE(sc, IWN_INT_MASK, 0);
1583 /* Reset ICT table. */
1584 memset(sc->ict, 0, IWN_ICT_SIZE);
1587 /* Set physical address of ICT table (4KB aligned). */
1588 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
1589 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1590 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1592 /* Enable periodic RX interrupt. */
1593 sc->int_mask |= IWN_INT_RX_PERIODIC;
1594 /* Switch to ICT interrupt mode in driver. */
1595 sc->sc_flags |= IWN_FLAG_USE_ICT;
1597 /* Re-enable interrupts. */
1598 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1599 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1603 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
1605 struct iwn_ops *ops = &sc->ops;
1609 /* Check whether adapter has an EEPROM or an OTPROM. */
1610 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1611 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1612 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1613 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
1614 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
1616 /* Adapter has to be powered on for EEPROM access to work. */
1617 if ((error = iwn_apm_init(sc)) != 0) {
1618 device_printf(sc->sc_dev,
1619 "%s: could not power ON adapter, error %d\n", __func__,
1624 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1625 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
1628 if ((error = iwn_eeprom_lock(sc)) != 0) {
1629 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n",
1633 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1634 if ((error = iwn_init_otprom(sc)) != 0) {
1635 device_printf(sc->sc_dev,
1636 "%s: could not initialize OTPROM, error %d\n",
1642 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
1643 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val));
1644 /* Check if HT support is bonded out. */
1645 if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
1646 sc->sc_flags |= IWN_FLAG_HAS_11N;
1648 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1649 sc->rfcfg = le16toh(val);
1650 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
1651 /* Read Tx/Rx chains from ROM unless it's known to be broken. */
1652 if (sc->txchainmask == 0)
1653 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
1654 if (sc->rxchainmask == 0)
1655 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
1657 /* Read MAC address. */
1658 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
1660 /* Read adapter-specific information from EEPROM. */
1661 ops->read_eeprom(sc);
1663 iwn_apm_stop(sc); /* Power OFF adapter. */
1665 iwn_eeprom_unlock(sc);
1670 iwn4965_read_eeprom(struct iwn_softc *sc)
1676 /* Read regulatory domain (4 ASCII characters). */
1677 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1679 /* Read the list of authorized channels (20MHz ones only). */
1680 for (i = 0; i < 7; i++) {
1681 addr = iwn4965_regulatory_bands[i];
1682 iwn_read_eeprom_channels(sc, i, addr);
1685 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1686 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1687 sc->maxpwr2GHz = val & 0xff;
1688 sc->maxpwr5GHz = val >> 8;
1689 /* Check that EEPROM values are within valid range. */
1690 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1691 sc->maxpwr5GHz = 38;
1692 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1693 sc->maxpwr2GHz = 38;
1694 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
1695 sc->maxpwr2GHz, sc->maxpwr5GHz);
1697 /* Read samples for each TX power group. */
1698 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1701 /* Read voltage at which samples were taken. */
1702 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1703 sc->eeprom_voltage = (int16_t)le16toh(val);
1704 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
1705 sc->eeprom_voltage);
1708 /* Print samples. */
1709 if (sc->sc_debug & IWN_DEBUG_ANY) {
1710 for (i = 0; i < IWN_NBANDS; i++)
1711 iwn4965_print_power_group(sc, i);
1718 iwn4965_print_power_group(struct iwn_softc *sc, int i)
1720 struct iwn4965_eeprom_band *band = &sc->bands[i];
1721 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1724 printf("===band %d===\n", i);
1725 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1726 printf("chan1 num=%d\n", chans[0].num);
1727 for (c = 0; c < 2; c++) {
1728 for (j = 0; j < IWN_NSAMPLES; j++) {
1729 printf("chain %d, sample %d: temp=%d gain=%d "
1730 "power=%d pa_det=%d\n", c, j,
1731 chans[0].samples[c][j].temp,
1732 chans[0].samples[c][j].gain,
1733 chans[0].samples[c][j].power,
1734 chans[0].samples[c][j].pa_det);
1737 printf("chan2 num=%d\n", chans[1].num);
1738 for (c = 0; c < 2; c++) {
1739 for (j = 0; j < IWN_NSAMPLES; j++) {
1740 printf("chain %d, sample %d: temp=%d gain=%d "
1741 "power=%d pa_det=%d\n", c, j,
1742 chans[1].samples[c][j].temp,
1743 chans[1].samples[c][j].gain,
1744 chans[1].samples[c][j].power,
1745 chans[1].samples[c][j].pa_det);
1752 iwn5000_read_eeprom(struct iwn_softc *sc)
1754 struct iwn5000_eeprom_calib_hdr hdr;
1756 uint32_t base, addr;
1760 /* Read regulatory domain (4 ASCII characters). */
1761 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1762 base = le16toh(val);
1763 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1764 sc->eeprom_domain, 4);
1766 /* Read the list of authorized channels (20MHz ones only). */
1767 for (i = 0; i < 7; i++) {
1768 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1769 addr = base + iwn6000_regulatory_bands[i];
1771 addr = base + iwn5000_regulatory_bands[i];
1772 iwn_read_eeprom_channels(sc, i, addr);
1775 /* Read enhanced TX power information for 6000 Series. */
1776 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1777 iwn_read_eeprom_enhinfo(sc);
1779 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1780 base = le16toh(val);
1781 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1782 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
1783 "%s: calib version=%u pa type=%u voltage=%u\n", __func__,
1784 hdr.version, hdr.pa_type, le16toh(hdr.volt));
1785 sc->calib_ver = hdr.version;
1787 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1788 /* Compute temperature offset. */
1789 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1790 sc->eeprom_temp = le16toh(val);
1791 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1792 volt = le16toh(val);
1793 sc->temp_off = sc->eeprom_temp - (volt / -5);
1794 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
1795 sc->eeprom_temp, volt, sc->temp_off);
1797 /* Read crystal calibration. */
1798 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1799 &sc->eeprom_crystal, sizeof (uint32_t));
1800 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
1801 le32toh(sc->eeprom_crystal));
1806 * Translate EEPROM flags to net80211.
1809 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
1814 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
1815 nflags |= IEEE80211_CHAN_PASSIVE;
1816 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
1817 nflags |= IEEE80211_CHAN_NOADHOC;
1818 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
1819 nflags |= IEEE80211_CHAN_DFS;
1820 /* XXX apparently IBSS may still be marked */
1821 nflags |= IEEE80211_CHAN_NOADHOC;
1828 iwn_read_eeprom_band(struct iwn_softc *sc, int n)
1830 struct ifnet *ifp = sc->sc_ifp;
1831 struct ieee80211com *ic = ifp->if_l2com;
1832 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1833 const struct iwn_chan_band *band = &iwn_bands[n];
1834 struct ieee80211_channel *c;
1838 for (i = 0; i < band->nchan; i++) {
1839 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1840 DPRINTF(sc, IWN_DEBUG_RESET,
1841 "skip chan %d flags 0x%x maxpwr %d\n",
1842 band->chan[i], channels[i].flags,
1843 channels[i].maxpwr);
1846 chan = band->chan[i];
1847 nflags = iwn_eeprom_channel_flags(&channels[i]);
1849 c = &ic->ic_channels[ic->ic_nchans++];
1851 c->ic_maxregpower = channels[i].maxpwr;
1852 c->ic_maxpower = 2*c->ic_maxregpower;
1854 if (n == 0) { /* 2GHz band */
1855 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G);
1856 /* G =>'s B is supported */
1857 c->ic_flags = IEEE80211_CHAN_B | nflags;
1858 c = &ic->ic_channels[ic->ic_nchans++];
1860 c->ic_flags = IEEE80211_CHAN_G | nflags;
1861 } else { /* 5GHz band */
1862 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A);
1863 c->ic_flags = IEEE80211_CHAN_A | nflags;
1866 /* Save maximum allowed TX power for this channel. */
1867 sc->maxpwr[chan] = channels[i].maxpwr;
1869 DPRINTF(sc, IWN_DEBUG_RESET,
1870 "add chan %d flags 0x%x maxpwr %d\n", chan,
1871 channels[i].flags, channels[i].maxpwr);
1873 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
1874 /* add HT20, HT40 added separately */
1875 c = &ic->ic_channels[ic->ic_nchans++];
1877 c->ic_flags |= IEEE80211_CHAN_HT20;
1883 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
1885 struct ifnet *ifp = sc->sc_ifp;
1886 struct ieee80211com *ic = ifp->if_l2com;
1887 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1888 const struct iwn_chan_band *band = &iwn_bands[n];
1889 struct ieee80211_channel *c, *cent, *extc;
1893 if (!(sc->sc_flags & IWN_FLAG_HAS_11N))
1896 for (i = 0; i < band->nchan; i++) {
1897 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1898 DPRINTF(sc, IWN_DEBUG_RESET,
1899 "skip chan %d flags 0x%x maxpwr %d\n",
1900 band->chan[i], channels[i].flags,
1901 channels[i].maxpwr);
1904 chan = band->chan[i];
1905 nflags = iwn_eeprom_channel_flags(&channels[i]);
1908 * Each entry defines an HT40 channel pair; find the
1909 * center channel, then the extension channel above.
1911 cent = ieee80211_find_channel_byieee(ic, chan,
1912 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
1913 if (cent == NULL) { /* XXX shouldn't happen */
1914 device_printf(sc->sc_dev,
1915 "%s: no entry for channel %d\n", __func__, chan);
1918 extc = ieee80211_find_channel(ic, cent->ic_freq+20,
1919 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
1921 DPRINTF(sc, IWN_DEBUG_RESET,
1922 "%s: skip chan %d, extension channel not found\n",
1927 DPRINTF(sc, IWN_DEBUG_RESET,
1928 "add ht40 chan %d flags 0x%x maxpwr %d\n",
1929 chan, channels[i].flags, channels[i].maxpwr);
1931 c = &ic->ic_channels[ic->ic_nchans++];
1933 c->ic_extieee = extc->ic_ieee;
1934 c->ic_flags &= ~IEEE80211_CHAN_HT;
1935 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags;
1936 c = &ic->ic_channels[ic->ic_nchans++];
1938 c->ic_extieee = cent->ic_ieee;
1939 c->ic_flags &= ~IEEE80211_CHAN_HT;
1940 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags;
1945 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1947 struct ifnet *ifp = sc->sc_ifp;
1948 struct ieee80211com *ic = ifp->if_l2com;
1950 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
1951 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
1954 iwn_read_eeprom_band(sc, n);
1956 iwn_read_eeprom_ht40(sc, n);
1957 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
1960 static struct iwn_eeprom_chan *
1961 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
1963 int band, chan, i, j;
1965 if (IEEE80211_IS_CHAN_HT40(c)) {
1966 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5;
1967 if (IEEE80211_IS_CHAN_HT40D(c))
1968 chan = c->ic_extieee;
1971 for (i = 0; i < iwn_bands[band].nchan; i++) {
1972 if (iwn_bands[band].chan[i] == chan)
1973 return &sc->eeprom_channels[band][i];
1976 for (j = 0; j < 5; j++) {
1977 for (i = 0; i < iwn_bands[j].nchan; i++) {
1978 if (iwn_bands[j].chan[i] == c->ic_ieee)
1979 return &sc->eeprom_channels[j][i];
1987 * Enforce flags read from EEPROM.
1990 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
1991 int nchan, struct ieee80211_channel chans[])
1993 struct iwn_softc *sc = ic->ic_ifp->if_softc;
1996 for (i = 0; i < nchan; i++) {
1997 struct ieee80211_channel *c = &chans[i];
1998 struct iwn_eeprom_chan *channel;
2000 channel = iwn_find_eeprom_channel(sc, c);
2001 if (channel == NULL) {
2002 if_printf(ic->ic_ifp,
2003 "%s: invalid channel %u freq %u/0x%x\n",
2004 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
2007 c->ic_flags |= iwn_eeprom_channel_flags(channel);
2013 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
2016 iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
2018 struct iwn_eeprom_enhinfo enhinfo[35];
2019 struct ifnet *ifp = sc->sc_ifp;
2020 struct ieee80211com *ic = ifp->if_l2com;
2021 struct ieee80211_channel *c;
2027 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2028 base = le16toh(val);
2029 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
2030 enhinfo, sizeof enhinfo);
2032 for (i = 0; i < nitems(enhinfo); i++) {
2033 flags = enhinfo[i].flags;
2034 if (!(flags & IWN_ENHINFO_VALID))
2035 continue; /* Skip invalid entries. */
2038 if (sc->txchainmask & IWN_ANT_A)
2039 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
2040 if (sc->txchainmask & IWN_ANT_B)
2041 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
2042 if (sc->txchainmask & IWN_ANT_C)
2043 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
2044 if (sc->ntxchains == 2)
2045 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
2046 else if (sc->ntxchains == 3)
2047 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
2049 for (j = 0; j < ic->ic_nchans; j++) {
2050 c = &ic->ic_channels[j];
2051 if ((flags & IWN_ENHINFO_5GHZ)) {
2052 if (!IEEE80211_IS_CHAN_A(c))
2054 } else if ((flags & IWN_ENHINFO_OFDM)) {
2055 if (!IEEE80211_IS_CHAN_G(c))
2057 } else if (!IEEE80211_IS_CHAN_B(c))
2059 if ((flags & IWN_ENHINFO_HT40)) {
2060 if (!IEEE80211_IS_CHAN_HT40(c))
2063 if (IEEE80211_IS_CHAN_HT40(c))
2066 if (enhinfo[i].chan != 0 &&
2067 enhinfo[i].chan != c->ic_ieee)
2070 DPRINTF(sc, IWN_DEBUG_RESET,
2071 "channel %d(%x), maxpwr %d\n", c->ic_ieee,
2072 c->ic_flags, maxpwr / 2);
2073 c->ic_maxregpower = maxpwr / 2;
2074 c->ic_maxpower = maxpwr;
2079 static struct ieee80211_node *
2080 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
2082 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO);
2088 switch (rate & 0xff) {
2089 case 12: return 0xd;
2090 case 18: return 0xf;
2091 case 24: return 0x5;
2092 case 36: return 0x7;
2093 case 48: return 0x9;
2094 case 72: return 0xb;
2095 case 96: return 0x1;
2096 case 108: return 0x3;
2100 case 22: return 110;
2106 iwn_newassoc(struct ieee80211_node *ni, int isnew)
2108 #define RV(v) ((v) & IEEE80211_RATE_VAL)
2109 struct ieee80211com *ic = ni->ni_ic;
2110 struct iwn_softc *sc = ic->ic_ifp->if_softc;
2111 struct iwn_node *wn = (void *)ni;
2112 uint8_t txant1, txant2;
2113 int i, plcp, rate, ridx;
2115 /* Use the first valid TX antenna. */
2116 txant1 = IWN_LSB(sc->txchainmask);
2117 txant2 = IWN_LSB(sc->txchainmask & ~txant1);
2119 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
2120 ridx = ni->ni_rates.rs_nrates - 1;
2121 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) {
2122 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS;
2123 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
2124 plcp |= IWN_RFLAG_HT40;
2125 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40)
2126 plcp |= IWN_RFLAG_SGI;
2127 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20)
2128 plcp |= IWN_RFLAG_SGI;
2130 plcp |= IWN_RFLAG_ANT(txant1 | txant2);
2132 plcp |= IWN_RFLAG_ANT(txant1);
2134 rate = RV(ni->ni_rates.rs_rates[ridx]);
2135 wn->ridx[rate] = plcp;
2137 wn->ridx[IEEE80211_RATE_MCS | i] = plcp;
2141 for (i = 0; i < ni->ni_rates.rs_nrates; i++) {
2142 rate = RV(ni->ni_rates.rs_rates[i]);
2143 plcp = rate2plcp(rate);
2144 ridx = ic->ic_rt->rateCodeToIndex[rate];
2145 if (ridx < IWN_RIDX_OFDM6 &&
2146 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
2147 plcp |= IWN_RFLAG_CCK;
2148 plcp |= IWN_RFLAG_ANT(txant1);
2149 wn->ridx[rate] = htole32(plcp);
2156 iwn_media_change(struct ifnet *ifp)
2160 error = ieee80211_media_change(ifp);
2161 /* NB: only the fixed rate can change and that doesn't need a reset */
2162 return (error == ENETRESET ? 0 : error);
2166 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2168 struct iwn_vap *ivp = IWN_VAP(vap);
2169 struct ieee80211com *ic = vap->iv_ic;
2170 struct iwn_softc *sc = ic->ic_ifp->if_softc;
2173 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
2174 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]);
2176 IEEE80211_UNLOCK(ic);
2178 callout_stop(&sc->calib_to);
2181 case IEEE80211_S_ASSOC:
2182 if (vap->iv_state != IEEE80211_S_RUN)
2185 case IEEE80211_S_AUTH:
2186 if (vap->iv_state == IEEE80211_S_AUTH)
2190 * !AUTH -> AUTH transition requires state reset to handle
2191 * reassociations correctly.
2193 sc->rxon.associd = 0;
2194 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
2195 sc->calib.state = IWN_CALIB_STATE_INIT;
2197 if ((error = iwn_auth(sc, vap)) != 0) {
2198 device_printf(sc->sc_dev,
2199 "%s: could not move to auth state\n", __func__);
2203 case IEEE80211_S_RUN:
2205 * RUN -> RUN transition; Just restart the timers.
2207 if (vap->iv_state == IEEE80211_S_RUN) {
2213 * !RUN -> RUN requires setting the association id
2214 * which is done with a firmware cmd. We also defer
2215 * starting the timers until that work is done.
2217 if ((error = iwn_run(sc, vap)) != 0) {
2218 device_printf(sc->sc_dev,
2219 "%s: could not move to run state\n", __func__);
2223 case IEEE80211_S_INIT:
2224 sc->calib.state = IWN_CALIB_STATE_INIT;
2234 return ivp->iv_newstate(vap, nstate, arg);
2238 iwn_calib_timeout(void *arg)
2240 struct iwn_softc *sc = arg;
2242 IWN_LOCK_ASSERT(sc);
2244 /* Force automatic TX power calibration every 60 secs. */
2245 if (++sc->calib_cnt >= 120) {
2248 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2249 "sending request for statistics");
2250 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2254 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
2259 * Process an RX_PHY firmware notification. This is usually immediately
2260 * followed by an MPDU_RX_DONE notification.
2263 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2264 struct iwn_rx_data *data)
2266 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
2268 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
2269 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2271 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
2272 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
2273 sc->last_rx_valid = 1;
2277 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2278 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2281 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2282 struct iwn_rx_data *data)
2284 struct iwn_ops *ops = &sc->ops;
2285 struct ifnet *ifp = sc->sc_ifp;
2286 struct ieee80211com *ic = ifp->if_l2com;
2287 struct iwn_rx_ring *ring = &sc->rxq;
2288 struct ieee80211_frame *wh;
2289 struct ieee80211_node *ni;
2290 struct mbuf *m, *m1;
2291 struct iwn_rx_stat *stat;
2295 int error, len, rssi, nf;
2297 if (desc->type == IWN_MPDU_RX_DONE) {
2298 /* Check for prior RX_PHY notification. */
2299 if (!sc->last_rx_valid) {
2300 DPRINTF(sc, IWN_DEBUG_ANY,
2301 "%s: missing RX_PHY\n", __func__);
2304 stat = &sc->last_rx_stat;
2306 stat = (struct iwn_rx_stat *)(desc + 1);
2308 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2310 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2311 device_printf(sc->sc_dev,
2312 "%s: invalid RX statistic header, len %d\n", __func__,
2316 if (desc->type == IWN_MPDU_RX_DONE) {
2317 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2318 head = (caddr_t)(mpdu + 1);
2319 len = le16toh(mpdu->len);
2321 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
2322 len = le16toh(stat->len);
2325 flags = le32toh(*(uint32_t *)(head + len));
2327 /* Discard frames with a bad FCS early. */
2328 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2329 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n",
2334 /* Discard frames that are too short. */
2335 if (len < sizeof (*wh)) {
2336 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
2342 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE);
2344 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
2349 bus_dmamap_unload(ring->data_dmat, data->map);
2351 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *),
2352 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
2353 if (error != 0 && error != EFBIG) {
2354 device_printf(sc->sc_dev,
2355 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
2358 /* Try to reload the old mbuf. */
2359 error = bus_dmamap_load(ring->data_dmat, data->map,
2360 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
2361 &paddr, BUS_DMA_NOWAIT);
2362 if (error != 0 && error != EFBIG) {
2363 panic("%s: could not load old RX mbuf", __func__);
2365 /* Physical address may have changed. */
2366 ring->desc[ring->cur] = htole32(paddr >> 8);
2367 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map,
2368 BUS_DMASYNC_PREWRITE);
2375 /* Update RX descriptor. */
2376 ring->desc[ring->cur] = htole32(paddr >> 8);
2377 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2378 BUS_DMASYNC_PREWRITE);
2380 /* Finalize mbuf. */
2381 m->m_pkthdr.rcvif = ifp;
2383 m->m_pkthdr.len = m->m_len = len;
2385 /* Grab a reference to the source node. */
2386 wh = mtod(m, struct ieee80211_frame *);
2387 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2388 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
2389 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
2391 rssi = ops->get_rssi(sc, stat);
2393 if (ieee80211_radiotap_active(ic)) {
2394 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2397 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2398 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2399 tap->wr_dbm_antsignal = (int8_t)rssi;
2400 tap->wr_dbm_antnoise = (int8_t)nf;
2401 tap->wr_tsft = stat->tstamp;
2402 switch (stat->rate) {
2404 case 10: tap->wr_rate = 2; break;
2405 case 20: tap->wr_rate = 4; break;
2406 case 55: tap->wr_rate = 11; break;
2407 case 110: tap->wr_rate = 22; break;
2409 case 0xd: tap->wr_rate = 12; break;
2410 case 0xf: tap->wr_rate = 18; break;
2411 case 0x5: tap->wr_rate = 24; break;
2412 case 0x7: tap->wr_rate = 36; break;
2413 case 0x9: tap->wr_rate = 48; break;
2414 case 0xb: tap->wr_rate = 72; break;
2415 case 0x1: tap->wr_rate = 96; break;
2416 case 0x3: tap->wr_rate = 108; break;
2417 /* Unknown rate: should not happen. */
2418 default: tap->wr_rate = 0;
2424 /* Send the frame to the 802.11 layer. */
2426 if (ni->ni_flags & IEEE80211_NODE_HT)
2427 m->m_flags |= M_AMPDU;
2428 (void)ieee80211_input(ni, m, rssi - nf, nf);
2429 /* Node is no longer needed. */
2430 ieee80211_free_node(ni);
2432 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
2437 /* Process an incoming Compressed BlockAck. */
2439 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2440 struct iwn_rx_data *data)
2442 struct ifnet *ifp = sc->sc_ifp;
2443 struct iwn_node *wn;
2444 struct ieee80211_node *ni;
2445 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2446 struct iwn_tx_ring *txq;
2447 struct ieee80211_tx_ampdu *tap;
2450 int ackfailcnt = 0, i, shift;
2452 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2454 txq = &sc->txq[le16toh(ba->qid)];
2455 tap = sc->qid2tap[le16toh(ba->qid)];
2456 tid = WME_AC_TO_TID(tap->txa_ac);
2460 if (wn->agg[tid].bitmap == 0)
2463 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff);
2467 if (wn->agg[tid].nframes > (64 - shift))
2470 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap;
2471 for (i = 0; bitmap; i++) {
2472 if ((bitmap & 1) == 0) {
2474 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
2475 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2478 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
2479 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2486 * Process a CALIBRATION_RESULT notification sent by the initialization
2487 * firmware on response to a CMD_CALIB_CONFIG command (5000 only).
2490 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2491 struct iwn_rx_data *data)
2493 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2496 /* Runtime firmware should not send such a notification. */
2497 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2500 len = (le32toh(desc->len) & 0x3fff) - 4;
2501 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2503 switch (calib->code) {
2504 case IWN5000_PHY_CALIB_DC:
2505 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 &&
2506 (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2507 sc->hw_type >= IWN_HW_REV_TYPE_6000))
2510 case IWN5000_PHY_CALIB_LO:
2513 case IWN5000_PHY_CALIB_TX_IQ:
2516 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2517 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2518 sc->hw_type != IWN_HW_REV_TYPE_5150)
2521 case IWN5000_PHY_CALIB_BASE_BAND:
2525 if (idx == -1) /* Ignore other results. */
2528 /* Save calibration result. */
2529 if (sc->calibcmd[idx].buf != NULL)
2530 free(sc->calibcmd[idx].buf, M_DEVBUF);
2531 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
2532 if (sc->calibcmd[idx].buf == NULL) {
2533 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2534 "not enough memory for calibration result %d\n",
2538 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2539 "saving calibration result code=%d len=%d\n", calib->code, len);
2540 sc->calibcmd[idx].len = len;
2541 memcpy(sc->calibcmd[idx].buf, calib, len);
2545 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2546 * The latter is sent by the firmware after each received beacon.
2549 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2550 struct iwn_rx_data *data)
2552 struct iwn_ops *ops = &sc->ops;
2553 struct ifnet *ifp = sc->sc_ifp;
2554 struct ieee80211com *ic = ifp->if_l2com;
2555 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2556 struct iwn_calib_state *calib = &sc->calib;
2557 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2560 /* Ignore statistics received during a scan. */
2561 if (vap->iv_state != IEEE80211_S_RUN ||
2562 (ic->ic_flags & IEEE80211_F_SCAN))
2565 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2567 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n",
2568 __func__, desc->type);
2569 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */
2571 /* Test if temperature has changed. */
2572 if (stats->general.temp != sc->rawtemp) {
2573 /* Convert "raw" temperature to degC. */
2574 sc->rawtemp = stats->general.temp;
2575 temp = ops->get_temperature(sc);
2576 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
2579 /* Update TX power if need be (4965AGN only). */
2580 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2581 iwn4965_power_calibration(sc, temp);
2584 if (desc->type != IWN_BEACON_STATISTICS)
2585 return; /* Reply to a statistics request. */
2587 sc->noise = iwn_get_noise(&stats->rx.general);
2588 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
2590 /* Test that RSSI and noise are present in stats report. */
2591 if (le32toh(stats->rx.general.flags) != 1) {
2592 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
2593 "received statistics without RSSI");
2597 if (calib->state == IWN_CALIB_STATE_ASSOC)
2598 iwn_collect_noise(sc, &stats->rx.general);
2599 else if (calib->state == IWN_CALIB_STATE_RUN)
2600 iwn_tune_sensitivity(sc, &stats->rx);
2604 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2605 * and 5000 adapters have different incompatible TX status formats.
2608 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2609 struct iwn_rx_data *data)
2611 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2612 struct iwn_tx_ring *ring;
2615 qid = desc->qid & 0xf;
2616 ring = &sc->txq[qid];
2618 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2619 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2620 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2621 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2622 le32toh(stat->status));
2624 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2625 if (qid >= sc->firstaggqueue) {
2626 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
2629 iwn_tx_done(sc, desc, stat->ackfailcnt,
2630 le32toh(stat->status) & 0xff);
2635 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2636 struct iwn_rx_data *data)
2638 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2639 struct iwn_tx_ring *ring;
2642 qid = desc->qid & 0xf;
2643 ring = &sc->txq[qid];
2645 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2646 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2647 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2648 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2649 le32toh(stat->status));
2652 /* Reset TX scheduler slot. */
2653 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2656 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2657 if (qid >= sc->firstaggqueue) {
2658 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
2661 iwn_tx_done(sc, desc, stat->ackfailcnt,
2662 le16toh(stat->status) & 0xff);
2667 * Adapter-independent backend for TX_DONE firmware notifications.
2670 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2673 struct ifnet *ifp = sc->sc_ifp;
2674 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2675 struct iwn_tx_data *data = &ring->data[desc->idx];
2677 struct ieee80211_node *ni;
2678 struct ieee80211vap *vap;
2680 KASSERT(data->ni != NULL, ("no node"));
2682 /* Unmap and free mbuf. */
2683 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
2684 bus_dmamap_unload(ring->data_dmat, data->map);
2685 m = data->m, data->m = NULL;
2686 ni = data->ni, data->ni = NULL;
2689 if (m->m_flags & M_TXCB) {
2691 * Channels marked for "radar" require traffic to be received
2692 * to unlock before we can transmit. Until traffic is seen
2693 * any attempt to transmit is returned immediately with status
2694 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
2695 * happen on first authenticate after scanning. To workaround
2696 * this we ignore a failure of this sort in AUTH state so the
2697 * 802.11 layer will fall back to using a timeout to wait for
2698 * the AUTH reply. This allows the firmware time to see
2699 * traffic so a subsequent retry of AUTH succeeds. It's
2700 * unclear why the firmware does not maintain state for
2701 * channels recently visited as this would allow immediate
2702 * use of the channel after a scan (where we see traffic).
2704 if (status == IWN_TX_FAIL_TX_LOCKED &&
2705 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
2706 ieee80211_process_callback(ni, m, 0);
2708 ieee80211_process_callback(ni, m,
2709 (status & IWN_TX_FAIL) != 0);
2713 * Update rate control statistics for the node.
2715 if (status & IWN_TX_FAIL) {
2717 ieee80211_ratectl_tx_complete(vap, ni,
2718 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2721 ieee80211_ratectl_tx_complete(vap, ni,
2722 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2725 ieee80211_free_node(ni);
2727 sc->sc_tx_timer = 0;
2728 if (--ring->queued < IWN_TX_RING_LOMARK) {
2729 sc->qfullmsk &= ~(1 << ring->qid);
2730 if (sc->qfullmsk == 0 &&
2731 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
2732 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2733 iwn_start_locked(ifp);
2739 * Process a "command done" firmware notification. This is where we wakeup
2740 * processes waiting for a synchronous command completion.
2743 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2745 struct iwn_tx_ring *ring = &sc->txq[4];
2746 struct iwn_tx_data *data;
2748 if ((desc->qid & 0xf) != 4)
2749 return; /* Not a command ack. */
2751 data = &ring->data[desc->idx];
2753 /* If the command was mapped in an mbuf, free it. */
2754 if (data->m != NULL) {
2755 bus_dmamap_sync(ring->data_dmat, data->map,
2756 BUS_DMASYNC_POSTWRITE);
2757 bus_dmamap_unload(ring->data_dmat, data->map);
2761 wakeup(&ring->desc[desc->idx]);
2765 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes,
2768 struct ifnet *ifp = sc->sc_ifp;
2769 struct iwn_tx_ring *ring = &sc->txq[qid];
2770 struct iwn_tx_data *data;
2772 struct iwn_node *wn;
2773 struct ieee80211_node *ni;
2774 struct ieee80211vap *vap;
2775 struct ieee80211_tx_ampdu *tap;
2777 uint32_t *status = stat;
2778 uint16_t *aggstatus = stat;
2780 int bit, i, lastidx, seqno, shift, start;
2784 if ((*status & 0xff) != 1 && (*status & 0xff) != 2)
2785 printf("ieee80211_send_bar()\n");
2791 for (i = 0; i < nframes; i++) {
2792 if (le16toh(aggstatus[i * 2]) & 0xc)
2795 idx = le16toh(aggstatus[2*i + 1]) & 0xff;
2799 shift = 0x100 - idx + start;
2802 } else if (bit <= -64)
2803 bit = 0x100 - start + idx;
2805 shift = start - idx;
2809 bitmap = bitmap << shift;
2810 bitmap |= 1ULL << bit;
2812 tap = sc->qid2tap[qid];
2813 tid = WME_AC_TO_TID(tap->txa_ac);
2814 wn = (void *)tap->txa_ni;
2815 wn->agg[tid].bitmap = bitmap;
2816 wn->agg[tid].startidx = start;
2817 wn->agg[tid].nframes = nframes;
2819 seqno = le32toh(*(status + nframes)) & 0xfff;
2820 for (lastidx = (seqno & 0xff); ring->read != lastidx;) {
2821 data = &ring->data[ring->read];
2823 KASSERT(data->ni != NULL, ("no node"));
2825 /* Unmap and free mbuf. */
2826 bus_dmamap_sync(ring->data_dmat, data->map,
2827 BUS_DMASYNC_POSTWRITE);
2828 bus_dmamap_unload(ring->data_dmat, data->map);
2829 m = data->m, data->m = NULL;
2830 ni = data->ni, data->ni = NULL;
2833 if (m->m_flags & M_TXCB)
2834 ieee80211_process_callback(ni, m, 1);
2837 ieee80211_free_node(ni);
2840 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT;
2843 sc->sc_tx_timer = 0;
2844 if (ring->queued < IWN_TX_RING_LOMARK) {
2845 sc->qfullmsk &= ~(1 << ring->qid);
2846 if (sc->qfullmsk == 0 &&
2847 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
2848 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2849 iwn_start_locked(ifp);
2855 * Process an INT_FH_RX or INT_SW_RX interrupt.
2858 iwn_notif_intr(struct iwn_softc *sc)
2860 struct iwn_ops *ops = &sc->ops;
2861 struct ifnet *ifp = sc->sc_ifp;
2862 struct ieee80211com *ic = ifp->if_l2com;
2863 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2866 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
2867 BUS_DMASYNC_POSTREAD);
2869 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2870 while (sc->rxq.cur != hw) {
2871 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2872 struct iwn_rx_desc *desc;
2874 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2875 BUS_DMASYNC_POSTREAD);
2876 desc = mtod(data->m, struct iwn_rx_desc *);
2878 DPRINTF(sc, IWN_DEBUG_RECV,
2879 "%s: qid %x idx %d flags %x type %d(%s) len %d\n",
2880 __func__, desc->qid & 0xf, desc->idx, desc->flags,
2881 desc->type, iwn_intr_str(desc->type),
2882 le16toh(desc->len));
2884 if (!(desc->qid & 0x80)) /* Reply to a command. */
2885 iwn_cmd_done(sc, desc);
2887 switch (desc->type) {
2889 iwn_rx_phy(sc, desc, data);
2892 case IWN_RX_DONE: /* 4965AGN only. */
2893 case IWN_MPDU_RX_DONE:
2894 /* An 802.11 frame has been received. */
2895 iwn_rx_done(sc, desc, data);
2898 case IWN_RX_COMPRESSED_BA:
2899 /* A Compressed BlockAck has been received. */
2900 iwn_rx_compressed_ba(sc, desc, data);
2904 /* An 802.11 frame has been transmitted. */
2905 ops->tx_done(sc, desc, data);
2908 case IWN_RX_STATISTICS:
2909 case IWN_BEACON_STATISTICS:
2910 iwn_rx_statistics(sc, desc, data);
2913 case IWN_BEACON_MISSED:
2915 struct iwn_beacon_missed *miss =
2916 (struct iwn_beacon_missed *)(desc + 1);
2919 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2920 BUS_DMASYNC_POSTREAD);
2921 misses = le32toh(miss->consecutive);
2923 DPRINTF(sc, IWN_DEBUG_STATE,
2924 "%s: beacons missed %d/%d\n", __func__,
2925 misses, le32toh(miss->total));
2927 * If more than 5 consecutive beacons are missed,
2928 * reinitialize the sensitivity state machine.
2930 if (vap->iv_state == IEEE80211_S_RUN &&
2931 (ic->ic_flags & IEEE80211_F_SCAN) != 0) {
2933 (void)iwn_init_sensitivity(sc);
2934 if (misses >= vap->iv_bmissthreshold) {
2936 ieee80211_beacon_miss(ic);
2944 struct iwn_ucode_info *uc =
2945 (struct iwn_ucode_info *)(desc + 1);
2947 /* The microcontroller is ready. */
2948 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2949 BUS_DMASYNC_POSTREAD);
2950 DPRINTF(sc, IWN_DEBUG_RESET,
2951 "microcode alive notification version=%d.%d "
2952 "subtype=%x alive=%x\n", uc->major, uc->minor,
2953 uc->subtype, le32toh(uc->valid));
2955 if (le32toh(uc->valid) != 1) {
2956 device_printf(sc->sc_dev,
2957 "microcontroller initialization failed");
2960 if (uc->subtype == IWN_UCODE_INIT) {
2961 /* Save microcontroller report. */
2962 memcpy(&sc->ucode_info, uc, sizeof (*uc));
2964 /* Save the address of the error log in SRAM. */
2965 sc->errptr = le32toh(uc->errptr);
2968 case IWN_STATE_CHANGED:
2970 uint32_t *status = (uint32_t *)(desc + 1);
2973 * State change allows hardware switch change to be
2974 * noted. However, we handle this in iwn_intr as we
2975 * get both the enable/disble intr.
2977 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2978 BUS_DMASYNC_POSTREAD);
2979 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
2983 case IWN_START_SCAN:
2985 struct iwn_start_scan *scan =
2986 (struct iwn_start_scan *)(desc + 1);
2988 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2989 BUS_DMASYNC_POSTREAD);
2990 DPRINTF(sc, IWN_DEBUG_ANY,
2991 "%s: scanning channel %d status %x\n",
2992 __func__, scan->chan, le32toh(scan->status));
2997 struct iwn_stop_scan *scan =
2998 (struct iwn_stop_scan *)(desc + 1);
3000 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3001 BUS_DMASYNC_POSTREAD);
3002 DPRINTF(sc, IWN_DEBUG_STATE,
3003 "scan finished nchan=%d status=%d chan=%d\n",
3004 scan->nchan, scan->status, scan->chan);
3007 ieee80211_scan_next(vap);
3011 case IWN5000_CALIBRATION_RESULT:
3012 iwn5000_rx_calib_results(sc, desc, data);
3015 case IWN5000_CALIBRATION_DONE:
3016 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
3021 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
3024 /* Tell the firmware what we have processed. */
3025 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
3026 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
3030 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
3031 * from power-down sleep mode.
3034 iwn_wakeup_intr(struct iwn_softc *sc)
3038 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
3041 /* Wakeup RX and TX rings. */
3042 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
3043 for (qid = 0; qid < sc->ntxqs; qid++) {
3044 struct iwn_tx_ring *ring = &sc->txq[qid];
3045 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
3050 iwn_rftoggle_intr(struct iwn_softc *sc)
3052 struct ifnet *ifp = sc->sc_ifp;
3053 struct ieee80211com *ic = ifp->if_l2com;
3054 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
3056 IWN_LOCK_ASSERT(sc);
3058 device_printf(sc->sc_dev, "RF switch: radio %s\n",
3059 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
3060 if (tmp & IWN_GP_CNTRL_RFKILL)
3061 ieee80211_runtask(ic, &sc->sc_radioon_task);
3063 ieee80211_runtask(ic, &sc->sc_radiooff_task);
3067 * Dump the error log of the firmware when a firmware panic occurs. Although
3068 * we can't debug the firmware because it is neither open source nor free, it
3069 * can help us to identify certain classes of problems.
3072 iwn_fatal_intr(struct iwn_softc *sc)
3074 struct iwn_fw_dump dump;
3077 IWN_LOCK_ASSERT(sc);
3079 /* Force a complete recalibration on next init. */
3080 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
3082 /* Check that the error log address is valid. */
3083 if (sc->errptr < IWN_FW_DATA_BASE ||
3084 sc->errptr + sizeof (dump) >
3085 IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
3086 printf("%s: bad firmware error log address 0x%08x\n", __func__,
3090 if (iwn_nic_lock(sc) != 0) {
3091 printf("%s: could not read firmware error log\n", __func__);
3094 /* Read firmware error log from SRAM. */
3095 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
3096 sizeof (dump) / sizeof (uint32_t));
3099 if (dump.valid == 0) {
3100 printf("%s: firmware error log is empty\n", __func__);
3103 printf("firmware error log:\n");
3104 printf(" error type = \"%s\" (0x%08X)\n",
3105 (dump.id < nitems(iwn_fw_errmsg)) ?
3106 iwn_fw_errmsg[dump.id] : "UNKNOWN",
3108 printf(" program counter = 0x%08X\n", dump.pc);
3109 printf(" source line = 0x%08X\n", dump.src_line);
3110 printf(" error data = 0x%08X%08X\n",
3111 dump.error_data[0], dump.error_data[1]);
3112 printf(" branch link = 0x%08X%08X\n",
3113 dump.branch_link[0], dump.branch_link[1]);
3114 printf(" interrupt link = 0x%08X%08X\n",
3115 dump.interrupt_link[0], dump.interrupt_link[1]);
3116 printf(" time = %u\n", dump.time[0]);
3118 /* Dump driver status (TX and RX rings) while we're here. */
3119 printf("driver status:\n");
3120 for (i = 0; i < sc->ntxqs; i++) {
3121 struct iwn_tx_ring *ring = &sc->txq[i];
3122 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
3123 i, ring->qid, ring->cur, ring->queued);
3125 printf(" rx ring: cur=%d\n", sc->rxq.cur);
3131 struct iwn_softc *sc = arg;
3132 struct ifnet *ifp = sc->sc_ifp;
3133 uint32_t r1, r2, tmp;
3137 /* Disable interrupts. */
3138 IWN_WRITE(sc, IWN_INT_MASK, 0);
3140 /* Read interrupts from ICT (fast) or from registers (slow). */
3141 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
3143 while (sc->ict[sc->ict_cur] != 0) {
3144 tmp |= sc->ict[sc->ict_cur];
3145 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
3146 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
3149 if (tmp == 0xffffffff) /* Shouldn't happen. */
3151 else if (tmp & 0xc0000) /* Workaround a HW bug. */
3153 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
3154 r2 = 0; /* Unused. */
3156 r1 = IWN_READ(sc, IWN_INT);
3157 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
3158 return; /* Hardware gone! */
3159 r2 = IWN_READ(sc, IWN_FH_INT);
3162 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2);
3164 if (r1 == 0 && r2 == 0)
3165 goto done; /* Interrupt not for us. */
3167 /* Acknowledge interrupts. */
3168 IWN_WRITE(sc, IWN_INT, r1);
3169 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
3170 IWN_WRITE(sc, IWN_FH_INT, r2);
3172 if (r1 & IWN_INT_RF_TOGGLED) {
3173 iwn_rftoggle_intr(sc);
3176 if (r1 & IWN_INT_CT_REACHED) {
3177 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
3180 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
3181 device_printf(sc->sc_dev, "%s: fatal firmware error\n",
3183 /* Dump firmware error log and stop. */
3185 ifp->if_flags &= ~IFF_UP;
3186 iwn_stop_locked(sc);
3189 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
3190 (r2 & IWN_FH_INT_RX)) {
3191 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
3192 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
3193 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
3194 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
3195 IWN_INT_PERIODIC_DIS);
3197 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
3198 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
3199 IWN_INT_PERIODIC_ENA);
3205 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
3206 if (sc->sc_flags & IWN_FLAG_USE_ICT)
3207 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
3208 wakeup(sc); /* FH DMA transfer completed. */
3211 if (r1 & IWN_INT_ALIVE)
3212 wakeup(sc); /* Firmware is alive. */
3214 if (r1 & IWN_INT_WAKEUP)
3215 iwn_wakeup_intr(sc);
3218 /* Re-enable interrupts. */
3219 if (ifp->if_flags & IFF_UP)
3220 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
3226 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
3227 * 5000 adapters use a slightly different format).
3230 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
3233 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
3235 *w = htole16(len + 8);
3236 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3237 BUS_DMASYNC_PREWRITE);
3238 if (idx < IWN_SCHED_WINSZ) {
3239 *(w + IWN_TX_RING_COUNT) = *w;
3240 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3241 BUS_DMASYNC_PREWRITE);
3246 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
3249 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
3251 *w = htole16(id << 12 | (len + 8));
3252 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3253 BUS_DMASYNC_PREWRITE);
3254 if (idx < IWN_SCHED_WINSZ) {
3255 *(w + IWN_TX_RING_COUNT) = *w;
3256 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3257 BUS_DMASYNC_PREWRITE);
3263 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
3265 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
3267 *w = (*w & htole16(0xf000)) | htole16(1);
3268 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3269 BUS_DMASYNC_PREWRITE);
3270 if (idx < IWN_SCHED_WINSZ) {
3271 *(w + IWN_TX_RING_COUNT) = *w;
3272 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3273 BUS_DMASYNC_PREWRITE);
3279 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
3281 struct iwn_ops *ops = &sc->ops;
3282 const struct ieee80211_txparam *tp;
3283 struct ieee80211vap *vap = ni->ni_vap;
3284 struct ieee80211com *ic = ni->ni_ic;
3285 struct iwn_node *wn = (void *)ni;
3286 struct iwn_tx_ring *ring;
3287 struct iwn_tx_desc *desc;
3288 struct iwn_tx_data *data;
3289 struct iwn_tx_cmd *cmd;
3290 struct iwn_cmd_data *tx;
3291 struct ieee80211_frame *wh;
3292 struct ieee80211_key *k = NULL;
3297 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
3298 uint8_t tid, ridx, txant, type;
3299 int ac, i, totlen, error, pad, nsegs = 0, rate;
3301 IWN_LOCK_ASSERT(sc);
3303 wh = mtod(m, struct ieee80211_frame *);
3304 hdrlen = ieee80211_anyhdrsize(wh);
3305 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3307 /* Select EDCA Access Category and TX ring for this frame. */
3308 if (IEEE80211_QOS_HAS_SEQ(wh)) {
3309 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
3310 tid = qos & IEEE80211_QOS_TID;
3315 ac = M_WME_GETAC(m);
3317 if (IEEE80211_QOS_HAS_SEQ(wh) &&
3318 IEEE80211_AMPDU_RUNNING(&ni->ni_tx_ampdu[ac])) {
3319 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac];
3321 ring = &sc->txq[*(int *)tap->txa_private];
3322 *(uint16_t *)wh->i_seq =
3323 htole16(ni->ni_txseqs[tid] << IEEE80211_SEQ_SEQ_SHIFT);
3324 ni->ni_txseqs[tid]++;
3326 ring = &sc->txq[ac];
3328 desc = &ring->desc[ring->cur];
3329 data = &ring->data[ring->cur];
3331 /* Choose a TX rate index. */
3332 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
3333 if (type == IEEE80211_FC0_TYPE_MGT)
3334 rate = tp->mgmtrate;
3335 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
3336 rate = tp->mcastrate;
3337 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
3338 rate = tp->ucastrate;
3340 /* XXX pass pktlen */
3341 (void) ieee80211_ratectl_rate(ni, NULL, 0);
3342 rate = ni->ni_txrate;
3344 ridx = ic->ic_rt->rateCodeToIndex[rate];
3346 /* Encrypt the frame if need be. */
3347 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
3348 /* Retrieve key for TX. */
3349 k = ieee80211_crypto_encap(ni, m);
3354 /* 802.11 header may have moved. */
3355 wh = mtod(m, struct ieee80211_frame *);
3357 totlen = m->m_pkthdr.len;
3359 if (ieee80211_radiotap_active_vap(vap)) {
3360 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3363 tap->wt_rate = rate;
3365 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3367 ieee80211_radiotap_tx(vap, m);
3370 /* Prepare TX firmware command. */
3371 cmd = &ring->cmd[ring->cur];
3372 cmd->code = IWN_CMD_TX_DATA;
3374 cmd->qid = ring->qid;
3375 cmd->idx = ring->cur;
3377 tx = (struct iwn_cmd_data *)cmd->data;
3378 /* NB: No need to clear tx, all fields are reinitialized here. */
3379 tx->scratch = 0; /* clear "scratch" area */
3382 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3383 /* Unicast frame, check if an ACK is expected. */
3384 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
3385 IEEE80211_QOS_ACKPOLICY_NOACK)
3386 flags |= IWN_TX_NEED_ACK;
3389 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
3390 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
3391 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
3393 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
3394 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
3396 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
3397 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3398 /* NB: Group frames are sent using CCK in 802.11b/g. */
3399 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
3400 flags |= IWN_TX_NEED_RTS;
3401 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3402 ridx >= IWN_RIDX_OFDM6) {
3403 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3404 flags |= IWN_TX_NEED_CTS;
3405 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3406 flags |= IWN_TX_NEED_RTS;
3408 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
3409 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3410 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3411 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
3412 flags |= IWN_TX_NEED_PROTECTION;
3414 flags |= IWN_TX_FULL_TXOP;
3418 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3419 type != IEEE80211_FC0_TYPE_DATA)
3420 tx->id = sc->broadcast_id;
3424 if (type == IEEE80211_FC0_TYPE_MGT) {
3425 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3427 /* Tell HW to set timestamp in probe responses. */
3428 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3429 flags |= IWN_TX_INSERT_TSTAMP;
3430 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3431 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3432 tx->timeout = htole16(3);
3434 tx->timeout = htole16(2);
3436 tx->timeout = htole16(0);
3439 /* First segment length must be a multiple of 4. */
3440 flags |= IWN_TX_NEED_PADDING;
3441 pad = 4 - (hdrlen & 3);
3445 tx->len = htole16(totlen);
3447 tx->rts_ntries = 60;
3448 tx->data_ntries = 15;
3449 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3450 tx->rate = wn->ridx[rate];
3451 if (tx->id == sc->broadcast_id) {
3452 /* Group or management frame. */
3454 /* XXX Alternate between antenna A and B? */
3455 txant = IWN_LSB(sc->txchainmask);
3456 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
3458 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1;
3459 flags |= IWN_TX_LINKQ; /* enable MRR */
3461 /* Set physical address of "scratch area". */
3462 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3463 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3465 /* Copy 802.11 header in TX command. */
3466 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3468 /* Trim 802.11 header. */
3471 tx->flags = htole32(flags);
3473 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
3474 &nsegs, BUS_DMA_NOWAIT);
3476 if (error != EFBIG) {
3477 device_printf(sc->sc_dev,
3478 "%s: can't map mbuf (error %d)\n", __func__, error);
3482 /* Too many DMA segments, linearize mbuf. */
3483 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER);
3485 device_printf(sc->sc_dev,
3486 "%s: could not defrag mbuf\n", __func__);
3492 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
3493 segs, &nsegs, BUS_DMA_NOWAIT);
3495 device_printf(sc->sc_dev,
3496 "%s: can't map mbuf (error %d)\n", __func__, error);
3505 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3506 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3508 /* Fill TX descriptor. */
3511 desc->nsegs += nsegs;
3512 /* First DMA segment is used by the TX command. */
3513 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3514 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3515 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3516 /* Other DMA segments are for data payload. */
3518 for (i = 1; i <= nsegs; i++) {
3519 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3520 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3525 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3526 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3527 BUS_DMASYNC_PREWRITE);
3528 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3529 BUS_DMASYNC_PREWRITE);
3531 /* Update TX scheduler. */
3532 if (ring->qid >= sc->firstaggqueue)
3533 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3536 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3537 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3539 /* Mark TX ring as full if we reach a certain threshold. */
3540 if (++ring->queued > IWN_TX_RING_HIMARK)
3541 sc->qfullmsk |= 1 << ring->qid;
3547 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
3548 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3550 struct iwn_ops *ops = &sc->ops;
3551 struct ifnet *ifp = sc->sc_ifp;
3552 struct ieee80211vap *vap = ni->ni_vap;
3553 struct ieee80211com *ic = ifp->if_l2com;
3554 struct iwn_tx_cmd *cmd;
3555 struct iwn_cmd_data *tx;
3556 struct ieee80211_frame *wh;
3557 struct iwn_tx_ring *ring;
3558 struct iwn_tx_desc *desc;
3559 struct iwn_tx_data *data;
3561 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
3564 int ac, totlen, error, pad, nsegs = 0, i, rate;
3565 uint8_t ridx, type, txant;
3567 IWN_LOCK_ASSERT(sc);
3569 wh = mtod(m, struct ieee80211_frame *);
3570 hdrlen = ieee80211_anyhdrsize(wh);
3571 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3573 ac = params->ibp_pri & 3;
3575 ring = &sc->txq[ac];
3576 desc = &ring->desc[ring->cur];
3577 data = &ring->data[ring->cur];
3579 /* Choose a TX rate index. */
3580 rate = params->ibp_rate0;
3581 ridx = ic->ic_rt->rateCodeToIndex[rate];
3582 if (ridx == (uint8_t)-1) {
3583 /* XXX fall back to mcast/mgmt rate? */
3588 totlen = m->m_pkthdr.len;
3590 /* Prepare TX firmware command. */
3591 cmd = &ring->cmd[ring->cur];
3592 cmd->code = IWN_CMD_TX_DATA;
3594 cmd->qid = ring->qid;
3595 cmd->idx = ring->cur;
3597 tx = (struct iwn_cmd_data *)cmd->data;
3598 /* NB: No need to clear tx, all fields are reinitialized here. */
3599 tx->scratch = 0; /* clear "scratch" area */
3602 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3603 flags |= IWN_TX_NEED_ACK;
3604 if (params->ibp_flags & IEEE80211_BPF_RTS) {
3605 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3606 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3607 flags &= ~IWN_TX_NEED_RTS;
3608 flags |= IWN_TX_NEED_PROTECTION;
3610 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
3612 if (params->ibp_flags & IEEE80211_BPF_CTS) {
3613 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3614 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3615 flags &= ~IWN_TX_NEED_CTS;
3616 flags |= IWN_TX_NEED_PROTECTION;
3618 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
3620 if (type == IEEE80211_FC0_TYPE_MGT) {
3621 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3623 /* Tell HW to set timestamp in probe responses. */
3624 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3625 flags |= IWN_TX_INSERT_TSTAMP;
3627 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3628 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3629 tx->timeout = htole16(3);
3631 tx->timeout = htole16(2);
3633 tx->timeout = htole16(0);
3636 /* First segment length must be a multiple of 4. */
3637 flags |= IWN_TX_NEED_PADDING;
3638 pad = 4 - (hdrlen & 3);
3642 if (ieee80211_radiotap_active_vap(vap)) {
3643 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3646 tap->wt_rate = rate;
3648 ieee80211_radiotap_tx(vap, m);
3651 tx->len = htole16(totlen);
3653 tx->id = sc->broadcast_id;
3654 tx->rts_ntries = params->ibp_try1;
3655 tx->data_ntries = params->ibp_try0;
3656 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3657 tx->rate = htole32(rate2plcp(rate));
3658 if (ridx < IWN_RIDX_OFDM6 &&
3659 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
3660 tx->rate |= htole32(IWN_RFLAG_CCK);
3661 /* Group or management frame. */
3663 txant = IWN_LSB(sc->txchainmask);
3664 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
3665 /* Set physical address of "scratch area". */
3666 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3667 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3669 /* Copy 802.11 header in TX command. */
3670 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3672 /* Trim 802.11 header. */
3675 tx->flags = htole32(flags);
3677 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
3678 &nsegs, BUS_DMA_NOWAIT);
3680 if (error != EFBIG) {
3681 device_printf(sc->sc_dev,
3682 "%s: can't map mbuf (error %d)\n", __func__, error);
3686 /* Too many DMA segments, linearize mbuf. */
3687 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER);
3689 device_printf(sc->sc_dev,
3690 "%s: could not defrag mbuf\n", __func__);
3696 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
3697 segs, &nsegs, BUS_DMA_NOWAIT);
3699 device_printf(sc->sc_dev,
3700 "%s: can't map mbuf (error %d)\n", __func__, error);
3709 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3710 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3712 /* Fill TX descriptor. */
3715 desc->nsegs += nsegs;
3716 /* First DMA segment is used by the TX command. */
3717 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3718 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3719 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3720 /* Other DMA segments are for data payload. */
3722 for (i = 1; i <= nsegs; i++) {
3723 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3724 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3729 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3730 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3731 BUS_DMASYNC_PREWRITE);
3732 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3733 BUS_DMASYNC_PREWRITE);
3735 /* Update TX scheduler. */
3736 if (ring->qid >= sc->firstaggqueue)
3737 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3740 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3741 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3743 /* Mark TX ring as full if we reach a certain threshold. */
3744 if (++ring->queued > IWN_TX_RING_HIMARK)
3745 sc->qfullmsk |= 1 << ring->qid;
3751 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3752 const struct ieee80211_bpf_params *params)
3754 struct ieee80211com *ic = ni->ni_ic;
3755 struct ifnet *ifp = ic->ic_ifp;
3756 struct iwn_softc *sc = ifp->if_softc;
3759 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3760 ieee80211_free_node(ni);
3766 if (params == NULL) {
3768 * Legacy path; interpret frame contents to decide
3769 * precisely how to send the frame.
3771 error = iwn_tx_data(sc, m, ni);
3774 * Caller supplied explicit parameters to use in
3775 * sending the frame.
3777 error = iwn_tx_data_raw(sc, m, ni, params);
3780 /* NB: m is reclaimed on tx failure */
3781 ieee80211_free_node(ni);
3784 sc->sc_tx_timer = 5;
3791 iwn_start(struct ifnet *ifp)
3793 struct iwn_softc *sc = ifp->if_softc;
3796 iwn_start_locked(ifp);
3801 iwn_start_locked(struct ifnet *ifp)
3803 struct iwn_softc *sc = ifp->if_softc;
3804 struct ieee80211_node *ni;
3807 IWN_LOCK_ASSERT(sc);
3809 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
3810 (ifp->if_drv_flags & IFF_DRV_OACTIVE))
3814 if (sc->qfullmsk != 0) {
3815 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3818 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
3821 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3822 if (iwn_tx_data(sc, m, ni) != 0) {
3823 ieee80211_free_node(ni);
3827 sc->sc_tx_timer = 5;
3832 iwn_watchdog(void *arg)
3834 struct iwn_softc *sc = arg;
3835 struct ifnet *ifp = sc->sc_ifp;
3836 struct ieee80211com *ic = ifp->if_l2com;
3838 IWN_LOCK_ASSERT(sc);
3840 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
3842 if (sc->sc_tx_timer > 0) {
3843 if (--sc->sc_tx_timer == 0) {
3844 if_printf(ifp, "device timeout\n");
3845 ieee80211_runtask(ic, &sc->sc_reinit_task);
3849 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
3853 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3855 struct iwn_softc *sc = ifp->if_softc;
3856 struct ieee80211com *ic = ifp->if_l2com;
3857 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3858 struct ifreq *ifr = (struct ifreq *) data;
3859 int error = 0, startall = 0, stop = 0;
3863 error = ether_ioctl(ifp, cmd, data);
3867 if (ifp->if_flags & IFF_UP) {
3868 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3869 iwn_init_locked(sc);
3870 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
3876 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3877 iwn_stop_locked(sc);
3881 ieee80211_start_all(ic);
3882 else if (vap != NULL && stop)
3883 ieee80211_stop(vap);
3886 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
3896 * Send a command to the firmware.
3899 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3901 struct iwn_tx_ring *ring = &sc->txq[4];
3902 struct iwn_tx_desc *desc;
3903 struct iwn_tx_data *data;
3904 struct iwn_tx_cmd *cmd;
3910 IWN_LOCK_ASSERT(sc);
3912 desc = &ring->desc[ring->cur];
3913 data = &ring->data[ring->cur];
3916 if (size > sizeof cmd->data) {
3917 /* Command is too large to fit in a descriptor. */
3918 if (totlen > MCLBYTES)
3920 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE);
3923 cmd = mtod(m, struct iwn_tx_cmd *);
3924 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
3925 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3932 cmd = &ring->cmd[ring->cur];
3933 paddr = data->cmd_paddr;
3938 cmd->qid = ring->qid;
3939 cmd->idx = ring->cur;
3940 memcpy(cmd->data, buf, size);
3943 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
3944 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
3946 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
3947 __func__, iwn_intr_str(cmd->code), cmd->code,
3948 cmd->flags, cmd->qid, cmd->idx);
3950 if (size > sizeof cmd->data) {
3951 bus_dmamap_sync(ring->data_dmat, data->map,
3952 BUS_DMASYNC_PREWRITE);
3954 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3955 BUS_DMASYNC_PREWRITE);
3957 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3958 BUS_DMASYNC_PREWRITE);
3960 /* Kick command ring. */
3961 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3962 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3964 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz);
3968 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3970 struct iwn4965_node_info hnode;
3974 * We use the node structure for 5000 Series internally (it is
3975 * a superset of the one for 4965AGN). We thus copy the common
3976 * fields before sending the command.
3978 src = (caddr_t)node;
3979 dst = (caddr_t)&hnode;
3980 memcpy(dst, src, 48);
3981 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
3982 memcpy(dst + 48, src + 72, 20);
3983 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
3987 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3989 /* Direct mapping. */
3990 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
3994 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni)
3996 #define RV(v) ((v) & IEEE80211_RATE_VAL)
3997 struct iwn_node *wn = (void *)ni;
3998 struct ieee80211_rateset *rs = &ni->ni_rates;
3999 struct iwn_cmd_link_quality linkq;
4001 int i, rate, txrate;
4003 /* Use the first valid TX antenna. */
4004 txant = IWN_LSB(sc->txchainmask);
4006 memset(&linkq, 0, sizeof linkq);
4008 linkq.antmsk_1stream = txant;
4009 linkq.antmsk_2stream = IWN_ANT_AB;
4010 linkq.ampdu_max = 64;
4011 linkq.ampdu_threshold = 3;
4012 linkq.ampdu_limit = htole16(4000); /* 4ms */
4014 /* Start at highest available bit-rate. */
4015 if (IEEE80211_IS_CHAN_HT(ni->ni_chan))
4016 txrate = ni->ni_htrates.rs_nrates - 1;
4018 txrate = rs->rs_nrates - 1;
4019 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
4020 if (IEEE80211_IS_CHAN_HT(ni->ni_chan))
4021 rate = IEEE80211_RATE_MCS | txrate;
4023 rate = RV(rs->rs_rates[txrate]);
4024 linkq.retry[i] = wn->ridx[rate];
4026 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) &&
4027 RV(le32toh(wn->ridx[rate])) > 7)
4030 /* Next retry at immediate lower bit-rate. */
4034 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1);
4039 * Broadcast node is used to send group-addressed and management frames.
4042 iwn_add_broadcast_node(struct iwn_softc *sc, int async)
4044 struct iwn_ops *ops = &sc->ops;
4045 struct ifnet *ifp = sc->sc_ifp;
4046 struct ieee80211com *ic = ifp->if_l2com;
4047 struct iwn_node_info node;
4048 struct iwn_cmd_link_quality linkq;
4052 memset(&node, 0, sizeof node);
4053 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
4054 node.id = sc->broadcast_id;
4055 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
4056 if ((error = ops->add_node(sc, &node, async)) != 0)
4059 /* Use the first valid TX antenna. */
4060 txant = IWN_LSB(sc->txchainmask);
4062 memset(&linkq, 0, sizeof linkq);
4063 linkq.id = sc->broadcast_id;
4064 linkq.antmsk_1stream = txant;
4065 linkq.antmsk_2stream = IWN_ANT_AB;
4066 linkq.ampdu_max = 64;
4067 linkq.ampdu_threshold = 3;
4068 linkq.ampdu_limit = htole16(4000); /* 4ms */
4070 /* Use lowest mandatory bit-rate. */
4071 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4072 linkq.retry[0] = htole32(0xd);
4074 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK);
4075 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant));
4076 /* Use same bit-rate for all TX retries. */
4077 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) {
4078 linkq.retry[i] = linkq.retry[0];
4080 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
4084 iwn_updateedca(struct ieee80211com *ic)
4086 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
4087 struct iwn_softc *sc = ic->ic_ifp->if_softc;
4088 struct iwn_edca_params cmd;
4091 memset(&cmd, 0, sizeof cmd);
4092 cmd.flags = htole32(IWN_EDCA_UPDATE);
4093 for (aci = 0; aci < WME_NUM_AC; aci++) {
4094 const struct wmeParams *ac =
4095 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
4096 cmd.ac[aci].aifsn = ac->wmep_aifsn;
4097 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
4098 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
4099 cmd.ac[aci].txoplimit =
4100 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit));
4102 IEEE80211_UNLOCK(ic);
4104 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
4112 iwn_update_mcast(struct ifnet *ifp)
4118 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
4120 struct iwn_cmd_led led;
4122 /* Clear microcode LED ownership. */
4123 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
4126 led.unit = htole32(10000); /* on/off in unit of 100ms */
4129 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
4133 * Set the critical temperature at which the firmware will stop the radio
4137 iwn_set_critical_temp(struct iwn_softc *sc)
4139 struct iwn_critical_temp crit;
4142 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
4144 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
4145 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
4146 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
4147 temp = IWN_CTOK(110);
4150 memset(&crit, 0, sizeof crit);
4151 crit.tempR = htole32(temp);
4152 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp);
4153 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
4157 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
4159 struct iwn_cmd_timing cmd;
4162 memset(&cmd, 0, sizeof cmd);
4163 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
4164 cmd.bintval = htole16(ni->ni_intval);
4165 cmd.lintval = htole16(10);
4167 /* Compute remaining time until next beacon. */
4168 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
4169 mod = le64toh(cmd.tstamp) % val;
4170 cmd.binitval = htole32((uint32_t)(val - mod));
4172 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
4173 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
4175 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
4179 iwn4965_power_calibration(struct iwn_softc *sc, int temp)
4181 struct ifnet *ifp = sc->sc_ifp;
4182 struct ieee80211com *ic = ifp->if_l2com;
4184 /* Adjust TX power if need be (delta >= 3 degC). */
4185 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
4186 __func__, sc->temp, temp);
4187 if (abs(temp - sc->temp) >= 3) {
4188 /* Record temperature of last calibration. */
4190 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
4195 * Set TX power for current channel (each rate has its own power settings).
4196 * This function takes into account the regulatory information from EEPROM,
4197 * the current temperature and the current voltage.
4200 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
4203 /* Fixed-point arithmetic division using a n-bit fractional part. */
4204 #define fdivround(a, b, n) \
4205 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
4206 /* Linear interpolation. */
4207 #define interpolate(x, x1, y1, x2, y2, n) \
4208 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
4210 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
4211 struct iwn_ucode_info *uc = &sc->ucode_info;
4212 struct iwn4965_cmd_txpower cmd;
4213 struct iwn4965_eeprom_chan_samples *chans;
4214 const uint8_t *rf_gain, *dsp_gain;
4215 int32_t vdiff, tdiff;
4216 int i, c, grp, maxpwr;
4219 /* Retrieve current channel from last RXON. */
4220 chan = sc->rxon.chan;
4221 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
4224 memset(&cmd, 0, sizeof cmd);
4225 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
4228 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
4229 maxpwr = sc->maxpwr5GHz;
4230 rf_gain = iwn4965_rf_gain_5ghz;
4231 dsp_gain = iwn4965_dsp_gain_5ghz;
4233 maxpwr = sc->maxpwr2GHz;
4234 rf_gain = iwn4965_rf_gain_2ghz;
4235 dsp_gain = iwn4965_dsp_gain_2ghz;
4238 /* Compute voltage compensation. */
4239 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
4244 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4245 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
4246 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
4248 /* Get channel attenuation group. */
4249 if (chan <= 20) /* 1-20 */
4251 else if (chan <= 43) /* 34-43 */
4253 else if (chan <= 70) /* 44-70 */
4255 else if (chan <= 124) /* 71-124 */
4259 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4260 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
4262 /* Get channel sub-band. */
4263 for (i = 0; i < IWN_NBANDS; i++)
4264 if (sc->bands[i].lo != 0 &&
4265 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
4267 if (i == IWN_NBANDS) /* Can't happen in real-life. */
4269 chans = sc->bands[i].chans;
4270 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4271 "%s: chan %d sub-band=%d\n", __func__, chan, i);
4273 for (c = 0; c < 2; c++) {
4274 uint8_t power, gain, temp;
4275 int maxchpwr, pwr, ridx, idx;
4277 power = interpolate(chan,
4278 chans[0].num, chans[0].samples[c][1].power,
4279 chans[1].num, chans[1].samples[c][1].power, 1);
4280 gain = interpolate(chan,
4281 chans[0].num, chans[0].samples[c][1].gain,
4282 chans[1].num, chans[1].samples[c][1].gain, 1);
4283 temp = interpolate(chan,
4284 chans[0].num, chans[0].samples[c][1].temp,
4285 chans[1].num, chans[1].samples[c][1].temp, 1);
4286 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4287 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
4288 __func__, c, power, gain, temp);
4290 /* Compute temperature compensation. */
4291 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
4292 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4293 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
4294 __func__, tdiff, sc->temp, temp);
4296 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
4297 /* Convert dBm to half-dBm. */
4298 maxchpwr = sc->maxpwr[chan] * 2;
4300 maxchpwr -= 6; /* MIMO 2T: -3dB */
4304 /* Adjust TX power based on rate. */
4305 if ((ridx % 8) == 5)
4306 pwr -= 15; /* OFDM48: -7.5dB */
4307 else if ((ridx % 8) == 6)
4308 pwr -= 17; /* OFDM54: -8.5dB */
4309 else if ((ridx % 8) == 7)
4310 pwr -= 20; /* OFDM60: -10dB */
4312 pwr -= 10; /* Others: -5dB */
4314 /* Do not exceed channel max TX power. */
4318 idx = gain - (pwr - power) - tdiff - vdiff;
4319 if ((ridx / 8) & 1) /* MIMO */
4320 idx += (int32_t)le32toh(uc->atten[grp][c]);
4323 idx += 9; /* 5GHz */
4324 if (ridx == IWN_RIDX_MAX)
4327 /* Make sure idx stays in a valid range. */
4330 else if (idx > IWN4965_MAX_PWR_INDEX)
4331 idx = IWN4965_MAX_PWR_INDEX;
4333 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4334 "%s: Tx chain %d, rate idx %d: power=%d\n",
4335 __func__, c, ridx, idx);
4336 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
4337 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
4341 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4342 "%s: set tx power for chan %d\n", __func__, chan);
4343 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
4350 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
4353 struct iwn5000_cmd_txpower cmd;
4356 * TX power calibration is handled automatically by the firmware
4359 memset(&cmd, 0, sizeof cmd);
4360 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
4361 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
4362 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
4363 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__);
4364 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
4368 * Retrieve the maximum RSSI (in dBm) among receivers.
4371 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4373 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
4377 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
4378 agc = (le16toh(phy->agc) >> 7) & 0x7f;
4381 if (mask & IWN_ANT_A)
4382 rssi = MAX(rssi, phy->rssi[0]);
4383 if (mask & IWN_ANT_B)
4384 rssi = MAX(rssi, phy->rssi[2]);
4385 if (mask & IWN_ANT_C)
4386 rssi = MAX(rssi, phy->rssi[4]);
4388 DPRINTF(sc, IWN_DEBUG_RECV,
4389 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc,
4390 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],
4391 rssi - agc - IWN_RSSI_TO_DBM);
4392 return rssi - agc - IWN_RSSI_TO_DBM;
4396 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4398 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
4402 agc = (le32toh(phy->agc) >> 9) & 0x7f;
4404 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
4405 le16toh(phy->rssi[1]) & 0xff);
4406 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
4408 DPRINTF(sc, IWN_DEBUG_RECV,
4409 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc,
4410 phy->rssi[0], phy->rssi[1], phy->rssi[2],
4411 rssi - agc - IWN_RSSI_TO_DBM);
4412 return rssi - agc - IWN_RSSI_TO_DBM;
4416 * Retrieve the average noise (in dBm) among receivers.
4419 iwn_get_noise(const struct iwn_rx_general_stats *stats)
4421 int i, total, nbant, noise;
4424 for (i = 0; i < 3; i++) {
4425 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
4430 /* There should be at least one antenna but check anyway. */
4431 return (nbant == 0) ? -127 : (total / nbant) - 107;
4435 * Compute temperature (in degC) from last received statistics.
4438 iwn4965_get_temperature(struct iwn_softc *sc)
4440 struct iwn_ucode_info *uc = &sc->ucode_info;
4441 int32_t r1, r2, r3, r4, temp;
4443 r1 = le32toh(uc->temp[0].chan20MHz);
4444 r2 = le32toh(uc->temp[1].chan20MHz);
4445 r3 = le32toh(uc->temp[2].chan20MHz);
4446 r4 = le32toh(sc->rawtemp);
4448 if (r1 == r3) /* Prevents division by 0 (should not happen). */
4451 /* Sign-extend 23-bit R4 value to 32-bit. */
4452 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
4453 /* Compute temperature in Kelvin. */
4454 temp = (259 * (r4 - r2)) / (r3 - r1);
4455 temp = (temp * 97) / 100 + 8;
4457 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
4459 return IWN_KTOC(temp);
4463 iwn5000_get_temperature(struct iwn_softc *sc)
4468 * Temperature is not used by the driver for 5000 Series because
4469 * TX power calibration is handled by firmware.
4471 temp = le32toh(sc->rawtemp);
4472 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
4473 temp = (temp / -5) + sc->temp_off;
4474 temp = IWN_KTOC(temp);
4480 * Initialize sensitivity calibration state machine.
4483 iwn_init_sensitivity(struct iwn_softc *sc)
4485 struct iwn_ops *ops = &sc->ops;
4486 struct iwn_calib_state *calib = &sc->calib;
4490 /* Reset calibration state machine. */
4491 memset(calib, 0, sizeof (*calib));
4492 calib->state = IWN_CALIB_STATE_INIT;
4493 calib->cck_state = IWN_CCK_STATE_HIFA;
4494 /* Set initial correlation values. */
4495 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
4496 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
4497 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
4498 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
4499 calib->cck_x4 = 125;
4500 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
4501 calib->energy_cck = sc->limits->energy_cck;
4503 /* Write initial sensitivity. */
4504 if ((error = iwn_send_sensitivity(sc)) != 0)
4507 /* Write initial gains. */
4508 if ((error = ops->init_gains(sc)) != 0)
4511 /* Request statistics at each beacon interval. */
4513 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n",
4515 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
4519 * Collect noise and RSSI statistics for the first 20 beacons received
4520 * after association and use them to determine connected antennas and
4521 * to set differential gains.
4524 iwn_collect_noise(struct iwn_softc *sc,
4525 const struct iwn_rx_general_stats *stats)
4527 struct iwn_ops *ops = &sc->ops;
4528 struct iwn_calib_state *calib = &sc->calib;
4532 /* Accumulate RSSI and noise for all 3 antennas. */
4533 for (i = 0; i < 3; i++) {
4534 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
4535 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
4537 /* NB: We update differential gains only once after 20 beacons. */
4538 if (++calib->nbeacons < 20)
4541 /* Determine highest average RSSI. */
4542 val = MAX(calib->rssi[0], calib->rssi[1]);
4543 val = MAX(calib->rssi[2], val);
4545 /* Determine which antennas are connected. */
4546 sc->chainmask = sc->rxchainmask;
4547 for (i = 0; i < 3; i++)
4548 if (val - calib->rssi[i] > 15 * 20)
4549 sc->chainmask &= ~(1 << i);
4550 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4551 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n",
4552 __func__, sc->rxchainmask, sc->chainmask);
4554 /* If none of the TX antennas are connected, keep at least one. */
4555 if ((sc->chainmask & sc->txchainmask) == 0)
4556 sc->chainmask |= IWN_LSB(sc->txchainmask);
4558 (void)ops->set_gains(sc);
4559 calib->state = IWN_CALIB_STATE_RUN;
4562 /* XXX Disable RX chains with no antennas connected. */
4563 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
4564 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
4569 /* Enable power-saving mode if requested by user. */
4570 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON)
4571 (void)iwn_set_pslevel(sc, 0, 3, 1);
4576 iwn4965_init_gains(struct iwn_softc *sc)
4578 struct iwn_phy_calib_gain cmd;
4580 memset(&cmd, 0, sizeof cmd);
4581 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4582 /* Differential gains initially set to 0 for all 3 antennas. */
4583 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4584 "%s: setting initial differential gains\n", __func__);
4585 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4589 iwn5000_init_gains(struct iwn_softc *sc)
4591 struct iwn_phy_calib cmd;
4593 memset(&cmd, 0, sizeof cmd);
4594 cmd.code = sc->reset_noise_gain;
4597 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4598 "%s: setting initial differential gains\n", __func__);
4599 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4603 iwn4965_set_gains(struct iwn_softc *sc)
4605 struct iwn_calib_state *calib = &sc->calib;
4606 struct iwn_phy_calib_gain cmd;
4607 int i, delta, noise;
4609 /* Get minimal noise among connected antennas. */
4610 noise = INT_MAX; /* NB: There's at least one antenna. */
4611 for (i = 0; i < 3; i++)
4612 if (sc->chainmask & (1 << i))
4613 noise = MIN(calib->noise[i], noise);
4615 memset(&cmd, 0, sizeof cmd);
4616 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4617 /* Set differential gains for connected antennas. */
4618 for (i = 0; i < 3; i++) {
4619 if (sc->chainmask & (1 << i)) {
4620 /* Compute attenuation (in unit of 1.5dB). */
4621 delta = (noise - (int32_t)calib->noise[i]) / 30;
4622 /* NB: delta <= 0 */
4623 /* Limit to [-4.5dB,0]. */
4624 cmd.gain[i] = MIN(abs(delta), 3);
4626 cmd.gain[i] |= 1 << 2; /* sign bit */
4629 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4630 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
4631 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
4632 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4636 iwn5000_set_gains(struct iwn_softc *sc)
4638 struct iwn_calib_state *calib = &sc->calib;
4639 struct iwn_phy_calib_gain cmd;
4640 int i, ant, div, delta;
4642 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
4643 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
4645 memset(&cmd, 0, sizeof cmd);
4646 cmd.code = sc->noise_gain;
4649 /* Get first available RX antenna as referential. */
4650 ant = IWN_LSB(sc->rxchainmask);
4651 /* Set differential gains for other antennas. */
4652 for (i = ant + 1; i < 3; i++) {
4653 if (sc->chainmask & (1 << i)) {
4654 /* The delta is relative to antenna "ant". */
4655 delta = ((int32_t)calib->noise[ant] -
4656 (int32_t)calib->noise[i]) / div;
4657 /* Limit to [-4.5dB,+4.5dB]. */
4658 cmd.gain[i - 1] = MIN(abs(delta), 3);
4660 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
4663 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4664 "setting differential gains Ant B/C: %x/%x (%x)\n",
4665 cmd.gain[0], cmd.gain[1], sc->chainmask);
4666 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4670 * Tune RF RX sensitivity based on the number of false alarms detected
4671 * during the last beacon period.
4674 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
4676 #define inc(val, inc, max) \
4677 if ((val) < (max)) { \
4678 if ((val) < (max) - (inc)) \
4684 #define dec(val, dec, min) \
4685 if ((val) > (min)) { \
4686 if ((val) > (min) + (dec)) \
4693 const struct iwn_sensitivity_limits *limits = sc->limits;
4694 struct iwn_calib_state *calib = &sc->calib;
4695 uint32_t val, rxena, fa;
4696 uint32_t energy[3], energy_min;
4697 uint8_t noise[3], noise_ref;
4698 int i, needs_update = 0;
4700 /* Check that we've been enabled long enough. */
4701 if ((rxena = le32toh(stats->general.load)) == 0)
4704 /* Compute number of false alarms since last call for OFDM. */
4705 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
4706 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
4707 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
4709 /* Save counters values for next call. */
4710 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp);
4711 calib->fa_ofdm = le32toh(stats->ofdm.fa);
4713 if (fa > 50 * rxena) {
4714 /* High false alarm count, decrease sensitivity. */
4715 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4716 "%s: OFDM high false alarm count: %u\n", __func__, fa);
4717 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
4718 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
4719 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
4720 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
4722 } else if (fa < 5 * rxena) {
4723 /* Low false alarm count, increase sensitivity. */
4724 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4725 "%s: OFDM low false alarm count: %u\n", __func__, fa);
4726 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
4727 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
4728 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
4729 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
4732 /* Compute maximum noise among 3 receivers. */
4733 for (i = 0; i < 3; i++)
4734 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
4735 val = MAX(noise[0], noise[1]);
4736 val = MAX(noise[2], val);
4737 /* Insert it into our samples table. */
4738 calib->noise_samples[calib->cur_noise_sample] = val;
4739 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
4741 /* Compute maximum noise among last 20 samples. */
4742 noise_ref = calib->noise_samples[0];
4743 for (i = 1; i < 20; i++)
4744 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
4746 /* Compute maximum energy among 3 receivers. */
4747 for (i = 0; i < 3; i++)
4748 energy[i] = le32toh(stats->general.energy[i]);
4749 val = MIN(energy[0], energy[1]);
4750 val = MIN(energy[2], val);
4751 /* Insert it into our samples table. */
4752 calib->energy_samples[calib->cur_energy_sample] = val;
4753 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
4755 /* Compute minimum energy among last 10 samples. */
4756 energy_min = calib->energy_samples[0];
4757 for (i = 1; i < 10; i++)
4758 energy_min = MAX(energy_min, calib->energy_samples[i]);
4761 /* Compute number of false alarms since last call for CCK. */
4762 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
4763 fa += le32toh(stats->cck.fa) - calib->fa_cck;
4764 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
4766 /* Save counters values for next call. */
4767 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp);
4768 calib->fa_cck = le32toh(stats->cck.fa);
4770 if (fa > 50 * rxena) {
4771 /* High false alarm count, decrease sensitivity. */
4772 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4773 "%s: CCK high false alarm count: %u\n", __func__, fa);
4774 calib->cck_state = IWN_CCK_STATE_HIFA;
4777 if (calib->cck_x4 > 160) {
4778 calib->noise_ref = noise_ref;
4779 if (calib->energy_cck > 2)
4780 dec(calib->energy_cck, 2, energy_min);
4782 if (calib->cck_x4 < 160) {
4783 calib->cck_x4 = 161;
4786 inc(calib->cck_x4, 3, limits->max_cck_x4);
4788 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
4790 } else if (fa < 5 * rxena) {
4791 /* Low false alarm count, increase sensitivity. */
4792 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4793 "%s: CCK low false alarm count: %u\n", __func__, fa);
4794 calib->cck_state = IWN_CCK_STATE_LOFA;
4797 if (calib->cck_state != IWN_CCK_STATE_INIT &&
4798 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
4799 calib->low_fa > 100)) {
4800 inc(calib->energy_cck, 2, limits->min_energy_cck);
4801 dec(calib->cck_x4, 3, limits->min_cck_x4);
4802 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
4805 /* Not worth to increase or decrease sensitivity. */
4806 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4807 "%s: CCK normal false alarm count: %u\n", __func__, fa);
4809 calib->noise_ref = noise_ref;
4811 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
4812 /* Previous interval had many false alarms. */
4813 dec(calib->energy_cck, 8, energy_min);
4815 calib->cck_state = IWN_CCK_STATE_INIT;
4819 (void)iwn_send_sensitivity(sc);
4825 iwn_send_sensitivity(struct iwn_softc *sc)
4827 struct iwn_calib_state *calib = &sc->calib;
4828 struct iwn_enhanced_sensitivity_cmd cmd;
4831 memset(&cmd, 0, sizeof cmd);
4832 len = sizeof (struct iwn_sensitivity_cmd);
4833 cmd.which = IWN_SENSITIVITY_WORKTBL;
4834 /* OFDM modulation. */
4835 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
4836 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
4837 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
4838 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
4839 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
4840 cmd.energy_ofdm_th = htole16(62);
4841 /* CCK modulation. */
4842 cmd.corr_cck_x4 = htole16(calib->cck_x4);
4843 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
4844 cmd.energy_cck = htole16(calib->energy_cck);
4845 /* Barker modulation: use default values. */
4846 cmd.corr_barker = htole16(190);
4847 cmd.corr_barker_mrc = htole16(390);
4849 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4850 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
4851 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
4852 calib->ofdm_mrc_x4, calib->cck_x4,
4853 calib->cck_mrc_x4, calib->energy_cck);
4855 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
4857 /* Enhanced sensitivity settings. */
4858 len = sizeof (struct iwn_enhanced_sensitivity_cmd);
4859 cmd.ofdm_det_slope_mrc = htole16(668);
4860 cmd.ofdm_det_icept_mrc = htole16(4);
4861 cmd.ofdm_det_slope = htole16(486);
4862 cmd.ofdm_det_icept = htole16(37);
4863 cmd.cck_det_slope_mrc = htole16(853);
4864 cmd.cck_det_icept_mrc = htole16(4);
4865 cmd.cck_det_slope = htole16(476);
4866 cmd.cck_det_icept = htole16(99);
4868 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
4872 * Set STA mode power saving level (between 0 and 5).
4873 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
4876 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
4878 struct iwn_pmgt_cmd cmd;
4879 const struct iwn_pmgt *pmgt;
4880 uint32_t max, skip_dtim;
4884 /* Select which PS parameters to use. */
4886 pmgt = &iwn_pmgt[0][level];
4887 else if (dtim <= 10)
4888 pmgt = &iwn_pmgt[1][level];
4890 pmgt = &iwn_pmgt[2][level];
4892 memset(&cmd, 0, sizeof cmd);
4893 if (level != 0) /* not CAM */
4894 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
4896 cmd.flags |= htole16(IWN_PS_FAST_PD);
4897 /* Retrieve PCIe Active State Power Management (ASPM). */
4898 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
4899 if (!(reg & 0x1)) /* L0s Entry disabled. */
4900 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
4901 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
4902 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
4908 skip_dtim = pmgt->skip_dtim;
4909 if (skip_dtim != 0) {
4910 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
4911 max = pmgt->intval[4];
4912 if (max == (uint32_t)-1)
4913 max = dtim * (skip_dtim + 1);
4914 else if (max > dtim)
4915 max = (max / dtim) * dtim;
4918 for (i = 0; i < 5; i++)
4919 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
4921 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
4923 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
4927 iwn_send_btcoex(struct iwn_softc *sc)
4929 struct iwn_bluetooth cmd;
4931 memset(&cmd, 0, sizeof cmd);
4932 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
4933 cmd.lead_time = IWN_BT_LEAD_TIME_DEF;
4934 cmd.max_kill = IWN_BT_MAX_KILL_DEF;
4935 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n",
4937 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0);
4941 iwn_send_advanced_btcoex(struct iwn_softc *sc)
4943 static const uint32_t btcoex_3wire[12] = {
4944 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa,
4945 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa,
4946 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000,
4948 struct iwn6000_btcoex_config btconfig;
4949 struct iwn_btcoex_priotable btprio;
4950 struct iwn_btcoex_prot btprot;
4953 memset(&btconfig, 0, sizeof btconfig);
4954 btconfig.flags = 145;
4955 btconfig.max_kill = 5;
4956 btconfig.bt3_t7_timer = 1;
4957 btconfig.kill_ack = htole32(0xffff0000);
4958 btconfig.kill_cts = htole32(0xffff0000);
4959 btconfig.sample_time = 2;
4960 btconfig.bt3_t2_timer = 0xc;
4961 for (i = 0; i < 12; i++)
4962 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]);
4963 btconfig.valid = htole16(0xff);
4964 btconfig.prio_boost = 0xf0;
4965 DPRINTF(sc, IWN_DEBUG_RESET,
4966 "%s: configuring advanced bluetooth coexistence\n", __func__);
4967 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1);
4971 memset(&btprio, 0, sizeof btprio);
4972 btprio.calib_init1 = 0x6;
4973 btprio.calib_init2 = 0x7;
4974 btprio.calib_periodic_low1 = 0x2;
4975 btprio.calib_periodic_low2 = 0x3;
4976 btprio.calib_periodic_high1 = 0x4;
4977 btprio.calib_periodic_high2 = 0x5;
4979 btprio.scan52 = 0x8;
4980 btprio.scan24 = 0xa;
4981 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio),
4986 /* Force BT state machine change. */
4987 memset(&btprot, 0, sizeof btprio);
4990 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
4994 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
4998 iwn_config(struct iwn_softc *sc)
5000 struct iwn_ops *ops = &sc->ops;
5001 struct ifnet *ifp = sc->sc_ifp;
5002 struct ieee80211com *ic = ifp->if_l2com;
5007 if (sc->hw_type == IWN_HW_REV_TYPE_6005) {
5008 /* Set radio temperature sensor offset. */
5009 error = iwn5000_temp_offset_calib(sc);
5011 device_printf(sc->sc_dev,
5012 "%s: could not set temperature offset\n", __func__);
5017 /* Configure valid TX chains for >=5000 Series. */
5018 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
5019 txmask = htole32(sc->txchainmask);
5020 DPRINTF(sc, IWN_DEBUG_RESET,
5021 "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
5022 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
5025 device_printf(sc->sc_dev,
5026 "%s: could not configure valid TX chains, "
5027 "error %d\n", __func__, error);
5032 /* Configure bluetooth coexistence. */
5033 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX)
5034 error = iwn_send_advanced_btcoex(sc);
5036 error = iwn_send_btcoex(sc);
5038 device_printf(sc->sc_dev,
5039 "%s: could not configure bluetooth coexistence, error %d\n",
5044 /* Set mode, channel, RX filter and enable RX. */
5045 memset(&sc->rxon, 0, sizeof (struct iwn_rxon));
5046 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp));
5047 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp));
5048 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
5049 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5050 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
5051 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5052 switch (ic->ic_opmode) {
5053 case IEEE80211_M_STA:
5054 sc->rxon.mode = IWN_MODE_STA;
5055 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST);
5057 case IEEE80211_M_MONITOR:
5058 sc->rxon.mode = IWN_MODE_MONITOR;
5059 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST |
5060 IWN_FILTER_CTL | IWN_FILTER_PROMISC);
5063 /* Should not get there. */
5066 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */
5067 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */
5068 sc->rxon.ht_single_mask = 0xff;
5069 sc->rxon.ht_dual_mask = 0xff;
5070 sc->rxon.ht_triple_mask = 0xff;
5072 IWN_RXCHAIN_VALID(sc->rxchainmask) |
5073 IWN_RXCHAIN_MIMO_COUNT(2) |
5074 IWN_RXCHAIN_IDLE_COUNT(2);
5075 sc->rxon.rxchain = htole16(rxchain);
5076 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__);
5077 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0);
5079 device_printf(sc->sc_dev, "%s: RXON command failed\n",
5084 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) {
5085 device_printf(sc->sc_dev, "%s: could not add broadcast node\n",
5090 /* Configuration has changed, set TX power accordingly. */
5091 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) {
5092 device_printf(sc->sc_dev, "%s: could not set TX power\n",
5097 if ((error = iwn_set_critical_temp(sc)) != 0) {
5098 device_printf(sc->sc_dev,
5099 "%s: could not set critical temperature\n", __func__);
5103 /* Set power saving level to CAM during initialization. */
5104 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) {
5105 device_printf(sc->sc_dev,
5106 "%s: could not set power saving level\n", __func__);
5113 * Add an ssid element to a frame.
5116 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len)
5118 *frm++ = IEEE80211_ELEMID_SSID;
5120 memcpy(frm, ssid, len);
5125 iwn_scan(struct iwn_softc *sc)
5127 struct ifnet *ifp = sc->sc_ifp;
5128 struct ieee80211com *ic = ifp->if_l2com;
5129 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/
5130 struct ieee80211_node *ni = ss->ss_vap->iv_bss;
5131 struct iwn_scan_hdr *hdr;
5132 struct iwn_cmd_data *tx;
5133 struct iwn_scan_essid *essid;
5134 struct iwn_scan_chan *chan;
5135 struct ieee80211_frame *wh;
5136 struct ieee80211_rateset *rs;
5137 struct ieee80211_channel *c;
5143 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO);
5145 device_printf(sc->sc_dev,
5146 "%s: could not allocate buffer for scan command\n",
5150 hdr = (struct iwn_scan_hdr *)buf;
5152 * Move to the next channel if no frames are received within 10ms
5153 * after sending the probe request.
5155 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
5156 hdr->quiet_threshold = htole16(1); /* min # of packets */
5158 /* Select antennas for scanning. */
5160 IWN_RXCHAIN_VALID(sc->rxchainmask) |
5161 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
5162 IWN_RXCHAIN_DRIVER_FORCE;
5163 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) &&
5164 sc->hw_type == IWN_HW_REV_TYPE_4965) {
5165 /* Ant A must be avoided in 5GHz because of an HW bug. */
5166 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B);
5167 } else /* Use all available RX antennas. */
5168 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
5169 hdr->rxchain = htole16(rxchain);
5170 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
5172 tx = (struct iwn_cmd_data *)(hdr + 1);
5173 tx->flags = htole32(IWN_TX_AUTO_SEQ);
5174 tx->id = sc->broadcast_id;
5175 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
5177 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
5178 /* Send probe requests at 6Mbps. */
5179 tx->rate = htole32(0xd);
5180 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
5182 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
5183 if (sc->hw_type == IWN_HW_REV_TYPE_4965 &&
5184 sc->rxon.associd && sc->rxon.chan > 14)
5185 tx->rate = htole32(0xd);
5187 /* Send probe requests at 1Mbps. */
5188 tx->rate = htole32(10 | IWN_RFLAG_CCK);
5190 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
5192 /* Use the first valid TX antenna. */
5193 txant = IWN_LSB(sc->txchainmask);
5194 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
5196 essid = (struct iwn_scan_essid *)(tx + 1);
5197 if (ss->ss_ssid[0].len != 0) {
5198 essid[0].id = IEEE80211_ELEMID_SSID;
5199 essid[0].len = ss->ss_ssid[0].len;
5200 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
5203 * Build a probe request frame. Most of the following code is a
5204 * copy & paste of what is done in net80211.
5206 wh = (struct ieee80211_frame *)(essid + 20);
5207 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
5208 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
5209 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
5210 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr);
5211 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp));
5212 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr);
5213 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
5214 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
5216 frm = (uint8_t *)(wh + 1);
5217 frm = ieee80211_add_ssid(frm, NULL, 0);
5218 frm = ieee80211_add_rates(frm, rs);
5219 if (rs->rs_nrates > IEEE80211_RATE_SIZE)
5220 frm = ieee80211_add_xrates(frm, rs);
5221 if (ic->ic_htcaps & IEEE80211_HTC_HT)
5222 frm = ieee80211_add_htcap(frm, ni);
5224 /* Set length of probe request. */
5225 tx->len = htole16(frm - (uint8_t *)wh);
5228 chan = (struct iwn_scan_chan *)frm;
5229 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
5231 if (ss->ss_nssid > 0)
5232 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
5233 chan->dsp_gain = 0x6e;
5234 if (IEEE80211_IS_CHAN_5GHZ(c) &&
5235 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
5236 chan->rf_gain = 0x3b;
5237 chan->active = htole16(24);
5238 chan->passive = htole16(110);
5239 chan->flags |= htole32(IWN_CHAN_ACTIVE);
5240 } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
5241 chan->rf_gain = 0x3b;
5242 chan->active = htole16(24);
5243 if (sc->rxon.associd)
5244 chan->passive = htole16(78);
5246 chan->passive = htole16(110);
5247 hdr->crc_threshold = 0xffff;
5248 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
5249 chan->rf_gain = 0x28;
5250 chan->active = htole16(36);
5251 chan->passive = htole16(120);
5252 chan->flags |= htole32(IWN_CHAN_ACTIVE);
5254 chan->rf_gain = 0x28;
5255 chan->active = htole16(36);
5256 if (sc->rxon.associd)
5257 chan->passive = htole16(88);
5259 chan->passive = htole16(120);
5260 hdr->crc_threshold = 0xffff;
5263 DPRINTF(sc, IWN_DEBUG_STATE,
5264 "%s: chan %u flags 0x%x rf_gain 0x%x "
5265 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__,
5266 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
5267 chan->active, chan->passive);
5271 buflen = (uint8_t *)chan - buf;
5272 hdr->len = htole16(buflen);
5274 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
5276 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
5277 free(buf, M_DEVBUF);
5282 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
5284 struct iwn_ops *ops = &sc->ops;
5285 struct ifnet *ifp = sc->sc_ifp;
5286 struct ieee80211com *ic = ifp->if_l2com;
5287 struct ieee80211_node *ni = vap->iv_bss;
5290 /* Update adapter configuration. */
5291 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
5292 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
5293 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5294 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
5295 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5296 if (ic->ic_flags & IEEE80211_F_SHSLOT)
5297 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
5298 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5299 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
5300 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
5301 sc->rxon.cck_mask = 0;
5302 sc->rxon.ofdm_mask = 0x15;
5303 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
5304 sc->rxon.cck_mask = 0x03;
5305 sc->rxon.ofdm_mask = 0;
5307 /* Assume 802.11b/g. */
5308 sc->rxon.cck_mask = 0x0f;
5309 sc->rxon.ofdm_mask = 0x15;
5311 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n",
5312 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask,
5313 sc->rxon.ofdm_mask);
5314 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
5316 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n",
5321 /* Configuration has changed, set TX power accordingly. */
5322 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
5323 device_printf(sc->sc_dev,
5324 "%s: could not set TX power, error %d\n", __func__, error);
5328 * Reconfiguring RXON clears the firmware nodes table so we must
5329 * add the broadcast node again.
5331 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) {
5332 device_printf(sc->sc_dev,
5333 "%s: could not add broadcast node, error %d\n", __func__,
5341 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
5343 struct iwn_ops *ops = &sc->ops;
5344 struct ifnet *ifp = sc->sc_ifp;
5345 struct ieee80211com *ic = ifp->if_l2com;
5346 struct ieee80211_node *ni = vap->iv_bss;
5347 struct iwn_node_info node;
5348 uint32_t htflags = 0;
5351 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
5352 /* Link LED blinks while monitoring. */
5353 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
5356 if ((error = iwn_set_timing(sc, ni)) != 0) {
5357 device_printf(sc->sc_dev,
5358 "%s: could not set timing, error %d\n", __func__, error);
5362 /* Update adapter configuration. */
5363 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
5364 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd));
5365 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
5366 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5367 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
5368 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5369 if (ic->ic_flags & IEEE80211_F_SHSLOT)
5370 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
5371 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5372 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
5373 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
5374 sc->rxon.cck_mask = 0;
5375 sc->rxon.ofdm_mask = 0x15;
5376 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
5377 sc->rxon.cck_mask = 0x03;
5378 sc->rxon.ofdm_mask = 0;
5380 /* Assume 802.11b/g. */
5381 sc->rxon.cck_mask = 0x0f;
5382 sc->rxon.ofdm_mask = 0x15;
5384 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
5385 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode);
5386 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
5387 switch (ic->ic_curhtprotmode) {
5388 case IEEE80211_HTINFO_OPMODE_HT20PR:
5389 htflags |= IWN_RXON_HT_MODEPURE40;
5392 htflags |= IWN_RXON_HT_MODEMIXED;
5396 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan))
5397 htflags |= IWN_RXON_HT_HT40MINUS;
5399 sc->rxon.flags |= htole32(htflags);
5400 sc->rxon.filter |= htole32(IWN_FILTER_BSS);
5401 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n",
5402 sc->rxon.chan, sc->rxon.flags);
5403 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
5405 device_printf(sc->sc_dev,
5406 "%s: could not update configuration, error %d\n", __func__,
5411 /* Configuration has changed, set TX power accordingly. */
5412 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
5413 device_printf(sc->sc_dev,
5414 "%s: could not set TX power, error %d\n", __func__, error);
5418 /* Fake a join to initialize the TX rate. */
5419 ((struct iwn_node *)ni)->id = IWN_ID_BSS;
5420 iwn_newassoc(ni, 1);
5423 memset(&node, 0, sizeof node);
5424 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
5425 node.id = IWN_ID_BSS;
5426 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
5427 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) {
5428 case IEEE80211_HTCAP_SMPS_ENA:
5429 node.htflags |= htole32(IWN_SMPS_MIMO_DIS);
5431 case IEEE80211_HTCAP_SMPS_DYNAMIC:
5432 node.htflags |= htole32(IWN_SMPS_MIMO_PROT);
5435 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) |
5436 IWN_AMDPU_DENSITY(5)); /* 4us */
5437 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan))
5438 node.htflags |= htole32(IWN_NODE_HT40);
5440 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__);
5441 error = ops->add_node(sc, &node, 1);
5443 device_printf(sc->sc_dev,
5444 "%s: could not add BSS node, error %d\n", __func__, error);
5447 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n",
5449 if ((error = iwn_set_link_quality(sc, ni)) != 0) {
5450 device_printf(sc->sc_dev,
5451 "%s: could not setup link quality for node %d, error %d\n",
5452 __func__, node.id, error);
5456 if ((error = iwn_init_sensitivity(sc)) != 0) {
5457 device_printf(sc->sc_dev,
5458 "%s: could not set sensitivity, error %d\n", __func__,
5462 /* Start periodic calibration timer. */
5463 sc->calib.state = IWN_CALIB_STATE_ASSOC;
5465 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
5468 /* Link LED always on while associated. */
5469 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
5474 * This function is called by upper layer when an ADDBA request is received
5475 * from another STA and before the ADDBA response is sent.
5478 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap,
5479 int baparamset, int batimeout, int baseqctl)
5481 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
5482 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5483 struct iwn_ops *ops = &sc->ops;
5484 struct iwn_node *wn = (void *)ni;
5485 struct iwn_node_info node;
5490 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID);
5491 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START);
5493 memset(&node, 0, sizeof node);
5495 node.control = IWN_NODE_UPDATE;
5496 node.flags = IWN_FLAG_SET_ADDBA;
5497 node.addba_tid = tid;
5498 node.addba_ssn = htole16(ssn);
5499 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
5501 error = ops->add_node(sc, &node, 1);
5504 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl);
5509 * This function is called by upper layer on teardown of an HT-immediate
5510 * Block Ack agreement (eg. uppon receipt of a DELBA frame).
5513 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap)
5515 struct ieee80211com *ic = ni->ni_ic;
5516 struct iwn_softc *sc = ic->ic_ifp->if_softc;
5517 struct iwn_ops *ops = &sc->ops;
5518 struct iwn_node *wn = (void *)ni;
5519 struct iwn_node_info node;
5522 /* XXX: tid as an argument */
5523 for (tid = 0; tid < WME_NUM_TID; tid++) {
5524 if (&ni->ni_rx_ampdu[tid] == rap)
5528 memset(&node, 0, sizeof node);
5530 node.control = IWN_NODE_UPDATE;
5531 node.flags = IWN_FLAG_SET_DELBA;
5532 node.delba_tid = tid;
5533 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
5534 (void)ops->add_node(sc, &node, 1);
5535 sc->sc_ampdu_rx_stop(ni, rap);
5539 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5540 int dialogtoken, int baparamset, int batimeout)
5542 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5545 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) {
5546 if (sc->qid2tap[qid] == NULL)
5549 if (qid == sc->ntxqs) {
5550 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n",
5554 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
5555 if (tap->txa_private == NULL) {
5556 device_printf(sc->sc_dev,
5557 "%s: failed to alloc TX aggregation structure\n", __func__);
5560 sc->qid2tap[qid] = tap;
5561 *(int *)tap->txa_private = qid;
5562 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
5567 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5568 int code, int baparamset, int batimeout)
5570 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5571 int qid = *(int *)tap->txa_private;
5572 uint8_t tid = WME_AC_TO_TID(tap->txa_ac);
5575 if (code == IEEE80211_STATUS_SUCCESS) {
5576 ni->ni_txseqs[tid] = tap->txa_start & 0xfff;
5577 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid);
5581 sc->qid2tap[qid] = NULL;
5582 free(tap->txa_private, M_DEVBUF);
5583 tap->txa_private = NULL;
5585 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout);
5589 * This function is called by upper layer when an ADDBA response is received
5593 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5596 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[TID_TO_WME_AC(tid)];
5597 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5598 struct iwn_ops *ops = &sc->ops;
5599 struct iwn_node *wn = (void *)ni;
5600 struct iwn_node_info node;
5603 /* Enable TX for the specified RA/TID. */
5604 wn->disable_tid &= ~(1 << tid);
5605 memset(&node, 0, sizeof node);
5607 node.control = IWN_NODE_UPDATE;
5608 node.flags = IWN_FLAG_SET_DISABLE_TID;
5609 node.disable_tid = htole16(wn->disable_tid);
5610 error = ops->add_node(sc, &node, 1);
5614 if ((error = iwn_nic_lock(sc)) != 0)
5616 qid = *(int *)tap->txa_private;
5617 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff);
5620 iwn_set_link_quality(sc, ni);
5625 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
5627 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5628 struct iwn_ops *ops = &sc->ops;
5629 uint8_t tid = WME_AC_TO_TID(tap->txa_ac);
5632 if (tap->txa_private == NULL)
5635 qid = *(int *)tap->txa_private;
5636 if (iwn_nic_lock(sc) != 0)
5638 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff);
5640 sc->qid2tap[qid] = NULL;
5641 free(tap->txa_private, M_DEVBUF);
5642 tap->txa_private = NULL;
5646 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5647 int qid, uint8_t tid, uint16_t ssn)
5649 struct iwn_node *wn = (void *)ni;
5651 /* Stop TX scheduler while we're changing its configuration. */
5652 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5653 IWN4965_TXQ_STATUS_CHGACT);
5655 /* Assign RA/TID translation to the queue. */
5656 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
5659 /* Enable chain-building mode for the queue. */
5660 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
5662 /* Set starting sequence number from the ADDBA request. */
5663 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
5664 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5665 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5667 /* Set scheduler window size. */
5668 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
5670 /* Set scheduler frame limit. */
5671 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5672 IWN_SCHED_LIMIT << 16);
5674 /* Enable interrupts for the queue. */
5675 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5677 /* Mark the queue as active. */
5678 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5679 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
5680 iwn_tid2fifo[tid] << 1);
5684 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
5686 /* Stop TX scheduler while we're changing its configuration. */
5687 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5688 IWN4965_TXQ_STATUS_CHGACT);
5690 /* Set starting sequence number from the ADDBA request. */
5691 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5692 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5694 /* Disable interrupts for the queue. */
5695 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5697 /* Mark the queue as inactive. */
5698 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5699 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
5703 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5704 int qid, uint8_t tid, uint16_t ssn)
5706 struct iwn_node *wn = (void *)ni;
5708 /* Stop TX scheduler while we're changing its configuration. */
5709 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5710 IWN5000_TXQ_STATUS_CHGACT);
5712 /* Assign RA/TID translation to the queue. */
5713 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
5716 /* Enable chain-building mode for the queue. */
5717 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
5719 /* Enable aggregation for the queue. */
5720 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5722 /* Set starting sequence number from the ADDBA request. */
5723 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
5724 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5725 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5727 /* Set scheduler window size and frame limit. */
5728 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5729 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5731 /* Enable interrupts for the queue. */
5732 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5734 /* Mark the queue as active. */
5735 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5736 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
5740 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
5742 /* Stop TX scheduler while we're changing its configuration. */
5743 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5744 IWN5000_TXQ_STATUS_CHGACT);
5746 /* Disable aggregation for the queue. */
5747 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5749 /* Set starting sequence number from the ADDBA request. */
5750 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5751 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5753 /* Disable interrupts for the queue. */
5754 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5756 /* Mark the queue as inactive. */
5757 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5758 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
5762 * Query calibration tables from the initialization firmware. We do this
5763 * only once at first boot. Called from a process context.
5766 iwn5000_query_calibration(struct iwn_softc *sc)
5768 struct iwn5000_calib_config cmd;
5771 memset(&cmd, 0, sizeof cmd);
5772 cmd.ucode.once.enable = 0xffffffff;
5773 cmd.ucode.once.start = 0xffffffff;
5774 cmd.ucode.once.send = 0xffffffff;
5775 cmd.ucode.flags = 0xffffffff;
5776 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
5778 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
5782 /* Wait at most two seconds for calibration to complete. */
5783 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
5784 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz);
5789 * Send calibration results to the runtime firmware. These results were
5790 * obtained on first boot from the initialization firmware.
5793 iwn5000_send_calibration(struct iwn_softc *sc)
5797 for (idx = 0; idx < 5; idx++) {
5798 if (sc->calibcmd[idx].buf == NULL)
5799 continue; /* No results available. */
5800 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5801 "send calibration result idx=%d len=%d\n", idx,
5802 sc->calibcmd[idx].len);
5803 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
5804 sc->calibcmd[idx].len, 0);
5806 device_printf(sc->sc_dev,
5807 "%s: could not send calibration result, error %d\n",
5816 iwn5000_send_wimax_coex(struct iwn_softc *sc)
5818 struct iwn5000_wimax_coex wimax;
5821 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5822 /* Enable WiMAX coexistence for combo adapters. */
5824 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
5825 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
5826 IWN_WIMAX_COEX_STA_TABLE_VALID |
5827 IWN_WIMAX_COEX_ENABLE;
5828 memcpy(wimax.events, iwn6050_wimax_events,
5829 sizeof iwn6050_wimax_events);
5833 /* Disable WiMAX coexistence. */
5835 memset(wimax.events, 0, sizeof wimax.events);
5837 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
5839 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
5843 iwn5000_crystal_calib(struct iwn_softc *sc)
5845 struct iwn5000_phy_calib_crystal cmd;
5847 memset(&cmd, 0, sizeof cmd);
5848 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
5851 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
5852 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
5853 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n",
5854 cmd.cap_pin[0], cmd.cap_pin[1]);
5855 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5859 iwn5000_temp_offset_calib(struct iwn_softc *sc)
5861 struct iwn5000_phy_calib_temp_offset cmd;
5863 memset(&cmd, 0, sizeof cmd);
5864 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
5867 if (sc->eeprom_temp != 0)
5868 cmd.offset = htole16(sc->eeprom_temp);
5870 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
5871 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n",
5872 le16toh(cmd.offset));
5873 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5877 * This function is called after the runtime firmware notifies us of its
5878 * readiness (called in a process context).
5881 iwn4965_post_alive(struct iwn_softc *sc)
5885 if ((error = iwn_nic_lock(sc)) != 0)
5888 /* Clear TX scheduler state in SRAM. */
5889 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5890 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
5891 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
5893 /* Set physical address of TX scheduler rings (1KB aligned). */
5894 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5896 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5898 /* Disable chain mode for all our 16 queues. */
5899 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
5901 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
5902 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
5903 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5905 /* Set scheduler window size. */
5906 iwn_mem_write(sc, sc->sched_base +
5907 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
5908 /* Set scheduler frame limit. */
5909 iwn_mem_write(sc, sc->sched_base +
5910 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5911 IWN_SCHED_LIMIT << 16);
5914 /* Enable interrupts for all our 16 queues. */
5915 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
5916 /* Identify TX FIFO rings (0-7). */
5917 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
5919 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5920 for (qid = 0; qid < 7; qid++) {
5921 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
5922 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5923 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
5930 * This function is called after the initialization or runtime firmware
5931 * notifies us of its readiness (called in a process context).
5934 iwn5000_post_alive(struct iwn_softc *sc)
5938 /* Switch to using ICT interrupt mode. */
5939 iwn5000_ict_reset(sc);
5941 if ((error = iwn_nic_lock(sc)) != 0)
5944 /* Clear TX scheduler state in SRAM. */
5945 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5946 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
5947 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
5949 /* Set physical address of TX scheduler rings (1KB aligned). */
5950 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5952 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5954 /* Enable chain mode for all queues, except command queue. */
5955 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
5956 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
5958 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
5959 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
5960 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5962 iwn_mem_write(sc, sc->sched_base +
5963 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
5964 /* Set scheduler window size and frame limit. */
5965 iwn_mem_write(sc, sc->sched_base +
5966 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5967 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5970 /* Enable interrupts for all our 20 queues. */
5971 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
5972 /* Identify TX FIFO rings (0-7). */
5973 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
5975 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5976 for (qid = 0; qid < 7; qid++) {
5977 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
5978 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5979 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
5983 /* Configure WiMAX coexistence for combo adapters. */
5984 error = iwn5000_send_wimax_coex(sc);
5986 device_printf(sc->sc_dev,
5987 "%s: could not configure WiMAX coexistence, error %d\n",
5991 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
5992 /* Perform crystal calibration. */
5993 error = iwn5000_crystal_calib(sc);
5995 device_printf(sc->sc_dev,
5996 "%s: crystal calibration failed, error %d\n",
6001 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
6002 /* Query calibration from the initialization firmware. */
6003 if ((error = iwn5000_query_calibration(sc)) != 0) {
6004 device_printf(sc->sc_dev,
6005 "%s: could not query calibration, error %d\n",
6010 * We have the calibration results now, reboot with the
6011 * runtime firmware (call ourselves recursively!)
6014 error = iwn_hw_init(sc);
6016 /* Send calibration results to runtime firmware. */
6017 error = iwn5000_send_calibration(sc);
6023 * The firmware boot code is small and is intended to be copied directly into
6024 * the NIC internal memory (no DMA transfer).
6027 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
6031 size /= sizeof (uint32_t);
6033 if ((error = iwn_nic_lock(sc)) != 0)
6036 /* Copy microcode image into NIC memory. */
6037 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
6038 (const uint32_t *)ucode, size);
6040 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
6041 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
6042 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
6044 /* Start boot load now. */
6045 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
6047 /* Wait for transfer to complete. */
6048 for (ntries = 0; ntries < 1000; ntries++) {
6049 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
6050 IWN_BSM_WR_CTRL_START))
6054 if (ntries == 1000) {
6055 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
6061 /* Enable boot after power up. */
6062 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
6069 iwn4965_load_firmware(struct iwn_softc *sc)
6071 struct iwn_fw_info *fw = &sc->fw;
6072 struct iwn_dma_info *dma = &sc->fw_dma;
6075 /* Copy initialization sections into pre-allocated DMA-safe memory. */
6076 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
6077 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6078 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
6079 fw->init.text, fw->init.textsz);
6080 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6082 /* Tell adapter where to find initialization sections. */
6083 if ((error = iwn_nic_lock(sc)) != 0)
6085 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
6086 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
6087 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
6088 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
6089 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
6092 /* Load firmware boot code. */
6093 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
6095 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
6099 /* Now press "execute". */
6100 IWN_WRITE(sc, IWN_RESET, 0);
6102 /* Wait at most one second for first alive notification. */
6103 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
6104 device_printf(sc->sc_dev,
6105 "%s: timeout waiting for adapter to initialize, error %d\n",
6110 /* Retrieve current temperature for initial TX power calibration. */
6111 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
6112 sc->temp = iwn4965_get_temperature(sc);
6114 /* Copy runtime sections into pre-allocated DMA-safe memory. */
6115 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
6116 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6117 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
6118 fw->main.text, fw->main.textsz);
6119 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6121 /* Tell adapter where to find runtime sections. */
6122 if ((error = iwn_nic_lock(sc)) != 0)
6124 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
6125 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
6126 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
6127 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
6128 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
6129 IWN_FW_UPDATED | fw->main.textsz);
6136 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
6137 const uint8_t *section, int size)
6139 struct iwn_dma_info *dma = &sc->fw_dma;
6142 /* Copy firmware section into pre-allocated DMA-safe memory. */
6143 memcpy(dma->vaddr, section, size);
6144 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6146 if ((error = iwn_nic_lock(sc)) != 0)
6149 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
6150 IWN_FH_TX_CONFIG_DMA_PAUSE);
6152 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
6153 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
6154 IWN_LOADDR(dma->paddr));
6155 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
6156 IWN_HIADDR(dma->paddr) << 28 | size);
6157 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
6158 IWN_FH_TXBUF_STATUS_TBNUM(1) |
6159 IWN_FH_TXBUF_STATUS_TBIDX(1) |
6160 IWN_FH_TXBUF_STATUS_TFBD_VALID);
6162 /* Kick Flow Handler to start DMA transfer. */
6163 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
6164 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
6168 /* Wait at most five seconds for FH DMA transfer to complete. */
6169 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz);
6173 iwn5000_load_firmware(struct iwn_softc *sc)
6175 struct iwn_fw_part *fw;
6178 /* Load the initialization firmware on first boot only. */
6179 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
6180 &sc->fw.main : &sc->fw.init;
6182 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
6183 fw->text, fw->textsz);
6185 device_printf(sc->sc_dev,
6186 "%s: could not load firmware %s section, error %d\n",
6187 __func__, ".text", error);
6190 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
6191 fw->data, fw->datasz);
6193 device_printf(sc->sc_dev,
6194 "%s: could not load firmware %s section, error %d\n",
6195 __func__, ".data", error);
6199 /* Now press "execute". */
6200 IWN_WRITE(sc, IWN_RESET, 0);
6205 * Extract text and data sections from a legacy firmware image.
6208 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw)
6210 const uint32_t *ptr;
6214 ptr = (const uint32_t *)fw->data;
6215 rev = le32toh(*ptr++);
6217 /* Check firmware API version. */
6218 if (IWN_FW_API(rev) <= 1) {
6219 device_printf(sc->sc_dev,
6220 "%s: bad firmware, need API version >=2\n", __func__);
6223 if (IWN_FW_API(rev) >= 3) {
6224 /* Skip build number (version 2 header). */
6228 if (fw->size < hdrlen) {
6229 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6230 __func__, fw->size);
6233 fw->main.textsz = le32toh(*ptr++);
6234 fw->main.datasz = le32toh(*ptr++);
6235 fw->init.textsz = le32toh(*ptr++);
6236 fw->init.datasz = le32toh(*ptr++);
6237 fw->boot.textsz = le32toh(*ptr++);
6239 /* Check that all firmware sections fit. */
6240 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
6241 fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
6242 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6243 __func__, fw->size);
6247 /* Get pointers to firmware sections. */
6248 fw->main.text = (const uint8_t *)ptr;
6249 fw->main.data = fw->main.text + fw->main.textsz;
6250 fw->init.text = fw->main.data + fw->main.datasz;
6251 fw->init.data = fw->init.text + fw->init.textsz;
6252 fw->boot.text = fw->init.data + fw->init.datasz;
6257 * Extract text and data sections from a TLV firmware image.
6260 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw,
6263 const struct iwn_fw_tlv_hdr *hdr;
6264 const struct iwn_fw_tlv *tlv;
6265 const uint8_t *ptr, *end;
6269 if (fw->size < sizeof (*hdr)) {
6270 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6271 __func__, fw->size);
6274 hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
6275 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
6276 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n",
6277 __func__, le32toh(hdr->signature));
6280 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr,
6281 le32toh(hdr->build));
6284 * Select the closest supported alternative that is less than
6285 * or equal to the specified one.
6287 altmask = le64toh(hdr->altmask);
6288 while (alt > 0 && !(altmask & (1ULL << alt)))
6289 alt--; /* Downgrade. */
6290 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt);
6292 ptr = (const uint8_t *)(hdr + 1);
6293 end = (const uint8_t *)(fw->data + fw->size);
6295 /* Parse type-length-value fields. */
6296 while (ptr + sizeof (*tlv) <= end) {
6297 tlv = (const struct iwn_fw_tlv *)ptr;
6298 len = le32toh(tlv->len);
6300 ptr += sizeof (*tlv);
6301 if (ptr + len > end) {
6302 device_printf(sc->sc_dev,
6303 "%s: firmware too short: %zu bytes\n", __func__,
6307 /* Skip other alternatives. */
6308 if (tlv->alt != 0 && tlv->alt != htole16(alt))
6311 switch (le16toh(tlv->type)) {
6312 case IWN_FW_TLV_MAIN_TEXT:
6313 fw->main.text = ptr;
6314 fw->main.textsz = len;
6316 case IWN_FW_TLV_MAIN_DATA:
6317 fw->main.data = ptr;
6318 fw->main.datasz = len;
6320 case IWN_FW_TLV_INIT_TEXT:
6321 fw->init.text = ptr;
6322 fw->init.textsz = len;
6324 case IWN_FW_TLV_INIT_DATA:
6325 fw->init.data = ptr;
6326 fw->init.datasz = len;
6328 case IWN_FW_TLV_BOOT_TEXT:
6329 fw->boot.text = ptr;
6330 fw->boot.textsz = len;
6332 case IWN_FW_TLV_ENH_SENS:
6334 sc->sc_flags |= IWN_FLAG_ENH_SENS;
6336 case IWN_FW_TLV_PHY_CALIB:
6337 tmp = htole32(*ptr);
6339 sc->reset_noise_gain = tmp;
6340 sc->noise_gain = tmp + 1;
6344 DPRINTF(sc, IWN_DEBUG_RESET,
6345 "TLV type %d not handled\n", le16toh(tlv->type));
6348 next: /* TLV fields are 32-bit aligned. */
6349 ptr += (len + 3) & ~3;
6355 iwn_read_firmware(struct iwn_softc *sc)
6357 struct iwn_fw_info *fw = &sc->fw;
6362 memset(fw, 0, sizeof (*fw));
6364 /* Read firmware image from filesystem. */
6365 sc->fw_fp = firmware_get(sc->fwname);
6366 if (sc->fw_fp == NULL) {
6367 device_printf(sc->sc_dev, "%s: could not read firmware %s\n",
6368 __func__, sc->fwname);
6374 fw->size = sc->fw_fp->datasize;
6375 fw->data = (const uint8_t *)sc->fw_fp->data;
6376 if (fw->size < sizeof (uint32_t)) {
6377 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6378 __func__, fw->size);
6379 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6384 /* Retrieve text and data sections. */
6385 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */
6386 error = iwn_read_firmware_leg(sc, fw);
6388 error = iwn_read_firmware_tlv(sc, fw, 1);
6390 device_printf(sc->sc_dev,
6391 "%s: could not read firmware sections, error %d\n",
6393 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6398 /* Make sure text and data sections fit in hardware memory. */
6399 if (fw->main.textsz > sc->fw_text_maxsz ||
6400 fw->main.datasz > sc->fw_data_maxsz ||
6401 fw->init.textsz > sc->fw_text_maxsz ||
6402 fw->init.datasz > sc->fw_data_maxsz ||
6403 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
6404 (fw->boot.textsz & 3) != 0) {
6405 device_printf(sc->sc_dev, "%s: firmware sections too large\n",
6407 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6412 /* We can proceed with loading the firmware. */
6417 iwn_clock_wait(struct iwn_softc *sc)
6421 /* Set "initialization complete" bit. */
6422 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
6424 /* Wait for clock stabilization. */
6425 for (ntries = 0; ntries < 2500; ntries++) {
6426 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
6430 device_printf(sc->sc_dev,
6431 "%s: timeout waiting for clock stabilization\n", __func__);
6436 iwn_apm_init(struct iwn_softc *sc)
6441 /* Disable L0s exit timer (NMI bug workaround). */
6442 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
6443 /* Don't wait for ICH L0s (ICH bug workaround). */
6444 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
6446 /* Set FH wait threshold to max (HW bug under stress workaround). */
6447 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
6449 /* Enable HAP INTA to move adapter from L1a to L0s. */
6450 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
6452 /* Retrieve PCIe Active State Power Management (ASPM). */
6453 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
6454 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
6455 if (reg & 0x02) /* L1 Entry enabled. */
6456 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
6458 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
6460 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
6461 sc->hw_type <= IWN_HW_REV_TYPE_1000)
6462 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT);
6464 /* Wait for clock stabilization before accessing prph. */
6465 if ((error = iwn_clock_wait(sc)) != 0)
6468 if ((error = iwn_nic_lock(sc)) != 0)
6470 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
6471 /* Enable DMA and BSM (Bootstrap State Machine). */
6472 iwn_prph_write(sc, IWN_APMG_CLK_EN,
6473 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
6474 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
6477 iwn_prph_write(sc, IWN_APMG_CLK_EN,
6478 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6481 /* Disable L1-Active. */
6482 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
6489 iwn_apm_stop_master(struct iwn_softc *sc)
6493 /* Stop busmaster DMA activity. */
6494 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
6495 for (ntries = 0; ntries < 100; ntries++) {
6496 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
6500 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__);
6504 iwn_apm_stop(struct iwn_softc *sc)
6506 iwn_apm_stop_master(sc);
6508 /* Reset the entire device. */
6509 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
6511 /* Clear "initialization complete" bit. */
6512 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
6516 iwn4965_nic_config(struct iwn_softc *sc)
6518 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
6520 * I don't believe this to be correct but this is what the
6521 * vendor driver is doing. Probably the bits should not be
6522 * shifted in IWN_RFCFG_*.
6524 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6525 IWN_RFCFG_TYPE(sc->rfcfg) |
6526 IWN_RFCFG_STEP(sc->rfcfg) |
6527 IWN_RFCFG_DASH(sc->rfcfg));
6529 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6530 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6535 iwn5000_nic_config(struct iwn_softc *sc)
6540 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
6541 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6542 IWN_RFCFG_TYPE(sc->rfcfg) |
6543 IWN_RFCFG_STEP(sc->rfcfg) |
6544 IWN_RFCFG_DASH(sc->rfcfg));
6546 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6547 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6549 if ((error = iwn_nic_lock(sc)) != 0)
6551 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
6553 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
6555 * Select first Switching Voltage Regulator (1.32V) to
6556 * solve a stability issue related to noisy DC2DC line
6557 * in the silicon of 1000 Series.
6559 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
6560 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
6561 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
6562 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
6566 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
6567 /* Use internal power amplifier only. */
6568 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
6570 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 ||
6571 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) {
6572 /* Indicate that ROM calibration version is >=6. */
6573 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
6575 if (sc->hw_type == IWN_HW_REV_TYPE_6005)
6576 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2);
6581 * Take NIC ownership over Intel Active Management Technology (AMT).
6584 iwn_hw_prepare(struct iwn_softc *sc)
6588 /* Check if hardware is ready. */
6589 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6590 for (ntries = 0; ntries < 5; ntries++) {
6591 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6592 IWN_HW_IF_CONFIG_NIC_READY)
6597 /* Hardware not ready, force into ready state. */
6598 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
6599 for (ntries = 0; ntries < 15000; ntries++) {
6600 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
6601 IWN_HW_IF_CONFIG_PREPARE_DONE))
6605 if (ntries == 15000)
6608 /* Hardware should be ready now. */
6609 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6610 for (ntries = 0; ntries < 5; ntries++) {
6611 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6612 IWN_HW_IF_CONFIG_NIC_READY)
6620 iwn_hw_init(struct iwn_softc *sc)
6622 struct iwn_ops *ops = &sc->ops;
6623 int error, chnl, qid;
6625 /* Clear pending interrupts. */
6626 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6628 if ((error = iwn_apm_init(sc)) != 0) {
6629 device_printf(sc->sc_dev,
6630 "%s: could not power ON adapter, error %d\n", __func__,
6635 /* Select VMAIN power source. */
6636 if ((error = iwn_nic_lock(sc)) != 0)
6638 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
6641 /* Perform adapter-specific initialization. */
6642 if ((error = ops->nic_config(sc)) != 0)
6645 /* Initialize RX ring. */
6646 if ((error = iwn_nic_lock(sc)) != 0)
6648 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
6649 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
6650 /* Set physical address of RX ring (256-byte aligned). */
6651 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
6652 /* Set physical address of RX status (16-byte aligned). */
6653 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
6655 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
6656 IWN_FH_RX_CONFIG_ENA |
6657 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
6658 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
6659 IWN_FH_RX_CONFIG_SINGLE_FRAME |
6660 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
6661 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
6663 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
6665 if ((error = iwn_nic_lock(sc)) != 0)
6668 /* Initialize TX scheduler. */
6669 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6671 /* Set physical address of "keep warm" page (16-byte aligned). */
6672 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
6674 /* Initialize TX rings. */
6675 for (qid = 0; qid < sc->ntxqs; qid++) {
6676 struct iwn_tx_ring *txq = &sc->txq[qid];
6678 /* Set physical address of TX ring (256-byte aligned). */
6679 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
6680 txq->desc_dma.paddr >> 8);
6684 /* Enable DMA channels. */
6685 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6686 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
6687 IWN_FH_TX_CONFIG_DMA_ENA |
6688 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
6691 /* Clear "radio off" and "commands blocked" bits. */
6692 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6693 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
6695 /* Clear pending interrupts. */
6696 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6697 /* Enable interrupt coalescing. */
6698 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
6699 /* Enable interrupts. */
6700 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6702 /* _Really_ make sure "radio off" bit is cleared! */
6703 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6704 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6706 /* Enable shadow registers. */
6707 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
6708 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff);
6710 if ((error = ops->load_firmware(sc)) != 0) {
6711 device_printf(sc->sc_dev,
6712 "%s: could not load firmware, error %d\n", __func__,
6716 /* Wait at most one second for firmware alive notification. */
6717 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
6718 device_printf(sc->sc_dev,
6719 "%s: timeout waiting for adapter to initialize, error %d\n",
6723 /* Do post-firmware initialization. */
6724 return ops->post_alive(sc);
6728 iwn_hw_stop(struct iwn_softc *sc)
6730 int chnl, qid, ntries;
6732 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
6734 /* Disable interrupts. */
6735 IWN_WRITE(sc, IWN_INT_MASK, 0);
6736 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6737 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
6738 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6740 /* Make sure we no longer hold the NIC lock. */
6743 /* Stop TX scheduler. */
6744 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6746 /* Stop all DMA channels. */
6747 if (iwn_nic_lock(sc) == 0) {
6748 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6749 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
6750 for (ntries = 0; ntries < 200; ntries++) {
6751 if (IWN_READ(sc, IWN_FH_TX_STATUS) &
6752 IWN_FH_TX_STATUS_IDLE(chnl))
6761 iwn_reset_rx_ring(sc, &sc->rxq);
6763 /* Reset all TX rings. */
6764 for (qid = 0; qid < sc->ntxqs; qid++)
6765 iwn_reset_tx_ring(sc, &sc->txq[qid]);
6767 if (iwn_nic_lock(sc) == 0) {
6768 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
6769 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6773 /* Power OFF adapter. */
6778 iwn_radio_on(void *arg0, int pending)
6780 struct iwn_softc *sc = arg0;
6781 struct ifnet *ifp = sc->sc_ifp;
6782 struct ieee80211com *ic = ifp->if_l2com;
6783 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6787 ieee80211_init(vap);
6792 iwn_radio_off(void *arg0, int pending)
6794 struct iwn_softc *sc = arg0;
6795 struct ifnet *ifp = sc->sc_ifp;
6796 struct ieee80211com *ic = ifp->if_l2com;
6797 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6801 ieee80211_stop(vap);
6803 /* Enable interrupts to get RF toggle notification. */
6805 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6806 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6811 iwn_init_locked(struct iwn_softc *sc)
6813 struct ifnet *ifp = sc->sc_ifp;
6816 IWN_LOCK_ASSERT(sc);
6818 if ((error = iwn_hw_prepare(sc)) != 0) {
6819 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n",
6824 /* Initialize interrupt mask to default value. */
6825 sc->int_mask = IWN_INT_MASK_DEF;
6826 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6828 /* Check that the radio is not disabled by hardware switch. */
6829 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
6830 device_printf(sc->sc_dev,
6831 "radio is disabled by hardware switch\n");
6832 /* Enable interrupts to get RF toggle notifications. */
6833 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6834 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6838 /* Read firmware images from the filesystem. */
6839 if ((error = iwn_read_firmware(sc)) != 0) {
6840 device_printf(sc->sc_dev,
6841 "%s: could not read firmware, error %d\n", __func__,
6846 /* Initialize hardware and upload firmware. */
6847 error = iwn_hw_init(sc);
6848 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6851 device_printf(sc->sc_dev,
6852 "%s: could not initialize hardware, error %d\n", __func__,
6857 /* Configure adapter now that it is ready. */
6858 if ((error = iwn_config(sc)) != 0) {
6859 device_printf(sc->sc_dev,
6860 "%s: could not configure device, error %d\n", __func__,
6865 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6866 ifp->if_drv_flags |= IFF_DRV_RUNNING;
6868 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
6871 fail: iwn_stop_locked(sc);
6877 struct iwn_softc *sc = arg;
6878 struct ifnet *ifp = sc->sc_ifp;
6879 struct ieee80211com *ic = ifp->if_l2com;
6882 iwn_init_locked(sc);
6885 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6886 ieee80211_start_all(ic);
6890 iwn_stop_locked(struct iwn_softc *sc)
6892 struct ifnet *ifp = sc->sc_ifp;
6894 IWN_LOCK_ASSERT(sc);
6896 sc->sc_tx_timer = 0;
6897 callout_stop(&sc->watchdog_to);
6898 callout_stop(&sc->calib_to);
6899 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6901 /* Power OFF hardware. */
6906 iwn_stop(struct iwn_softc *sc)
6909 iwn_stop_locked(sc);
6914 * Callback from net80211 to start a scan.
6917 iwn_scan_start(struct ieee80211com *ic)
6919 struct ifnet *ifp = ic->ic_ifp;
6920 struct iwn_softc *sc = ifp->if_softc;
6923 /* make the link LED blink while we're scanning */
6924 iwn_set_led(sc, IWN_LED_LINK, 20, 2);
6929 * Callback from net80211 to terminate a scan.
6932 iwn_scan_end(struct ieee80211com *ic)
6934 struct ifnet *ifp = ic->ic_ifp;
6935 struct iwn_softc *sc = ifp->if_softc;
6936 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6939 if (vap->iv_state == IEEE80211_S_RUN) {
6940 /* Set link LED to ON status if we are associated */
6941 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
6947 * Callback from net80211 to force a channel change.
6950 iwn_set_channel(struct ieee80211com *ic)
6952 const struct ieee80211_channel *c = ic->ic_curchan;
6953 struct ifnet *ifp = ic->ic_ifp;
6954 struct iwn_softc *sc = ifp->if_softc;
6958 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
6959 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
6960 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
6961 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
6964 * Only need to set the channel in Monitor mode. AP scanning and auth
6965 * are already taken care of by their respective firmware commands.
6967 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
6968 error = iwn_config(sc);
6970 device_printf(sc->sc_dev,
6971 "%s: error %d settting channel\n", __func__, error);
6977 * Callback from net80211 to start scanning of the current channel.
6980 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
6982 struct ieee80211vap *vap = ss->ss_vap;
6983 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6987 error = iwn_scan(sc);
6990 ieee80211_cancel_scan(vap);
6994 * Callback from net80211 to handle the minimum dwell time being met.
6995 * The intent is to terminate the scan but we just let the firmware
6996 * notify us when it's finished as we have no safe way to abort it.
6999 iwn_scan_mindwell(struct ieee80211_scan_state *ss)
7001 /* NB: don't try to abort scan; wait for firmware to finish */
7005 iwn_hw_reset(void *arg0, int pending)
7007 struct iwn_softc *sc = arg0;
7008 struct ifnet *ifp = sc->sc_ifp;
7009 struct ieee80211com *ic = ifp->if_l2com;
7013 ieee80211_notify_radio(ic, 1);