2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #define IWN_TX_RING_COUNT 256
22 #define IWN_TX_RING_LOMARK 192
23 #define IWN_TX_RING_HIMARK 224
24 #define IWN_RX_RING_COUNT_LOG 6
25 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
27 #define IWN4965_NTXQUEUES 16
28 #define IWN5000_NTXQUEUES 20
30 #define IWN4965_FIRSTAGGQUEUE 7
31 #define IWN5000_FIRSTAGGQUEUE 10
33 #define IWN4965_NDMACHNLS 7
34 #define IWN5000_NDMACHNLS 8
36 #define IWN_SRVC_DMACHNL 9
38 #define IWN_ICT_SIZE 4096
39 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))
41 /* Maximum number of DMA segments for TX. */
42 #define IWN_MAX_SCATTER 20
44 /* RX buffers must be large enough to hold a full 4K A-MPDU. */
45 #define IWN_RBUF_SIZE (4 * 1024)
48 /* HW supports 36-bit DMA addresses. */
49 #define IWN_LOADDR(paddr) ((uint32_t)(paddr))
50 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
52 #define IWN_LOADDR(paddr) (paddr)
53 #define IWN_HIADDR(paddr) (0)
57 * Control and status registers.
59 #define IWN_HW_IF_CONFIG 0x000
60 #define IWN_INT_COALESCING 0x004
61 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
63 #define IWN_INT_MASK 0x00c
64 #define IWN_FH_INT 0x010
65 #define IWN_RESET 0x020
66 #define IWN_GP_CNTRL 0x024
67 #define IWN_HW_REV 0x028
68 #define IWN_EEPROM 0x02c
69 #define IWN_EEPROM_GP 0x030
70 #define IWN_OTP_GP 0x034
72 #define IWN_GP_DRIVER 0x050
73 #define IWN_UCODE_GP1_CLR 0x05c
75 #define IWN_DRAM_INT_TBL 0x0a0
76 #define IWN_SHADOW_REG_CTRL 0x0a8
77 #define IWN_GIO_CHICKEN 0x100
78 #define IWN_ANA_PLL 0x20c
79 #define IWN_HW_REV_WA 0x22c
80 #define IWN_DBG_HPET_MEM 0x240
81 #define IWN_DBG_LINK_PWR_MGMT 0x250
82 #define IWN_MEM_RADDR 0x40c
83 #define IWN_MEM_WADDR 0x410
84 #define IWN_MEM_WDATA 0x418
85 #define IWN_MEM_RDATA 0x41c
86 #define IWN_PRPH_WADDR 0x444
87 #define IWN_PRPH_RADDR 0x448
88 #define IWN_PRPH_WDATA 0x44c
89 #define IWN_PRPH_RDATA 0x450
90 #define IWN_HBUS_TARG_WRPTR 0x460
93 * Flow-Handler registers.
95 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
96 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
97 #define IWN_FH_KW_ADDR 0x197c
98 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
99 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
100 #define IWN_FH_STATUS_WPTR 0x1bc0
101 #define IWN_FH_RX_BASE 0x1bc4
102 #define IWN_FH_RX_WPTR 0x1bc8
103 #define IWN_FH_RX_CONFIG 0x1c00
104 #define IWN_FH_RX_STATUS 0x1c44
105 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
106 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
107 #define IWN_FH_TX_CHICKEN 0x1e98
108 #define IWN_FH_TX_STATUS 0x1eb0
111 * TX scheduler registers.
113 #define IWN_SCHED_BASE 0xa02c00
114 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
115 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
116 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
117 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
118 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
119 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
120 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
121 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
122 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
123 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
124 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
125 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
126 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
127 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
130 * Offsets in TX scheduler's SRAM.
132 #define IWN4965_SCHED_CTX_OFF 0x380
133 #define IWN4965_SCHED_CTX_LEN 416
134 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
135 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
136 #define IWN5000_SCHED_CTX_OFF 0x600
137 #define IWN5000_SCHED_CTX_LEN 520
138 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
139 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
142 * NIC internal memory offsets.
144 #define IWN_APMG_CLK_CTRL 0x3000
145 #define IWN_APMG_CLK_EN 0x3004
146 #define IWN_APMG_CLK_DIS 0x3008
147 #define IWN_APMG_PS 0x300c
148 #define IWN_APMG_DIGITAL_SVR 0x3058
149 #define IWN_APMG_ANALOG_SVR 0x306c
150 #define IWN_APMG_PCI_STT 0x3010
151 #define IWN_BSM_WR_CTRL 0x3400
152 #define IWN_BSM_WR_MEM_SRC 0x3404
153 #define IWN_BSM_WR_MEM_DST 0x3408
154 #define IWN_BSM_WR_DWCOUNT 0x340c
155 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490
156 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494
157 #define IWN_BSM_DRAM_DATA_ADDR 0x3498
158 #define IWN_BSM_DRAM_DATA_SIZE 0x349c
159 #define IWN_BSM_SRAM_BASE 0x3800
161 /* Possible flags for register IWN_HW_IF_CONFIG. */
162 #define IWN_HW_IF_CONFIG_4965_R (1 << 4)
163 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
164 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
165 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
166 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22)
167 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
168 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
169 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27)
171 /* Possible values for register IWN_INT_PERIODIC. */
172 #define IWN_INT_PERIODIC_DIS 0x00
173 #define IWN_INT_PERIODIC_ENA 0xff
175 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
176 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
178 /* Possible values for IWN_BSM_WR_MEM_DST. */
179 #define IWN_FW_TEXT_BASE 0x00000000
180 #define IWN_FW_DATA_BASE 0x00800000
182 /* Possible flags for register IWN_RESET. */
183 #define IWN_RESET_NEVO (1 << 0)
184 #define IWN_RESET_SW (1 << 7)
185 #define IWN_RESET_MASTER_DISABLED (1 << 8)
186 #define IWN_RESET_STOP_MASTER (1 << 9)
187 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31)
189 /* Possible flags for register IWN_GP_CNTRL. */
190 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
191 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
192 #define IWN_GP_CNTRL_INIT_DONE (1 << 2)
193 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
194 #define IWN_GP_CNTRL_SLEEP (1 << 4)
195 #define IWN_GP_CNTRL_RFKILL (1 << 27)
197 /* Possible flags for register IWN_HW_REV. */
198 #define IWN_HW_REV_TYPE_SHIFT 4
199 #define IWN_HW_REV_TYPE_MASK 0x000000f0
200 #define IWN_HW_REV_TYPE_4965 0
201 #define IWN_HW_REV_TYPE_5300 2
202 #define IWN_HW_REV_TYPE_5350 3
203 #define IWN_HW_REV_TYPE_5150 4
204 #define IWN_HW_REV_TYPE_5100 5
205 #define IWN_HW_REV_TYPE_1000 6
206 #define IWN_HW_REV_TYPE_6000 7
207 #define IWN_HW_REV_TYPE_6050 8
208 #define IWN_HW_REV_TYPE_6005 11
210 /* Possible flags for register IWN_GIO_CHICKEN. */
211 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
212 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
214 /* Possible flags for register IWN_GIO. */
215 #define IWN_GIO_L0S_ENA (1 << 1)
217 /* Possible flags for register IWN_GP_DRIVER. */
218 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0)
219 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0)
220 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0)
221 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2)
222 #define IWN_GP_DRIVER_6050_1X2 (1 << 3)
224 /* Possible flags for register IWN_UCODE_GP1_CLR. */
225 #define IWN_UCODE_GP1_RFKILL (1 << 1)
226 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
227 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
229 /* Possible flags/values for register IWN_LED. */
230 #define IWN_LED_BSM_CTRL (1 << 5)
231 #define IWN_LED_OFF 0x00000038
232 #define IWN_LED_ON 0x00000078
234 /* Possible flags for register IWN_DRAM_INT_TBL. */
235 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27)
236 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31)
238 /* Possible values for register IWN_ANA_PLL. */
239 #define IWN_ANA_PLL_INIT 0x00880300
241 /* Possible flags for register IWN_FH_RX_STATUS. */
242 #define IWN_FH_RX_STATUS_IDLE (1 << 24)
244 /* Possible flags for register IWN_BSM_WR_CTRL. */
245 #define IWN_BSM_WR_CTRL_START_EN (1 << 30)
246 #define IWN_BSM_WR_CTRL_START (1 << 31)
248 /* Possible flags for register IWN_INT. */
249 #define IWN_INT_ALIVE (1 << 0)
250 #define IWN_INT_WAKEUP (1 << 1)
251 #define IWN_INT_SW_RX (1 << 3)
252 #define IWN_INT_CT_REACHED (1 << 6)
253 #define IWN_INT_RF_TOGGLED (1 << 7)
254 #define IWN_INT_SW_ERR (1 << 25)
255 #define IWN_INT_SCHED (1 << 26)
256 #define IWN_INT_FH_TX (1 << 27)
257 #define IWN_INT_RX_PERIODIC (1 << 28)
258 #define IWN_INT_HW_ERR (1 << 29)
259 #define IWN_INT_FH_RX (1 << 31)
262 #define IWN_INT_MASK_DEF \
263 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
264 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
265 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
267 /* Possible flags for register IWN_FH_INT. */
268 #define IWN_FH_INT_TX_CHNL(x) (1 << (x))
269 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
270 #define IWN_FH_INT_HI_PRIOR (1 << 30)
271 /* Shortcuts for the above. */
272 #define IWN_FH_INT_TX \
273 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
274 #define IWN_FH_INT_RX \
275 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
277 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
278 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0
279 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
280 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20)
282 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
283 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20)
284 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12)
285 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3
287 /* Possible flags for register IWN_FH_TX_CHICKEN. */
288 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1)
290 /* Possible flags for register IWN_FH_TX_STATUS. */
291 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16))
293 /* Possible flags for register IWN_FH_RX_CONFIG. */
294 #define IWN_FH_RX_CONFIG_ENA (1 << 31)
295 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20)
296 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16)
297 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15)
298 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12)
299 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4)
300 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2)
302 /* Possible flags for register IWN_FH_TX_CONFIG. */
303 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
304 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3)
306 /* Possible flags for register IWN_EEPROM. */
307 #define IWN_EEPROM_READ_VALID (1 << 0)
308 #define IWN_EEPROM_CMD (1 << 1)
310 /* Possible flags for register IWN_EEPROM_GP. */
311 #define IWN_EEPROM_GP_IF_OWNER 0x00000180
313 /* Possible flags for register IWN_OTP_GP. */
314 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16)
315 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17)
316 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20)
317 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21)
319 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
320 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
321 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
322 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
323 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
324 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
325 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
326 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
328 /* Possible flags for registers IWN_APMG_CLK_*. */
329 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
330 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
332 /* Possible flags for register IWN_APMG_PS. */
333 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
334 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
335 #define IWN_APMG_PS_PWR_SRC_VMAIN 0
336 #define IWN_APMG_PS_PWR_SRC_VAUX 2
337 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
338 #define IWN_APMG_PS_RESET_REQ (1 << 26)
340 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */
341 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
342 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \
343 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
344 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \
345 IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
347 /* Possible flags for IWN_APMG_PCI_STT. */
348 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
350 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
351 #define IWN_FW_UPDATED (1 << 31)
353 #define IWN_SCHED_WINSZ 64
354 #define IWN_SCHED_LIMIT 64
355 #define IWN4965_SCHED_COUNT 512
356 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
357 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
358 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
361 uint8_t reserved1[3];
366 } __packed segs[IWN_MAX_SCATTER];
367 /* Pad to 128 bytes. */
371 struct iwn_rx_status {
372 uint16_t closed_count;
373 uint16_t closed_rx_count;
374 uint16_t finished_count;
375 uint16_t finished_rx_count;
376 uint32_t reserved[2];
382 #define IWN_UC_READY 1
383 #define IWN_ADD_NODE_DONE 24
384 #define IWN_TX_DONE 28
385 #define IWN5000_CALIBRATION_RESULT 102
386 #define IWN5000_CALIBRATION_DONE 103
387 #define IWN_START_SCAN 130
388 #define IWN_STOP_SCAN 132
389 #define IWN_RX_STATISTICS 156
390 #define IWN_BEACON_STATISTICS 157
391 #define IWN_STATE_CHANGED 161
392 #define IWN_BEACON_MISSED 162
393 #define IWN_RX_PHY 192
394 #define IWN_MPDU_RX_DONE 193
395 #define IWN_RX_DONE 195
396 #define IWN_RX_COMPRESSED_BA 197
403 /* Possible RX status flags. */
404 #define IWN_RX_NO_CRC_ERR (1 << 0)
405 #define IWN_RX_NO_OVFL_ERR (1 << 1)
406 /* Shortcut for the above. */
407 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
408 #define IWN_RX_MPDU_MIC_OK (1 << 6)
409 #define IWN_RX_CIPHER_MASK (7 << 8)
410 #define IWN_RX_CIPHER_CCMP (2 << 8)
411 #define IWN_RX_MPDU_DEC (1 << 11)
412 #define IWN_RX_DECRYPT_MASK (3 << 11)
413 #define IWN_RX_DECRYPT_OK (3 << 11)
417 #define IWN_CMD_RXON 16
418 #define IWN_CMD_RXON_ASSOC 17
419 #define IWN_CMD_EDCA_PARAMS 19
420 #define IWN_CMD_TIMING 20
421 #define IWN_CMD_ADD_NODE 24
422 #define IWN_CMD_TX_DATA 28
423 #define IWN_CMD_LINK_QUALITY 78
424 #define IWN_CMD_SET_LED 72
425 #define IWN5000_CMD_WIMAX_COEX 90
426 #define IWN5000_CMD_CALIB_CONFIG 101
427 #define IWN5000_CMD_CALIB_RESULT 102
428 #define IWN5000_CMD_CALIB_COMPLETE 103
429 #define IWN_CMD_SET_POWER_MODE 119
430 #define IWN_CMD_SCAN 128
431 #define IWN_CMD_SCAN_RESULTS 131
432 #define IWN_CMD_TXPOWER_DBM 149
433 #define IWN_CMD_TXPOWER 151
434 #define IWN5000_CMD_TX_ANT_CONFIG 152
435 #define IWN_CMD_BT_COEX 155
436 #define IWN_CMD_GET_STATISTICS 156
437 #define IWN_CMD_SET_CRITICAL_TEMP 164
438 #define IWN_CMD_SET_SENSITIVITY 168
439 #define IWN_CMD_PHY_CALIB 176
440 #define IWN_CMD_BT_COEX_PRIOTABLE 204
441 #define IWN_CMD_BT_COEX_PROT 205
449 /* Antenna flags, used in various commands. */
450 #define IWN_ANT_A (1 << 0)
451 #define IWN_ANT_B (1 << 1)
452 #define IWN_ANT_C (1 << 2)
454 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B)
455 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C)
456 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
458 /* Structure for command IWN_CMD_RXON. */
460 uint8_t myaddr[IEEE80211_ADDR_LEN];
462 uint8_t bssid[IEEE80211_ADDR_LEN];
464 uint8_t wlap[IEEE80211_ADDR_LEN];
467 #define IWN_MODE_HOSTAP 1
468 #define IWN_MODE_STA 3
469 #define IWN_MODE_IBSS 4
470 #define IWN_MODE_MONITOR 6
474 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0)
475 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1)
476 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4)
477 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7)
478 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
479 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
480 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
486 #define IWN_RXON_24GHZ (1 << 0)
487 #define IWN_RXON_CCK (1 << 1)
488 #define IWN_RXON_AUTO (1 << 2)
489 #define IWN_RXON_SHSLOT (1 << 4)
490 #define IWN_RXON_SHPREAMBLE (1 << 5)
491 #define IWN_RXON_NODIVERSITY (1 << 7)
492 #define IWN_RXON_ANTENNA_A (1 << 8)
493 #define IWN_RXON_ANTENNA_B (1 << 9)
494 #define IWN_RXON_TSF (1 << 15)
495 #define IWN_RXON_HT_HT40MINUS (1 << 22)
496 #define IWN_RXON_HT_PROTMODE(x) (x << 23)
497 #define IWN_RXON_HT_MODEPURE40 (1 << 25)
498 #define IWN_RXON_HT_MODEMIXED (2 << 25)
499 #define IWN_RXON_CTS_TO_SELF (1 << 30)
502 #define IWN_FILTER_PROMISC (1 << 0)
503 #define IWN_FILTER_CTL (1 << 1)
504 #define IWN_FILTER_MULTICAST (1 << 2)
505 #define IWN_FILTER_NODECRYPT (1 << 3)
506 #define IWN_FILTER_BSS (1 << 5)
507 #define IWN_FILTER_BEACON (1 << 6)
511 uint8_t ht_single_mask;
512 uint8_t ht_dual_mask;
513 /* The following fields are for >=5000 Series only. */
514 uint8_t ht_triple_mask;
516 uint16_t acquisition;
520 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
521 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon))
523 /* Structure for command IWN_CMD_ASSOCIATE. */
532 /* Structure for command IWN_CMD_EDCA_PARAMS. */
533 struct iwn_edca_params {
535 #define IWN_EDCA_UPDATE (1 << 0)
536 #define IWN_EDCA_TXOP (1 << 4)
544 } __packed ac[WME_NUM_AC];
547 /* Structure for command IWN_CMD_TIMING. */
548 struct iwn_cmd_timing {
557 /* Structure for command IWN_CMD_ADD_NODE. */
558 struct iwn_node_info {
560 #define IWN_NODE_UPDATE (1 << 0)
562 uint8_t reserved1[3];
564 uint8_t macaddr[IEEE80211_ADDR_LEN];
568 #define IWN5000_ID_BROADCAST 15
569 #define IWN4965_ID_BROADCAST 31
572 #define IWN_FLAG_SET_KEY (1 << 0)
573 #define IWN_FLAG_SET_DISABLE_TID (1 << 1)
574 #define IWN_FLAG_SET_TXRATE (1 << 2)
575 #define IWN_FLAG_SET_ADDBA (1 << 3)
576 #define IWN_FLAG_SET_DELBA (1 << 4)
580 #define IWN_KFLAG_CCMP (1 << 1)
581 #define IWN_KFLAG_MAP (1 << 3)
582 #define IWN_KFLAG_KID(kid) ((kid) << 8)
583 #define IWN_KFLAG_INVALID (1 << 11)
584 #define IWN_KFLAG_GROUP (1 << 14)
586 uint8_t tsc2; /* TKIP TSC2 */
592 /* The following 3 fields are for 5000 Series only. */
598 #define IWN_SMPS_MIMO_PROT (1 << 17)
599 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19)
600 #define IWN_NODE_HT40 (1 << 21)
601 #define IWN_SMPS_MIMO_DIS (1 << 22)
602 #define IWN_AMDPU_DENSITY(x) ((x) << 23)
605 uint16_t disable_tid;
613 struct iwn4965_node_info {
615 uint8_t reserved1[3];
616 uint8_t macaddr[IEEE80211_ADDR_LEN];
622 uint8_t tsc2; /* TKIP TSC2 */
630 uint16_t disable_tid;
638 #define IWN_RFLAG_MCS (1 << 8)
639 #define IWN_RFLAG_CCK (1 << 9)
640 #define IWN_RFLAG_GREENFIELD (1 << 10)
641 #define IWN_RFLAG_HT40 (1 << 11)
642 #define IWN_RFLAG_DUPLICATE (1 << 12)
643 #define IWN_RFLAG_SGI (1 << 13)
644 #define IWN_RFLAG_ANT(x) ((x) << 14)
646 /* Structure for command IWN_CMD_TX_DATA. */
647 struct iwn_cmd_data {
651 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
652 #define IWN_TX_NEED_RTS (1 << 1)
653 #define IWN_TX_NEED_CTS (1 << 2)
654 #define IWN_TX_NEED_ACK (1 << 3)
655 #define IWN_TX_LINKQ (1 << 4)
656 #define IWN_TX_IMM_BA (1 << 6)
657 #define IWN_TX_FULL_TXOP (1 << 7)
658 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
659 #define IWN_TX_AUTO_SEQ (1 << 13)
660 #define IWN_TX_MORE_FRAG (1 << 14)
661 #define IWN_TX_INSERT_TSTAMP (1 << 16)
662 #define IWN_TX_NEED_PADDING (1 << 20)
669 #define IWN_CIPHER_WEP40 1
670 #define IWN_CIPHER_CCMP 2
671 #define IWN_CIPHER_TKIP 3
672 #define IWN_CIPHER_WEP104 9
680 #define IWN_LIFETIME_INFINITE 0xffffffff
691 /* Structure for command IWN_CMD_LINK_QUALITY. */
692 #define IWN_MAX_TX_RETRIES 16
693 struct iwn_cmd_link_quality {
699 uint8_t antmsk_1stream;
700 uint8_t antmsk_2stream;
701 uint8_t ridx[WME_NUM_AC];
702 uint16_t ampdu_limit;
703 uint8_t ampdu_threshold;
706 uint32_t retry[IWN_MAX_TX_RETRIES];
710 /* Structure for command IWN_CMD_SET_LED. */
712 uint32_t unit; /* multiplier (in usecs) */
714 #define IWN_LED_ACTIVITY 1
715 #define IWN_LED_LINK 2
722 /* Structure for command IWN5000_CMD_WIMAX_COEX. */
723 struct iwn5000_wimax_coex {
725 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
726 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2)
727 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3)
728 #define IWN_WIMAX_COEX_ENABLE (1 << 7)
730 struct iwn5000_wimax_event {
735 } __packed events[16];
738 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
739 struct iwn5000_calib_elem {
742 #define IWN5000_CALIB_DC (1 << 1)
749 struct iwn5000_calib_status {
750 struct iwn5000_calib_elem once;
751 struct iwn5000_calib_elem perd;
755 struct iwn5000_calib_config {
756 struct iwn5000_calib_status ucode;
757 struct iwn5000_calib_status driver;
761 /* Structure for command IWN_CMD_SET_POWER_MODE. */
762 struct iwn_pmgt_cmd {
764 #define IWN_PS_ALLOW_SLEEP (1 << 0)
765 #define IWN_PS_NOTIFY (1 << 1)
766 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2)
767 #define IWN_PS_PCI_PMGT (1 << 3)
768 #define IWN_PS_FAST_PD (1 << 4)
778 /* Structures for command IWN_CMD_SCAN. */
779 struct iwn_scan_essid {
782 uint8_t data[IEEE80211_NWID_LEN];
785 struct iwn_scan_hdr {
790 uint16_t quiet_threshold;
791 uint16_t crc_threshold;
793 uint32_t max_svc; /* background scans */
794 uint32_t pause_svc; /* background scans */
798 /* Followed by a struct iwn_cmd_data. */
799 /* Followed by an array of 20 structs iwn_scan_essid. */
800 /* Followed by probe request body. */
801 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */
804 struct iwn_scan_chan {
806 #define IWN_CHAN_ACTIVE (1 << 0)
807 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1)
812 uint16_t active; /* msecs */
813 uint16_t passive; /* msecs */
816 /* Maximum size of a scan command. */
817 #define IWN_SCAN_MAXSZ (MCLBYTES - 4)
819 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
820 #define IWN_RIDX_MAX 32
821 struct iwn4965_cmd_txpower {
829 } __packed power[IWN_RIDX_MAX + 1];
832 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
833 struct iwn5000_cmd_txpower {
834 int8_t global_limit; /* in half-dBm */
835 #define IWN5000_TXPOWER_AUTO 0x7f
836 #define IWN5000_TXPOWER_MAX_DBM 16
839 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6)
841 int8_t srv_limit; /* in half-dBm */
845 /* Structures for command IWN_CMD_BLUETOOTH. */
846 struct iwn_bluetooth {
848 #define IWN_BT_COEX_CHAN_ANN (1 << 0)
849 #define IWN_BT_COEX_BT_PRIO (1 << 1)
850 #define IWN_BT_COEX_2_WIRE (1 << 2)
853 #define IWN_BT_LEAD_TIME_DEF 30
856 #define IWN_BT_MAX_KILL_DEF 5
863 struct iwn6000_btcoex_config {
867 uint8_t bt3_t7_timer;
871 uint8_t bt3_t2_timer;
872 uint16_t bt4_reaction;
873 uint32_t lookup_table[12];
874 uint16_t bt4_decision;
877 uint8_t tx_prio_boost;
878 uint16_t rx_prio_boost;
881 struct iwn_btcoex_priotable {
884 uint8_t calib_periodic_low1;
885 uint8_t calib_periodic_low2;
886 uint8_t calib_periodic_high1;
887 uint8_t calib_periodic_high2;
894 struct iwn_btcoex_prot {
900 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
901 struct iwn_critical_temp {
905 /* degK <-> degC conversion macros. */
906 #define IWN_CTOK(c) ((c) + 273)
907 #define IWN_KTOC(k) ((k) - 273)
908 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
911 /* Structures for command IWN_CMD_SET_SENSITIVITY. */
912 struct iwn_sensitivity_cmd {
914 #define IWN_SENSITIVITY_DEFAULTTBL 0
915 #define IWN_SENSITIVITY_WORKTBL 1
918 uint16_t energy_ofdm;
919 uint16_t corr_ofdm_x1;
920 uint16_t corr_ofdm_mrc_x1;
921 uint16_t corr_cck_mrc_x4;
922 uint16_t corr_ofdm_x4;
923 uint16_t corr_ofdm_mrc_x4;
924 uint16_t corr_barker;
925 uint16_t corr_barker_mrc;
926 uint16_t corr_cck_x4;
927 uint16_t energy_ofdm_th;
930 struct iwn_enhanced_sensitivity_cmd {
933 uint16_t energy_ofdm;
934 uint16_t corr_ofdm_x1;
935 uint16_t corr_ofdm_mrc_x1;
936 uint16_t corr_cck_mrc_x4;
937 uint16_t corr_ofdm_x4;
938 uint16_t corr_ofdm_mrc_x4;
939 uint16_t corr_barker;
940 uint16_t corr_barker_mrc;
941 uint16_t corr_cck_x4;
942 uint16_t energy_ofdm_th;
943 /* "Enhanced" part. */
944 uint16_t ina_det_ofdm;
945 uint16_t ina_det_cck;
946 uint16_t corr_11_9_en;
947 uint16_t ofdm_det_slope_mrc;
948 uint16_t ofdm_det_icept_mrc;
949 uint16_t ofdm_det_slope;
950 uint16_t ofdm_det_icept;
951 uint16_t cck_det_slope_mrc;
952 uint16_t cck_det_icept_mrc;
953 uint16_t cck_det_slope;
954 uint16_t cck_det_icept;
958 /* Structures for command IWN_CMD_PHY_CALIB. */
959 struct iwn_phy_calib {
961 #define IWN4965_PHY_CALIB_DIFF_GAIN 7
962 #define IWN5000_PHY_CALIB_DC 8
963 #define IWN5000_PHY_CALIB_LO 9
964 #define IWN5000_PHY_CALIB_TX_IQ 11
965 #define IWN5000_PHY_CALIB_CRYSTAL 15
966 #define IWN5000_PHY_CALIB_BASE_BAND 16
967 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17
968 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18
970 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
971 #define IWN5000_PHY_CALIB_NOISE_GAIN 19
978 struct iwn5000_phy_calib_crystal {
988 struct iwn5000_phy_calib_temp_offset {
994 #define IWN_DEFAULT_TEMP_OFFSET 2700
999 struct iwn_phy_calib_gain {
1009 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
1010 struct iwn_spectrum_cmd {
1027 #define IWN_MEASUREMENT_BASIC (1 << 0)
1028 #define IWN_MEASUREMENT_CCA (1 << 1)
1029 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2)
1030 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3)
1031 #define IWN_MEASUREMENT_FRAME (1 << 4)
1032 #define IWN_MEASUREMENT_IDLE (1 << 7)
1035 } __packed chan[10];
1038 /* Structure for IWN_UC_READY notification. */
1039 #define IWN_NATTEN_GROUPS 5
1040 struct iwn_ucode_info {
1044 uint8_t revision[8];
1047 #define IWN_UCODE_RUNTIME 0
1048 #define IWN_UCODE_INIT 9
1056 /* The following fields are for UCODE_INIT only. */
1062 int32_t atten[IWN_NATTEN_GROUPS][2];
1065 /* Structures for IWN_TX_DONE notification. */
1066 #define IWN_TX_SUCCESS 0x00
1067 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */
1068 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
1069 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
1070 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
1071 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
1072 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
1074 struct iwn4965_tx_stat {
1086 struct iwn5000_tx_stat {
1105 /* Structure for IWN_BEACON_MISSED notification. */
1106 struct iwn_beacon_missed {
1107 uint32_t consecutive;
1113 /* Structure for IWN_MPDU_RX_DONE notification. */
1114 struct iwn_rx_mpdu {
1119 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
1120 struct iwn4965_rx_phystat {
1126 struct iwn5000_rx_phystat {
1132 struct iwn_rx_stat {
1134 uint8_t cfg_phy_len;
1135 #define IWN_STAT_MAXLEN 20
1142 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2)
1151 #define IWN_RSSI_TO_DBM 44
1153 /* Structure for IWN_RX_COMPRESSED_BA notification. */
1154 struct iwn_compressed_ba {
1155 uint8_t macaddr[IEEE80211_ADDR_LEN];
1165 /* Structure for IWN_START_SCAN notification. */
1166 struct iwn_start_scan {
1175 /* Structure for IWN_STOP_SCAN notification. */
1176 struct iwn_stop_scan {
1184 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
1185 struct iwn_spectrum_notif {
1190 #define IWN_MEASUREMENT_START 0
1191 #define IWN_MEASUREMENT_STOP 1
1202 uint8_t reserved2[3];
1207 #define IWN_MEASUREMENT_OK 0
1208 #define IWN_MEASUREMENT_CONCURRENT 1
1209 #define IWN_MEASUREMENT_CSA_CONFLICT 2
1210 #define IWN_MEASUREMENT_TGH_CONFLICT 3
1211 #define IWN_MEASUREMENT_STOPPED 6
1212 #define IWN_MEASUREMENT_TIMEOUT 7
1213 #define IWN_MEASUREMENT_FAILED 8
1216 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
1217 struct iwn_rx_phy_stats {
1224 uint32_t good_crc32;
1226 uint32_t bad_fina_sync;
1227 uint32_t sfd_timeout;
1228 uint32_t fina_timeout;
1229 uint32_t no_rts_ack;
1240 struct iwn_rx_general_stats {
1247 uint32_t missed_beacons;
1248 uint32_t adc_saturated; /* time in 0.8us */
1249 uint32_t ina_searched; /* time in 0.8us */
1258 struct iwn_rx_ht_phy_stats {
1262 uint32_t good_crc32;
1265 uint32_t good_ampdu_crc32;
1271 struct iwn_rx_stats {
1272 struct iwn_rx_phy_stats ofdm;
1273 struct iwn_rx_phy_stats cck;
1274 struct iwn_rx_general_stats general;
1275 struct iwn_rx_ht_phy_stats ht;
1278 struct iwn_tx_stats {
1280 uint32_t rx_detected;
1284 uint32_t cts_timeout;
1285 uint32_t ack_timeout;
1289 uint32_t busrt_err1;
1290 uint32_t burst_err2;
1291 uint32_t cts_collision;
1292 uint32_t ack_collision;
1293 uint32_t ba_timeout;
1294 uint32_t ba_resched;
1295 uint32_t query_ampdu;
1297 uint32_t query_ampdu_frag;
1298 uint32_t query_mismatch;
1301 uint32_t bt_ht_kill;
1302 uint32_t rx_ba_resp;
1303 uint32_t reserved[2];
1306 struct iwn_general_stats {
1309 uint32_t burst_check;
1311 uint32_t reserved1[4];
1315 uint32_t ttl_tstamp;
1320 uint32_t reserved2[2];
1321 uint32_t rx_enabled;
1322 uint32_t reserved3[3];
1327 struct iwn_rx_stats rx;
1328 struct iwn_tx_stats tx;
1329 struct iwn_general_stats general;
1333 /* Firmware error dump. */
1334 struct iwn_fw_dump {
1338 uint32_t branch_link[2];
1339 uint32_t interrupt_link[2];
1340 uint32_t error_data[2];
1346 /* TLV firmware header. */
1347 struct iwn_fw_tlv_hdr {
1348 uint32_t zero; /* Always 0, to differentiate from legacy. */
1350 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */
1354 #define IWN_FW_API(x) (((x) >> 8) & 0xff)
1363 #define IWN_FW_TLV_MAIN_TEXT 1
1364 #define IWN_FW_TLV_MAIN_DATA 2
1365 #define IWN_FW_TLV_INIT_TEXT 3
1366 #define IWN_FW_TLV_INIT_DATA 4
1367 #define IWN_FW_TLV_BOOT_TEXT 5
1368 #define IWN_FW_TLV_PBREQ_MAXLEN 6
1369 #define IWN_FW_TLV_ENH_SENS 14
1370 #define IWN_FW_TLV_PHY_CALIB 15
1376 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1377 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1378 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1379 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1380 #define IWN_FW_BOOT_TEXT_MAXSZ 1024
1381 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1382 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1385 * Offsets into EEPROM.
1387 #define IWN_EEPROM_MAC 0x015
1388 #define IWN_EEPROM_SKU_CAP 0x045
1389 #define IWN_EEPROM_RFCFG 0x048
1390 #define IWN4965_EEPROM_DOMAIN 0x060
1391 #define IWN4965_EEPROM_BAND1 0x063
1392 #define IWN5000_EEPROM_REG 0x066
1393 #define IWN5000_EEPROM_CAL 0x067
1394 #define IWN4965_EEPROM_BAND2 0x072
1395 #define IWN4965_EEPROM_BAND3 0x080
1396 #define IWN4965_EEPROM_BAND4 0x08d
1397 #define IWN4965_EEPROM_BAND5 0x099
1398 #define IWN4965_EEPROM_BAND6 0x0a0
1399 #define IWN4965_EEPROM_BAND7 0x0a8
1400 #define IWN4965_EEPROM_MAXPOW 0x0e8
1401 #define IWN4965_EEPROM_VOLTAGE 0x0e9
1402 #define IWN4965_EEPROM_BANDS 0x0ea
1403 /* Indirect offsets. */
1404 #define IWN5000_EEPROM_DOMAIN 0x001
1405 #define IWN5000_EEPROM_BAND1 0x004
1406 #define IWN5000_EEPROM_BAND2 0x013
1407 #define IWN5000_EEPROM_BAND3 0x021
1408 #define IWN5000_EEPROM_BAND4 0x02e
1409 #define IWN5000_EEPROM_BAND5 0x03a
1410 #define IWN5000_EEPROM_BAND6 0x041
1411 #define IWN6000_EEPROM_BAND6 0x040
1412 #define IWN5000_EEPROM_BAND7 0x049
1413 #define IWN6000_EEPROM_ENHINFO 0x054
1414 #define IWN5000_EEPROM_CRYSTAL 0x128
1415 #define IWN5000_EEPROM_TEMP 0x12a
1416 #define IWN5000_EEPROM_VOLT 0x12b
1418 /* Possible flags for IWN_EEPROM_SKU_CAP. */
1419 #define IWN_EEPROM_SKU_CAP_11N (1 << 6)
1420 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7)
1421 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8)
1423 /* Possible flags for IWN_EEPROM_RFCFG. */
1424 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1425 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1426 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1427 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1428 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1430 struct iwn_eeprom_chan {
1432 #define IWN_EEPROM_CHAN_VALID (1 << 0)
1433 #define IWN_EEPROM_CHAN_IBSS (1 << 1)
1434 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1435 #define IWN_EEPROM_CHAN_RADAR (1 << 4)
1440 struct iwn_eeprom_enhinfo {
1442 #define IWN_ENHINFO_VALID 0x01
1443 #define IWN_ENHINFO_5GHZ 0x02
1444 #define IWN_ENHINFO_OFDM 0x04
1445 #define IWN_ENHINFO_HT40 0x08
1446 #define IWN_ENHINFO_HTAP 0x10
1447 #define IWN_ENHINFO_RES1 0x20
1448 #define IWN_ENHINFO_RES2 0x40
1449 #define IWN_ENHINFO_COMMON 0x80
1452 int8_t chain[3]; /* max power in half-dBm */
1454 int8_t mimo2; /* max power in half-dBm */
1455 int8_t mimo3; /* max power in half-dBm */
1458 struct iwn5000_eeprom_calib_hdr {
1464 #define IWN_NSAMPLES 3
1465 struct iwn4965_eeprom_chan_samples {
1472 } samples[2][IWN_NSAMPLES];
1475 #define IWN_NBANDS 8
1476 struct iwn4965_eeprom_band {
1477 uint8_t lo; /* low channel number */
1478 uint8_t hi; /* high channel number */
1479 struct iwn4965_eeprom_chan_samples chans[2];
1483 * Offsets of channels descriptions in EEPROM.
1485 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
1486 IWN4965_EEPROM_BAND1,
1487 IWN4965_EEPROM_BAND2,
1488 IWN4965_EEPROM_BAND3,
1489 IWN4965_EEPROM_BAND4,
1490 IWN4965_EEPROM_BAND5,
1491 IWN4965_EEPROM_BAND6,
1492 IWN4965_EEPROM_BAND7
1495 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
1496 IWN5000_EEPROM_BAND1,
1497 IWN5000_EEPROM_BAND2,
1498 IWN5000_EEPROM_BAND3,
1499 IWN5000_EEPROM_BAND4,
1500 IWN5000_EEPROM_BAND5,
1501 IWN5000_EEPROM_BAND6,
1502 IWN5000_EEPROM_BAND7
1505 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = {
1506 IWN5000_EEPROM_BAND1,
1507 IWN5000_EEPROM_BAND2,
1508 IWN5000_EEPROM_BAND3,
1509 IWN5000_EEPROM_BAND4,
1510 IWN5000_EEPROM_BAND5,
1511 IWN6000_EEPROM_BAND6,
1512 IWN5000_EEPROM_BAND7
1515 #define IWN_CHAN_BANDS_COUNT 7
1516 #define IWN_MAX_CHAN_PER_BAND 14
1517 static const struct iwn_chan_band {
1519 uint8_t chan[IWN_MAX_CHAN_PER_BAND];
1521 /* 20MHz channels, 2GHz band. */
1522 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
1523 /* 20MHz channels, 5GHz band. */
1524 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
1525 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
1526 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1527 { 6, { 145, 149, 153, 157, 161, 165 } },
1528 /* 40MHz channels (primary channels), 2GHz band. */
1529 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1530 /* 40MHz channels (primary channels), 5GHz band. */
1531 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1534 #define IWN1000_OTP_NBLOCKS 3
1535 #define IWN6000_OTP_NBLOCKS 4
1536 #define IWN6050_OTP_NBLOCKS 7
1538 /* HW rate indices. */
1539 #define IWN_RIDX_CCK1 0
1540 #define IWN_RIDX_OFDM6 4
1542 #define IWN4965_MAX_PWR_INDEX 107
1545 * RF Tx gain values from highest to lowest power (values obtained from
1546 * the reference driver.)
1548 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1549 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
1550 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
1551 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
1552 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
1553 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
1554 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
1555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1561 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1562 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
1563 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
1564 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
1565 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
1566 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
1567 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
1568 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
1569 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
1570 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
1571 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1575 * DSP pre-DAC gain values from highest to lowest power (values obtained
1576 * from the reference driver.)
1578 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1579 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1580 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1581 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1582 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1583 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1584 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1585 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
1586 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
1587 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
1588 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
1591 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1592 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1593 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1594 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1595 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1596 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1597 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1598 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1599 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1600 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1601 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
1605 * Power saving settings (values obtained from the reference driver.)
1607 #define IWN_NDTIMRANGES 3
1608 #define IWN_NPOWERLEVELS 6
1609 static const struct iwn_pmgt {
1614 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
1617 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1618 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
1619 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
1620 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
1621 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */
1622 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */
1624 /* 3 <= DTIM <= 10 */
1626 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1627 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
1628 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
1629 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
1630 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */
1631 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */
1635 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1636 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
1637 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
1638 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
1639 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
1640 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
1644 struct iwn_sensitivity_limits {
1645 uint32_t min_ofdm_x1;
1646 uint32_t max_ofdm_x1;
1647 uint32_t min_ofdm_mrc_x1;
1648 uint32_t max_ofdm_mrc_x1;
1649 uint32_t min_ofdm_x4;
1650 uint32_t max_ofdm_x4;
1651 uint32_t min_ofdm_mrc_x4;
1652 uint32_t max_ofdm_mrc_x4;
1653 uint32_t min_cck_x4;
1654 uint32_t max_cck_x4;
1655 uint32_t min_cck_mrc_x4;
1656 uint32_t max_cck_mrc_x4;
1657 uint32_t min_energy_cck;
1658 uint32_t energy_cck;
1659 uint32_t energy_ofdm;
1663 * RX sensitivity limits (values obtained from the reference driver.)
1665 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
1677 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
1678 120, 120, /* min = max for performance bug in DSP. */
1679 240, 240, /* min = max for performance bug in DSP. */
1689 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
1690 105, 105, /* min = max for performance bug in DSP. */
1691 220, 220, /* min = max for performance bug in DSP. */
1701 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = {
1713 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
1725 /* Map TID to TX scheduler's FIFO. */
1726 static const uint8_t iwn_tid2fifo[] = {
1727 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1730 /* WiFi/WiMAX coexist event priority table for 6050. */
1731 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
1732 { 0x04, 0x03, 0x00, 0x00 },
1733 { 0x04, 0x03, 0x00, 0x03 },
1734 { 0x04, 0x03, 0x00, 0x03 },
1735 { 0x04, 0x03, 0x00, 0x03 },
1736 { 0x04, 0x03, 0x00, 0x00 },
1737 { 0x04, 0x03, 0x00, 0x07 },
1738 { 0x04, 0x03, 0x00, 0x00 },
1739 { 0x04, 0x03, 0x00, 0x03 },
1740 { 0x04, 0x03, 0x00, 0x03 },
1741 { 0x04, 0x03, 0x00, 0x00 },
1742 { 0x06, 0x03, 0x00, 0x07 },
1743 { 0x04, 0x03, 0x00, 0x00 },
1744 { 0x06, 0x06, 0x00, 0x03 },
1745 { 0x04, 0x03, 0x00, 0x07 },
1746 { 0x04, 0x03, 0x00, 0x00 },
1747 { 0x04, 0x03, 0x00, 0x00 }
1750 /* Firmware errors. */
1751 static const char * const iwn_fw_errmsg[] = {
1756 "NMI_INTERRUPT_WDG",
1760 "HW_ERROR_TUNE_LOCK",
1761 "HW_ERROR_TEMPERATURE",
1762 "ILLEGAL_CHAN_FREQ",
1765 "NMI_INTERRUPT_HOST",
1766 "NMI_INTERRUPT_ACTION_PT",
1767 "NMI_INTERRUPT_UNKNOWN",
1768 "UCODE_VERSION_MISMATCH",
1769 "HW_ERROR_ABS_LOCK",
1770 "HW_ERROR_CAL_LOCK_FAIL",
1771 "NMI_INTERRUPT_INST_ACTION_PT",
1772 "NMI_INTERRUPT_DATA_ACTION_PT",
1774 "NMI_INTERRUPT_TRM",
1775 "NMI_INTERRUPT_BREAKPOINT",
1780 "ADVANCED_SYSASSERT"
1783 /* Find least significant bit that is set. */
1784 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
1786 #define IWN_READ(sc, reg) \
1787 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
1789 #define IWN_WRITE(sc, reg, val) \
1790 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1792 #define IWN_WRITE_1(sc, reg, val) \
1793 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1795 #define IWN_SETBITS(sc, reg, mask) \
1796 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
1798 #define IWN_CLRBITS(sc, reg, mask) \
1799 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
1801 #define IWN_BARRIER_WRITE(sc) \
1802 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1803 BUS_SPACE_BARRIER_WRITE)
1805 #define IWN_BARRIER_READ_WRITE(sc) \
1806 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1807 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)