1 /*******************************************************************************
3 Copyright (c) 2001-2004, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 *******************************************************************************/
38 #include <dev/ixgb/if_ixgb_osdep.h>
47 /* Types of physical layer modules */
49 ixgb_phy_type_unknown = 0,
50 ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */
51 ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */
52 ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */
53 ixgb_phy_type_txn17401 /* 1310nm, SM fiber, XENPAK transceiver */
56 /* XPAK transceiver vendors, for the SR adapters */
58 ixgb_xpak_vendor_intel,
59 ixgb_xpak_vendor_infineon
64 ixgb_media_type_unknown = 0,
65 ixgb_media_type_fiber = 1,
69 /* Flow Control Settings */
75 ixgb_fc_default = 0xFF
80 ixgb_bus_type_unknown = 0,
87 ixgb_bus_speed_unknown = 0,
92 ixgb_bus_speed_reserved
97 ixgb_bus_width_unknown = 0,
103 #define IXGB_ETH_LENGTH_OF_ADDRESS 6
105 #define IXGB_EEPROM_SIZE 64 /* Size in words */
107 #define SPEED_10000 10000
108 #define FULL_DUPLEX 2
110 #define MIN_NUMBER_OF_DESCRIPTORS 8
111 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */
113 #define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */
114 #define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */
115 #define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */
117 #define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */
118 /* NOTE: this is MICROSECONDS */
119 #define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */
121 /* General Registers */
122 #define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */
123 #define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */
124 #define IXGB_STATUS 0x00010 /* Device Status Register - RO */
125 #define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */
126 #define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */
129 #define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */
130 #define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */
131 #define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */
132 #define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */
135 #define IXGB_RCTL 0x00100 /* RX Control - RW */
136 #define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */
137 #define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */
138 #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */
139 #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */
140 #define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */
141 #define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */
142 #define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */
143 #define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */
144 #define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */
145 #define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */
146 #define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */
147 #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */
148 #define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */
149 #define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */
150 #define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */
151 #define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */
152 #define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
155 #define IXGB_TCTL 0x00600 /* TX Control - RW */
156 #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */
157 #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */
158 #define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */
159 #define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */
160 #define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */
161 #define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */
162 #define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */
163 #define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */
164 #define IXGB_PAP 0x00640 /* Pause and Pace - RW */
165 #define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
168 #define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */
169 #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */
170 #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */
171 #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */
172 #define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */
173 #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */
174 #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */
175 #define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */
176 #define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */
177 #define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */
178 #define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */
179 #define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */
180 #define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */
183 #define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */
184 #define IXGB_WUS 0x00810 /* Wake Up Status - RO */
185 #define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */
186 #define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */
187 #define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */
190 #define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */
191 #define IXGB_TPRH 0x02004 /* Total Packets Received (High) */
192 #define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */
193 #define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */
194 #define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */
195 #define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */
196 #define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */
197 #define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */
198 #define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */
199 #define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */
200 #define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */
201 #define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */
202 #define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */
203 #define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */
204 #define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */
205 #define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */
206 #define IXGB_TORL 0x02040 /* Total Octets Received (Low) */
207 #define IXGB_TORH 0x02044 /* Total Octets Received (High) */
208 #define IXGB_RNBC 0x02048 /* Receive No Buffers Count */
209 #define IXGB_RUC 0x02050 /* Receive Undersize Count */
210 #define IXGB_ROC 0x02058 /* Receive Oversize Count */
211 #define IXGB_RLEC 0x02060 /* Receive Length Error Count */
212 #define IXGB_CRCERRS 0x02068 /* CRC Error Count */
213 #define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */
214 #define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */
215 #define IXGB_MPC 0x02080 /* Missed Packets Count */
216 #define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */
217 #define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */
218 #define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */
219 #define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */
220 #define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */
221 #define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */
222 #define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */
223 #define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */
224 #define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */
225 #define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */
226 #define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */
227 #define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */
228 #define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */
229 #define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */
230 #define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */
231 #define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */
232 #define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */
233 #define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */
234 #define IXGB_DC 0x02148 /* Defer Count */
235 #define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */
236 #define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */
237 #define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */
238 #define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */
239 #define IXGB_RFC 0x02188 /* Remote Fault Count */
240 #define IXGB_LFC 0x02190 /* Local Fault Count */
241 #define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */
242 #define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */
243 #define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */
244 #define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */
245 #define IXGB_XONRXC 0x021B8 /* XON Received Count */
246 #define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */
247 #define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */
248 #define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */
249 #define IXGB_RJC 0x021D8 /* Receive Jabber Count */
252 /* CTRL0 Bit Masks */
253 #define IXGB_CTRL0_LRST 0x00000008
254 #define IXGB_CTRL0_JFE 0x00000010
255 #define IXGB_CTRL0_XLE 0x00000020
256 #define IXGB_CTRL0_MDCS 0x00000040
257 #define IXGB_CTRL0_CMDC 0x00000080
258 #define IXGB_CTRL0_SDP0 0x00040000
259 #define IXGB_CTRL0_SDP1 0x00080000
260 #define IXGB_CTRL0_SDP2 0x00100000
261 #define IXGB_CTRL0_SDP3 0x00200000
262 #define IXGB_CTRL0_SDP0_DIR 0x00400000
263 #define IXGB_CTRL0_SDP1_DIR 0x00800000
264 #define IXGB_CTRL0_SDP2_DIR 0x01000000
265 #define IXGB_CTRL0_SDP3_DIR 0x02000000
266 #define IXGB_CTRL0_RST 0x04000000
267 #define IXGB_CTRL0_RPE 0x08000000
268 #define IXGB_CTRL0_TPE 0x10000000
269 #define IXGB_CTRL0_VME 0x40000000
271 /* CTRL1 Bit Masks */
272 #define IXGB_CTRL1_GPI0_EN 0x00000001
273 #define IXGB_CTRL1_GPI1_EN 0x00000002
274 #define IXGB_CTRL1_GPI2_EN 0x00000004
275 #define IXGB_CTRL1_GPI3_EN 0x00000008
276 #define IXGB_CTRL1_SDP4 0x00000010
277 #define IXGB_CTRL1_SDP5 0x00000020
278 #define IXGB_CTRL1_SDP6 0x00000040
279 #define IXGB_CTRL1_SDP7 0x00000080
280 #define IXGB_CTRL1_SDP4_DIR 0x00000100
281 #define IXGB_CTRL1_SDP5_DIR 0x00000200
282 #define IXGB_CTRL1_SDP6_DIR 0x00000400
283 #define IXGB_CTRL1_SDP7_DIR 0x00000800
284 #define IXGB_CTRL1_EE_RST 0x00002000
285 #define IXGB_CTRL1_RO_DIS 0x00020000
286 #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
287 #define IXGB_CTRL1_PCIXHM_1_2 0x00000000
288 #define IXGB_CTRL1_PCIXHM_5_8 0x00400000
289 #define IXGB_CTRL1_PCIXHM_3_4 0x00800000
290 #define IXGB_CTRL1_PCIXHM_7_8 0x00C00000
292 /* STATUS Bit Masks */
293 #define IXGB_STATUS_LU 0x00000002
294 #define IXGB_STATUS_AIP 0x00000004
295 #define IXGB_STATUS_TXOFF 0x00000010
296 #define IXGB_STATUS_XAUIME 0x00000020
297 #define IXGB_STATUS_RES 0x00000040
298 #define IXGB_STATUS_RIS 0x00000080
299 #define IXGB_STATUS_RIE 0x00000100
300 #define IXGB_STATUS_RLF 0x00000200
301 #define IXGB_STATUS_RRF 0x00000400
302 #define IXGB_STATUS_PCI_SPD 0x00000800
303 #define IXGB_STATUS_BUS64 0x00001000
304 #define IXGB_STATUS_PCIX_MODE 0x00002000
305 #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
306 #define IXGB_STATUS_PCIX_SPD_66 0x00000000
307 #define IXGB_STATUS_PCIX_SPD_100 0x00004000
308 #define IXGB_STATUS_PCIX_SPD_133 0x00008000
309 #define IXGB_STATUS_REV_ID_MASK 0x000F0000
310 #define IXGB_STATUS_REV_ID_SHIFT 16
313 #define IXGB_EECD_SK 0x00000001
314 #define IXGB_EECD_CS 0x00000002
315 #define IXGB_EECD_DI 0x00000004
316 #define IXGB_EECD_DO 0x00000008
317 #define IXGB_EECD_FWE_MASK 0x00000030
318 #define IXGB_EECD_FWE_DIS 0x00000010
319 #define IXGB_EECD_FWE_EN 0x00000020
322 #define IXGB_MFS_SHIFT 16
324 /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
325 #define IXGB_INT_TXDW 0x00000001
326 #define IXGB_INT_TXQE 0x00000002
327 #define IXGB_INT_LSC 0x00000004
328 #define IXGB_INT_RXSEQ 0x00000008
329 #define IXGB_INT_RXDMT0 0x00000010
330 #define IXGB_INT_RXO 0x00000040
331 #define IXGB_INT_RXT0 0x00000080
332 #define IXGB_INT_AUTOSCAN 0x00000200
333 #define IXGB_INT_GPI0 0x00000800
334 #define IXGB_INT_GPI1 0x00001000
335 #define IXGB_INT_GPI2 0x00002000
336 #define IXGB_INT_GPI3 0x00004000
339 #define IXGB_RCTL_RXEN 0x00000002
340 #define IXGB_RCTL_SBP 0x00000004
341 #define IXGB_RCTL_UPE 0x00000008
342 #define IXGB_RCTL_MPE 0x00000010
343 #define IXGB_RCTL_RDMTS_MASK 0x00000300
344 #define IXGB_RCTL_RDMTS_1_2 0x00000000
345 #define IXGB_RCTL_RDMTS_1_4 0x00000100
346 #define IXGB_RCTL_RDMTS_1_8 0x00000200
347 #define IXGB_RCTL_MO_MASK 0x00003000
348 #define IXGB_RCTL_MO_47_36 0x00000000
349 #define IXGB_RCTL_MO_46_35 0x00001000
350 #define IXGB_RCTL_MO_45_34 0x00002000
351 #define IXGB_RCTL_MO_43_32 0x00003000
352 #define IXGB_RCTL_MO_SHIFT 12
353 #define IXGB_RCTL_BAM 0x00008000
354 #define IXGB_RCTL_BSIZE_MASK 0x00030000
355 #define IXGB_RCTL_BSIZE_2048 0x00000000
356 #define IXGB_RCTL_BSIZE_4096 0x00010000
357 #define IXGB_RCTL_BSIZE_8192 0x00020000
358 #define IXGB_RCTL_BSIZE_16384 0x00030000
359 #define IXGB_RCTL_VFE 0x00040000
360 #define IXGB_RCTL_CFIEN 0x00080000
361 #define IXGB_RCTL_CFI 0x00100000
362 #define IXGB_RCTL_RPDA_MASK 0x00600000
363 #define IXGB_RCTL_RPDA_MC_MAC 0x00000000
364 #define IXGB_RCTL_MC_ONLY 0x00400000
365 #define IXGB_RCTL_CFF 0x00800000
366 #define IXGB_RCTL_SECRC 0x04000000
367 #define IXGB_RDT_FPDB 0x80000000
369 #define IXGB_RCTL_IDLE_RX_UNIT 0
371 /* FCRTL Bit Masks */
372 #define IXGB_FCRTL_XONE 0x80000000
374 /* RXDCTL Bit Masks */
375 #define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF
376 #define IXGB_RXDCTL_PTHRESH_SHIFT 0
377 #define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00
378 #define IXGB_RXDCTL_HTHRESH_SHIFT 9
379 #define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000
380 #define IXGB_RXDCTL_WTHRESH_SHIFT 18
382 /* RAIDC Bit Masks */
383 #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
384 #define IXGB_RAIDC_DELAY_MASK 0x000FF800
385 #define IXGB_RAIDC_DELAY_SHIFT 11
386 #define IXGB_RAIDC_POLL_MASK 0x1FF00000
387 #define IXGB_RAIDC_POLL_SHIFT 20
388 #define IXGB_RAIDC_RXT_GATE 0x40000000
389 #define IXGB_RAIDC_EN 0x80000000
391 #define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220
392 #define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244
393 #define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122
394 #define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61
396 /* RXCSUM Bit Masks */
397 #define IXGB_RXCSUM_IPOFL 0x00000100
398 #define IXGB_RXCSUM_TUOFL 0x00000200
401 #define IXGB_RAH_ASEL_MASK 0x00030000
402 #define IXGB_RAH_ASEL_DEST 0x00000000
403 #define IXGB_RAH_ASEL_SRC 0x00010000
404 #define IXGB_RAH_AV 0x80000000
407 #define IXGB_TCTL_TCE 0x00000001
408 #define IXGB_TCTL_TXEN 0x00000002
409 #define IXGB_TCTL_TPDE 0x00000004
411 #define IXGB_TCTL_IDLE_TX_UNIT 0
413 /* TXDCTL Bit Masks */
414 #define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F
415 #define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00
416 #define IXGB_TXDCTL_HTHRESH_SHIFT 8
417 #define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000
418 #define IXGB_TXDCTL_WTHRESH_SHIFT 16
420 /* TSPMT Bit Masks */
421 #define IXGB_TSPMT_TSMT_MASK 0x0000FFFF
422 #define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000
423 #define IXGB_TSPMT_TSPBP_SHIFT 16
426 #define IXGB_PAP_TXPC_MASK 0x0000FFFF
427 #define IXGB_PAP_TXPV_MASK 0x000F0000
428 #define IXGB_PAP_TXPV_10G 0x00000000
429 #define IXGB_PAP_TXPV_1G 0x00010000
430 #define IXGB_PAP_TXPV_2G 0x00020000
431 #define IXGB_PAP_TXPV_3G 0x00030000
432 #define IXGB_PAP_TXPV_4G 0x00040000
433 #define IXGB_PAP_TXPV_5G 0x00050000
434 #define IXGB_PAP_TXPV_6G 0x00060000
435 #define IXGB_PAP_TXPV_7G 0x00070000
436 #define IXGB_PAP_TXPV_8G 0x00080000
437 #define IXGB_PAP_TXPV_9G 0x00090000
438 #define IXGB_PAP_TXPV_WAN 0x000F0000
440 /* PCSC1 Bit Masks */
441 #define IXGB_PCSC1_LOOPBACK 0x00004000
443 /* PCSC2 Bit Masks */
444 #define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003
445 #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
447 /* PCSS1 Bit Masks */
448 #define IXGB_PCSS1_LOCAL_FAULT 0x00000080
449 #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
451 /* PCSS2 Bit Masks */
452 #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
453 #define IXGB_PCSS2_DEV_PRES 0x00004000
454 #define IXGB_PCSS2_TX_LF 0x00000800
455 #define IXGB_PCSS2_RX_LF 0x00000400
456 #define IXGB_PCSS2_10GBW 0x00000004
457 #define IXGB_PCSS2_10GBX 0x00000002
458 #define IXGB_PCSS2_10GBR 0x00000001
460 /* XPCSS Bit Masks */
461 #define IXGB_XPCSS_ALIGN_STATUS 0x00001000
462 #define IXGB_XPCSS_PATTERN_TEST 0x00000800
463 #define IXGB_XPCSS_LANE_3_SYNC 0x00000008
464 #define IXGB_XPCSS_LANE_2_SYNC 0x00000004
465 #define IXGB_XPCSS_LANE_1_SYNC 0x00000002
466 #define IXGB_XPCSS_LANE_0_SYNC 0x00000001
468 /* XPCSTC Bit Masks */
469 #define IXGB_XPCSTC_BERT_TRIG 0x00200000
470 #define IXGB_XPCSTC_BERT_SST 0x00100000
471 #define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000
472 #define IXGB_XPCSTC_BERT_PSZ_SHIFT 17
473 #define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003
474 #define IXGB_XPCSTC_BERT_PSZ_68 0x00000001
475 #define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000
478 /* New Protocol Address */
479 #define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF
480 #define IXGB_MSCA_NP_ADDR_SHIFT 0
481 /* Either Device Type or Register Address,depending on ST_CODE */
482 #define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000
483 #define IXGB_MSCA_DEV_TYPE_SHIFT 16
484 #define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000
485 #define IXGB_MSCA_PHY_ADDR_SHIFT 21
486 #define IXGB_MSCA_OP_CODE_MASK 0x0C000000
487 /* OP_CODE == 00, Address cycle, New Protocol */
488 /* OP_CODE == 01, Write operation */
489 /* OP_CODE == 10, Read operation */
490 /* OP_CODE == 11, Read, auto increment, New Protocol */
491 #define IXGB_MSCA_ADDR_CYCLE 0x00000000
492 #define IXGB_MSCA_WRITE 0x04000000
493 #define IXGB_MSCA_READ 0x08000000
494 #define IXGB_MSCA_READ_AUTOINC 0x0C000000
495 #define IXGB_MSCA_OP_CODE_SHIFT 26
496 #define IXGB_MSCA_ST_CODE_MASK 0x30000000
497 /* ST_CODE == 00, New Protocol */
498 /* ST_CODE == 01, Old Protocol */
499 #define IXGB_MSCA_NEW_PROTOCOL 0x00000000
500 #define IXGB_MSCA_OLD_PROTOCOL 0x10000000
501 #define IXGB_MSCA_ST_CODE_SHIFT 28
502 /* Initiate command, self-clearing when command completes */
503 #define IXGB_MSCA_MDI_COMMAND 0x40000000
504 /*MDI In Progress Enable. */
505 #define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000
507 /* MSRWD bit masks */
508 #define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF
509 #define IXGB_MSRWD_WRITE_DATA_SHIFT 0
510 #define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000
511 #define IXGB_MSRWD_READ_DATA_SHIFT 16
513 /* Definitions for the optics devices on the MDIO bus. */
514 #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */
516 /* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */
517 #define MDIO_PMA_PMD_DID 0x01
518 #define MDIO_WIS_DID 0x02
519 #define MDIO_PCS_DID 0x03
520 #define MDIO_XGXS_DID 0x04
522 /* Standard PMA/PMD registers and bit definitions. */
523 /* Note: This is a very limited set of definitions, */
524 /* only implemented features are defined. */
525 #define MDIO_PMA_PMD_CR1 0x0000
526 #define MDIO_PMA_PMD_CR1_RESET 0x8000
528 #define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */
530 /* Vendor-specific MDIO registers */
531 #define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */
532 #define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */
534 #define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80
535 #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00
536 #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */
538 /* Layout of a single receive descriptor. The controller assumes that this
539 * structure is packed into 16 bytes, which is a safe assumption with most
540 * compilers. However, some compilers may insert padding between the fields,
541 * in which case the structure must be packed in some compiler-specific
543 struct ixgb_rx_desc {
552 #define IXGB_RX_DESC_STATUS_DD 0x01
553 #define IXGB_RX_DESC_STATUS_EOP 0x02
554 #define IXGB_RX_DESC_STATUS_IXSM 0x04
555 #define IXGB_RX_DESC_STATUS_VP 0x08
556 #define IXGB_RX_DESC_STATUS_TCPCS 0x20
557 #define IXGB_RX_DESC_STATUS_IPCS 0x40
558 #define IXGB_RX_DESC_STATUS_PIF 0x80
560 #define IXGB_RX_DESC_ERRORS_CE 0x01
561 #define IXGB_RX_DESC_ERRORS_SE 0x02
562 #define IXGB_RX_DESC_ERRORS_P 0x08
563 #define IXGB_RX_DESC_ERRORS_TCPE 0x20
564 #define IXGB_RX_DESC_ERRORS_IPE 0x40
565 #define IXGB_RX_DESC_ERRORS_RXE 0x80
567 #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
568 #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
569 #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
571 /* Layout of a single transmit descriptor. The controller assumes that this
572 * structure is packed into 16 bytes, which is a safe assumption with most
573 * compilers. However, some compilers may insert padding between the fields,
574 * in which case the structure must be packed in some compiler-specific
576 struct ixgb_tx_desc {
578 uint32_t cmd_type_len;
584 #define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF
585 #define IXGB_TX_DESC_TYPE_MASK 0x00F00000
586 #define IXGB_TX_DESC_TYPE_SHIFT 20
587 #define IXGB_TX_DESC_CMD_MASK 0xFF000000
588 #define IXGB_TX_DESC_CMD_SHIFT 24
589 #define IXGB_TX_DESC_CMD_EOP 0x01000000
590 #define IXGB_TX_DESC_CMD_TSE 0x04000000
591 #define IXGB_TX_DESC_CMD_RS 0x08000000
592 #define IXGB_TX_DESC_CMD_VLE 0x40000000
593 #define IXGB_TX_DESC_CMD_IDE 0x80000000
595 #define IXGB_TX_DESC_TYPE 0x00100000
597 #define IXGB_TX_DESC_STATUS_DD 0x01
599 #define IXGB_TX_DESC_POPTS_IXSM 0x01
600 #define IXGB_TX_DESC_POPTS_TXSM 0x02
601 #define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */
603 struct ixgb_context_desc {
610 uint32_t cmd_type_len;
616 #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
617 #define IXGB_CONTEXT_DESC_CMD_IP 0x02000000
618 #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
619 #define IXGB_CONTEXT_DESC_CMD_RS 0x08000000
620 #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
622 #define IXGB_CONTEXT_DESC_TYPE 0x00000000
624 #define IXGB_CONTEXT_DESC_STATUS_DD 0x01
627 #define IXGB_RAR_ENTRIES 16 /* Number of entries in Rx Address array */
628 #define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
629 #define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
631 #define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0
632 #define ENET_HEADER_SIZE 14
633 #define ENET_FCS_LENGTH 4
634 #define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128
635 #define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60
636 #define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514
637 #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00
640 #define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address*/
641 #define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address*/
642 #define IXGB_DIAG_PHY_ADDR 0x1F/* Diagnostic Device phy address*/
644 /* This structure takes a 64k flash and maps it for identification commands */
645 struct ixgb_flash_buffer {
646 uint8_t manufacturer_id;
648 uint8_t filler1[0x2AA8];
650 uint8_t filler2[0x2AAA];
652 uint8_t filler3[0xAAAA];
656 * This is a little-endian specific check.
658 #define IS_MULTICAST(Address) \
659 (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
663 * Check whether an address is broadcast.
665 #define IS_BROADCAST(Address) \
666 ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
668 /* Flow control parameters */
670 uint32_t high_water; /* Flow Control High-water */
671 uint32_t low_water; /* Flow Control Low-water */
672 uint16_t pause_time; /* Flow Control Pause timer */
673 boolean_t send_xon; /* Flow control send XON */
674 ixgb_fc_type type; /* Type of flow control */
677 /* The historical defaults for the flow control values are given below. */
678 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
679 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
680 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
682 /* Phy definitions */
683 #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF
684 #define IXGB_MAX_PHY_ADDRESS 31
685 #define IXGB_MAX_PHY_DEV_TYPE 31
689 ixgb_bus_speed speed;
690 ixgb_bus_width width;
695 uint8_t *hw_addr; /* Base Address of the hardware */
696 void *back; /* Pointer to OS-dependent struct */
697 struct ixgb_fc fc; /* Flow control parameters */
698 struct ixgb_bus bus; /* Bus parameters */
699 uint32_t phy_id; /* Phy Identifier */
700 uint32_t phy_addr; /* XGMII address of Phy */
701 ixgb_mac_type mac_type; /* Identifier for MAC controller */
702 ixgb_phy_type phy_type; /* Transceiver/phy identifier */
703 uint32_t max_frame_size; /* Maximum frame size supported */
704 uint32_t mc_filter_type; /* Multicast filter hash type */
705 uint32_t num_mc_addrs; /* Number of current Multicast addrs*/
706 uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */
707 uint32_t num_tx_desc; /* Number of Transmit descriptors */
708 uint32_t num_rx_desc; /* Number of Receive descriptors */
709 uint32_t rx_buffer_size; /* Size of Receive buffer */
710 boolean_t link_up; /* TRUE if link is valid */
711 boolean_t adapter_stopped; /* State of adapter */
712 uint16_t device_id; /* device id from PCI configuration space */
713 uint16_t vendor_id; /* vendor id from PCI configuration space */
714 uint8_t revision_id; /* revision id from PCI configuration space */
715 uint16_t subsystem_vendor_id;/* subsystem vendor id from PCI configuration space */
716 uint16_t subsystem_id; /* subsystem id from PCI configuration space */
717 uint32_t bar0; /* Base Address registers */
721 uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */
722 uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */
723 unsigned long io_base; /* Our I/O mapped location */
728 /* Statistics reported by the hardware */
729 struct ixgb_hw_stats {
792 /* Function Prototypes */
793 extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
794 extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
795 extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
796 extern void ixgb_init_rx_addrs(struct ixgb_hw *hw);
797 extern void ixgb_check_for_link(struct ixgb_hw *hw);
798 extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
799 extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
800 extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
801 extern boolean_t mac_addr_valid(uint8_t *mac_addr);
803 extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw,
806 uint32_t device_type);
808 extern void ixgb_write_phy_reg(struct ixgb_hw *hw,
811 uint32_t device_type,
814 extern void ixgb_rar_set(struct ixgb_hw *hw,
819 /* Filters (multicast, vlan, receive) */
820 extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw,
821 uint8_t * mc_addr_list,
822 uint32_t mc_addr_count,
826 extern void ixgb_write_vfta(struct ixgb_hw *hw,
830 extern void ixgb_clear_vfta(struct ixgb_hw *hw);
833 /* Access functions to eeprom data */
834 void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
835 uint16_t ixgb_get_ee_compatibility(struct ixgb_hw *hw);
836 uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
837 uint16_t ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw);
838 uint16_t ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw);
839 uint16_t ixgb_get_ee_subsystem_id(struct ixgb_hw *hw);
840 uint16_t ixgb_get_ee_subvendor_id(struct ixgb_hw *hw);
841 uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
842 uint16_t ixgb_get_ee_vendor_id(struct ixgb_hw *hw);
843 uint16_t ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw);
844 uint8_t ixgb_get_ee_d3_power(struct ixgb_hw *hw);
845 uint8_t ixgb_get_ee_d0_power(struct ixgb_hw *hw);
846 boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
847 uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);
849 /* Everything else */
850 void ixgb_led_on(struct ixgb_hw *hw);
851 void ixgb_led_off(struct ixgb_hw *hw);
852 void ixgb_write_pci_cfg(struct ixgb_hw *hw,
857 #endif /* _IXGB_HW_H_ */