1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
41 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed *speed,
45 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
47 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
50 ixgbe_link_speed *speed, bool *link_up,
51 bool link_up_wait_to_complete);
52 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
53 ixgbe_link_speed speed,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
61 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
62 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
63 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
64 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
65 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
66 u32 vind, bool vlan_on);
67 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
68 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
69 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
70 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
72 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
73 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
74 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
75 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
78 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
79 * @hw: pointer to the HW structure
81 * The defaults for 82598 should be in the range of 50us to 50ms,
82 * however the hardware default for these parts is 500us to 1ms which is less
83 * than the 10ms recommended by the pci-e spec. To address this we need to
84 * increase the value to either 10ms to 250ms for capability version 1 config,
85 * or 16ms to 55ms for version 2.
87 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
89 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
92 /* only take action if timeout value is defaulted to 0 */
93 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
97 * if capababilities version is type 1 we can write the
98 * timeout of 10ms to 250ms through the GCR register
100 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
101 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
106 * for version 2 capabilities we need to write the config space
107 * directly in order to set the completion timeout value for
110 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
111 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
112 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
114 /* disable completion timeout resend */
115 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
116 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
120 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
121 * @hw: pointer to hardware structure
123 * Read PCIe configuration space, and get the MSI-X vector count from
124 * the capabilities table.
126 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
130 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
132 if (hw->mac.msix_vectors_from_pcie) {
133 msix_count = IXGBE_READ_PCIE_WORD(hw,
134 IXGBE_PCIE_MSIX_82598_CAPS);
135 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
137 /* MSI-X count is zero-based in HW, so increment to give
145 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
146 * @hw: pointer to hardware structure
148 * Initialize the function pointers and assign the MAC type for 82598.
149 * Does not touch the hardware.
151 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
153 struct ixgbe_mac_info *mac = &hw->mac;
154 struct ixgbe_phy_info *phy = &hw->phy;
157 DEBUGFUNC("ixgbe_init_ops_82598");
159 ret_val = ixgbe_init_phy_ops_generic(hw);
160 ret_val = ixgbe_init_ops_generic(hw);
163 phy->ops.init = &ixgbe_init_phy_ops_82598;
166 mac->ops.start_hw = &ixgbe_start_hw_82598;
167 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
168 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
169 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
170 mac->ops.get_supported_physical_layer =
171 &ixgbe_get_supported_physical_layer_82598;
172 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
173 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
174 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
176 /* RAR, Multicast, VLAN */
177 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
178 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
179 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
180 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
183 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
185 mac->mcft_size = 128;
187 mac->num_rar_entries = 16;
188 mac->rx_pb_size = 512;
189 mac->max_tx_queues = 32;
190 mac->max_rx_queues = 64;
191 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
194 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
197 mac->ops.check_link = &ixgbe_check_mac_link_82598;
198 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
199 mac->ops.flap_tx_laser = NULL;
200 mac->ops.get_link_capabilities =
201 &ixgbe_get_link_capabilities_82598;
207 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
208 * @hw: pointer to hardware structure
210 * Initialize any function pointers that were not able to be
211 * set during init_shared_code because the PHY/SFP type was
212 * not known. Perform the SFP init if necessary.
215 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
217 struct ixgbe_mac_info *mac = &hw->mac;
218 struct ixgbe_phy_info *phy = &hw->phy;
219 s32 ret_val = IXGBE_SUCCESS;
220 u16 list_offset, data_offset;
222 DEBUGFUNC("ixgbe_init_phy_ops_82598");
224 /* Identify the PHY */
225 phy->ops.identify(hw);
227 /* Overwrite the link function pointers if copper PHY */
228 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
229 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
230 mac->ops.get_link_capabilities =
231 &ixgbe_get_copper_link_capabilities_generic;
234 switch (hw->phy.type) {
236 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
237 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
238 phy->ops.get_firmware_version =
239 &ixgbe_get_phy_firmware_version_tnx;
242 phy->ops.get_firmware_version =
243 &ixgbe_get_phy_firmware_version_generic;
246 phy->ops.reset = &ixgbe_reset_phy_nl;
248 /* Call SFP+ identify routine to get the SFP+ module type */
249 ret_val = phy->ops.identify_sfp(hw);
250 if (ret_val != IXGBE_SUCCESS)
252 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
253 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
257 /* Check to see if SFP+ module is supported */
258 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
261 if (ret_val != IXGBE_SUCCESS) {
262 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
275 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
276 * @hw: pointer to hardware structure
278 * Starts the hardware using the generic start_hw function.
279 * Disables relaxed ordering Then set pcie completion timeout
282 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
286 s32 ret_val = IXGBE_SUCCESS;
288 DEBUGFUNC("ixgbe_start_hw_82598");
290 ret_val = ixgbe_start_hw_generic(hw);
292 /* Disable relaxed ordering */
293 for (i = 0; ((i < hw->mac.max_tx_queues) &&
294 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
295 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
296 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
297 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
300 for (i = 0; ((i < hw->mac.max_rx_queues) &&
301 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
302 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
303 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
304 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
305 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
308 /* set the completion timeout for interface */
309 if (ret_val == IXGBE_SUCCESS)
310 ixgbe_set_pcie_completion_timeout(hw);
316 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
317 * @hw: pointer to hardware structure
318 * @speed: pointer to link speed
319 * @autoneg: boolean auto-negotiation value
321 * Determines the link capabilities by reading the AUTOC register.
323 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
324 ixgbe_link_speed *speed,
327 s32 status = IXGBE_SUCCESS;
330 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
333 * Determine link capabilities based on the stored value of AUTOC,
334 * which represents EEPROM defaults. If AUTOC value has not been
335 * stored, use the current register value.
337 if (hw->mac.orig_link_settings_stored)
338 autoc = hw->mac.orig_autoc;
340 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
342 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
343 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
344 *speed = IXGBE_LINK_SPEED_1GB_FULL;
348 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
349 *speed = IXGBE_LINK_SPEED_10GB_FULL;
353 case IXGBE_AUTOC_LMS_1G_AN:
354 *speed = IXGBE_LINK_SPEED_1GB_FULL;
358 case IXGBE_AUTOC_LMS_KX4_AN:
359 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
360 *speed = IXGBE_LINK_SPEED_UNKNOWN;
361 if (autoc & IXGBE_AUTOC_KX4_SUPP)
362 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
363 if (autoc & IXGBE_AUTOC_KX_SUPP)
364 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
369 status = IXGBE_ERR_LINK_SETUP;
377 * ixgbe_get_media_type_82598 - Determines media type
378 * @hw: pointer to hardware structure
380 * Returns the media type (fiber, copper, backplane)
382 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
384 enum ixgbe_media_type media_type;
386 DEBUGFUNC("ixgbe_get_media_type_82598");
388 /* Detect if there is a copper PHY attached. */
389 switch (hw->phy.type) {
390 case ixgbe_phy_cu_unknown:
393 media_type = ixgbe_media_type_copper;
399 /* Media type for I82598 is based on device ID */
400 switch (hw->device_id) {
401 case IXGBE_DEV_ID_82598:
402 case IXGBE_DEV_ID_82598_BX:
403 /* Default device ID is mezzanine card KX/KX4 */
404 media_type = ixgbe_media_type_backplane;
406 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
407 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
408 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
409 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
410 case IXGBE_DEV_ID_82598EB_XF_LR:
411 case IXGBE_DEV_ID_82598EB_SFP_LOM:
412 media_type = ixgbe_media_type_fiber;
414 case IXGBE_DEV_ID_82598EB_CX4:
415 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
416 media_type = ixgbe_media_type_cx4;
418 case IXGBE_DEV_ID_82598AT:
419 case IXGBE_DEV_ID_82598AT2:
420 media_type = ixgbe_media_type_copper;
423 media_type = ixgbe_media_type_unknown;
431 * ixgbe_fc_enable_82598 - Enable flow control
432 * @hw: pointer to hardware structure
433 * @packetbuf_num: packet buffer number (0-7)
435 * Enable flow control according to the current settings.
437 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
439 s32 ret_val = IXGBE_SUCCESS;
447 DEBUGFUNC("ixgbe_fc_enable_82598");
450 * On 82598 having Rx FC on causes resets while doing 1G
451 * so if it's on turn it off once we know link_speed. For
452 * more details see 82598 Specification update.
454 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
455 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
456 switch (hw->fc.requested_mode) {
458 hw->fc.requested_mode = ixgbe_fc_tx_pause;
460 case ixgbe_fc_rx_pause:
461 hw->fc.requested_mode = ixgbe_fc_none;
469 /* Negotiate the fc mode to use */
470 ret_val = ixgbe_fc_autoneg(hw);
471 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
474 /* Disable any previous flow control settings */
475 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
476 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
478 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
479 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
482 * The possible values of fc.current_mode are:
483 * 0: Flow control is completely disabled
484 * 1: Rx flow control is enabled (we can receive pause frames,
485 * but not send pause frames).
486 * 2: Tx flow control is enabled (we can send pause frames but
487 * we do not support receiving pause frames).
488 * 3: Both Rx and Tx flow control (symmetric) are enabled.
491 switch (hw->fc.current_mode) {
494 * Flow control is disabled by software override or autoneg.
495 * The code below will actually disable it in the HW.
498 case ixgbe_fc_rx_pause:
500 * Rx Flow control is enabled and Tx Flow control is
501 * disabled by software override. Since there really
502 * isn't a way to advertise that we are capable of RX
503 * Pause ONLY, we will advertise that we support both
504 * symmetric and asymmetric Rx PAUSE. Later, we will
505 * disable the adapter's ability to send PAUSE frames.
507 fctrl_reg |= IXGBE_FCTRL_RFCE;
509 case ixgbe_fc_tx_pause:
511 * Tx Flow control is enabled, and Rx Flow control is
512 * disabled by software override.
514 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
517 /* Flow control (both Rx and Tx) is enabled by SW override. */
518 fctrl_reg |= IXGBE_FCTRL_RFCE;
519 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
522 DEBUGOUT("Flow control param set incorrectly\n");
523 ret_val = IXGBE_ERR_CONFIG;
528 /* Set 802.3x based flow control settings. */
529 fctrl_reg |= IXGBE_FCTRL_DPF;
530 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
531 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
533 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
534 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
535 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
536 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
538 reg = (rx_pba_size - hw->fc.low_water) << 6;
540 reg |= IXGBE_FCRTL_XONE;
542 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
544 reg = (rx_pba_size - hw->fc.high_water) << 6;
545 reg |= IXGBE_FCRTH_FCEN;
547 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
550 /* Configure pause time (2 TCs per register) */
551 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
552 if ((packetbuf_num & 1) == 0)
553 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
555 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
556 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
558 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
565 * ixgbe_start_mac_link_82598 - Configures MAC link settings
566 * @hw: pointer to hardware structure
568 * Configures link settings based on values in the ixgbe_hw struct.
569 * Restarts the link. Performs autonegotiation if needed.
571 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
572 bool autoneg_wait_to_complete)
577 s32 status = IXGBE_SUCCESS;
579 DEBUGFUNC("ixgbe_start_mac_link_82598");
582 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
583 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
584 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
586 /* Only poll for autoneg to complete if specified to do so */
587 if (autoneg_wait_to_complete) {
588 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
589 IXGBE_AUTOC_LMS_KX4_AN ||
590 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
591 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
592 links_reg = 0; /* Just in case Autoneg time = 0 */
593 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
594 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
595 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
599 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
600 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
601 DEBUGOUT("Autonegotiation did not complete.\n");
606 /* Add delay to filter out noises during initial link setup */
613 * ixgbe_validate_link_ready - Function looks for phy link
614 * @hw: pointer to hardware structure
616 * Function indicates success when phy link is available. If phy is not ready
617 * within 5 seconds of MAC indicating link, the function returns error.
619 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
624 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
625 return IXGBE_SUCCESS;
628 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
629 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
630 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
632 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
633 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
639 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
640 DEBUGOUT("Link was indicated but link is down\n");
641 return IXGBE_ERR_LINK_SETUP;
644 return IXGBE_SUCCESS;
648 * ixgbe_check_mac_link_82598 - Get link/speed status
649 * @hw: pointer to hardware structure
650 * @speed: pointer to link speed
651 * @link_up: TRUE is link is up, FALSE otherwise
652 * @link_up_wait_to_complete: bool used to wait for link up or not
654 * Reads the links register to determine if link is up and the current speed
656 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
657 ixgbe_link_speed *speed, bool *link_up,
658 bool link_up_wait_to_complete)
662 u16 link_reg, adapt_comp_reg;
664 DEBUGFUNC("ixgbe_check_mac_link_82598");
667 * SERDES PHY requires us to read link status from undocumented
668 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
669 * indicates link down. OxC00C is read to check that the XAUI lanes
670 * are active. Bit 0 clear indicates active; set indicates inactive.
672 if (hw->phy.type == ixgbe_phy_nl) {
673 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
674 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
675 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
677 if (link_up_wait_to_complete) {
678 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
679 if ((link_reg & 1) &&
680 ((adapt_comp_reg & 1) == 0)) {
687 hw->phy.ops.read_reg(hw, 0xC79F,
690 hw->phy.ops.read_reg(hw, 0xC00C,
695 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
701 if (*link_up == FALSE)
705 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
706 if (link_up_wait_to_complete) {
707 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
708 if (links_reg & IXGBE_LINKS_UP) {
715 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
718 if (links_reg & IXGBE_LINKS_UP)
724 if (links_reg & IXGBE_LINKS_SPEED)
725 *speed = IXGBE_LINK_SPEED_10GB_FULL;
727 *speed = IXGBE_LINK_SPEED_1GB_FULL;
729 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
730 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
733 /* if link is down, zero out the current_mode */
734 if (*link_up == FALSE) {
735 hw->fc.current_mode = ixgbe_fc_none;
736 hw->fc.fc_was_autonegged = FALSE;
739 return IXGBE_SUCCESS;
743 * ixgbe_setup_mac_link_82598 - Set MAC link speed
744 * @hw: pointer to hardware structure
745 * @speed: new link speed
746 * @autoneg: TRUE if autonegotiation enabled
747 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
749 * Set the link speed in the AUTOC register and restarts link.
751 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
752 ixgbe_link_speed speed, bool autoneg,
753 bool autoneg_wait_to_complete)
755 s32 status = IXGBE_SUCCESS;
756 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
757 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
758 u32 autoc = curr_autoc;
759 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
761 DEBUGFUNC("ixgbe_setup_mac_link_82598");
763 /* Check to see if speed passed in is supported. */
764 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
765 speed &= link_capabilities;
767 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
768 status = IXGBE_ERR_LINK_SETUP;
770 /* Set KX4/KX support according to speed requested */
771 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
772 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
773 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
774 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
775 autoc |= IXGBE_AUTOC_KX4_SUPP;
776 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
777 autoc |= IXGBE_AUTOC_KX_SUPP;
778 if (autoc != curr_autoc)
779 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
782 if (status == IXGBE_SUCCESS) {
784 * Setup and restart the link based on the new values in
785 * ixgbe_hw This will write the AUTOC register based on the new
788 status = ixgbe_start_mac_link_82598(hw,
789 autoneg_wait_to_complete);
797 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
798 * @hw: pointer to hardware structure
799 * @speed: new link speed
800 * @autoneg: TRUE if autonegotiation enabled
801 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
803 * Sets the link speed in the AUTOC register in the MAC and restarts link.
805 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
806 ixgbe_link_speed speed,
808 bool autoneg_wait_to_complete)
812 DEBUGFUNC("ixgbe_setup_copper_link_82598");
814 /* Setup the PHY according to input speed */
815 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
816 autoneg_wait_to_complete);
818 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
824 * ixgbe_reset_hw_82598 - Performs hardware reset
825 * @hw: pointer to hardware structure
827 * Resets the hardware by resetting the transmit and receive units, masks and
828 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
831 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
833 s32 status = IXGBE_SUCCESS;
834 s32 phy_status = IXGBE_SUCCESS;
841 DEBUGFUNC("ixgbe_reset_hw_82598");
843 /* Call adapter stop to disable tx/rx and clear interrupts */
844 hw->mac.ops.stop_adapter(hw);
847 * Power up the Atlas Tx lanes if they are currently powered down.
848 * Atlas Tx lanes are powered down for MAC loopback tests, but
849 * they are not automatically restored on reset.
851 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
852 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
853 /* Enable Tx Atlas so packets can be transmitted again */
854 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
856 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
857 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
860 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
862 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
863 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
866 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
868 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
869 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
872 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
874 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
875 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
880 if (hw->phy.reset_disable == FALSE) {
881 /* PHY ops must be identified and initialized prior to reset */
883 /* Init PHY and function pointers, perform SFP setup */
884 phy_status = hw->phy.ops.init(hw);
885 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
887 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
890 hw->phy.ops.reset(hw);
895 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
896 * access and verify no pending requests before reset
898 ixgbe_disable_pcie_master(hw);
902 * Issue global reset to the MAC. This needs to be a SW reset.
903 * If link reset is used, it might reset the MAC when mng is using it
905 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
906 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
907 IXGBE_WRITE_FLUSH(hw);
909 /* Poll for reset bit to self-clear indicating reset is complete */
910 for (i = 0; i < 10; i++) {
912 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
913 if (!(ctrl & IXGBE_CTRL_RST))
916 if (ctrl & IXGBE_CTRL_RST) {
917 status = IXGBE_ERR_RESET_FAILED;
918 DEBUGOUT("Reset polling failed to complete.\n");
922 * Double resets are required for recovery from certain error
923 * conditions. Between resets, it is necessary to stall to allow time
924 * for any pending HW events to complete. We use 1usec since that is
925 * what is needed for ixgbe_disable_pcie_master(). The second reset
926 * then clears out any effects of those events.
928 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
929 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
936 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
937 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
938 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
941 * Store the original AUTOC value if it has not been
942 * stored off yet. Otherwise restore the stored original
943 * AUTOC value since the reset operation sets back to deaults.
945 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
946 if (hw->mac.orig_link_settings_stored == FALSE) {
947 hw->mac.orig_autoc = autoc;
948 hw->mac.orig_link_settings_stored = TRUE;
949 } else if (autoc != hw->mac.orig_autoc) {
950 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
953 /* Store the permanent mac address */
954 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
957 * Store MAC address from RAR0, clear receive address registers, and
958 * clear the multicast table
960 hw->mac.ops.init_rx_addrs(hw);
963 if (phy_status != IXGBE_SUCCESS)
970 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
971 * @hw: pointer to hardware struct
972 * @rar: receive address register index to associate with a VMDq index
973 * @vmdq: VMDq set index
975 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
978 u32 rar_entries = hw->mac.num_rar_entries;
980 DEBUGFUNC("ixgbe_set_vmdq_82598");
982 /* Make sure we are using a valid rar index range */
983 if (rar >= rar_entries) {
984 DEBUGOUT1("RAR index %d is out of range.\n", rar);
985 return IXGBE_ERR_INVALID_ARGUMENT;
988 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
989 rar_high &= ~IXGBE_RAH_VIND_MASK;
990 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
991 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
992 return IXGBE_SUCCESS;
996 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
997 * @hw: pointer to hardware struct
998 * @rar: receive address register index to associate with a VMDq index
999 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
1001 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1004 u32 rar_entries = hw->mac.num_rar_entries;
1006 UNREFERENCED_PARAMETER(vmdq);
1008 /* Make sure we are using a valid rar index range */
1009 if (rar >= rar_entries) {
1010 DEBUGOUT1("RAR index %d is out of range.\n", rar);
1011 return IXGBE_ERR_INVALID_ARGUMENT;
1014 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
1015 if (rar_high & IXGBE_RAH_VIND_MASK) {
1016 rar_high &= ~IXGBE_RAH_VIND_MASK;
1017 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
1020 return IXGBE_SUCCESS;
1024 * ixgbe_set_vfta_82598 - Set VLAN filter table
1025 * @hw: pointer to hardware structure
1026 * @vlan: VLAN id to write to VLAN filter
1027 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1028 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1030 * Turn on/off specified VLAN in the VLAN filter table.
1032 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1040 DEBUGFUNC("ixgbe_set_vfta_82598");
1043 return IXGBE_ERR_PARAM;
1045 /* Determine 32-bit word position in array */
1046 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1048 /* Determine the location of the (VMD) queue index */
1049 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1050 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1052 /* Set the nibble for VMD queue index */
1053 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
1054 bits &= (~(0x0F << bitindex));
1055 bits |= (vind << bitindex);
1056 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
1058 /* Determine the location of the bit for this VLAN id */
1059 bitindex = vlan & 0x1F; /* lower five bits */
1061 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1063 /* Turn on this VLAN id */
1064 bits |= (1 << bitindex);
1066 /* Turn off this VLAN id */
1067 bits &= ~(1 << bitindex);
1068 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1070 return IXGBE_SUCCESS;
1074 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1075 * @hw: pointer to hardware structure
1077 * Clears the VLAN filer table, and the VMDq index associated with the filter
1079 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1084 DEBUGFUNC("ixgbe_clear_vfta_82598");
1086 for (offset = 0; offset < hw->mac.vft_size; offset++)
1087 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1089 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1090 for (offset = 0; offset < hw->mac.vft_size; offset++)
1091 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1094 return IXGBE_SUCCESS;
1098 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1099 * @hw: pointer to hardware structure
1100 * @reg: analog register to read
1103 * Performs read operation to Atlas analog register specified.
1105 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1109 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1111 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1112 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1113 IXGBE_WRITE_FLUSH(hw);
1115 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1116 *val = (u8)atlas_ctl;
1118 return IXGBE_SUCCESS;
1122 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1123 * @hw: pointer to hardware structure
1124 * @reg: atlas register to write
1125 * @val: value to write
1127 * Performs write operation to Atlas analog register specified.
1129 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1133 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1135 atlas_ctl = (reg << 8) | val;
1136 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1137 IXGBE_WRITE_FLUSH(hw);
1140 return IXGBE_SUCCESS;
1144 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1145 * @hw: pointer to hardware structure
1146 * @byte_offset: EEPROM byte offset to read
1147 * @eeprom_data: value read
1149 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1151 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1154 s32 status = IXGBE_SUCCESS;
1160 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1162 if (hw->phy.type == ixgbe_phy_nl) {
1164 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1165 * 0xC30D. These registers are used to talk to the SFP+
1166 * module's EEPROM through the SDA/SCL (I2C) interface.
1168 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1169 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1170 hw->phy.ops.write_reg(hw,
1171 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1172 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1176 for (i = 0; i < 100; i++) {
1177 hw->phy.ops.read_reg(hw,
1178 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1179 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1181 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1182 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1187 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1188 DEBUGOUT("EEPROM read did not pass.\n");
1189 status = IXGBE_ERR_SFP_NOT_PRESENT;
1194 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1195 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1197 *eeprom_data = (u8)(sfp_data >> 8);
1199 status = IXGBE_ERR_PHY;
1208 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1209 * @hw: pointer to hardware structure
1211 * Determines physical layer capabilities of the current configuration.
1213 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1215 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1216 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1217 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1218 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1219 u16 ext_ability = 0;
1221 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1223 hw->phy.ops.identify(hw);
1225 /* Copper PHY must be checked before AUTOC LMS to determine correct
1226 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1227 switch (hw->phy.type) {
1230 case ixgbe_phy_cu_unknown:
1231 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1232 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1233 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1234 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1235 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1236 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1237 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1238 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1244 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1245 case IXGBE_AUTOC_LMS_1G_AN:
1246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1247 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1248 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1250 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1252 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1253 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1254 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1255 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1256 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1258 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1260 case IXGBE_AUTOC_LMS_KX4_AN:
1261 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1262 if (autoc & IXGBE_AUTOC_KX_SUPP)
1263 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1264 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1265 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1271 if (hw->phy.type == ixgbe_phy_nl) {
1272 hw->phy.ops.identify_sfp(hw);
1274 switch (hw->phy.sfp_type) {
1275 case ixgbe_sfp_type_da_cu:
1276 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1278 case ixgbe_sfp_type_sr:
1279 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1281 case ixgbe_sfp_type_lr:
1282 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1285 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1290 switch (hw->device_id) {
1291 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1292 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1294 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1295 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1296 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1297 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1299 case IXGBE_DEV_ID_82598EB_XF_LR:
1300 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1307 return physical_layer;
1311 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1313 * @hw: pointer to the HW structure
1315 * Calls common function and corrects issue with some single port devices
1316 * that enable LAN1 but not LAN0.
1318 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1320 struct ixgbe_bus_info *bus = &hw->bus;
1324 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1326 ixgbe_set_lan_id_multi_port_pcie(hw);
1328 /* check if LAN0 is disabled */
1329 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1330 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1332 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1334 /* if LAN0 is completely disabled force function to 0 */
1335 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1336 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1337 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1345 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1346 * @hw: pointer to hardware structure
1349 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1354 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1356 /* Enable relaxed ordering */
1357 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1358 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1359 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1360 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1361 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1364 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1365 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1366 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1367 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
1368 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
1369 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);