1 /******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_dcb.h"
38 #include "ixgbe_dcb_82599.h"
39 #include "ixgbe_api.h"
41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = prot_autoc_write_generic;
113 mac->ops.led_on = ixgbe_led_on_generic;
114 mac->ops.led_off = ixgbe_led_off_generic;
115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = ixgbe_set_rar_generic;
120 mac->ops.clear_rar = ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = ixgbe_fc_enable_generic;
138 mac->ops.setup_fc = ixgbe_setup_fc_generic;
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
148 return IXGBE_SUCCESS;
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
154 * @hw: pointer to hardware structure
156 * This function returns TRUE if the device supports flow control
157 * autonegotiation, and FALSE if it does not.
160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
162 bool supported = FALSE;
163 ixgbe_link_speed speed;
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_fixed:
170 case ixgbe_media_type_fiber_qsfp:
171 case ixgbe_media_type_fiber:
172 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
173 /* if link is down, assume supported */
175 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
180 case ixgbe_media_type_backplane:
183 case ixgbe_media_type_copper:
184 /* only some copper devices support flow control autoneg */
185 switch (hw->device_id) {
186 case IXGBE_DEV_ID_82599_T3_LOM:
187 case IXGBE_DEV_ID_X540T:
188 case IXGBE_DEV_ID_X540T1:
189 case IXGBE_DEV_ID_X540_BYPASS:
190 case IXGBE_DEV_ID_X550T:
191 case IXGBE_DEV_ID_X550T1:
192 case IXGBE_DEV_ID_X550EM_X_10G_T:
203 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
204 "Device %x does not support flow control autoneg",
212 * ixgbe_setup_fc_generic - Set up flow control
213 * @hw: pointer to hardware structure
215 * Called at init time to set up flow control.
217 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
219 s32 ret_val = IXGBE_SUCCESS;
220 u32 reg = 0, reg_bp = 0;
224 DEBUGFUNC("ixgbe_setup_fc_generic");
226 /* Validate the requested mode */
227 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
228 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
229 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
230 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
235 * 10gig parts do not have a word in the EEPROM to determine the
236 * default flow control setting, so we explicitly set it to full.
238 if (hw->fc.requested_mode == ixgbe_fc_default)
239 hw->fc.requested_mode = ixgbe_fc_full;
242 * Set up the 1G and 10G flow control advertisement registers so the
243 * HW will be able to do fc autoneg once the cable is plugged in. If
244 * we link at 10G, the 1G advertisement is harmless and vice versa.
246 switch (hw->phy.media_type) {
247 case ixgbe_media_type_backplane:
248 /* some MAC's need RMW protection on AUTOC */
249 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
250 if (ret_val != IXGBE_SUCCESS)
253 /* only backplane uses autoc so fall though */
254 case ixgbe_media_type_fiber_fixed:
255 case ixgbe_media_type_fiber_qsfp:
256 case ixgbe_media_type_fiber:
257 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
260 case ixgbe_media_type_copper:
261 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
262 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
269 * The possible values of fc.requested_mode are:
270 * 0: Flow control is completely disabled
271 * 1: Rx flow control is enabled (we can receive pause frames,
272 * but not send pause frames).
273 * 2: Tx flow control is enabled (we can send pause frames but
274 * we do not support receiving pause frames).
275 * 3: Both Rx and Tx flow control (symmetric) are enabled.
278 switch (hw->fc.requested_mode) {
280 /* Flow control completely disabled by software override. */
281 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
282 if (hw->phy.media_type == ixgbe_media_type_backplane)
283 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
284 IXGBE_AUTOC_ASM_PAUSE);
285 else if (hw->phy.media_type == ixgbe_media_type_copper)
286 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
288 case ixgbe_fc_tx_pause:
290 * Tx Flow control is enabled, and Rx Flow control is
291 * disabled by software override.
293 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
294 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
295 if (hw->phy.media_type == ixgbe_media_type_backplane) {
296 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
297 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
298 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
299 reg_cu |= IXGBE_TAF_ASM_PAUSE;
300 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
303 case ixgbe_fc_rx_pause:
305 * Rx Flow control is enabled and Tx Flow control is
306 * disabled by software override. Since there really
307 * isn't a way to advertise that we are capable of RX
308 * Pause ONLY, we will advertise that we support both
309 * symmetric and asymmetric Rx PAUSE, as such we fall
310 * through to the fc_full statement. Later, we will
311 * disable the adapter's ability to send PAUSE frames.
314 /* Flow control (both Rx and Tx) is enabled by SW override. */
315 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
316 if (hw->phy.media_type == ixgbe_media_type_backplane)
317 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
318 IXGBE_AUTOC_ASM_PAUSE;
319 else if (hw->phy.media_type == ixgbe_media_type_copper)
320 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
323 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
324 "Flow control param set incorrectly\n");
325 ret_val = IXGBE_ERR_CONFIG;
330 if (hw->mac.type < ixgbe_mac_X540) {
332 * Enable auto-negotiation between the MAC & PHY;
333 * the MAC will advertise clause 37 flow control.
335 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
336 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
338 /* Disable AN timeout */
339 if (hw->fc.strict_ieee)
340 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
342 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
343 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
347 * AUTOC restart handles negotiation of 1G and 10G on backplane
348 * and copper. There is no need to set the PCS1GCTL register.
351 if (hw->phy.media_type == ixgbe_media_type_backplane) {
352 reg_bp |= IXGBE_AUTOC_AN_RESTART;
353 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
356 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
357 (ixgbe_device_supports_autoneg_fc(hw))) {
358 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
359 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
362 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
368 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
369 * @hw: pointer to hardware structure
371 * Starts the hardware by filling the bus info structure and media type, clears
372 * all on chip counters, initializes receive address registers, multicast
373 * table, VLAN filter table, calls routine to set up link and flow control
374 * settings, and leaves transmit and receive units disabled and uninitialized
376 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
381 DEBUGFUNC("ixgbe_start_hw_generic");
383 /* Set the media type */
384 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
386 /* PHY ops initialization must be done in reset_hw() */
388 /* Clear the VLAN filter table */
389 hw->mac.ops.clear_vfta(hw);
391 /* Clear statistics registers */
392 hw->mac.ops.clear_hw_cntrs(hw);
394 /* Set No Snoop Disable */
395 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
396 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
397 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
398 IXGBE_WRITE_FLUSH(hw);
400 /* Setup flow control */
401 ret_val = ixgbe_setup_fc(hw);
402 if (ret_val != IXGBE_SUCCESS)
405 /* Clear adapter stopped flag */
406 hw->adapter_stopped = FALSE;
413 * ixgbe_start_hw_gen2 - Init sequence for common device family
414 * @hw: pointer to hw structure
416 * Performs the init sequence common to the second generation
418 * Devices in the second generation:
422 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
427 /* Clear the rate limiters */
428 for (i = 0; i < hw->mac.max_tx_queues; i++) {
429 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
430 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
432 IXGBE_WRITE_FLUSH(hw);
434 /* Disable relaxed ordering */
435 for (i = 0; i < hw->mac.max_tx_queues; i++) {
436 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
437 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
438 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
441 for (i = 0; i < hw->mac.max_rx_queues; i++) {
442 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
443 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
444 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
445 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
448 return IXGBE_SUCCESS;
452 * ixgbe_init_hw_generic - Generic hardware initialization
453 * @hw: pointer to hardware structure
455 * Initialize the hardware by resetting the hardware, filling the bus info
456 * structure and media type, clears all on chip counters, initializes receive
457 * address registers, multicast table, VLAN filter table, calls routine to set
458 * up link and flow control settings, and leaves transmit and receive units
459 * disabled and uninitialized
461 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
465 DEBUGFUNC("ixgbe_init_hw_generic");
467 /* Reset the hardware */
468 status = hw->mac.ops.reset_hw(hw);
470 if (status == IXGBE_SUCCESS) {
472 status = hw->mac.ops.start_hw(hw);
479 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
480 * @hw: pointer to hardware structure
482 * Clears all hardware statistics counters by reading them from the hardware
483 * Statistics counters are clear on read.
485 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
489 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
491 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
492 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
493 IXGBE_READ_REG(hw, IXGBE_ERRBC);
494 IXGBE_READ_REG(hw, IXGBE_MSPDC);
495 for (i = 0; i < 8; i++)
496 IXGBE_READ_REG(hw, IXGBE_MPC(i));
498 IXGBE_READ_REG(hw, IXGBE_MLFC);
499 IXGBE_READ_REG(hw, IXGBE_MRFC);
500 IXGBE_READ_REG(hw, IXGBE_RLEC);
501 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
502 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
503 if (hw->mac.type >= ixgbe_mac_82599EB) {
504 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
505 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
507 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
508 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
511 for (i = 0; i < 8; i++) {
512 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
513 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
514 if (hw->mac.type >= ixgbe_mac_82599EB) {
515 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
516 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
518 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
519 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
522 if (hw->mac.type >= ixgbe_mac_82599EB)
523 for (i = 0; i < 8; i++)
524 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
525 IXGBE_READ_REG(hw, IXGBE_PRC64);
526 IXGBE_READ_REG(hw, IXGBE_PRC127);
527 IXGBE_READ_REG(hw, IXGBE_PRC255);
528 IXGBE_READ_REG(hw, IXGBE_PRC511);
529 IXGBE_READ_REG(hw, IXGBE_PRC1023);
530 IXGBE_READ_REG(hw, IXGBE_PRC1522);
531 IXGBE_READ_REG(hw, IXGBE_GPRC);
532 IXGBE_READ_REG(hw, IXGBE_BPRC);
533 IXGBE_READ_REG(hw, IXGBE_MPRC);
534 IXGBE_READ_REG(hw, IXGBE_GPTC);
535 IXGBE_READ_REG(hw, IXGBE_GORCL);
536 IXGBE_READ_REG(hw, IXGBE_GORCH);
537 IXGBE_READ_REG(hw, IXGBE_GOTCL);
538 IXGBE_READ_REG(hw, IXGBE_GOTCH);
539 if (hw->mac.type == ixgbe_mac_82598EB)
540 for (i = 0; i < 8; i++)
541 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
542 IXGBE_READ_REG(hw, IXGBE_RUC);
543 IXGBE_READ_REG(hw, IXGBE_RFC);
544 IXGBE_READ_REG(hw, IXGBE_ROC);
545 IXGBE_READ_REG(hw, IXGBE_RJC);
546 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
547 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
548 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
549 IXGBE_READ_REG(hw, IXGBE_TORL);
550 IXGBE_READ_REG(hw, IXGBE_TORH);
551 IXGBE_READ_REG(hw, IXGBE_TPR);
552 IXGBE_READ_REG(hw, IXGBE_TPT);
553 IXGBE_READ_REG(hw, IXGBE_PTC64);
554 IXGBE_READ_REG(hw, IXGBE_PTC127);
555 IXGBE_READ_REG(hw, IXGBE_PTC255);
556 IXGBE_READ_REG(hw, IXGBE_PTC511);
557 IXGBE_READ_REG(hw, IXGBE_PTC1023);
558 IXGBE_READ_REG(hw, IXGBE_PTC1522);
559 IXGBE_READ_REG(hw, IXGBE_MPTC);
560 IXGBE_READ_REG(hw, IXGBE_BPTC);
561 for (i = 0; i < 16; i++) {
562 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
563 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
564 if (hw->mac.type >= ixgbe_mac_82599EB) {
565 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
566 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
567 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
568 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
569 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
571 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
572 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
576 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
578 ixgbe_identify_phy(hw);
579 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
580 IXGBE_MDIO_PCS_DEV_TYPE, &i);
581 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
582 IXGBE_MDIO_PCS_DEV_TYPE, &i);
583 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
584 IXGBE_MDIO_PCS_DEV_TYPE, &i);
585 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
586 IXGBE_MDIO_PCS_DEV_TYPE, &i);
589 return IXGBE_SUCCESS;
593 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
594 * @hw: pointer to hardware structure
595 * @pba_num: stores the part number string from the EEPROM
596 * @pba_num_size: part number string buffer length
598 * Reads the part number string from the EEPROM.
600 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
609 DEBUGFUNC("ixgbe_read_pba_string_generic");
611 if (pba_num == NULL) {
612 DEBUGOUT("PBA string buffer was null\n");
613 return IXGBE_ERR_INVALID_ARGUMENT;
616 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
618 DEBUGOUT("NVM Read Error\n");
622 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
624 DEBUGOUT("NVM Read Error\n");
629 * if data is not ptr guard the PBA must be in legacy format which
630 * means pba_ptr is actually our second data word for the PBA number
631 * and we can decode it into an ascii string
633 if (data != IXGBE_PBANUM_PTR_GUARD) {
634 DEBUGOUT("NVM PBA number is not stored as string\n");
636 /* we will need 11 characters to store the PBA */
637 if (pba_num_size < 11) {
638 DEBUGOUT("PBA string buffer too small\n");
639 return IXGBE_ERR_NO_SPACE;
642 /* extract hex string from data and pba_ptr */
643 pba_num[0] = (data >> 12) & 0xF;
644 pba_num[1] = (data >> 8) & 0xF;
645 pba_num[2] = (data >> 4) & 0xF;
646 pba_num[3] = data & 0xF;
647 pba_num[4] = (pba_ptr >> 12) & 0xF;
648 pba_num[5] = (pba_ptr >> 8) & 0xF;
651 pba_num[8] = (pba_ptr >> 4) & 0xF;
652 pba_num[9] = pba_ptr & 0xF;
654 /* put a null character on the end of our string */
657 /* switch all the data but the '-' to hex char */
658 for (offset = 0; offset < 10; offset++) {
659 if (pba_num[offset] < 0xA)
660 pba_num[offset] += '0';
661 else if (pba_num[offset] < 0x10)
662 pba_num[offset] += 'A' - 0xA;
665 return IXGBE_SUCCESS;
668 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
670 DEBUGOUT("NVM Read Error\n");
674 if (length == 0xFFFF || length == 0) {
675 DEBUGOUT("NVM PBA number section invalid length\n");
676 return IXGBE_ERR_PBA_SECTION;
679 /* check if pba_num buffer is big enough */
680 if (pba_num_size < (((u32)length * 2) - 1)) {
681 DEBUGOUT("PBA string buffer too small\n");
682 return IXGBE_ERR_NO_SPACE;
685 /* trim pba length from start of string */
689 for (offset = 0; offset < length; offset++) {
690 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
692 DEBUGOUT("NVM Read Error\n");
695 pba_num[offset * 2] = (u8)(data >> 8);
696 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
698 pba_num[offset * 2] = '\0';
700 return IXGBE_SUCCESS;
704 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
705 * @hw: pointer to hardware structure
706 * @pba_num: stores the part number from the EEPROM
708 * Reads the part number from the EEPROM.
710 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
715 DEBUGFUNC("ixgbe_read_pba_num_generic");
717 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
719 DEBUGOUT("NVM Read Error\n");
721 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
722 DEBUGOUT("NVM Not supported\n");
723 return IXGBE_NOT_IMPLEMENTED;
725 *pba_num = (u32)(data << 16);
727 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
729 DEBUGOUT("NVM Read Error\n");
734 return IXGBE_SUCCESS;
739 * @hw: pointer to the HW structure
740 * @eeprom_buf: optional pointer to EEPROM image
741 * @eeprom_buf_size: size of EEPROM image in words
742 * @max_pba_block_size: PBA block size limit
743 * @pba: pointer to output PBA structure
745 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
746 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
749 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
750 u32 eeprom_buf_size, u16 max_pba_block_size,
751 struct ixgbe_pba *pba)
757 return IXGBE_ERR_PARAM;
759 if (eeprom_buf == NULL) {
760 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
765 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
766 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
767 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
769 return IXGBE_ERR_PARAM;
773 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
774 if (pba->pba_block == NULL)
775 return IXGBE_ERR_PARAM;
777 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
783 if (pba_block_size > max_pba_block_size)
784 return IXGBE_ERR_PARAM;
786 if (eeprom_buf == NULL) {
787 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
793 if (eeprom_buf_size > (u32)(pba->word[1] +
795 memcpy(pba->pba_block,
796 &eeprom_buf[pba->word[1]],
797 pba_block_size * sizeof(u16));
799 return IXGBE_ERR_PARAM;
804 return IXGBE_SUCCESS;
808 * ixgbe_write_pba_raw
809 * @hw: pointer to the HW structure
810 * @eeprom_buf: optional pointer to EEPROM image
811 * @eeprom_buf_size: size of EEPROM image in words
812 * @pba: pointer to PBA structure
814 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
815 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
818 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
819 u32 eeprom_buf_size, struct ixgbe_pba *pba)
824 return IXGBE_ERR_PARAM;
826 if (eeprom_buf == NULL) {
827 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
832 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
833 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
834 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
836 return IXGBE_ERR_PARAM;
840 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
841 if (pba->pba_block == NULL)
842 return IXGBE_ERR_PARAM;
844 if (eeprom_buf == NULL) {
845 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
851 if (eeprom_buf_size > (u32)(pba->word[1] +
852 pba->pba_block[0])) {
853 memcpy(&eeprom_buf[pba->word[1]],
855 pba->pba_block[0] * sizeof(u16));
857 return IXGBE_ERR_PARAM;
862 return IXGBE_SUCCESS;
866 * ixgbe_get_pba_block_size
867 * @hw: pointer to the HW structure
868 * @eeprom_buf: optional pointer to EEPROM image
869 * @eeprom_buf_size: size of EEPROM image in words
870 * @pba_data_size: pointer to output variable
872 * Returns the size of the PBA block in words. Function operates on EEPROM
873 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
877 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
878 u32 eeprom_buf_size, u16 *pba_block_size)
884 DEBUGFUNC("ixgbe_get_pba_block_size");
886 if (eeprom_buf == NULL) {
887 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
892 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
893 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
894 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
896 return IXGBE_ERR_PARAM;
900 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
901 if (eeprom_buf == NULL) {
902 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
907 if (eeprom_buf_size > pba_word[1])
908 length = eeprom_buf[pba_word[1] + 0];
910 return IXGBE_ERR_PARAM;
913 if (length == 0xFFFF || length == 0)
914 return IXGBE_ERR_PBA_SECTION;
916 /* PBA number in legacy format, there is no PBA Block. */
920 if (pba_block_size != NULL)
921 *pba_block_size = length;
923 return IXGBE_SUCCESS;
927 * ixgbe_get_mac_addr_generic - Generic get MAC address
928 * @hw: pointer to hardware structure
929 * @mac_addr: Adapter MAC address
931 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
932 * A reset of the adapter must be performed prior to calling this function
933 * in order for the MAC address to have been loaded from the EEPROM into RAR0
935 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
941 DEBUGFUNC("ixgbe_get_mac_addr_generic");
943 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
944 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
946 for (i = 0; i < 4; i++)
947 mac_addr[i] = (u8)(rar_low >> (i*8));
949 for (i = 0; i < 2; i++)
950 mac_addr[i+4] = (u8)(rar_high >> (i*8));
952 return IXGBE_SUCCESS;
956 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
957 * @hw: pointer to hardware structure
958 * @link_status: the link status returned by the PCI config space
960 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
962 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
964 struct ixgbe_mac_info *mac = &hw->mac;
966 if (hw->bus.type == ixgbe_bus_type_unknown)
967 hw->bus.type = ixgbe_bus_type_pci_express;
969 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
970 case IXGBE_PCI_LINK_WIDTH_1:
971 hw->bus.width = ixgbe_bus_width_pcie_x1;
973 case IXGBE_PCI_LINK_WIDTH_2:
974 hw->bus.width = ixgbe_bus_width_pcie_x2;
976 case IXGBE_PCI_LINK_WIDTH_4:
977 hw->bus.width = ixgbe_bus_width_pcie_x4;
979 case IXGBE_PCI_LINK_WIDTH_8:
980 hw->bus.width = ixgbe_bus_width_pcie_x8;
983 hw->bus.width = ixgbe_bus_width_unknown;
987 switch (link_status & IXGBE_PCI_LINK_SPEED) {
988 case IXGBE_PCI_LINK_SPEED_2500:
989 hw->bus.speed = ixgbe_bus_speed_2500;
991 case IXGBE_PCI_LINK_SPEED_5000:
992 hw->bus.speed = ixgbe_bus_speed_5000;
994 case IXGBE_PCI_LINK_SPEED_8000:
995 hw->bus.speed = ixgbe_bus_speed_8000;
998 hw->bus.speed = ixgbe_bus_speed_unknown;
1002 mac->ops.set_lan_id(hw);
1006 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1007 * @hw: pointer to hardware structure
1009 * Gets the PCI bus info (speed, width, type) then calls helper function to
1010 * store this data within the ixgbe_hw structure.
1012 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1016 DEBUGFUNC("ixgbe_get_bus_info_generic");
1018 /* Get the negotiated link width and speed from PCI config space */
1019 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1021 ixgbe_set_pci_config_data_generic(hw, link_status);
1023 return IXGBE_SUCCESS;
1027 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1028 * @hw: pointer to the HW structure
1030 * Determines the LAN function id by reading memory-mapped registers
1031 * and swaps the port value if requested.
1033 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1035 struct ixgbe_bus_info *bus = &hw->bus;
1038 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1040 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1041 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1042 bus->lan_id = bus->func;
1044 /* check for a port swap */
1045 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1046 if (reg & IXGBE_FACTPS_LFS)
1051 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1052 * @hw: pointer to hardware structure
1054 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1055 * disables transmit and receive units. The adapter_stopped flag is used by
1056 * the shared code and drivers to determine if the adapter is in a stopped
1057 * state and should not touch the hardware.
1059 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1064 DEBUGFUNC("ixgbe_stop_adapter_generic");
1067 * Set the adapter_stopped flag so other driver functions stop touching
1070 hw->adapter_stopped = TRUE;
1072 /* Disable the receive unit */
1073 ixgbe_disable_rx(hw);
1075 /* Clear interrupt mask to stop interrupts from being generated */
1076 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1078 /* Clear any pending interrupts, flush previous writes */
1079 IXGBE_READ_REG(hw, IXGBE_EICR);
1081 /* Disable the transmit unit. Each queue must be disabled. */
1082 for (i = 0; i < hw->mac.max_tx_queues; i++)
1083 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1085 /* Disable the receive unit by stopping each queue */
1086 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1087 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1088 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1089 reg_val |= IXGBE_RXDCTL_SWFLSH;
1090 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1093 /* flush all queues disables */
1094 IXGBE_WRITE_FLUSH(hw);
1098 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1099 * access and verify no pending requests
1101 return ixgbe_disable_pcie_master(hw);
1105 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1106 * @hw: pointer to hardware structure
1107 * @index: led number to turn on
1109 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1111 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1113 DEBUGFUNC("ixgbe_led_on_generic");
1115 /* To turn on the LED, set mode to ON. */
1116 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1117 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1118 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1119 IXGBE_WRITE_FLUSH(hw);
1121 return IXGBE_SUCCESS;
1125 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1126 * @hw: pointer to hardware structure
1127 * @index: led number to turn off
1129 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1131 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1133 DEBUGFUNC("ixgbe_led_off_generic");
1135 /* To turn off the LED, set mode to OFF. */
1136 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1137 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1138 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1139 IXGBE_WRITE_FLUSH(hw);
1141 return IXGBE_SUCCESS;
1145 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1146 * @hw: pointer to hardware structure
1148 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1149 * ixgbe_hw struct in order to set up EEPROM access.
1151 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1153 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1157 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1159 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1160 eeprom->type = ixgbe_eeprom_none;
1161 /* Set default semaphore delay to 10ms which is a well
1163 eeprom->semaphore_delay = 10;
1164 /* Clear EEPROM page size, it will be initialized as needed */
1165 eeprom->word_page_size = 0;
1168 * Check for EEPROM present first.
1169 * If not present leave as none
1171 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1172 if (eec & IXGBE_EEC_PRES) {
1173 eeprom->type = ixgbe_eeprom_spi;
1176 * SPI EEPROM is assumed here. This code would need to
1177 * change if a future EEPROM is not SPI.
1179 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1180 IXGBE_EEC_SIZE_SHIFT);
1181 eeprom->word_size = 1 << (eeprom_size +
1182 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1185 if (eec & IXGBE_EEC_ADDR_SIZE)
1186 eeprom->address_bits = 16;
1188 eeprom->address_bits = 8;
1189 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1190 "%d\n", eeprom->type, eeprom->word_size,
1191 eeprom->address_bits);
1194 return IXGBE_SUCCESS;
1198 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1199 * @hw: pointer to hardware structure
1200 * @offset: offset within the EEPROM to write
1201 * @words: number of word(s)
1202 * @data: 16 bit word(s) to write to EEPROM
1204 * Reads 16 bit word(s) from EEPROM through bit-bang method
1206 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1207 u16 words, u16 *data)
1209 s32 status = IXGBE_SUCCESS;
1212 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1214 hw->eeprom.ops.init_params(hw);
1217 status = IXGBE_ERR_INVALID_ARGUMENT;
1221 if (offset + words > hw->eeprom.word_size) {
1222 status = IXGBE_ERR_EEPROM;
1227 * The EEPROM page size cannot be queried from the chip. We do lazy
1228 * initialization. It is worth to do that when we write large buffer.
1230 if ((hw->eeprom.word_page_size == 0) &&
1231 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1232 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1235 * We cannot hold synchronization semaphores for too long
1236 * to avoid other entity starvation. However it is more efficient
1237 * to read in bursts than synchronizing access for each word.
1239 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1240 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1241 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1242 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1245 if (status != IXGBE_SUCCESS)
1254 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1255 * @hw: pointer to hardware structure
1256 * @offset: offset within the EEPROM to be written to
1257 * @words: number of word(s)
1258 * @data: 16 bit word(s) to be written to the EEPROM
1260 * If ixgbe_eeprom_update_checksum is not called after this function, the
1261 * EEPROM will most likely contain an invalid checksum.
1263 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1264 u16 words, u16 *data)
1270 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1272 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1274 /* Prepare the EEPROM for writing */
1275 status = ixgbe_acquire_eeprom(hw);
1277 if (status == IXGBE_SUCCESS) {
1278 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1279 ixgbe_release_eeprom(hw);
1280 status = IXGBE_ERR_EEPROM;
1284 if (status == IXGBE_SUCCESS) {
1285 for (i = 0; i < words; i++) {
1286 ixgbe_standby_eeprom(hw);
1288 /* Send the WRITE ENABLE command (8 bit opcode ) */
1289 ixgbe_shift_out_eeprom_bits(hw,
1290 IXGBE_EEPROM_WREN_OPCODE_SPI,
1291 IXGBE_EEPROM_OPCODE_BITS);
1293 ixgbe_standby_eeprom(hw);
1296 * Some SPI eeproms use the 8th address bit embedded
1299 if ((hw->eeprom.address_bits == 8) &&
1300 ((offset + i) >= 128))
1301 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1303 /* Send the Write command (8-bit opcode + addr) */
1304 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1305 IXGBE_EEPROM_OPCODE_BITS);
1306 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1307 hw->eeprom.address_bits);
1309 page_size = hw->eeprom.word_page_size;
1311 /* Send the data in burst via SPI*/
1314 word = (word >> 8) | (word << 8);
1315 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1320 /* do not wrap around page */
1321 if (((offset + i) & (page_size - 1)) ==
1324 } while (++i < words);
1326 ixgbe_standby_eeprom(hw);
1329 /* Done with writing - release the EEPROM */
1330 ixgbe_release_eeprom(hw);
1337 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1338 * @hw: pointer to hardware structure
1339 * @offset: offset within the EEPROM to be written to
1340 * @data: 16 bit word to be written to the EEPROM
1342 * If ixgbe_eeprom_update_checksum is not called after this function, the
1343 * EEPROM will most likely contain an invalid checksum.
1345 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1349 DEBUGFUNC("ixgbe_write_eeprom_generic");
1351 hw->eeprom.ops.init_params(hw);
1353 if (offset >= hw->eeprom.word_size) {
1354 status = IXGBE_ERR_EEPROM;
1358 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1365 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1366 * @hw: pointer to hardware structure
1367 * @offset: offset within the EEPROM to be read
1368 * @data: read 16 bit words(s) from EEPROM
1369 * @words: number of word(s)
1371 * Reads 16 bit word(s) from EEPROM through bit-bang method
1373 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1374 u16 words, u16 *data)
1376 s32 status = IXGBE_SUCCESS;
1379 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1381 hw->eeprom.ops.init_params(hw);
1384 status = IXGBE_ERR_INVALID_ARGUMENT;
1388 if (offset + words > hw->eeprom.word_size) {
1389 status = IXGBE_ERR_EEPROM;
1394 * We cannot hold synchronization semaphores for too long
1395 * to avoid other entity starvation. However it is more efficient
1396 * to read in bursts than synchronizing access for each word.
1398 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1399 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1400 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1402 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1405 if (status != IXGBE_SUCCESS)
1414 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1415 * @hw: pointer to hardware structure
1416 * @offset: offset within the EEPROM to be read
1417 * @words: number of word(s)
1418 * @data: read 16 bit word(s) from EEPROM
1420 * Reads 16 bit word(s) from EEPROM through bit-bang method
1422 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1423 u16 words, u16 *data)
1427 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1430 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1432 /* Prepare the EEPROM for reading */
1433 status = ixgbe_acquire_eeprom(hw);
1435 if (status == IXGBE_SUCCESS) {
1436 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1437 ixgbe_release_eeprom(hw);
1438 status = IXGBE_ERR_EEPROM;
1442 if (status == IXGBE_SUCCESS) {
1443 for (i = 0; i < words; i++) {
1444 ixgbe_standby_eeprom(hw);
1446 * Some SPI eeproms use the 8th address bit embedded
1449 if ((hw->eeprom.address_bits == 8) &&
1450 ((offset + i) >= 128))
1451 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1453 /* Send the READ command (opcode + addr) */
1454 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1455 IXGBE_EEPROM_OPCODE_BITS);
1456 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1457 hw->eeprom.address_bits);
1459 /* Read the data. */
1460 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1461 data[i] = (word_in >> 8) | (word_in << 8);
1464 /* End this read operation */
1465 ixgbe_release_eeprom(hw);
1472 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1473 * @hw: pointer to hardware structure
1474 * @offset: offset within the EEPROM to be read
1475 * @data: read 16 bit value from EEPROM
1477 * Reads 16 bit value from EEPROM through bit-bang method
1479 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1484 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1486 hw->eeprom.ops.init_params(hw);
1488 if (offset >= hw->eeprom.word_size) {
1489 status = IXGBE_ERR_EEPROM;
1493 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1500 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1501 * @hw: pointer to hardware structure
1502 * @offset: offset of word in the EEPROM to read
1503 * @words: number of word(s)
1504 * @data: 16 bit word(s) from the EEPROM
1506 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1508 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1509 u16 words, u16 *data)
1512 s32 status = IXGBE_SUCCESS;
1515 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1517 hw->eeprom.ops.init_params(hw);
1520 status = IXGBE_ERR_INVALID_ARGUMENT;
1521 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1525 if (offset >= hw->eeprom.word_size) {
1526 status = IXGBE_ERR_EEPROM;
1527 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1531 for (i = 0; i < words; i++) {
1532 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1533 IXGBE_EEPROM_RW_REG_START;
1535 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1536 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1538 if (status == IXGBE_SUCCESS) {
1539 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1540 IXGBE_EEPROM_RW_REG_DATA);
1542 DEBUGOUT("Eeprom read timed out\n");
1551 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1552 * @hw: pointer to hardware structure
1553 * @offset: offset within the EEPROM to be used as a scratch pad
1555 * Discover EEPROM page size by writing marching data at given offset.
1556 * This function is called only when we are writing a new large buffer
1557 * at given offset so the data would be overwritten anyway.
1559 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1562 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1563 s32 status = IXGBE_SUCCESS;
1566 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1568 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1571 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1572 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1573 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1574 hw->eeprom.word_page_size = 0;
1575 if (status != IXGBE_SUCCESS)
1578 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1579 if (status != IXGBE_SUCCESS)
1583 * When writing in burst more than the actual page size
1584 * EEPROM address wraps around current page.
1586 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1588 DEBUGOUT1("Detected EEPROM page size = %d words.",
1589 hw->eeprom.word_page_size);
1595 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1596 * @hw: pointer to hardware structure
1597 * @offset: offset of word in the EEPROM to read
1598 * @data: word read from the EEPROM
1600 * Reads a 16 bit word from the EEPROM using the EERD register.
1602 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1604 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1608 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1609 * @hw: pointer to hardware structure
1610 * @offset: offset of word in the EEPROM to write
1611 * @words: number of word(s)
1612 * @data: word(s) write to the EEPROM
1614 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1616 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1617 u16 words, u16 *data)
1620 s32 status = IXGBE_SUCCESS;
1623 DEBUGFUNC("ixgbe_write_eewr_generic");
1625 hw->eeprom.ops.init_params(hw);
1628 status = IXGBE_ERR_INVALID_ARGUMENT;
1629 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1633 if (offset >= hw->eeprom.word_size) {
1634 status = IXGBE_ERR_EEPROM;
1635 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1639 for (i = 0; i < words; i++) {
1640 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1641 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1642 IXGBE_EEPROM_RW_REG_START;
1644 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1645 if (status != IXGBE_SUCCESS) {
1646 DEBUGOUT("Eeprom write EEWR timed out\n");
1650 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1652 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1653 if (status != IXGBE_SUCCESS) {
1654 DEBUGOUT("Eeprom write EEWR timed out\n");
1664 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1665 * @hw: pointer to hardware structure
1666 * @offset: offset of word in the EEPROM to write
1667 * @data: word write to the EEPROM
1669 * Write a 16 bit word to the EEPROM using the EEWR register.
1671 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1673 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1677 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1678 * @hw: pointer to hardware structure
1679 * @ee_reg: EEPROM flag for polling
1681 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1682 * read or write is done respectively.
1684 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1688 s32 status = IXGBE_ERR_EEPROM;
1690 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1692 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1693 if (ee_reg == IXGBE_NVM_POLL_READ)
1694 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1696 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1698 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1699 status = IXGBE_SUCCESS;
1705 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1706 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1707 "EEPROM read/write done polling timed out");
1713 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1714 * @hw: pointer to hardware structure
1716 * Prepares EEPROM for access using bit-bang method. This function should
1717 * be called before issuing a command to the EEPROM.
1719 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1721 s32 status = IXGBE_SUCCESS;
1725 DEBUGFUNC("ixgbe_acquire_eeprom");
1727 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1729 status = IXGBE_ERR_SWFW_SYNC;
1731 if (status == IXGBE_SUCCESS) {
1732 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1734 /* Request EEPROM Access */
1735 eec |= IXGBE_EEC_REQ;
1736 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1738 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1739 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1740 if (eec & IXGBE_EEC_GNT)
1745 /* Release if grant not acquired */
1746 if (!(eec & IXGBE_EEC_GNT)) {
1747 eec &= ~IXGBE_EEC_REQ;
1748 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1749 DEBUGOUT("Could not acquire EEPROM grant\n");
1751 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1752 status = IXGBE_ERR_EEPROM;
1755 /* Setup EEPROM for Read/Write */
1756 if (status == IXGBE_SUCCESS) {
1757 /* Clear CS and SK */
1758 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1759 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1760 IXGBE_WRITE_FLUSH(hw);
1768 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1769 * @hw: pointer to hardware structure
1771 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1773 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1775 s32 status = IXGBE_ERR_EEPROM;
1780 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1783 /* Get SMBI software semaphore between device drivers first */
1784 for (i = 0; i < timeout; i++) {
1786 * If the SMBI bit is 0 when we read it, then the bit will be
1787 * set and we have the semaphore
1789 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1790 if (!(swsm & IXGBE_SWSM_SMBI)) {
1791 status = IXGBE_SUCCESS;
1798 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1801 * this release is particularly important because our attempts
1802 * above to get the semaphore may have succeeded, and if there
1803 * was a timeout, we should unconditionally clear the semaphore
1804 * bits to free the driver to make progress
1806 ixgbe_release_eeprom_semaphore(hw);
1811 * If the SMBI bit is 0 when we read it, then the bit will be
1812 * set and we have the semaphore
1814 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1815 if (!(swsm & IXGBE_SWSM_SMBI))
1816 status = IXGBE_SUCCESS;
1819 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1820 if (status == IXGBE_SUCCESS) {
1821 for (i = 0; i < timeout; i++) {
1822 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1824 /* Set the SW EEPROM semaphore bit to request access */
1825 swsm |= IXGBE_SWSM_SWESMBI;
1826 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1829 * If we set the bit successfully then we got the
1832 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1833 if (swsm & IXGBE_SWSM_SWESMBI)
1840 * Release semaphores and return error if SW EEPROM semaphore
1841 * was not granted because we don't have access to the EEPROM
1844 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1845 "SWESMBI Software EEPROM semaphore not granted.\n");
1846 ixgbe_release_eeprom_semaphore(hw);
1847 status = IXGBE_ERR_EEPROM;
1850 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1851 "Software semaphore SMBI between device drivers "
1859 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1860 * @hw: pointer to hardware structure
1862 * This function clears hardware semaphore bits.
1864 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1868 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1870 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1872 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1873 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1874 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1875 IXGBE_WRITE_FLUSH(hw);
1879 * ixgbe_ready_eeprom - Polls for EEPROM ready
1880 * @hw: pointer to hardware structure
1882 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1884 s32 status = IXGBE_SUCCESS;
1888 DEBUGFUNC("ixgbe_ready_eeprom");
1891 * Read "Status Register" repeatedly until the LSB is cleared. The
1892 * EEPROM will signal that the command has been completed by clearing
1893 * bit 0 of the internal status register. If it's not cleared within
1894 * 5 milliseconds, then error out.
1896 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1897 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1898 IXGBE_EEPROM_OPCODE_BITS);
1899 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1900 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1904 ixgbe_standby_eeprom(hw);
1908 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1909 * devices (and only 0-5mSec on 5V devices)
1911 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1912 DEBUGOUT("SPI EEPROM Status error\n");
1913 status = IXGBE_ERR_EEPROM;
1920 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1921 * @hw: pointer to hardware structure
1923 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1927 DEBUGFUNC("ixgbe_standby_eeprom");
1929 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1931 /* Toggle CS to flush commands */
1932 eec |= IXGBE_EEC_CS;
1933 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1934 IXGBE_WRITE_FLUSH(hw);
1936 eec &= ~IXGBE_EEC_CS;
1937 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1938 IXGBE_WRITE_FLUSH(hw);
1943 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1944 * @hw: pointer to hardware structure
1945 * @data: data to send to the EEPROM
1946 * @count: number of bits to shift out
1948 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1955 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1957 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1960 * Mask is used to shift "count" bits of "data" out to the EEPROM
1961 * one bit at a time. Determine the starting bit based on count
1963 mask = 0x01 << (count - 1);
1965 for (i = 0; i < count; i++) {
1967 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1968 * "1", and then raising and then lowering the clock (the SK
1969 * bit controls the clock input to the EEPROM). A "0" is
1970 * shifted out to the EEPROM by setting "DI" to "0" and then
1971 * raising and then lowering the clock.
1974 eec |= IXGBE_EEC_DI;
1976 eec &= ~IXGBE_EEC_DI;
1978 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1979 IXGBE_WRITE_FLUSH(hw);
1983 ixgbe_raise_eeprom_clk(hw, &eec);
1984 ixgbe_lower_eeprom_clk(hw, &eec);
1987 * Shift mask to signify next bit of data to shift in to the
1993 /* We leave the "DI" bit set to "0" when we leave this routine. */
1994 eec &= ~IXGBE_EEC_DI;
1995 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1996 IXGBE_WRITE_FLUSH(hw);
2000 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2001 * @hw: pointer to hardware structure
2003 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2009 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2012 * In order to read a register from the EEPROM, we need to shift
2013 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2014 * the clock input to the EEPROM (setting the SK bit), and then reading
2015 * the value of the "DO" bit. During this "shifting in" process the
2016 * "DI" bit should always be clear.
2018 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2020 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2022 for (i = 0; i < count; i++) {
2024 ixgbe_raise_eeprom_clk(hw, &eec);
2026 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2028 eec &= ~(IXGBE_EEC_DI);
2029 if (eec & IXGBE_EEC_DO)
2032 ixgbe_lower_eeprom_clk(hw, &eec);
2039 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2040 * @hw: pointer to hardware structure
2041 * @eec: EEC register's current value
2043 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2045 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2048 * Raise the clock input to the EEPROM
2049 * (setting the SK bit), then delay
2051 *eec = *eec | IXGBE_EEC_SK;
2052 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2053 IXGBE_WRITE_FLUSH(hw);
2058 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2059 * @hw: pointer to hardware structure
2060 * @eecd: EECD's current value
2062 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2064 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2067 * Lower the clock input to the EEPROM (clearing the SK bit), then
2070 *eec = *eec & ~IXGBE_EEC_SK;
2071 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2072 IXGBE_WRITE_FLUSH(hw);
2077 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2078 * @hw: pointer to hardware structure
2080 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2084 DEBUGFUNC("ixgbe_release_eeprom");
2086 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2088 eec |= IXGBE_EEC_CS; /* Pull CS high */
2089 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2091 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2092 IXGBE_WRITE_FLUSH(hw);
2096 /* Stop requesting EEPROM access */
2097 eec &= ~IXGBE_EEC_REQ;
2098 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2100 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2102 /* Delay before attempt to obtain semaphore again to allow FW access */
2103 msec_delay(hw->eeprom.semaphore_delay);
2107 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2108 * @hw: pointer to hardware structure
2110 * Returns a negative error code on error, or the 16-bit checksum
2112 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2121 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2123 /* Include 0x0-0x3F in the checksum */
2124 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2125 if (hw->eeprom.ops.read(hw, i, &word)) {
2126 DEBUGOUT("EEPROM read failed\n");
2127 return IXGBE_ERR_EEPROM;
2132 /* Include all data from pointers except for the fw pointer */
2133 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2134 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2135 DEBUGOUT("EEPROM read failed\n");
2136 return IXGBE_ERR_EEPROM;
2139 /* If the pointer seems invalid */
2140 if (pointer == 0xFFFF || pointer == 0)
2143 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2144 DEBUGOUT("EEPROM read failed\n");
2145 return IXGBE_ERR_EEPROM;
2148 if (length == 0xFFFF || length == 0)
2151 for (j = pointer + 1; j <= pointer + length; j++) {
2152 if (hw->eeprom.ops.read(hw, j, &word)) {
2153 DEBUGOUT("EEPROM read failed\n");
2154 return IXGBE_ERR_EEPROM;
2160 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2162 return (s32)checksum;
2166 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2167 * @hw: pointer to hardware structure
2168 * @checksum_val: calculated checksum
2170 * Performs checksum calculation and validates the EEPROM checksum. If the
2171 * caller does not need checksum_val, the value can be NULL.
2173 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2178 u16 read_checksum = 0;
2180 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2182 /* Read the first word from the EEPROM. If this times out or fails, do
2183 * not continue or we could be in for a very long wait while every
2186 status = hw->eeprom.ops.read(hw, 0, &checksum);
2188 DEBUGOUT("EEPROM read failed\n");
2192 status = hw->eeprom.ops.calc_checksum(hw);
2196 checksum = (u16)(status & 0xffff);
2198 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2200 DEBUGOUT("EEPROM read failed\n");
2204 /* Verify read checksum from EEPROM is the same as
2205 * calculated checksum
2207 if (read_checksum != checksum)
2208 status = IXGBE_ERR_EEPROM_CHECKSUM;
2210 /* If the user cares, return the calculated checksum */
2212 *checksum_val = checksum;
2218 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2219 * @hw: pointer to hardware structure
2221 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2226 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2228 /* Read the first word from the EEPROM. If this times out or fails, do
2229 * not continue or we could be in for a very long wait while every
2232 status = hw->eeprom.ops.read(hw, 0, &checksum);
2234 DEBUGOUT("EEPROM read failed\n");
2238 status = hw->eeprom.ops.calc_checksum(hw);
2242 checksum = (u16)(status & 0xffff);
2244 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2250 * ixgbe_validate_mac_addr - Validate MAC address
2251 * @mac_addr: pointer to MAC address.
2253 * Tests a MAC address to ensure it is a valid Individual Address
2255 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2257 s32 status = IXGBE_SUCCESS;
2259 DEBUGFUNC("ixgbe_validate_mac_addr");
2261 /* Make sure it is not a multicast address */
2262 if (IXGBE_IS_MULTICAST(mac_addr)) {
2263 DEBUGOUT("MAC address is multicast\n");
2264 status = IXGBE_ERR_INVALID_MAC_ADDR;
2265 /* Not a broadcast address */
2266 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2267 DEBUGOUT("MAC address is broadcast\n");
2268 status = IXGBE_ERR_INVALID_MAC_ADDR;
2269 /* Reject the zero address */
2270 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2271 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2272 DEBUGOUT("MAC address is all zeros\n");
2273 status = IXGBE_ERR_INVALID_MAC_ADDR;
2279 * ixgbe_set_rar_generic - Set Rx address register
2280 * @hw: pointer to hardware structure
2281 * @index: Receive address register to write
2282 * @addr: Address to put into receive address register
2283 * @vmdq: VMDq "set" or "pool" index
2284 * @enable_addr: set flag that address is active
2286 * Puts an ethernet address into a receive address register.
2288 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2291 u32 rar_low, rar_high;
2292 u32 rar_entries = hw->mac.num_rar_entries;
2294 DEBUGFUNC("ixgbe_set_rar_generic");
2296 /* Make sure we are using a valid rar index range */
2297 if (index >= rar_entries) {
2298 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2299 "RAR index %d is out of range.\n", index);
2300 return IXGBE_ERR_INVALID_ARGUMENT;
2303 /* setup VMDq pool selection before this RAR gets enabled */
2304 hw->mac.ops.set_vmdq(hw, index, vmdq);
2307 * HW expects these in little endian so we reverse the byte
2308 * order from network order (big endian) to little endian
2310 rar_low = ((u32)addr[0] |
2311 ((u32)addr[1] << 8) |
2312 ((u32)addr[2] << 16) |
2313 ((u32)addr[3] << 24));
2315 * Some parts put the VMDq setting in the extra RAH bits,
2316 * so save everything except the lower 16 bits that hold part
2317 * of the address and the address valid bit.
2319 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2320 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2321 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2323 if (enable_addr != 0)
2324 rar_high |= IXGBE_RAH_AV;
2326 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2327 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2329 return IXGBE_SUCCESS;
2333 * ixgbe_clear_rar_generic - Remove Rx address register
2334 * @hw: pointer to hardware structure
2335 * @index: Receive address register to write
2337 * Clears an ethernet address from a receive address register.
2339 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2342 u32 rar_entries = hw->mac.num_rar_entries;
2344 DEBUGFUNC("ixgbe_clear_rar_generic");
2346 /* Make sure we are using a valid rar index range */
2347 if (index >= rar_entries) {
2348 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2349 "RAR index %d is out of range.\n", index);
2350 return IXGBE_ERR_INVALID_ARGUMENT;
2354 * Some parts put the VMDq setting in the extra RAH bits,
2355 * so save everything except the lower 16 bits that hold part
2356 * of the address and the address valid bit.
2358 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2359 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2361 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2362 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2364 /* clear VMDq pool/queue selection for this RAR */
2365 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2367 return IXGBE_SUCCESS;
2371 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2372 * @hw: pointer to hardware structure
2374 * Places the MAC address in receive address register 0 and clears the rest
2375 * of the receive address registers. Clears the multicast table. Assumes
2376 * the receiver is in reset when the routine is called.
2378 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2381 u32 rar_entries = hw->mac.num_rar_entries;
2383 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2386 * If the current mac address is valid, assume it is a software override
2387 * to the permanent address.
2388 * Otherwise, use the permanent address from the eeprom.
2390 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2391 IXGBE_ERR_INVALID_MAC_ADDR) {
2392 /* Get the MAC address from the RAR0 for later reference */
2393 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2395 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2396 hw->mac.addr[0], hw->mac.addr[1],
2398 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2399 hw->mac.addr[4], hw->mac.addr[5]);
2401 /* Setup the receive address. */
2402 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2403 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2404 hw->mac.addr[0], hw->mac.addr[1],
2406 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2407 hw->mac.addr[4], hw->mac.addr[5]);
2409 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2411 /* clear VMDq pool/queue selection for RAR 0 */
2412 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2414 hw->addr_ctrl.overflow_promisc = 0;
2416 hw->addr_ctrl.rar_used_count = 1;
2418 /* Zero out the other receive addresses. */
2419 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2420 for (i = 1; i < rar_entries; i++) {
2421 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2422 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2426 hw->addr_ctrl.mta_in_use = 0;
2427 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2429 DEBUGOUT(" Clearing MTA\n");
2430 for (i = 0; i < hw->mac.mcft_size; i++)
2431 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2433 ixgbe_init_uta_tables(hw);
2435 return IXGBE_SUCCESS;
2439 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2440 * @hw: pointer to hardware structure
2441 * @addr: new address
2443 * Adds it to unused receive address register or goes into promiscuous mode.
2445 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2447 u32 rar_entries = hw->mac.num_rar_entries;
2450 DEBUGFUNC("ixgbe_add_uc_addr");
2452 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2453 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2456 * Place this address in the RAR if there is room,
2457 * else put the controller into promiscuous mode
2459 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2460 rar = hw->addr_ctrl.rar_used_count;
2461 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2462 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2463 hw->addr_ctrl.rar_used_count++;
2465 hw->addr_ctrl.overflow_promisc++;
2468 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2472 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2473 * @hw: pointer to hardware structure
2474 * @addr_list: the list of new addresses
2475 * @addr_count: number of addresses
2476 * @next: iterator function to walk the address list
2478 * The given list replaces any existing list. Clears the secondary addrs from
2479 * receive address registers. Uses unused receive address registers for the
2480 * first secondary addresses, and falls back to promiscuous mode as needed.
2482 * Drivers using secondary unicast addresses must set user_set_promisc when
2483 * manually putting the device into promiscuous mode.
2485 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2486 u32 addr_count, ixgbe_mc_addr_itr next)
2490 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2495 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2498 * Clear accounting of old secondary address list,
2499 * don't count RAR[0]
2501 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2502 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2503 hw->addr_ctrl.overflow_promisc = 0;
2505 /* Zero out the other receive addresses */
2506 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2507 for (i = 0; i < uc_addr_in_use; i++) {
2508 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2509 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2512 /* Add the new addresses */
2513 for (i = 0; i < addr_count; i++) {
2514 DEBUGOUT(" Adding the secondary addresses:\n");
2515 addr = next(hw, &addr_list, &vmdq);
2516 ixgbe_add_uc_addr(hw, addr, vmdq);
2519 if (hw->addr_ctrl.overflow_promisc) {
2520 /* enable promisc if not already in overflow or set by user */
2521 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2522 DEBUGOUT(" Entering address overflow promisc mode\n");
2523 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2524 fctrl |= IXGBE_FCTRL_UPE;
2525 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2528 /* only disable if set by overflow, not by user */
2529 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2530 DEBUGOUT(" Leaving address overflow promisc mode\n");
2531 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2532 fctrl &= ~IXGBE_FCTRL_UPE;
2533 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2537 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2538 return IXGBE_SUCCESS;
2542 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2543 * @hw: pointer to hardware structure
2544 * @mc_addr: the multicast address
2546 * Extracts the 12 bits, from a multicast address, to determine which
2547 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2548 * incoming rx multicast addresses, to determine the bit-vector to check in
2549 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2550 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2551 * to mc_filter_type.
2553 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2557 DEBUGFUNC("ixgbe_mta_vector");
2559 switch (hw->mac.mc_filter_type) {
2560 case 0: /* use bits [47:36] of the address */
2561 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2563 case 1: /* use bits [46:35] of the address */
2564 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2566 case 2: /* use bits [45:34] of the address */
2567 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2569 case 3: /* use bits [43:32] of the address */
2570 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2572 default: /* Invalid mc_filter_type */
2573 DEBUGOUT("MC filter type param set incorrectly\n");
2578 /* vector can only be 12-bits or boundary will be exceeded */
2584 * ixgbe_set_mta - Set bit-vector in multicast table
2585 * @hw: pointer to hardware structure
2586 * @hash_value: Multicast address hash value
2588 * Sets the bit-vector in the multicast table.
2590 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2596 DEBUGFUNC("ixgbe_set_mta");
2598 hw->addr_ctrl.mta_in_use++;
2600 vector = ixgbe_mta_vector(hw, mc_addr);
2601 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2604 * The MTA is a register array of 128 32-bit registers. It is treated
2605 * like an array of 4096 bits. We want to set bit
2606 * BitArray[vector_value]. So we figure out what register the bit is
2607 * in, read it, OR in the new bit, then write back the new value. The
2608 * register is determined by the upper 7 bits of the vector value and
2609 * the bit within that register are determined by the lower 5 bits of
2612 vector_reg = (vector >> 5) & 0x7F;
2613 vector_bit = vector & 0x1F;
2614 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2618 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2619 * @hw: pointer to hardware structure
2620 * @mc_addr_list: the list of new multicast addresses
2621 * @mc_addr_count: number of addresses
2622 * @next: iterator function to walk the multicast address list
2623 * @clear: flag, when set clears the table beforehand
2625 * When the clear flag is set, the given list replaces any existing list.
2626 * Hashes the given addresses into the multicast table.
2628 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2629 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2635 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2638 * Set the new number of MC addresses that we are being requested to
2641 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2642 hw->addr_ctrl.mta_in_use = 0;
2644 /* Clear mta_shadow */
2646 DEBUGOUT(" Clearing MTA\n");
2647 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2650 /* Update mta_shadow */
2651 for (i = 0; i < mc_addr_count; i++) {
2652 DEBUGOUT(" Adding the multicast addresses:\n");
2653 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2657 for (i = 0; i < hw->mac.mcft_size; i++)
2658 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2659 hw->mac.mta_shadow[i]);
2661 if (hw->addr_ctrl.mta_in_use > 0)
2662 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2663 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2665 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2666 return IXGBE_SUCCESS;
2670 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2671 * @hw: pointer to hardware structure
2673 * Enables multicast address in RAR and the use of the multicast hash table.
2675 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2677 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2679 DEBUGFUNC("ixgbe_enable_mc_generic");
2681 if (a->mta_in_use > 0)
2682 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2683 hw->mac.mc_filter_type);
2685 return IXGBE_SUCCESS;
2689 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2690 * @hw: pointer to hardware structure
2692 * Disables multicast address in RAR and the use of the multicast hash table.
2694 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2696 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2698 DEBUGFUNC("ixgbe_disable_mc_generic");
2700 if (a->mta_in_use > 0)
2701 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2703 return IXGBE_SUCCESS;
2707 * ixgbe_fc_enable_generic - Enable flow control
2708 * @hw: pointer to hardware structure
2710 * Enable flow control according to the current settings.
2712 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2714 s32 ret_val = IXGBE_SUCCESS;
2715 u32 mflcn_reg, fccfg_reg;
2720 DEBUGFUNC("ixgbe_fc_enable_generic");
2722 /* Validate the water mark configuration */
2723 if (!hw->fc.pause_time) {
2724 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2728 /* Low water mark of zero causes XOFF floods */
2729 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2730 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2731 hw->fc.high_water[i]) {
2732 if (!hw->fc.low_water[i] ||
2733 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2734 DEBUGOUT("Invalid water mark configuration\n");
2735 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2741 /* Negotiate the fc mode to use */
2742 ixgbe_fc_autoneg(hw);
2744 /* Disable any previous flow control settings */
2745 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2746 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2748 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2749 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2752 * The possible values of fc.current_mode are:
2753 * 0: Flow control is completely disabled
2754 * 1: Rx flow control is enabled (we can receive pause frames,
2755 * but not send pause frames).
2756 * 2: Tx flow control is enabled (we can send pause frames but
2757 * we do not support receiving pause frames).
2758 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2761 switch (hw->fc.current_mode) {
2764 * Flow control is disabled by software override or autoneg.
2765 * The code below will actually disable it in the HW.
2768 case ixgbe_fc_rx_pause:
2770 * Rx Flow control is enabled and Tx Flow control is
2771 * disabled by software override. Since there really
2772 * isn't a way to advertise that we are capable of RX
2773 * Pause ONLY, we will advertise that we support both
2774 * symmetric and asymmetric Rx PAUSE. Later, we will
2775 * disable the adapter's ability to send PAUSE frames.
2777 mflcn_reg |= IXGBE_MFLCN_RFCE;
2779 case ixgbe_fc_tx_pause:
2781 * Tx Flow control is enabled, and Rx Flow control is
2782 * disabled by software override.
2784 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2787 /* Flow control (both Rx and Tx) is enabled by SW override. */
2788 mflcn_reg |= IXGBE_MFLCN_RFCE;
2789 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2792 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2793 "Flow control param set incorrectly\n");
2794 ret_val = IXGBE_ERR_CONFIG;
2799 /* Set 802.3x based flow control settings. */
2800 mflcn_reg |= IXGBE_MFLCN_DPF;
2801 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2802 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2805 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2806 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2807 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2808 hw->fc.high_water[i]) {
2809 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2810 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2811 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2813 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2815 * In order to prevent Tx hangs when the internal Tx
2816 * switch is enabled we must set the high water mark
2817 * to the Rx packet buffer size - 24KB. This allows
2818 * the Tx switch to function even under heavy Rx
2821 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2824 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2827 /* Configure pause time (2 TCs per register) */
2828 reg = hw->fc.pause_time * 0x00010001;
2829 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2830 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2832 /* Configure flow control refresh threshold value */
2833 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2840 * ixgbe_negotiate_fc - Negotiate flow control
2841 * @hw: pointer to hardware structure
2842 * @adv_reg: flow control advertised settings
2843 * @lp_reg: link partner's flow control settings
2844 * @adv_sym: symmetric pause bit in advertisement
2845 * @adv_asm: asymmetric pause bit in advertisement
2846 * @lp_sym: symmetric pause bit in link partner advertisement
2847 * @lp_asm: asymmetric pause bit in link partner advertisement
2849 * Find the intersection between advertised settings and link partner's
2850 * advertised settings
2852 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2853 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2855 if ((!(adv_reg)) || (!(lp_reg))) {
2856 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2857 "Local or link partner's advertised flow control "
2858 "settings are NULL. Local: %x, link partner: %x\n",
2860 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2863 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2865 * Now we need to check if the user selected Rx ONLY
2866 * of pause frames. In this case, we had to advertise
2867 * FULL flow control because we could not advertise RX
2868 * ONLY. Hence, we must now check to see if we need to
2869 * turn OFF the TRANSMISSION of PAUSE frames.
2871 if (hw->fc.requested_mode == ixgbe_fc_full) {
2872 hw->fc.current_mode = ixgbe_fc_full;
2873 DEBUGOUT("Flow Control = FULL.\n");
2875 hw->fc.current_mode = ixgbe_fc_rx_pause;
2876 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2878 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2879 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2880 hw->fc.current_mode = ixgbe_fc_tx_pause;
2881 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2882 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2883 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2884 hw->fc.current_mode = ixgbe_fc_rx_pause;
2885 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2887 hw->fc.current_mode = ixgbe_fc_none;
2888 DEBUGOUT("Flow Control = NONE.\n");
2890 return IXGBE_SUCCESS;
2894 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2895 * @hw: pointer to hardware structure
2897 * Enable flow control according on 1 gig fiber.
2899 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2901 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2902 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2905 * On multispeed fiber at 1g, bail out if
2906 * - link is up but AN did not complete, or if
2907 * - link is up and AN completed but timed out
2910 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2911 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2912 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2913 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2917 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2918 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2920 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2921 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2922 IXGBE_PCS1GANA_ASM_PAUSE,
2923 IXGBE_PCS1GANA_SYM_PAUSE,
2924 IXGBE_PCS1GANA_ASM_PAUSE);
2931 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2932 * @hw: pointer to hardware structure
2934 * Enable flow control according to IEEE clause 37.
2936 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2938 u32 links2, anlp1_reg, autoc_reg, links;
2939 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2942 * On backplane, bail out if
2943 * - backplane autoneg was not completed, or if
2944 * - we are 82599 and link partner is not AN enabled
2946 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2947 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2948 DEBUGOUT("Auto-Negotiation did not complete\n");
2952 if (hw->mac.type == ixgbe_mac_82599EB) {
2953 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2954 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2955 DEBUGOUT("Link partner is not AN enabled\n");
2960 * Read the 10g AN autoc and LP ability registers and resolve
2961 * local flow control settings accordingly
2963 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2964 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2966 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2967 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2968 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2975 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2976 * @hw: pointer to hardware structure
2978 * Enable flow control according to IEEE clause 37.
2980 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2982 u16 technology_ability_reg = 0;
2983 u16 lp_technology_ability_reg = 0;
2985 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2986 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2987 &technology_ability_reg);
2988 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2989 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2990 &lp_technology_ability_reg);
2992 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2993 (u32)lp_technology_ability_reg,
2994 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2995 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2999 * ixgbe_fc_autoneg - Configure flow control
3000 * @hw: pointer to hardware structure
3002 * Compares our advertised flow control capabilities to those advertised by
3003 * our link partner, and determines the proper flow control mode to use.
3005 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3007 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3008 ixgbe_link_speed speed;
3011 DEBUGFUNC("ixgbe_fc_autoneg");
3014 * AN should have completed when the cable was plugged in.
3015 * Look for reasons to bail out. Bail out if:
3016 * - FC autoneg is disabled, or if
3019 if (hw->fc.disable_fc_autoneg) {
3020 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3021 "Flow control autoneg is disabled");
3025 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3027 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3031 switch (hw->phy.media_type) {
3032 /* Autoneg flow control on fiber adapters */
3033 case ixgbe_media_type_fiber_fixed:
3034 case ixgbe_media_type_fiber_qsfp:
3035 case ixgbe_media_type_fiber:
3036 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3037 ret_val = ixgbe_fc_autoneg_fiber(hw);
3040 /* Autoneg flow control on backplane adapters */
3041 case ixgbe_media_type_backplane:
3042 ret_val = ixgbe_fc_autoneg_backplane(hw);
3045 /* Autoneg flow control on copper adapters */
3046 case ixgbe_media_type_copper:
3047 if (ixgbe_device_supports_autoneg_fc(hw))
3048 ret_val = ixgbe_fc_autoneg_copper(hw);
3056 if (ret_val == IXGBE_SUCCESS) {
3057 hw->fc.fc_was_autonegged = TRUE;
3059 hw->fc.fc_was_autonegged = FALSE;
3060 hw->fc.current_mode = hw->fc.requested_mode;
3065 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3066 * @hw: pointer to hardware structure
3068 * System-wide timeout range is encoded in PCIe Device Control2 register.
3070 * Add 10% to specified maximum and return the number of times to poll for
3071 * completion timeout, in units of 100 microsec. Never return less than
3072 * 800 = 80 millisec.
3074 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3079 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3080 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3083 case IXGBE_PCIDEVCTRL2_65_130ms:
3084 pollcnt = 1300; /* 130 millisec */
3086 case IXGBE_PCIDEVCTRL2_260_520ms:
3087 pollcnt = 5200; /* 520 millisec */
3089 case IXGBE_PCIDEVCTRL2_1_2s:
3090 pollcnt = 20000; /* 2 sec */
3092 case IXGBE_PCIDEVCTRL2_4_8s:
3093 pollcnt = 80000; /* 8 sec */
3095 case IXGBE_PCIDEVCTRL2_17_34s:
3096 pollcnt = 34000; /* 34 sec */
3098 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3099 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3100 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3101 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3103 pollcnt = 800; /* 80 millisec minimum */
3107 /* add 10% to spec maximum */
3108 return (pollcnt * 11) / 10;
3112 * ixgbe_disable_pcie_master - Disable PCI-express master access
3113 * @hw: pointer to hardware structure
3115 * Disables PCI-Express master access and verifies there are no pending
3116 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3117 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3118 * is returned signifying master requests disabled.
3120 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3122 s32 status = IXGBE_SUCCESS;
3126 DEBUGFUNC("ixgbe_disable_pcie_master");
3128 /* Always set this bit to ensure any future transactions are blocked */
3129 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3131 /* Exit if master requests are blocked */
3132 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3133 IXGBE_REMOVED(hw->hw_addr))
3136 /* Poll for master request bit to clear */
3137 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3139 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3144 * Two consecutive resets are required via CTRL.RST per datasheet
3145 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3146 * of this need. The first reset prevents new master requests from
3147 * being issued by our device. We then must wait 1usec or more for any
3148 * remaining completions from the PCIe bus to trickle in, and then reset
3149 * again to clear out any effects they may have had on our device.
3151 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3152 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3154 if (hw->mac.type >= ixgbe_mac_X550)
3158 * Before proceeding, make sure that the PCIe block does not have
3159 * transactions pending.
3161 poll = ixgbe_pcie_timeout_poll(hw);
3162 for (i = 0; i < poll; i++) {
3164 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3165 if (IXGBE_REMOVED(hw->hw_addr))
3167 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3171 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3172 "PCIe transaction pending bit also did not clear.\n");
3173 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3180 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3181 * @hw: pointer to hardware structure
3182 * @mask: Mask to specify which semaphore to acquire
3184 * Acquires the SWFW semaphore through the GSSR register for the specified
3185 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3187 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3191 u32 fwmask = mask << 5;
3195 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3197 for (i = 0; i < timeout; i++) {
3199 * SW NVM semaphore bit is used for access to all
3200 * SW_FW_SYNC bits (not just NVM)
3202 if (ixgbe_get_eeprom_semaphore(hw))
3203 return IXGBE_ERR_SWFW_SYNC;
3205 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3206 if (!(gssr & (fwmask | swmask))) {
3208 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3209 ixgbe_release_eeprom_semaphore(hw);
3210 return IXGBE_SUCCESS;
3212 /* Resource is currently in use by FW or SW */
3213 ixgbe_release_eeprom_semaphore(hw);
3218 /* If time expired clear the bits holding the lock and retry */
3219 if (gssr & (fwmask | swmask))
3220 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3223 return IXGBE_ERR_SWFW_SYNC;
3227 * ixgbe_release_swfw_sync - Release SWFW semaphore
3228 * @hw: pointer to hardware structure
3229 * @mask: Mask to specify which semaphore to release
3231 * Releases the SWFW semaphore through the GSSR register for the specified
3232 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3234 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3239 DEBUGFUNC("ixgbe_release_swfw_sync");
3241 ixgbe_get_eeprom_semaphore(hw);
3243 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3245 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3247 ixgbe_release_eeprom_semaphore(hw);
3251 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3252 * @hw: pointer to hardware structure
3254 * Stops the receive data path and waits for the HW to internally empty
3255 * the Rx security block
3257 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3259 #define IXGBE_MAX_SECRX_POLL 40
3264 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3267 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3268 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3269 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3270 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3271 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3272 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3275 /* Use interrupt-safe sleep just in case */
3279 /* For informational purposes only */
3280 if (i >= IXGBE_MAX_SECRX_POLL)
3281 DEBUGOUT("Rx unit being enabled before security "
3282 "path fully disabled. Continuing with init.\n");
3284 return IXGBE_SUCCESS;
3288 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3289 * @hw: pointer to hardware structure
3290 * @reg_val: Value we read from AUTOC
3292 * The default case requires no protection so just to the register read.
3294 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3297 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3298 return IXGBE_SUCCESS;
3302 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3303 * @hw: pointer to hardware structure
3304 * @reg_val: value to write to AUTOC
3305 * @locked: bool to indicate whether the SW/FW lock was already taken by
3308 * The default case requires no protection so just to the register write.
3310 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3312 UNREFERENCED_1PARAMETER(locked);
3314 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3315 return IXGBE_SUCCESS;
3319 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3320 * @hw: pointer to hardware structure
3322 * Enables the receive data path.
3324 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3328 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3330 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3331 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3332 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3333 IXGBE_WRITE_FLUSH(hw);
3335 return IXGBE_SUCCESS;
3339 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3340 * @hw: pointer to hardware structure
3341 * @regval: register value to write to RXCTRL
3343 * Enables the Rx DMA unit
3345 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3347 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3349 if (regval & IXGBE_RXCTRL_RXEN)
3350 ixgbe_enable_rx(hw);
3352 ixgbe_disable_rx(hw);
3354 return IXGBE_SUCCESS;
3358 * ixgbe_blink_led_start_generic - Blink LED based on index.
3359 * @hw: pointer to hardware structure
3360 * @index: led number to blink
3362 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3364 ixgbe_link_speed speed = 0;
3367 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3368 s32 ret_val = IXGBE_SUCCESS;
3369 bool locked = FALSE;
3371 DEBUGFUNC("ixgbe_blink_led_start_generic");
3374 * Link must be up to auto-blink the LEDs;
3375 * Force it if link is down.
3377 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3380 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3381 if (ret_val != IXGBE_SUCCESS)
3384 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3385 autoc_reg |= IXGBE_AUTOC_FLU;
3387 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3388 if (ret_val != IXGBE_SUCCESS)
3391 IXGBE_WRITE_FLUSH(hw);
3395 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3396 led_reg |= IXGBE_LED_BLINK(index);
3397 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3398 IXGBE_WRITE_FLUSH(hw);
3405 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3406 * @hw: pointer to hardware structure
3407 * @index: led number to stop blinking
3409 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3412 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3413 s32 ret_val = IXGBE_SUCCESS;
3414 bool locked = FALSE;
3416 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3418 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3419 if (ret_val != IXGBE_SUCCESS)
3422 autoc_reg &= ~IXGBE_AUTOC_FLU;
3423 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3425 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3426 if (ret_val != IXGBE_SUCCESS)
3429 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3430 led_reg &= ~IXGBE_LED_BLINK(index);
3431 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3432 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3433 IXGBE_WRITE_FLUSH(hw);
3440 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3441 * @hw: pointer to hardware structure
3442 * @san_mac_offset: SAN MAC address offset
3444 * This function will read the EEPROM location for the SAN MAC address
3445 * pointer, and returns the value at that location. This is used in both
3446 * get and set mac_addr routines.
3448 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3449 u16 *san_mac_offset)
3453 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3456 * First read the EEPROM pointer to see if the MAC addresses are
3459 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3462 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3463 "eeprom at offset %d failed",
3464 IXGBE_SAN_MAC_ADDR_PTR);
3471 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3472 * @hw: pointer to hardware structure
3473 * @san_mac_addr: SAN MAC address
3475 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3476 * per-port, so set_lan_id() must be called before reading the addresses.
3477 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3478 * upon for non-SFP connections, so we must call it here.
3480 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3482 u16 san_mac_data, san_mac_offset;
3486 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3489 * First read the EEPROM pointer to see if the MAC addresses are
3490 * available. If they're not, no point in calling set_lan_id() here.
3492 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3493 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3494 goto san_mac_addr_out;
3496 /* make sure we know which port we need to program */
3497 hw->mac.ops.set_lan_id(hw);
3498 /* apply the port offset to the address offset */
3499 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3500 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3501 for (i = 0; i < 3; i++) {
3502 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3505 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3506 "eeprom read at offset %d failed",
3508 goto san_mac_addr_out;
3510 san_mac_addr[i * 2] = (u8)(san_mac_data);
3511 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3514 return IXGBE_SUCCESS;
3518 * No addresses available in this EEPROM. It's not an
3519 * error though, so just wipe the local address and return.
3521 for (i = 0; i < 6; i++)
3522 san_mac_addr[i] = 0xFF;
3523 return IXGBE_SUCCESS;
3527 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3528 * @hw: pointer to hardware structure
3529 * @san_mac_addr: SAN MAC address
3531 * Write a SAN MAC address to the EEPROM.
3533 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3536 u16 san_mac_data, san_mac_offset;
3539 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3541 /* Look for SAN mac address pointer. If not defined, return */
3542 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3543 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3544 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3546 /* Make sure we know which port we need to write */
3547 hw->mac.ops.set_lan_id(hw);
3548 /* Apply the port offset to the address offset */
3549 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3550 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3552 for (i = 0; i < 3; i++) {
3553 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3554 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3555 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3559 return IXGBE_SUCCESS;
3563 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3564 * @hw: pointer to hardware structure
3566 * Read PCIe configuration space, and get the MSI-X vector count from
3567 * the capabilities table.
3569 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3575 switch (hw->mac.type) {
3576 case ixgbe_mac_82598EB:
3577 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3578 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3580 case ixgbe_mac_82599EB:
3581 case ixgbe_mac_X540:
3582 case ixgbe_mac_X550:
3583 case ixgbe_mac_X550EM_x:
3584 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3585 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3591 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3592 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3593 if (IXGBE_REMOVED(hw->hw_addr))
3595 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3597 /* MSI-X count is zero-based in HW */
3600 if (msix_count > max_msix_count)
3601 msix_count = max_msix_count;
3607 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3608 * @hw: pointer to hardware structure
3609 * @addr: Address to put into receive address register
3610 * @vmdq: VMDq pool to assign
3612 * Puts an ethernet address into a receive address register, or
3613 * finds the rar that it is aleady in; adds to the pool list
3615 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3617 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3618 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3620 u32 rar_low, rar_high;
3621 u32 addr_low, addr_high;
3623 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3625 /* swap bytes for HW little endian */
3626 addr_low = addr[0] | (addr[1] << 8)
3629 addr_high = addr[4] | (addr[5] << 8);
3632 * Either find the mac_id in rar or find the first empty space.
3633 * rar_highwater points to just after the highest currently used
3634 * rar in order to shorten the search. It grows when we add a new
3637 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3638 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3640 if (((IXGBE_RAH_AV & rar_high) == 0)
3641 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3642 first_empty_rar = rar;
3643 } else if ((rar_high & 0xFFFF) == addr_high) {
3644 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3645 if (rar_low == addr_low)
3646 break; /* found it already in the rars */
3650 if (rar < hw->mac.rar_highwater) {
3651 /* already there so just add to the pool bits */
3652 ixgbe_set_vmdq(hw, rar, vmdq);
3653 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3654 /* stick it into first empty RAR slot we found */
3655 rar = first_empty_rar;
3656 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3657 } else if (rar == hw->mac.rar_highwater) {
3658 /* add it to the top of the list and inc the highwater mark */
3659 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3660 hw->mac.rar_highwater++;
3661 } else if (rar >= hw->mac.num_rar_entries) {
3662 return IXGBE_ERR_INVALID_MAC_ADDR;
3666 * If we found rar[0], make sure the default pool bit (we use pool 0)
3667 * remains cleared to be sure default pool packets will get delivered
3670 ixgbe_clear_vmdq(hw, rar, 0);
3676 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3677 * @hw: pointer to hardware struct
3678 * @rar: receive address register index to disassociate
3679 * @vmdq: VMDq pool index to remove from the rar
3681 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3683 u32 mpsar_lo, mpsar_hi;
3684 u32 rar_entries = hw->mac.num_rar_entries;
3686 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3688 /* Make sure we are using a valid rar index range */
3689 if (rar >= rar_entries) {
3690 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3691 "RAR index %d is out of range.\n", rar);
3692 return IXGBE_ERR_INVALID_ARGUMENT;
3695 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3696 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3698 if (IXGBE_REMOVED(hw->hw_addr))
3701 if (!mpsar_lo && !mpsar_hi)
3704 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3706 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3710 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3713 } else if (vmdq < 32) {
3714 mpsar_lo &= ~(1 << vmdq);
3715 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3717 mpsar_hi &= ~(1 << (vmdq - 32));
3718 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3721 /* was that the last pool using this rar? */
3722 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3723 hw->mac.ops.clear_rar(hw, rar);
3725 return IXGBE_SUCCESS;
3729 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3730 * @hw: pointer to hardware struct
3731 * @rar: receive address register index to associate with a VMDq index
3732 * @vmdq: VMDq pool index
3734 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3737 u32 rar_entries = hw->mac.num_rar_entries;
3739 DEBUGFUNC("ixgbe_set_vmdq_generic");
3741 /* Make sure we are using a valid rar index range */
3742 if (rar >= rar_entries) {
3743 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3744 "RAR index %d is out of range.\n", rar);
3745 return IXGBE_ERR_INVALID_ARGUMENT;
3749 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3751 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3753 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3754 mpsar |= 1 << (vmdq - 32);
3755 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3757 return IXGBE_SUCCESS;
3761 * This function should only be involved in the IOV mode.
3762 * In IOV mode, Default pool is next pool after the number of
3763 * VFs advertized and not 0.
3764 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3766 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3767 * @hw: pointer to hardware struct
3768 * @vmdq: VMDq pool index
3770 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3772 u32 rar = hw->mac.san_mac_rar_index;
3774 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3777 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3778 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3780 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3781 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3784 return IXGBE_SUCCESS;
3788 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3789 * @hw: pointer to hardware structure
3791 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3795 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3796 DEBUGOUT(" Clearing UTA\n");
3798 for (i = 0; i < 128; i++)
3799 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3801 return IXGBE_SUCCESS;
3805 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3806 * @hw: pointer to hardware structure
3807 * @vlan: VLAN id to write to VLAN filter
3809 * return the VLVF index where this VLAN id should be placed
3812 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3815 u32 first_empty_slot = 0;
3818 /* short cut the special case */
3823 * Search for the vlan id in the VLVF entries. Save off the first empty
3824 * slot found along the way
3826 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3827 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3828 if (!bits && !(first_empty_slot))
3829 first_empty_slot = regindex;
3830 else if ((bits & 0x0FFF) == vlan)
3835 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3836 * in the VLVF. Else use the first empty VLVF register for this
3839 if (regindex >= IXGBE_VLVF_ENTRIES) {
3840 if (first_empty_slot)
3841 regindex = first_empty_slot;
3843 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3844 "No space in VLVF.\n");
3845 regindex = IXGBE_ERR_NO_SPACE;
3853 * ixgbe_set_vfta_generic - Set VLAN filter table
3854 * @hw: pointer to hardware structure
3855 * @vlan: VLAN id to write to VLAN filter
3856 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3857 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3859 * Turn on/off specified VLAN in the VLAN filter table.
3861 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3868 s32 ret_val = IXGBE_SUCCESS;
3869 bool vfta_changed = FALSE;
3871 DEBUGFUNC("ixgbe_set_vfta_generic");
3874 return IXGBE_ERR_PARAM;
3877 * this is a 2 part operation - first the VFTA, then the
3878 * VLVF and VLVFB if VT Mode is set
3879 * We don't write the VFTA until we know the VLVF part succeeded.
3883 * The VFTA is a bitstring made up of 128 32-bit registers
3884 * that enable the particular VLAN id, much like the MTA:
3885 * bits[11-5]: which register
3886 * bits[4-0]: which bit in the register
3888 regindex = (vlan >> 5) & 0x7F;
3889 bitindex = vlan & 0x1F;
3890 targetbit = (1 << bitindex);
3891 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3894 if (!(vfta & targetbit)) {
3896 vfta_changed = TRUE;
3899 if ((vfta & targetbit)) {
3901 vfta_changed = TRUE;
3906 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3908 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3910 if (ret_val != IXGBE_SUCCESS)
3914 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3916 return IXGBE_SUCCESS;
3920 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3921 * @hw: pointer to hardware structure
3922 * @vlan: VLAN id to write to VLAN filter
3923 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3924 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3925 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3928 * Turn on/off specified bit in VLVF table.
3930 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3931 bool vlan_on, bool *vfta_changed)
3935 DEBUGFUNC("ixgbe_set_vlvf_generic");
3938 return IXGBE_ERR_PARAM;
3940 /* If VT Mode is set
3942 * make sure the vlan is in VLVF
3943 * set the vind bit in the matching VLVFB
3945 * clear the pool bit and possibly the vind
3947 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3948 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3952 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3957 /* set the pool bit */
3959 bits = IXGBE_READ_REG(hw,
3960 IXGBE_VLVFB(vlvf_index * 2));
3961 bits |= (1 << vind);
3963 IXGBE_VLVFB(vlvf_index * 2),
3966 bits = IXGBE_READ_REG(hw,
3967 IXGBE_VLVFB((vlvf_index * 2) + 1));
3968 bits |= (1 << (vind - 32));
3970 IXGBE_VLVFB((vlvf_index * 2) + 1),
3974 /* clear the pool bit */
3976 bits = IXGBE_READ_REG(hw,
3977 IXGBE_VLVFB(vlvf_index * 2));
3978 bits &= ~(1 << vind);
3980 IXGBE_VLVFB(vlvf_index * 2),
3982 bits |= IXGBE_READ_REG(hw,
3983 IXGBE_VLVFB((vlvf_index * 2) + 1));
3985 bits = IXGBE_READ_REG(hw,
3986 IXGBE_VLVFB((vlvf_index * 2) + 1));
3987 bits &= ~(1 << (vind - 32));
3989 IXGBE_VLVFB((vlvf_index * 2) + 1),
3991 bits |= IXGBE_READ_REG(hw,
3992 IXGBE_VLVFB(vlvf_index * 2));
3997 * If there are still bits set in the VLVFB registers
3998 * for the VLAN ID indicated we need to see if the
3999 * caller is requesting that we clear the VFTA entry bit.
4000 * If the caller has requested that we clear the VFTA
4001 * entry bit but there are still pools/VFs using this VLAN
4002 * ID entry then ignore the request. We're not worried
4003 * about the case where we're turning the VFTA VLAN ID
4004 * entry bit on, only when requested to turn it off as
4005 * there may be multiple pools and/or VFs using the
4006 * VLAN ID entry. In that case we cannot clear the
4007 * VFTA bit until all pools/VFs using that VLAN ID have also
4008 * been cleared. This will be indicated by "bits" being
4012 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
4013 (IXGBE_VLVF_VIEN | vlan));
4014 if ((!vlan_on) && (vfta_changed != NULL)) {
4015 /* someone wants to clear the vfta entry
4016 * but some pools/VFs are still using it.
4018 *vfta_changed = FALSE;
4021 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4024 return IXGBE_SUCCESS;
4028 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4029 * @hw: pointer to hardware structure
4031 * Clears the VLAN filer table, and the VMDq index associated with the filter
4033 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4037 DEBUGFUNC("ixgbe_clear_vfta_generic");
4039 for (offset = 0; offset < hw->mac.vft_size; offset++)
4040 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4042 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4043 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4044 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4045 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4048 return IXGBE_SUCCESS;
4052 * ixgbe_check_mac_link_generic - Determine link and speed status
4053 * @hw: pointer to hardware structure
4054 * @speed: pointer to link speed
4055 * @link_up: TRUE when link is up
4056 * @link_up_wait_to_complete: bool used to wait for link up or not
4058 * Reads the links register to determine if link is up and the current speed
4060 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4061 bool *link_up, bool link_up_wait_to_complete)
4063 u32 links_reg, links_orig;
4066 DEBUGFUNC("ixgbe_check_mac_link_generic");
4068 /* clear the old state */
4069 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4071 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4073 if (links_orig != links_reg) {
4074 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4075 links_orig, links_reg);
4078 if (link_up_wait_to_complete) {
4079 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4080 if (links_reg & IXGBE_LINKS_UP) {
4087 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4090 if (links_reg & IXGBE_LINKS_UP)
4096 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4097 case IXGBE_LINKS_SPEED_10G_82599:
4098 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4099 if (hw->mac.type >= ixgbe_mac_X550) {
4100 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4101 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4104 case IXGBE_LINKS_SPEED_1G_82599:
4105 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4107 case IXGBE_LINKS_SPEED_100_82599:
4108 *speed = IXGBE_LINK_SPEED_100_FULL;
4109 if (hw->mac.type >= ixgbe_mac_X550) {
4110 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4111 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4115 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4118 return IXGBE_SUCCESS;
4122 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4124 * @hw: pointer to hardware structure
4125 * @wwnn_prefix: the alternative WWNN prefix
4126 * @wwpn_prefix: the alternative WWPN prefix
4128 * This function will read the EEPROM from the alternative SAN MAC address
4129 * block to check the support for the alternative WWNN/WWPN prefix support.
4131 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4135 u16 alt_san_mac_blk_offset;
4137 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4139 /* clear output first */
4140 *wwnn_prefix = 0xFFFF;
4141 *wwpn_prefix = 0xFFFF;
4143 /* check if alternative SAN MAC is supported */
4144 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4145 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4146 goto wwn_prefix_err;
4148 if ((alt_san_mac_blk_offset == 0) ||
4149 (alt_san_mac_blk_offset == 0xFFFF))
4150 goto wwn_prefix_out;
4152 /* check capability in alternative san mac address block */
4153 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4154 if (hw->eeprom.ops.read(hw, offset, &caps))
4155 goto wwn_prefix_err;
4156 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4157 goto wwn_prefix_out;
4159 /* get the corresponding prefix for WWNN/WWPN */
4160 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4161 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4162 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4163 "eeprom read at offset %d failed", offset);
4166 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4167 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4168 goto wwn_prefix_err;
4171 return IXGBE_SUCCESS;
4174 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4175 "eeprom read at offset %d failed", offset);
4176 return IXGBE_SUCCESS;
4180 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4181 * @hw: pointer to hardware structure
4182 * @bs: the fcoe boot status
4184 * This function will read the FCOE boot status from the iSCSI FCOE block
4186 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4188 u16 offset, caps, flags;
4191 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4193 /* clear output first */
4194 *bs = ixgbe_fcoe_bootstatus_unavailable;
4196 /* check if FCOE IBA block is present */
4197 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4198 status = hw->eeprom.ops.read(hw, offset, &caps);
4199 if (status != IXGBE_SUCCESS)
4202 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4205 /* check if iSCSI FCOE block is populated */
4206 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4207 if (status != IXGBE_SUCCESS)
4210 if ((offset == 0) || (offset == 0xFFFF))
4213 /* read fcoe flags in iSCSI FCOE block */
4214 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4215 status = hw->eeprom.ops.read(hw, offset, &flags);
4216 if (status != IXGBE_SUCCESS)
4219 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4220 *bs = ixgbe_fcoe_bootstatus_enabled;
4222 *bs = ixgbe_fcoe_bootstatus_disabled;
4229 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4230 * @hw: pointer to hardware structure
4231 * @enable: enable or disable switch for anti-spoofing
4232 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4235 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4238 int pf_target_reg = pf >> 3;
4239 int pf_target_shift = pf % 8;
4242 if (hw->mac.type == ixgbe_mac_82598EB)
4246 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4249 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4250 * MAC anti-spoof enables in each register array element.
4252 for (j = 0; j < pf_target_reg; j++)
4253 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4256 * The PF should be allowed to spoof so that it can support
4257 * emulation mode NICs. Do not set the bits assigned to the PF
4259 pfvfspoof &= (1 << pf_target_shift) - 1;
4260 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4263 * Remaining pools belong to the PF so they do not need to have
4264 * anti-spoofing enabled.
4266 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4267 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4271 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4272 * @hw: pointer to hardware structure
4273 * @enable: enable or disable switch for VLAN anti-spoofing
4274 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4277 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4279 int vf_target_reg = vf >> 3;
4280 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4283 if (hw->mac.type == ixgbe_mac_82598EB)
4286 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4288 pfvfspoof |= (1 << vf_target_shift);
4290 pfvfspoof &= ~(1 << vf_target_shift);
4291 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4295 * ixgbe_get_device_caps_generic - Get additional device capabilities
4296 * @hw: pointer to hardware structure
4297 * @device_caps: the EEPROM word with the extra device capabilities
4299 * This function will read the EEPROM location for the device capabilities,
4300 * and return the word through device_caps.
4302 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4304 DEBUGFUNC("ixgbe_get_device_caps_generic");
4306 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4308 return IXGBE_SUCCESS;
4312 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4313 * @hw: pointer to hardware structure
4316 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4321 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4323 /* Enable relaxed ordering */
4324 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4325 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4326 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4327 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4330 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4331 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4332 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4333 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4334 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4340 * ixgbe_calculate_checksum - Calculate checksum for buffer
4341 * @buffer: pointer to EEPROM
4342 * @length: size of EEPROM to calculate a checksum for
4343 * Calculates the checksum for some buffer on a specified length. The
4344 * checksum calculated is returned.
4346 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4351 DEBUGFUNC("ixgbe_calculate_checksum");
4356 for (i = 0; i < length; i++)
4359 return (u8) (0 - sum);
4363 * ixgbe_host_interface_command - Issue command to manageability block
4364 * @hw: pointer to the HW structure
4365 * @buffer: contains the command to write and where the return status will
4367 * @length: length of buffer, must be multiple of 4 bytes
4368 * @timeout: time in ms to wait for command completion
4369 * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4370 * Needed because FW structures are big endian and decoding of
4371 * these fields can be 8 bit or 16 bit based on command. Decoding
4372 * is not easily understood without making a table of commands.
4373 * So we will leave this up to the caller to read back the data
4376 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4377 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4379 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4380 u32 length, u32 timeout, bool return_data)
4382 u32 hicr, i, bi, fwsts;
4383 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4387 DEBUGFUNC("ixgbe_host_interface_command");
4389 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4390 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4391 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4393 /* Set bit 9 of FWSTS clearing FW reset indication */
4394 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4395 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4397 /* Check that the host interface is enabled. */
4398 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4399 if ((hicr & IXGBE_HICR_EN) == 0) {
4400 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4401 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4404 /* Calculate length in DWORDs. We must be DWORD aligned */
4405 if ((length % (sizeof(u32))) != 0) {
4406 DEBUGOUT("Buffer length failure, not aligned to dword");
4407 return IXGBE_ERR_INVALID_ARGUMENT;
4410 dword_len = length >> 2;
4412 /* The device driver writes the relevant command block
4413 * into the ram area.
4415 for (i = 0; i < dword_len; i++)
4416 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4417 i, IXGBE_CPU_TO_LE32(buffer[i]));
4419 /* Setting this bit tells the ARC that a new command is pending. */
4420 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4422 for (i = 0; i < timeout; i++) {
4423 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4424 if (!(hicr & IXGBE_HICR_C))
4429 /* Check command completion */
4430 if ((timeout != 0 && i == timeout) ||
4431 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4432 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4433 "Command has failed with no status valid.\n");
4434 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4440 /* Calculate length in DWORDs */
4441 dword_len = hdr_size >> 2;
4443 /* first pull in the header so we know the buffer length */
4444 for (bi = 0; bi < dword_len; bi++) {
4445 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4446 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4449 /* If there is any thing in data position pull it in */
4450 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4454 if (length < buf_len + hdr_size) {
4455 DEBUGOUT("Buffer not large enough for reply message.\n");
4456 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4459 /* Calculate length in DWORDs, add 3 for odd lengths */
4460 dword_len = (buf_len + 3) >> 2;
4462 /* Pull in the rest of the buffer (bi is where we left off) */
4463 for (; bi <= dword_len; bi++) {
4464 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4465 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4472 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4473 * @hw: pointer to the HW structure
4474 * @maj: driver version major number
4475 * @min: driver version minor number
4476 * @build: driver version build number
4477 * @sub: driver version sub build number
4479 * Sends driver version number to firmware through the manageability
4480 * block. On success return IXGBE_SUCCESS
4481 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4482 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4484 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4487 struct ixgbe_hic_drv_info fw_cmd;
4489 s32 ret_val = IXGBE_SUCCESS;
4491 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4493 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4495 ret_val = IXGBE_ERR_SWFW_SYNC;
4499 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4500 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4501 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4502 fw_cmd.port_num = (u8)hw->bus.func;
4503 fw_cmd.ver_maj = maj;
4504 fw_cmd.ver_min = min;
4505 fw_cmd.ver_build = build;
4506 fw_cmd.ver_sub = sub;
4507 fw_cmd.hdr.checksum = 0;
4508 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4509 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4513 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4514 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4516 IXGBE_HI_COMMAND_TIMEOUT,
4518 if (ret_val != IXGBE_SUCCESS)
4521 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4522 FW_CEM_RESP_STATUS_SUCCESS)
4523 ret_val = IXGBE_SUCCESS;
4525 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4530 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4536 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4537 * @hw: pointer to hardware structure
4538 * @num_pb: number of packet buffers to allocate
4539 * @headroom: reserve n KB of headroom
4540 * @strategy: packet buffer allocation strategy
4542 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4545 u32 pbsize = hw->mac.rx_pb_size;
4547 u32 rxpktsize, txpktsize, txpbthresh;
4549 /* Reserve headroom */
4555 /* Divide remaining packet buffer space amongst the number of packet
4556 * buffers requested using supplied strategy.
4559 case PBA_STRATEGY_WEIGHTED:
4560 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4561 * buffer with 5/8 of the packet buffer space.
4563 rxpktsize = (pbsize * 5) / (num_pb * 4);
4564 pbsize -= rxpktsize * (num_pb / 2);
4565 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4566 for (; i < (num_pb / 2); i++)
4567 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4568 /* Fall through to configure remaining packet buffers */
4569 case PBA_STRATEGY_EQUAL:
4570 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4571 for (; i < num_pb; i++)
4572 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4578 /* Only support an equally distributed Tx packet buffer strategy. */
4579 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4580 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4581 for (i = 0; i < num_pb; i++) {
4582 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4583 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4586 /* Clear unused TCs, if any, to zero buffer size*/
4587 for (; i < IXGBE_MAX_PB; i++) {
4588 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4589 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4590 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4595 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4596 * @hw: pointer to the hardware structure
4598 * The 82599 and x540 MACs can experience issues if TX work is still pending
4599 * when a reset occurs. This function prevents this by flushing the PCIe
4600 * buffers on the system.
4602 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4604 u32 gcr_ext, hlreg0, i, poll;
4608 * If double reset is not requested then all transactions should
4609 * already be clear and as such there is no work to do
4611 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4615 * Set loopback enable to prevent any transmits from being sent
4616 * should the link come up. This assumes that the RXCTRL.RXEN bit
4617 * has already been cleared.
4619 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4620 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4622 /* Wait for a last completion before clearing buffers */
4623 IXGBE_WRITE_FLUSH(hw);
4627 * Before proceeding, make sure that the PCIe block does not have
4628 * transactions pending.
4630 poll = ixgbe_pcie_timeout_poll(hw);
4631 for (i = 0; i < poll; i++) {
4633 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4634 if (IXGBE_REMOVED(hw->hw_addr))
4636 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4641 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4642 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4643 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4644 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4646 /* Flush all writes and allow 20usec for all transactions to clear */
4647 IXGBE_WRITE_FLUSH(hw);
4650 /* restore previous register values */
4651 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4652 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4657 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4658 * @hw: pointer to hardware structure
4659 * @map: pointer to u8 arr for returning map
4661 * Read the rtrup2tc HW register and resolve its content into map
4663 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4667 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4668 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4669 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4670 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4674 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4679 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4680 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4681 if (hw->mac.type != ixgbe_mac_82598EB) {
4682 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4683 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4684 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4685 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4686 hw->mac.set_lben = TRUE;
4688 hw->mac.set_lben = FALSE;
4691 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4692 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4696 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4701 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4702 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4704 if (hw->mac.type != ixgbe_mac_82598EB) {
4705 if (hw->mac.set_lben) {
4706 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4707 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4708 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4709 hw->mac.set_lben = FALSE;
4715 * ixgbe_mng_present - returns TRUE when management capability is present
4716 * @hw: pointer to hardware structure
4718 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4722 if (hw->mac.type < ixgbe_mac_82599EB)
4725 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4726 fwsm &= IXGBE_FWSM_MODE_MASK;
4727 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4731 * ixgbe_mng_enabled - Is the manageability engine enabled?
4732 * @hw: pointer to hardware structure
4734 * Returns TRUE if the manageability engine is enabled.
4736 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4738 u32 fwsm, manc, factps;
4740 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4741 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4744 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4745 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4748 if (hw->mac.type <= ixgbe_mac_X540) {
4749 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
4750 if (factps & IXGBE_FACTPS_MNGCG)
4758 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4759 * @hw: pointer to hardware structure
4760 * @speed: new link speed
4761 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
4763 * Set the link speed in the MAC and/or PHY register and restarts link.
4765 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4766 ixgbe_link_speed speed,
4767 bool autoneg_wait_to_complete)
4769 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4770 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4771 s32 status = IXGBE_SUCCESS;
4774 bool autoneg, link_up = FALSE;
4776 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
4778 /* Mask off requested but non-supported speeds */
4779 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
4780 if (status != IXGBE_SUCCESS)
4783 speed &= link_speed;
4785 /* Try each speed one by one, highest priority first. We do this in
4786 * software because 10Gb fiber doesn't support speed autonegotiation.
4788 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4790 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4792 /* If we already have link at this speed, just jump out */
4793 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4794 if (status != IXGBE_SUCCESS)
4797 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
4800 /* Set the module link speed */
4801 switch (hw->phy.media_type) {
4802 case ixgbe_media_type_fiber_fixed:
4803 case ixgbe_media_type_fiber:
4804 ixgbe_set_rate_select_speed(hw,
4805 IXGBE_LINK_SPEED_10GB_FULL);
4807 case ixgbe_media_type_fiber_qsfp:
4808 /* QSFP module automatically detects MAC link speed */
4811 DEBUGOUT("Unexpected media type.\n");
4815 /* Allow module to change analog characteristics (1G->10G) */
4818 status = ixgbe_setup_mac_link(hw,
4819 IXGBE_LINK_SPEED_10GB_FULL,
4820 autoneg_wait_to_complete);
4821 if (status != IXGBE_SUCCESS)
4824 /* Flap the Tx laser if it has not already been done */
4825 ixgbe_flap_tx_laser(hw);
4827 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4828 * Section 73.10.2, we may have to wait up to 500ms if KR is
4829 * attempted. 82599 uses the same timing for 10g SFI.
4831 for (i = 0; i < 5; i++) {
4832 /* Wait for the link partner to also set speed */
4835 /* If we have link, just jump out */
4836 status = ixgbe_check_link(hw, &link_speed,
4838 if (status != IXGBE_SUCCESS)
4846 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4848 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4849 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4851 /* If we already have link at this speed, just jump out */
4852 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4853 if (status != IXGBE_SUCCESS)
4856 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
4859 /* Set the module link speed */
4860 switch (hw->phy.media_type) {
4861 case ixgbe_media_type_fiber_fixed:
4862 case ixgbe_media_type_fiber:
4863 ixgbe_set_rate_select_speed(hw,
4864 IXGBE_LINK_SPEED_1GB_FULL);
4866 case ixgbe_media_type_fiber_qsfp:
4867 /* QSFP module automatically detects link speed */
4870 DEBUGOUT("Unexpected media type.\n");
4874 /* Allow module to change analog characteristics (10G->1G) */
4877 status = ixgbe_setup_mac_link(hw,
4878 IXGBE_LINK_SPEED_1GB_FULL,
4879 autoneg_wait_to_complete);
4880 if (status != IXGBE_SUCCESS)
4883 /* Flap the Tx laser if it has not already been done */
4884 ixgbe_flap_tx_laser(hw);
4886 /* Wait for the link partner to also set speed */
4889 /* If we have link, just jump out */
4890 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4891 if (status != IXGBE_SUCCESS)
4898 /* We didn't get link. Configure back to the highest speed we tried,
4899 * (if there was more than one). We call ourselves back with just the
4900 * single highest speed that the user requested.
4903 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4905 autoneg_wait_to_complete);
4908 /* Set autoneg_advertised value based on input link speed */
4909 hw->phy.autoneg_advertised = 0;
4911 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4914 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4921 * ixgbe_set_soft_rate_select_speed - Set module link speed
4922 * @hw: pointer to hardware structure
4923 * @speed: link speed to set
4925 * Set module link speed via the soft rate select.
4927 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4928 ixgbe_link_speed speed)
4934 case IXGBE_LINK_SPEED_10GB_FULL:
4935 /* one bit mask same as setting on */
4936 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4938 case IXGBE_LINK_SPEED_1GB_FULL:
4939 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4942 DEBUGOUT("Invalid fixed module speed\n");
4947 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4948 IXGBE_I2C_EEPROM_DEV_ADDR2,
4951 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
4955 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4957 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4958 IXGBE_I2C_EEPROM_DEV_ADDR2,
4961 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
4966 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4967 IXGBE_I2C_EEPROM_DEV_ADDR2,
4970 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
4974 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4976 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4977 IXGBE_I2C_EEPROM_DEV_ADDR2,
4980 DEBUGOUT("Failed to write Rx Rate Select RS1\n");