sys/dev/ixgbe/ixgbe_phy.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2017, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #include "ixgbe_api.h"
  36 #include "ixgbe_common.h"
  37 #include "ixgbe_phy.h"
  38
  39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  55  * @hw: pointer to the hardware structure
  56  * @byte: byte to send
  57  *
  58  * Returns an error code on error.
  59  */
  60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  61 {
  62         s32 status;
  63
  64         status = ixgbe_clock_out_i2c_byte(hw, byte);
  65         if (status)
  66                 return status;
  67         return ixgbe_get_i2c_ack(hw);
  68 }
  69
  70 /**
  71  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  72  * @hw: pointer to the hardware structure
  73  * @byte: pointer to a u8 to receive the byte
  74  *
  75  * Returns an error code on error.
  76  */
  77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  78 {
  79         s32 status;
  80
  81         status = ixgbe_clock_in_i2c_byte(hw, byte);
  82         if (status)
  83                 return status;
  84         /* ACK */
  85         return ixgbe_clock_out_i2c_bit(hw, FALSE);
  86 }
  87
  88 /**
  89  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  90  * @add1 - addend 1
  91  * @add2 - addend 2
  92  *
  93  * Returns one's complement 8-bit sum.
  94  */
  95 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  96 {
  97         u16 sum = add1 + add2;
  98
  99         sum = (sum & 0xFF) + (sum >> 8);
 100         return sum & 0xFF;
 101 }
 102
 103 /**
 104  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 105  * @hw: pointer to the hardware structure
 106  * @addr: I2C bus address to read from
 107  * @reg: I2C device register to read from
 108  * @val: pointer to location to receive read value
 109  * @lock: TRUE if to take and release semaphore
 110  *
 111  * Returns an error code on error.
 112  */
 113 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 114                                         u16 *val, bool lock)
 115 {
 116         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 117         int max_retry = 3;
 118         int retry = 0;
 119         u8 csum_byte;
 120         u8 high_bits;
 121         u8 low_bits;
 122         u8 reg_high;
 123         u8 csum;
 124
 125         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 126         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 127         csum = ~csum;
 128         do {
 129                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 130                         return IXGBE_ERR_SWFW_SYNC;
 131                 ixgbe_i2c_start(hw);
 132                 /* Device Address and write indication */
 133                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 134                         goto fail;
 135                 /* Write bits 14:8 */
 136                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 137                         goto fail;
 138                 /* Write bits 7:0 */
 139                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 140                         goto fail;
 141                 /* Write csum */
 142                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 143                         goto fail;
 144                 /* Re-start condition */
 145                 ixgbe_i2c_start(hw);
 146                 /* Device Address and read indication */
 147                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 148                         goto fail;
 149                 /* Get upper bits */
 150                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 151                         goto fail;
 152                 /* Get low bits */
 153                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 154                         goto fail;
 155                 /* Get csum */
 156                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 157                         goto fail;
 158                 /* NACK */
 159                 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
 160                         goto fail;
 161                 ixgbe_i2c_stop(hw);
 162                 if (lock)
 163                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 164                 *val = (high_bits << 8) | low_bits;
 165                 return 0;
 166
 167 fail:
 168                 ixgbe_i2c_bus_clear(hw);
 169                 if (lock)
 170                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 171                 retry++;
 172                 if (retry < max_retry)
 173                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 174                 else
 175                         DEBUGOUT("I2C byte read combined error.\n");
 176         } while (retry < max_retry);
 177
 178         return IXGBE_ERR_I2C;
 179 }
 180
 181 /**
 182  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 183  * @hw: pointer to the hardware structure
 184  * @addr: I2C bus address to write to
 185  * @reg: I2C device register to write to
 186  * @val: value to write
 187  * @lock: TRUE if to take and release semaphore
 188  *
 189  * Returns an error code on error.
 190  */
 191 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 192                                          u16 val, bool lock)
 193 {
 194         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 195         int max_retry = 1;
 196         int retry = 0;
 197         u8 reg_high;
 198         u8 csum;
 199
 200         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 201         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 202         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 203         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 204         csum = ~csum;
 205         do {
 206                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 207                         return IXGBE_ERR_SWFW_SYNC;
 208                 ixgbe_i2c_start(hw);
 209                 /* Device Address and write indication */
 210                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 211                         goto fail;
 212                 /* Write bits 14:8 */
 213                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 214                         goto fail;
 215                 /* Write bits 7:0 */
 216                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 217                         goto fail;
 218                 /* Write data 15:8 */
 219                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 220                         goto fail;
 221                 /* Write data 7:0 */
 222                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 223                         goto fail;
 224                 /* Write csum */
 225                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 226                         goto fail;
 227                 ixgbe_i2c_stop(hw);
 228                 if (lock)
 229                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 230                 return 0;
 231
 232 fail:
 233                 ixgbe_i2c_bus_clear(hw);
 234                 if (lock)
 235                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 236                 retry++;
 237                 if (retry < max_retry)
 238                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 239                 else
 240                         DEBUGOUT("I2C byte write combined error.\n");
 241         } while (retry < max_retry);
 242
 243         return IXGBE_ERR_I2C;
 244 }
 245
 246 /**
 247  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 248  *  @hw: pointer to the hardware structure
 249  *
 250  *  Initialize the function pointers.
 251  **/
 252 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 253 {
 254         struct ixgbe_phy_info *phy = &hw->phy;
 255
 256         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 257
 258         /* PHY */
 259         phy->ops.identify = ixgbe_identify_phy_generic;
 260         phy->ops.reset = ixgbe_reset_phy_generic;
 261         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 262         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 263         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 264         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 265         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 266         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 267         phy->ops.check_link = NULL;
 268         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 269         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 270         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 271         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 272         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 273         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 274         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 275         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 276         phy->sfp_type = ixgbe_sfp_type_unknown;
 277         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 278         phy->ops.write_i2c_byte_unlocked =
 279                                 ixgbe_write_i2c_byte_generic_unlocked;
 280         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 281         return IXGBE_SUCCESS;
 282 }
 283
 284 /**
 285  * ixgbe_probe_phy - Probe a single address for a PHY
 286  * @hw: pointer to hardware structure
 287  * @phy_addr: PHY address to probe
 288  *
 289  * Returns TRUE if PHY found
 290  */
 291 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 292 {
 293         u16 ext_ability = 0;
 294
 295         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 296                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 297                         phy_addr);
 298                 return FALSE;
 299         }
 300
 301         if (ixgbe_get_phy_id(hw))
 302                 return FALSE;
 303
 304         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 305
 306         if (hw->phy.type == ixgbe_phy_unknown) {
 307                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 308                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 309                 if (ext_ability &
 310                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 311                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 312                         hw->phy.type = ixgbe_phy_cu_unknown;
 313                 else
 314                         hw->phy.type = ixgbe_phy_generic;
 315         }
 316
 317         return TRUE;
 318 }
 319
 320 /**
 321  *  ixgbe_identify_phy_generic - Get physical layer module
 322  *  @hw: pointer to hardware structure
 323  *
 324  *  Determines the physical layer module found on the current adapter.
 325  **/
 326 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 327 {
 328         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 329         u16 phy_addr;
 330
 331         DEBUGFUNC("ixgbe_identify_phy_generic");
 332
 333         if (!hw->phy.phy_semaphore_mask) {
 334                 if (hw->bus.lan_id)
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 336                 else
 337                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 338         }
 339
 340         if (hw->phy.type != ixgbe_phy_unknown)
 341                 return IXGBE_SUCCESS;
 342
 343         if (hw->phy.nw_mng_if_sel) {
 344                 phy_addr = (hw->phy.nw_mng_if_sel &
 345                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 346                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 347                 if (ixgbe_probe_phy(hw, phy_addr))
 348                         return IXGBE_SUCCESS;
 349                 else
 350                         return IXGBE_ERR_PHY_ADDR_INVALID;
 351         }
 352
 353         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 354                 if (ixgbe_probe_phy(hw, phy_addr)) {
 355                         status = IXGBE_SUCCESS;
 356                         break;
 357                 }
 358         }
 359
 360         /* Certain media types do not have a phy so an address will not
 361          * be found and the code will take this path.  Caller has to
 362          * decide if it is an error or not.
 363          */
 364         if (status != IXGBE_SUCCESS)
 365                 hw->phy.addr = 0;
 366
 367         return status;
 368 }
 369
 370 /**
 371  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 372  * @hw: pointer to the hardware structure
 373  *
 374  * This function checks the MMNGC.MNG_VETO bit to see if there are
 375  * any constraints on link from manageability.  For MAC's that don't
 376  * have this bit just return faluse since the link can not be blocked
 377  * via this method.
 378  **/
 379 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 380 {
 381         u32 mmngc;
 382
 383         DEBUGFUNC("ixgbe_check_reset_blocked");
 384
 385         /* If we don't have this bit, it can't be blocking */
 386         if (hw->mac.type == ixgbe_mac_82598EB)
 387                 return FALSE;
 388
 389         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 390         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 391                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 392                               "MNG_VETO bit detected.\n");
 393                 return TRUE;
 394         }
 395
 396         return FALSE;
 397 }
 398
 399 /**
 400  *  ixgbe_validate_phy_addr - Determines phy address is valid
 401  *  @hw: pointer to hardware structure
 402  *
 403  **/
 404 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 405 {
 406         u16 phy_id = 0;
 407         bool valid = FALSE;
 408
 409         DEBUGFUNC("ixgbe_validate_phy_addr");
 410
 411         hw->phy.addr = phy_addr;
 412         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 413                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 414
 415         if (phy_id != 0xFFFF && phy_id != 0x0)
 416                 valid = TRUE;
 417
 418         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 419
 420         return valid;
 421 }
 422
 423 /**
 424  *  ixgbe_get_phy_id - Get the phy type
 425  *  @hw: pointer to hardware structure
 426  *
 427  **/
 428 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 429 {
 430         u32 status;
 431         u16 phy_id_high = 0;
 432         u16 phy_id_low = 0;
 433
 434         DEBUGFUNC("ixgbe_get_phy_id");
 435
 436         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 437                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 438                                       &phy_id_high);
 439
 440         if (status == IXGBE_SUCCESS) {
 441                 hw->phy.id = (u32)(phy_id_high << 16);
 442                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 443                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 444                                               &phy_id_low);
 445                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 446                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 447         }
 448         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 449                   phy_id_high, phy_id_low);
 450
 451         return status;
 452 }
 453
 454 /**
 455  *  ixgbe_get_phy_type_from_id - Get the phy type
 456  *  @phy_id: PHY ID information
 457  *
 458  **/
 459 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 460 {
 461         enum ixgbe_phy_type phy_type;
 462
 463         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 464
 465         switch (phy_id) {
 466         case TN1010_PHY_ID:
 467                 phy_type = ixgbe_phy_tn;
 468                 break;
 469         case X550_PHY_ID2:
 470         case X550_PHY_ID3:
 471         case X540_PHY_ID:
 472                 phy_type = ixgbe_phy_aq;
 473                 break;
 474         case QT2022_PHY_ID:
 475                 phy_type = ixgbe_phy_qt;
 476                 break;
 477         case ATH_PHY_ID:
 478                 phy_type = ixgbe_phy_nl;
 479                 break;
 480         case X557_PHY_ID:
 481         case X557_PHY_ID2:
 482                 phy_type = ixgbe_phy_x550em_ext_t;
 483                 break;
 484         default:
 485                 phy_type = ixgbe_phy_unknown;
 486                 break;
 487         }
 488         return phy_type;
 489 }
 490
 491 /**
 492  *  ixgbe_reset_phy_generic - Performs a PHY reset
 493  *  @hw: pointer to hardware structure
 494  **/
 495 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 496 {
 497         u32 i;
 498         u16 ctrl = 0;
 499         s32 status = IXGBE_SUCCESS;
 500
 501         DEBUGFUNC("ixgbe_reset_phy_generic");
 502
 503         if (hw->phy.type == ixgbe_phy_unknown)
 504                 status = ixgbe_identify_phy_generic(hw);
 505
 506         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 507                 goto out;
 508
 509         /* Don't reset PHY if it's shut down due to overtemp. */
 510         if (!hw->phy.reset_if_overtemp &&
 511             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 512                 goto out;
 513
 514         /* Blocked by MNG FW so bail */
 515         if (ixgbe_check_reset_blocked(hw))
 516                 goto out;
 517
 518         /*
 519          * Perform soft PHY reset to the PHY_XS.
 520          * This will cause a soft reset to the PHY
 521          */
 522         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 523                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 524                               IXGBE_MDIO_PHY_XS_RESET);
 525
 526         /*
 527          * Poll for reset bit to self-clear indicating reset is complete.
 528          * Some PHYs could take up to 3 seconds to complete and need about
 529          * 1.7 usec delay after the reset is complete.
 530          */
 531         for (i = 0; i < 30; i++) {
 532                 msec_delay(100);
 533                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 534                         status = hw->phy.ops.read_reg(hw,
 535                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 536                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 537                                                   &ctrl);
 538                         if (status != IXGBE_SUCCESS)
 539                                 return status;
 540
 541                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 542                                 usec_delay(2);
 543                                 break;
 544                         }
 545                 } else {
 546                         status = hw->phy.ops.read_reg(hw,
 547                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 548                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 549                                                      &ctrl);
 550                         if (status != IXGBE_SUCCESS)
 551                                 return status;
 552
 553                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 554                                 usec_delay(2);
 555                                 break;
 556                         }
 557                 }
 558         }
 559
 560         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 561                 status = IXGBE_ERR_RESET_FAILED;
 562                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 563                              "PHY reset polling failed to complete.\n");
 564         }
 565
 566 out:
 567         return status;
 568 }
 569
 570 /**
 571  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 572  *  the SWFW lock
 573  *  @hw: pointer to hardware structure
 574  *  @reg_addr: 32 bit address of PHY register to read
 575  *  @phy_data: Pointer to read data from PHY register
 576  **/
 577 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 578                            u16 *phy_data)
 579 {
 580         u32 i, data, command;
 581
 582         /* Setup and write the address cycle command */
 583         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 584                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 585                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 586                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 587
 588         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 589
 590         /*
 591          * Check every 10 usec to see if the address cycle completed.
 592          * The MDI Command bit will clear when the operation is
 593          * complete
 594          */
 595         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 596                 usec_delay(10);
 597
 598                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 599                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 600                         break;
 601         }
 602
 603
 604         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 605                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 606                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 607                 return IXGBE_ERR_PHY;
 608         }
 609
 610         /*
 611          * Address cycle complete, setup and write the read
 612          * command
 613          */
 614         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 615                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 616                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 617                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 618
 619         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 620
 621         /*
 622          * Check every 10 usec to see if the address cycle
 623          * completed. The MDI Command bit will clear when the
 624          * operation is complete
 625          */
 626         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 627                 usec_delay(10);
 628
 629                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 630                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 631                         break;
 632         }
 633
 634         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 635                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 636                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 637                 return IXGBE_ERR_PHY;
 638         }
 639
 640         /*
 641          * Read operation is complete.  Get the data
 642          * from MSRWD
 643          */
 644         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 645         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 646         *phy_data = (u16)(data);
 647
 648         return IXGBE_SUCCESS;
 649 }
 650
 651 /**
 652  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 653  *  using the SWFW lock - this function is needed in most cases
 654  *  @hw: pointer to hardware structure
 655  *  @reg_addr: 32 bit address of PHY register to read
 656  *  @phy_data: Pointer to read data from PHY register
 657  **/
 658 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 659                                u32 device_type, u16 *phy_data)
 660 {
 661         s32 status;
 662         u32 gssr = hw->phy.phy_semaphore_mask;
 663
 664         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 665
 666         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 667                 return IXGBE_ERR_SWFW_SYNC;
 668
 669         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 670
 671         hw->mac.ops.release_swfw_sync(hw, gssr);
 672
 673         return status;
 674 }
 675
 676 /**
 677  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 678  *  without SWFW lock
 679  *  @hw: pointer to hardware structure
 680  *  @reg_addr: 32 bit PHY register to write
 681  *  @device_type: 5 bit device type
 682  *  @phy_data: Data to write to the PHY register
 683  **/
 684 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 685                                 u32 device_type, u16 phy_data)
 686 {
 687         u32 i, command;
 688
 689         /* Put the data in the MDI single read and write data register*/
 690         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 691
 692         /* Setup and write the address cycle command */
 693         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 694                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 695                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 696                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 697
 698         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 699
 700         /*
 701          * Check every 10 usec to see if the address cycle completed.
 702          * The MDI Command bit will clear when the operation is
 703          * complete
 704          */
 705         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 706                 usec_delay(10);
 707
 708                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 709                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 710                         break;
 711         }
 712
 713         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 714                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 715                 return IXGBE_ERR_PHY;
 716         }
 717
 718         /*
 719          * Address cycle complete, setup and write the write
 720          * command
 721          */
 722         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 723                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 724                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 725                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 726
 727         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 728
 729         /*
 730          * Check every 10 usec to see if the address cycle
 731          * completed. The MDI Command bit will clear when the
 732          * operation is complete
 733          */
 734         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 735                 usec_delay(10);
 736
 737                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 738                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 739                         break;
 740         }
 741
 742         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 743                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 744                 return IXGBE_ERR_PHY;
 745         }
 746
 747         return IXGBE_SUCCESS;
 748 }
 749
 750 /**
 751  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 752  *  using SWFW lock- this function is needed in most cases
 753  *  @hw: pointer to hardware structure
 754  *  @reg_addr: 32 bit PHY register to write
 755  *  @device_type: 5 bit device type
 756  *  @phy_data: Data to write to the PHY register
 757  **/
 758 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 759                                 u32 device_type, u16 phy_data)
 760 {
 761         s32 status;
 762         u32 gssr = hw->phy.phy_semaphore_mask;
 763
 764         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 765
 766         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 767                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 768                                                  phy_data);
 769                 hw->mac.ops.release_swfw_sync(hw, gssr);
 770         } else {
 771                 status = IXGBE_ERR_SWFW_SYNC;
 772         }
 773
 774         return status;
 775 }
 776
 777 /**
 778  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 779  *  @hw: pointer to hardware structure
 780  *
 781  *  Restart auto-negotiation and PHY and waits for completion.
 782  **/
 783 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 784 {
 785         s32 status = IXGBE_SUCCESS;
 786         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 787         bool autoneg = FALSE;
 788         ixgbe_link_speed speed;
 789
 790         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 791
 792         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 793
 794         /* Set or unset auto-negotiation 10G advertisement */
 795         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 796                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 797                              &autoneg_reg);
 798
 799         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 800         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 801             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 802                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 803
 804         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 805                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 806                               autoneg_reg);
 807
 808         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 809                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 810                              &autoneg_reg);
 811
 812         if (hw->mac.type == ixgbe_mac_X550) {
 813                 /* Set or unset auto-negotiation 5G advertisement */
 814                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 815                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 816                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 817                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 818
 819                 /* Set or unset auto-negotiation 2.5G advertisement */
 820                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 821                 if ((hw->phy.autoneg_advertised &
 822                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 823                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 824                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 825         }
 826
 827         /* Set or unset auto-negotiation 1G advertisement */
 828         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 829         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 830             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 831                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 832
 833         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 834                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 835                               autoneg_reg);
 836
 837         /* Set or unset auto-negotiation 100M advertisement */
 838         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 839                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 840                              &autoneg_reg);
 841
 842         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 843                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 844         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 845             (speed & IXGBE_LINK_SPEED_100_FULL))
 846                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 847
 848         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 849                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 850                               autoneg_reg);
 851
 852         /* Blocked by MNG FW so don't reset PHY */
 853         if (ixgbe_check_reset_blocked(hw))
 854                 return status;
 855
 856         /* Restart PHY auto-negotiation. */
 857         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 858                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 859
 860         autoneg_reg |= IXGBE_MII_RESTART;
 861
 862         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 863                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 864
 865         return status;
 866 }
 867
 868 /**
 869  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 870  *  @hw: pointer to hardware structure
 871  *  @speed: new link speed
 872  **/
 873 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 874                                        ixgbe_link_speed speed,
 875                                        bool autoneg_wait_to_complete)
 876 {
 877         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 878
 879         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 880
 881         /*
 882          * Clear autoneg_advertised and set new values based on input link
 883          * speed.
 884          */
 885         hw->phy.autoneg_advertised = 0;
 886
 887         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 888                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 889
 890         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 891                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 892
 893         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 894                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 895
 896         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 897                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 898
 899         if (speed & IXGBE_LINK_SPEED_100_FULL)
 900                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 901
 902         if (speed & IXGBE_LINK_SPEED_10_FULL)
 903                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 904
 905         /* Setup link based on the new speed settings */
 906         ixgbe_setup_phy_link(hw);
 907
 908         return IXGBE_SUCCESS;
 909 }
 910
 911 /**
 912  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 913  * @hw: pointer to hardware structure
 914  *
 915  * Determines the supported link capabilities by reading the PHY auto
 916  * negotiation register.
 917  **/
 918 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 919 {
 920         s32 status;
 921         u16 speed_ability;
 922
 923         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 924                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 925                                       &speed_ability);
 926         if (status)
 927                 return status;
 928
 929         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 930                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 931         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 932                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 933         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 934                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 935
 936         switch (hw->mac.type) {
 937         case ixgbe_mac_X550:
 938                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 939                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 940                 break;
 941         case ixgbe_mac_X550EM_x:
 942         case ixgbe_mac_X550EM_a:
 943                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 944                 break;
 945         default:
 946                 break;
 947         }
 948
 949         return status;
 950 }
 951
 952 /**
 953  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 954  *  @hw: pointer to hardware structure
 955  *  @speed: pointer to link speed
 956  *  @autoneg: boolean auto-negotiation value
 957  **/
 958 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 959                                                ixgbe_link_speed *speed,
 960                                                bool *autoneg)
 961 {
 962         s32 status = IXGBE_SUCCESS;
 963
 964         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 965
 966         *autoneg = TRUE;
 967         if (!hw->phy.speeds_supported)
 968                 status = ixgbe_get_copper_speeds_supported(hw);
 969
 970         *speed = hw->phy.speeds_supported;
 971         return status;
 972 }
 973
 974 /**
 975  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 976  *  @hw: pointer to hardware structure
 977  *
 978  *  Reads the VS1 register to determine if link is up and the current speed for
 979  *  the PHY.
 980  **/
 981 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 982                              bool *link_up)
 983 {
 984         s32 status = IXGBE_SUCCESS;
 985         u32 time_out;
 986         u32 max_time_out = 10;
 987         u16 phy_link = 0;
 988         u16 phy_speed = 0;
 989         u16 phy_data = 0;
 990
 991         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 992
 993         /* Initialize speed and link to default case */
 994         *link_up = FALSE;
 995         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 996
 997         /*
 998          * Check current speed and link status of the PHY register.
 999          * This is a vendor specific register and may have to
1000          * be changed for other copper PHYs.
1001          */
1002         for (time_out = 0; time_out < max_time_out; time_out++) {
1003                 usec_delay(10);
1004                 status = hw->phy.ops.read_reg(hw,
1005                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1006                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1007                                         &phy_data);
1008                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1009                 phy_speed = phy_data &
1010                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1011                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1012                         *link_up = TRUE;
1013                         if (phy_speed ==
1014                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1015                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1016                         break;
1017                 }
1018         }
1019
1020         return status;
1021 }
1022
1023 /**
1024  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1025  *      @hw: pointer to hardware structure
1026  *
1027  *      Restart auto-negotiation and PHY and waits for completion.
1028  **/
1029 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1030 {
1031         s32 status = IXGBE_SUCCESS;
1032         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1033         bool autoneg = FALSE;
1034         ixgbe_link_speed speed;
1035
1036         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1037
1038         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1039
1040         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1041                 /* Set or unset auto-negotiation 10G advertisement */
1042                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1043                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1044                                      &autoneg_reg);
1045
1046                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1047                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1048                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1049
1050                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1051                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1052                                       autoneg_reg);
1053         }
1054
1055         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1056                 /* Set or unset auto-negotiation 1G advertisement */
1057                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1058                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1059                                      &autoneg_reg);
1060
1061                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1062                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1063                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1064
1065                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1066                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1067                                       autoneg_reg);
1068         }
1069
1070         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1071                 /* Set or unset auto-negotiation 100M advertisement */
1072                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1073                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1074                                      &autoneg_reg);
1075
1076                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1077                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1078                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1079
1080                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1081                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1082                                       autoneg_reg);
1083         }
1084
1085         /* Blocked by MNG FW so don't reset PHY */
1086         if (ixgbe_check_reset_blocked(hw))
1087                 return status;
1088
1089         /* Restart PHY auto-negotiation. */
1090         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1091                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1092
1093         autoneg_reg |= IXGBE_MII_RESTART;
1094
1095         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1096                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1097
1098         return status;
1099 }
1100
1101 /**
1102  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1103  *  @hw: pointer to hardware structure
1104  *  @firmware_version: pointer to the PHY Firmware Version
1105  **/
1106 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1107                                        u16 *firmware_version)
1108 {
1109         s32 status;
1110
1111         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1112
1113         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1114                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1115                                       firmware_version);
1116
1117         return status;
1118 }
1119
1120 /**
1121  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1122  *  @hw: pointer to hardware structure
1123  *  @firmware_version: pointer to the PHY Firmware Version
1124  **/
1125 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1126                                            u16 *firmware_version)
1127 {
1128         s32 status;
1129
1130         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1131
1132         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1133                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1134                                       firmware_version);
1135
1136         return status;
1137 }
1138
1139 /**
1140  *  ixgbe_reset_phy_nl - Performs a PHY reset
1141  *  @hw: pointer to hardware structure
1142  **/
1143 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1144 {
1145         u16 phy_offset, control, eword, edata, block_crc;
1146         bool end_data = FALSE;
1147         u16 list_offset, data_offset;
1148         u16 phy_data = 0;
1149         s32 ret_val = IXGBE_SUCCESS;
1150         u32 i;
1151
1152         DEBUGFUNC("ixgbe_reset_phy_nl");
1153
1154         /* Blocked by MNG FW so bail */
1155         if (ixgbe_check_reset_blocked(hw))
1156                 goto out;
1157
1158         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1159                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1160
1161         /* reset the PHY and poll for completion */
1162         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1163                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1164                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1165
1166         for (i = 0; i < 100; i++) {
1167                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1169                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1170                         break;
1171                 msec_delay(10);
1172         }
1173
1174         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1175                 DEBUGOUT("PHY reset did not complete.\n");
1176                 ret_val = IXGBE_ERR_PHY;
1177                 goto out;
1178         }
1179
1180         /* Get init offsets */
1181         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1182                                                       &data_offset);
1183         if (ret_val != IXGBE_SUCCESS)
1184                 goto out;
1185
1186         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1187         data_offset++;
1188         while (!end_data) {
1189                 /*
1190                  * Read control word from PHY init contents offset
1191                  */
1192                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1193                 if (ret_val)
1194                         goto err_eeprom;
1195                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1196                            IXGBE_CONTROL_SHIFT_NL;
1197                 edata = eword & IXGBE_DATA_MASK_NL;
1198                 switch (control) {
1199                 case IXGBE_DELAY_NL:
1200                         data_offset++;
1201                         DEBUGOUT1("DELAY: %d MS\n", edata);
1202                         msec_delay(edata);
1203                         break;
1204                 case IXGBE_DATA_NL:
1205                         DEBUGOUT("DATA:\n");
1206                         data_offset++;
1207                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1208                                                       &phy_offset);
1209                         if (ret_val)
1210                                 goto err_eeprom;
1211                         data_offset++;
1212                         for (i = 0; i < edata; i++) {
1213                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1214                                                               &eword);
1215                                 if (ret_val)
1216                                         goto err_eeprom;
1217                                 hw->phy.ops.write_reg(hw, phy_offset,
1218                                                       IXGBE_TWINAX_DEV, eword);
1219                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1220                                           phy_offset);
1221                                 data_offset++;
1222                                 phy_offset++;
1223                         }
1224                         break;
1225                 case IXGBE_CONTROL_NL:
1226                         data_offset++;
1227                         DEBUGOUT("CONTROL:\n");
1228                         if (edata == IXGBE_CONTROL_EOL_NL) {
1229                                 DEBUGOUT("EOL\n");
1230                                 end_data = TRUE;
1231                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1232                                 DEBUGOUT("SOL\n");
1233                         } else {
1234                                 DEBUGOUT("Bad control value\n");
1235                                 ret_val = IXGBE_ERR_PHY;
1236                                 goto out;
1237                         }
1238                         break;
1239                 default:
1240                         DEBUGOUT("Bad control type\n");
1241                         ret_val = IXGBE_ERR_PHY;
1242                         goto out;
1243                 }
1244         }
1245
1246 out:
1247         return ret_val;
1248
1249 err_eeprom:
1250         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1251                       "eeprom read at offset %d failed", data_offset);
1252         return IXGBE_ERR_PHY;
1253 }
1254
1255 /**
1256  *  ixgbe_identify_module_generic - Identifies module type
1257  *  @hw: pointer to hardware structure
1258  *
1259  *  Determines HW type and calls appropriate function.
1260  **/
1261 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1262 {
1263         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1264
1265         DEBUGFUNC("ixgbe_identify_module_generic");
1266
1267         switch (hw->mac.ops.get_media_type(hw)) {
1268         case ixgbe_media_type_fiber:
1269                 status = ixgbe_identify_sfp_module_generic(hw);
1270                 break;
1271
1272         case ixgbe_media_type_fiber_qsfp:
1273                 status = ixgbe_identify_qsfp_module_generic(hw);
1274                 break;
1275
1276         default:
1277                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1278                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1279                 break;
1280         }
1281
1282         return status;
1283 }
1284
1285 /**
1286  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1287  *  @hw: pointer to hardware structure
1288  *
1289  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1290  **/
1291 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1292 {
1293         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1294         u32 vendor_oui = 0;
1295         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1296         u8 identifier = 0;
1297         u8 comp_codes_1g = 0;
1298         u8 comp_codes_10g = 0;
1299         u8 oui_bytes[3] = {0, 0, 0};
1300         u8 cable_tech = 0;
1301         u8 cable_spec = 0;
1302         u16 enforce_sfp = 0;
1303
1304         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1305
1306         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1307                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1308                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1309                 goto out;
1310         }
1311
1312         /* LAN ID is needed for I2C access */
1313         hw->mac.ops.set_lan_id(hw);
1314
1315         status = hw->phy.ops.read_i2c_eeprom(hw,
1316                                              IXGBE_SFF_IDENTIFIER,
1317                                              &identifier);
1318
1319         if (status != IXGBE_SUCCESS)
1320                 goto err_read_i2c_eeprom;
1321
1322         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1323                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1324                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1325         } else {
1326                 status = hw->phy.ops.read_i2c_eeprom(hw,
1327                                                      IXGBE_SFF_1GBE_COMP_CODES,
1328                                                      &comp_codes_1g);
1329
1330                 if (status != IXGBE_SUCCESS)
1331                         goto err_read_i2c_eeprom;
1332
1333                 status = hw->phy.ops.read_i2c_eeprom(hw,
1334                                                      IXGBE_SFF_10GBE_COMP_CODES,
1335                                                      &comp_codes_10g);
1336
1337                 if (status != IXGBE_SUCCESS)
1338                         goto err_read_i2c_eeprom;
1339                 status = hw->phy.ops.read_i2c_eeprom(hw,
1340                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1341                                                      &cable_tech);
1342
1343                 if (status != IXGBE_SUCCESS)
1344                         goto err_read_i2c_eeprom;
1345
1346                  /* ID Module
1347                   * =========
1348                   * 0   SFP_DA_CU
1349                   * 1   SFP_SR
1350                   * 2   SFP_LR
1351                   * 3   SFP_DA_CORE0 - 82599-specific
1352                   * 4   SFP_DA_CORE1 - 82599-specific
1353                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1354                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1355                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1356                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1357                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1358                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1359                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1360                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1361                   */
1362                 if (hw->mac.type == ixgbe_mac_82598EB) {
1363                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1364                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1365                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1366                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1367                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1368                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1369                         else
1370                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1371                 } else {
1372                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1373                                 if (hw->bus.lan_id == 0)
1374                                         hw->phy.sfp_type =
1375                                                      ixgbe_sfp_type_da_cu_core0;
1376                                 else
1377                                         hw->phy.sfp_type =
1378                                                      ixgbe_sfp_type_da_cu_core1;
1379                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1380                                 hw->phy.ops.read_i2c_eeprom(
1381                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1382                                                 &cable_spec);
1383                                 if (cable_spec &
1384                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1385                                         if (hw->bus.lan_id == 0)
1386                                                 hw->phy.sfp_type =
1387                                                 ixgbe_sfp_type_da_act_lmt_core0;
1388                                         else
1389                                                 hw->phy.sfp_type =
1390                                                 ixgbe_sfp_type_da_act_lmt_core1;
1391                                 } else {
1392                                         hw->phy.sfp_type =
1393                                                         ixgbe_sfp_type_unknown;
1394                                 }
1395                         } else if (comp_codes_10g &
1396                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1397                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1398                                 if (hw->bus.lan_id == 0)
1399                                         hw->phy.sfp_type =
1400                                                       ixgbe_sfp_type_srlr_core0;
1401                                 else
1402                                         hw->phy.sfp_type =
1403                                                       ixgbe_sfp_type_srlr_core1;
1404                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1405                                 if (hw->bus.lan_id == 0)
1406                                         hw->phy.sfp_type =
1407                                                 ixgbe_sfp_type_1g_cu_core0;
1408                                 else
1409                                         hw->phy.sfp_type =
1410                                                 ixgbe_sfp_type_1g_cu_core1;
1411                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1412                                 if (hw->bus.lan_id == 0)
1413                                         hw->phy.sfp_type =
1414                                                 ixgbe_sfp_type_1g_sx_core0;
1415                                 else
1416                                         hw->phy.sfp_type =
1417                                                 ixgbe_sfp_type_1g_sx_core1;
1418                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1419                                 if (hw->bus.lan_id == 0)
1420                                         hw->phy.sfp_type =
1421                                                 ixgbe_sfp_type_1g_lx_core0;
1422                                 else
1423                                         hw->phy.sfp_type =
1424                                                 ixgbe_sfp_type_1g_lx_core1;
1425                         } else {
1426                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1427                         }
1428                 }
1429
1430                 if (hw->phy.sfp_type != stored_sfp_type)
1431                         hw->phy.sfp_setup_needed = TRUE;
1432
1433                 /* Determine if the SFP+ PHY is dual speed or not. */
1434                 hw->phy.multispeed_fiber = FALSE;
1435                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1436                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1437                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1438                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1439                         hw->phy.multispeed_fiber = TRUE;
1440
1441                 /* Determine PHY vendor */
1442                 if (hw->phy.type != ixgbe_phy_nl) {
1443                         hw->phy.id = identifier;
1444                         status = hw->phy.ops.read_i2c_eeprom(hw,
1445                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1446                                                     &oui_bytes[0]);
1447
1448                         if (status != IXGBE_SUCCESS)
1449                                 goto err_read_i2c_eeprom;
1450
1451                         status = hw->phy.ops.read_i2c_eeprom(hw,
1452                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1453                                                     &oui_bytes[1]);
1454
1455                         if (status != IXGBE_SUCCESS)
1456                                 goto err_read_i2c_eeprom;
1457
1458                         status = hw->phy.ops.read_i2c_eeprom(hw,
1459                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1460                                                     &oui_bytes[2]);
1461
1462                         if (status != IXGBE_SUCCESS)
1463                                 goto err_read_i2c_eeprom;
1464
1465                         vendor_oui =
1466                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1467                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1468                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1469
1470                         switch (vendor_oui) {
1471                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1472                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1473                                         hw->phy.type =
1474                                                     ixgbe_phy_sfp_passive_tyco;
1475                                 break;
1476                         case IXGBE_SFF_VENDOR_OUI_FTL:
1477                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1478                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1479                                 else
1480                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1481                                 break;
1482                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1483                                 hw->phy.type = ixgbe_phy_sfp_avago;
1484                                 break;
1485                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1486                                 hw->phy.type = ixgbe_phy_sfp_intel;
1487                                 break;
1488                         default:
1489                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1490                                         hw->phy.type =
1491                                                  ixgbe_phy_sfp_passive_unknown;
1492                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1493                                         hw->phy.type =
1494                                                 ixgbe_phy_sfp_active_unknown;
1495                                 else
1496                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1497                                 break;
1498                         }
1499                 }
1500
1501                 /* Allow any DA cable vendor */
1502                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1503                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1504                         status = IXGBE_SUCCESS;
1505                         goto out;
1506                 }
1507
1508                 /* Verify supported 1G SFP modules */
1509                 if (comp_codes_10g == 0 &&
1510                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1512                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1513                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1514                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1515                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1516                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1517                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1518                         goto out;
1519                 }
1520
1521                 /* Anything else 82598-based is supported */
1522                 if (hw->mac.type == ixgbe_mac_82598EB) {
1523                         status = IXGBE_SUCCESS;
1524                         goto out;
1525                 }
1526
1527                 ixgbe_get_device_caps(hw, &enforce_sfp);
1528                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1529                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1530                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1531                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1532                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1533                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1534                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1535                         /* Make sure we're a supported PHY type */
1536                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1537                                 status = IXGBE_SUCCESS;
1538                         } else {
1539                                 if (hw->allow_unsupported_sfp == TRUE) {
1540                                         EWARN(hw, "WARNING: Intel (R) Network "
1541                                               "Connections are quality tested "
1542                                               "using Intel (R) Ethernet Optics."
1543                                               " Using untested modules is not "
1544                                               "supported and may cause unstable"
1545                                               " operation or damage to the "
1546                                               "module or the adapter. Intel "
1547                                               "Corporation is not responsible "
1548                                               "for any harm caused by using "
1549                                               "untested modules.\n", status);
1550                                         status = IXGBE_SUCCESS;
1551                                 } else {
1552                                         DEBUGOUT("SFP+ module not supported\n");
1553                                         hw->phy.type =
1554                                                 ixgbe_phy_sfp_unsupported;
1555                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1556                                 }
1557                         }
1558                 } else {
1559                         status = IXGBE_SUCCESS;
1560                 }
1561         }
1562
1563 out:
1564         return status;
1565
1566 err_read_i2c_eeprom:
1567         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1568         if (hw->phy.type != ixgbe_phy_nl) {
1569                 hw->phy.id = 0;
1570                 hw->phy.type = ixgbe_phy_unknown;
1571         }
1572         return IXGBE_ERR_SFP_NOT_PRESENT;
1573 }
1574
1575 /**
1576  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1577  *  @hw: pointer to hardware structure
1578  *
1579  *  Determines physical layer capabilities of the current SFP.
1580  */
1581 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1582 {
1583         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1584         u8 comp_codes_10g = 0;
1585         u8 comp_codes_1g = 0;
1586
1587         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1588
1589         hw->phy.ops.identify_sfp(hw);
1590         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1591                 return physical_layer;
1592
1593         switch (hw->phy.type) {
1594         case ixgbe_phy_sfp_passive_tyco:
1595         case ixgbe_phy_sfp_passive_unknown:
1596         case ixgbe_phy_qsfp_passive_unknown:
1597                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1598                 break;
1599         case ixgbe_phy_sfp_ftl_active:
1600         case ixgbe_phy_sfp_active_unknown:
1601         case ixgbe_phy_qsfp_active_unknown:
1602                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1603                 break;
1604         case ixgbe_phy_sfp_avago:
1605         case ixgbe_phy_sfp_ftl:
1606         case ixgbe_phy_sfp_intel:
1607         case ixgbe_phy_sfp_unknown:
1608                 hw->phy.ops.read_i2c_eeprom(hw,
1609                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1610                 hw->phy.ops.read_i2c_eeprom(hw,
1611                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1612                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1613                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1614                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1615                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1616                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1617                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1618                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1619                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1620                 break;
1621         case ixgbe_phy_qsfp_intel:
1622         case ixgbe_phy_qsfp_unknown:
1623                 hw->phy.ops.read_i2c_eeprom(hw,
1624                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1625                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1626                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1627                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1628                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1629                 break;
1630         default:
1631                 break;
1632         }
1633
1634         return physical_layer;
1635 }
1636
1637 /**
1638  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1639  *  @hw: pointer to hardware structure
1640  *
1641  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1642  **/
1643 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1644 {
1645         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1646         u32 vendor_oui = 0;
1647         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1648         u8 identifier = 0;
1649         u8 comp_codes_1g = 0;
1650         u8 comp_codes_10g = 0;
1651         u8 oui_bytes[3] = {0, 0, 0};
1652         u16 enforce_sfp = 0;
1653         u8 connector = 0;
1654         u8 cable_length = 0;
1655         u8 device_tech = 0;
1656         bool active_cable = FALSE;
1657
1658         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1659
1660         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1661                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1662                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1663                 goto out;
1664         }
1665
1666         /* LAN ID is needed for I2C access */
1667         hw->mac.ops.set_lan_id(hw);
1668
1669         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1670                                              &identifier);
1671
1672         if (status != IXGBE_SUCCESS)
1673                 goto err_read_i2c_eeprom;
1674
1675         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1676                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1677                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1678                 goto out;
1679         }
1680
1681         hw->phy.id = identifier;
1682
1683         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1684                                              &comp_codes_10g);
1685
1686         if (status != IXGBE_SUCCESS)
1687                 goto err_read_i2c_eeprom;
1688
1689         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1690                                              &comp_codes_1g);
1691
1692         if (status != IXGBE_SUCCESS)
1693                 goto err_read_i2c_eeprom;
1694
1695         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1696                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1697                 if (hw->bus.lan_id == 0)
1698                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1699                 else
1700                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1701         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1702                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1703                 if (hw->bus.lan_id == 0)
1704                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1705                 else
1706                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1707         } else {
1708                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1709                         active_cable = TRUE;
1710
1711                 if (!active_cable) {
1712                         /* check for active DA cables that pre-date
1713                          * SFF-8436 v3.6 */
1714                         hw->phy.ops.read_i2c_eeprom(hw,
1715                                         IXGBE_SFF_QSFP_CONNECTOR,
1716                                         &connector);
1717
1718                         hw->phy.ops.read_i2c_eeprom(hw,
1719                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1720                                         &cable_length);
1721
1722                         hw->phy.ops.read_i2c_eeprom(hw,
1723                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1724                                         &device_tech);
1725
1726                         if ((connector ==
1727                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1728                             (cable_length > 0) &&
1729                             ((device_tech >> 4) ==
1730                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1731                                 active_cable = TRUE;
1732                 }
1733
1734                 if (active_cable) {
1735                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1736                         if (hw->bus.lan_id == 0)
1737                                 hw->phy.sfp_type =
1738                                                 ixgbe_sfp_type_da_act_lmt_core0;
1739                         else
1740                                 hw->phy.sfp_type =
1741                                                 ixgbe_sfp_type_da_act_lmt_core1;
1742                 } else {
1743                         /* unsupported module type */
1744                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1745                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1746                         goto out;
1747                 }
1748         }
1749
1750         if (hw->phy.sfp_type != stored_sfp_type)
1751                 hw->phy.sfp_setup_needed = TRUE;
1752
1753         /* Determine if the QSFP+ PHY is dual speed or not. */
1754         hw->phy.multispeed_fiber = FALSE;
1755         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1756            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1757            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1758            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1759                 hw->phy.multispeed_fiber = TRUE;
1760
1761         /* Determine PHY vendor for optical modules */
1762         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1763                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1764                 status = hw->phy.ops.read_i2c_eeprom(hw,
1765                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1766                                             &oui_bytes[0]);
1767
1768                 if (status != IXGBE_SUCCESS)
1769                         goto err_read_i2c_eeprom;
1770
1771                 status = hw->phy.ops.read_i2c_eeprom(hw,
1772                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1773                                             &oui_bytes[1]);
1774
1775                 if (status != IXGBE_SUCCESS)
1776                         goto err_read_i2c_eeprom;
1777
1778                 status = hw->phy.ops.read_i2c_eeprom(hw,
1779                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1780                                             &oui_bytes[2]);
1781
1782                 if (status != IXGBE_SUCCESS)
1783                         goto err_read_i2c_eeprom;
1784
1785                 vendor_oui =
1786                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1787                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1788                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1789
1790                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1791                         hw->phy.type = ixgbe_phy_qsfp_intel;
1792                 else
1793                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1794
1795                 ixgbe_get_device_caps(hw, &enforce_sfp);
1796                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1797                         /* Make sure we're a supported PHY type */
1798                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1799                                 status = IXGBE_SUCCESS;
1800                         } else {
1801                                 if (hw->allow_unsupported_sfp == TRUE) {
1802                                         EWARN(hw, "WARNING: Intel (R) Network "
1803                                               "Connections are quality tested "
1804                                               "using Intel (R) Ethernet Optics."
1805                                               " Using untested modules is not "
1806                                               "supported and may cause unstable"
1807                                               " operation or damage to the "
1808                                               "module or the adapter. Intel "
1809                                               "Corporation is not responsible "
1810                                               "for any harm caused by using "
1811                                               "untested modules.\n", status);
1812                                         status = IXGBE_SUCCESS;
1813                                 } else {
1814                                         DEBUGOUT("QSFP module not supported\n");
1815                                         hw->phy.type =
1816                                                 ixgbe_phy_sfp_unsupported;
1817                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1818                                 }
1819                         }
1820                 } else {
1821                         status = IXGBE_SUCCESS;
1822                 }
1823         }
1824
1825 out:
1826         return status;
1827
1828 err_read_i2c_eeprom:
1829         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1830         hw->phy.id = 0;
1831         hw->phy.type = ixgbe_phy_unknown;
1832
1833         return IXGBE_ERR_SFP_NOT_PRESENT;
1834 }
1835
1836
1837 /**
1838  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1839  *  @hw: pointer to hardware structure
1840  *  @list_offset: offset to the SFP ID list
1841  *  @data_offset: offset to the SFP data block
1842  *
1843  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1844  *  so it returns the offsets to the phy init sequence block.
1845  **/
1846 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1847                                         u16 *list_offset,
1848                                         u16 *data_offset)
1849 {
1850         u16 sfp_id;
1851         u16 sfp_type = hw->phy.sfp_type;
1852
1853         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1854
1855         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1856                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1857
1858         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1859                 return IXGBE_ERR_SFP_NOT_PRESENT;
1860
1861         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1862             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1863                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1864
1865         /*
1866          * Limiting active cables and 1G Phys must be initialized as
1867          * SR modules
1868          */
1869         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1870             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1871             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1872             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1873                 sfp_type = ixgbe_sfp_type_srlr_core0;
1874         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1875                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1876                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1877                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1878                 sfp_type = ixgbe_sfp_type_srlr_core1;
1879
1880         /* Read offset to PHY init contents */
1881         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1882                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1883                               "eeprom read at offset %d failed",
1884                               IXGBE_PHY_INIT_OFFSET_NL);
1885                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1886         }
1887
1888         if ((!*list_offset) || (*list_offset == 0xFFFF))
1889                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1890
1891         /* Shift offset to first ID word */
1892         (*list_offset)++;
1893
1894         /*
1895          * Find the matching SFP ID in the EEPROM
1896          * and program the init sequence
1897          */
1898         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1899                 goto err_phy;
1900
1901         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1902                 if (sfp_id == sfp_type) {
1903                         (*list_offset)++;
1904                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1905                                 goto err_phy;
1906                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1907                                 DEBUGOUT("SFP+ module not supported\n");
1908                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1909                         } else {
1910                                 break;
1911                         }
1912                 } else {
1913                         (*list_offset) += 2;
1914                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1915                                 goto err_phy;
1916                 }
1917         }
1918
1919         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1920                 DEBUGOUT("No matching SFP+ module found\n");
1921                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1922         }
1923
1924         return IXGBE_SUCCESS;
1925
1926 err_phy:
1927         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1928                       "eeprom read at offset %d failed", *list_offset);
1929         return IXGBE_ERR_PHY;
1930 }
1931
1932 /**
1933  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1934  *  @hw: pointer to hardware structure
1935  *  @byte_offset: EEPROM byte offset to read
1936  *  @eeprom_data: value read
1937  *
1938  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1939  **/
1940 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1941                                   u8 *eeprom_data)
1942 {
1943         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1944
1945         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1946                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1947                                          eeprom_data);
1948 }
1949
1950 /**
1951  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1952  *  @hw: pointer to hardware structure
1953  *  @byte_offset: byte offset at address 0xA2
1954  *  @eeprom_data: value read
1955  *
1956  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1957  **/
1958 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1959                                           u8 *sff8472_data)
1960 {
1961         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1962                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1963                                          sff8472_data);
1964 }
1965
1966 /**
1967  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1968  *  @hw: pointer to hardware structure
1969  *  @byte_offset: EEPROM byte offset to write
1970  *  @eeprom_data: value to write
1971  *
1972  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1973  **/
1974 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1975                                    u8 eeprom_data)
1976 {
1977         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1978
1979         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1980                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1981                                           eeprom_data);
1982 }
1983
1984 /**
1985  * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
1986  * @hw: pointer to hardware structure
1987  * @offset: eeprom offset to be read
1988  * @addr: I2C address to be read
1989  */
1990 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1991 {
1992         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1993             offset == IXGBE_SFF_IDENTIFIER &&
1994             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1995                 return TRUE;
1996         return FALSE;
1997 }
1998
1999 /**
2000  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2001  *  @hw: pointer to hardware structure
2002  *  @byte_offset: byte offset to read
2003  *  @data: value read
2004  *  @lock: TRUE if to take and release semaphore
2005  *
2006  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2007  *  a specified device address.
2008  **/
2009 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2010                                            u8 dev_addr, u8 *data, bool lock)
2011 {
2012         s32 status;
2013         u32 max_retry = 10;
2014         u32 retry = 0;
2015         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2016         bool nack = 1;
2017         *data = 0;
2018
2019         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2020
2021         if (hw->mac.type >= ixgbe_mac_X550)
2022                 max_retry = 3;
2023         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2024                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2025
2026         do {
2027                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2028                         return IXGBE_ERR_SWFW_SYNC;
2029
2030                 ixgbe_i2c_start(hw);
2031
2032                 /* Device Address and write indication */
2033                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2034                 if (status != IXGBE_SUCCESS)
2035                         goto fail;
2036
2037                 status = ixgbe_get_i2c_ack(hw);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2042                 if (status != IXGBE_SUCCESS)
2043                         goto fail;
2044
2045                 status = ixgbe_get_i2c_ack(hw);
2046                 if (status != IXGBE_SUCCESS)
2047                         goto fail;
2048
2049                 ixgbe_i2c_start(hw);
2050
2051                 /* Device Address and read indication */
2052                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2053                 if (status != IXGBE_SUCCESS)
2054                         goto fail;
2055
2056                 status = ixgbe_get_i2c_ack(hw);
2057                 if (status != IXGBE_SUCCESS)
2058                         goto fail;
2059
2060                 status = ixgbe_clock_in_i2c_byte(hw, data);
2061                 if (status != IXGBE_SUCCESS)
2062                         goto fail;
2063
2064                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2065                 if (status != IXGBE_SUCCESS)
2066                         goto fail;
2067
2068                 ixgbe_i2c_stop(hw);
2069                 if (lock)
2070                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2071                 return IXGBE_SUCCESS;
2072
2073 fail:
2074                 ixgbe_i2c_bus_clear(hw);
2075                 if (lock) {
2076                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2077                         msec_delay(100);
2078                 }
2079                 retry++;
2080                 if (retry < max_retry)
2081                         DEBUGOUT("I2C byte read error - Retrying.\n");
2082                 else
2083                         DEBUGOUT("I2C byte read error.\n");
2084
2085         } while (retry < max_retry);
2086
2087         return status;
2088 }
2089
2090 /**
2091  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2092  *  @hw: pointer to hardware structure
2093  *  @byte_offset: byte offset to read
2094  *  @data: value read
2095  *
2096  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2097  *  a specified device address.
2098  **/
2099 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2100                                 u8 dev_addr, u8 *data)
2101 {
2102         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2103                                                data, TRUE);
2104 }
2105
2106 /**
2107  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2108  *  @hw: pointer to hardware structure
2109  *  @byte_offset: byte offset to read
2110  *  @data: value read
2111  *
2112  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2113  *  a specified device address.
2114  **/
2115 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2116                                          u8 dev_addr, u8 *data)
2117 {
2118         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2119                                                data, FALSE);
2120 }
2121
2122 /**
2123  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2124  *  @hw: pointer to hardware structure
2125  *  @byte_offset: byte offset to write
2126  *  @data: value to write
2127  *  @lock: TRUE if to take and release semaphore
2128  *
2129  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2130  *  a specified device address.
2131  **/
2132 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2133                                             u8 dev_addr, u8 data, bool lock)
2134 {
2135         s32 status;
2136         u32 max_retry = 1;
2137         u32 retry = 0;
2138         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2139
2140         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2141
2142         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2143             IXGBE_SUCCESS)
2144                 return IXGBE_ERR_SWFW_SYNC;
2145
2146         do {
2147                 ixgbe_i2c_start(hw);
2148
2149                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2150                 if (status != IXGBE_SUCCESS)
2151                         goto fail;
2152
2153                 status = ixgbe_get_i2c_ack(hw);
2154                 if (status != IXGBE_SUCCESS)
2155                         goto fail;
2156
2157                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2158                 if (status != IXGBE_SUCCESS)
2159                         goto fail;
2160
2161                 status = ixgbe_get_i2c_ack(hw);
2162                 if (status != IXGBE_SUCCESS)
2163                         goto fail;
2164
2165                 status = ixgbe_clock_out_i2c_byte(hw, data);
2166                 if (status != IXGBE_SUCCESS)
2167                         goto fail;
2168
2169                 status = ixgbe_get_i2c_ack(hw);
2170                 if (status != IXGBE_SUCCESS)
2171                         goto fail;
2172
2173                 ixgbe_i2c_stop(hw);
2174                 if (lock)
2175                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176                 return IXGBE_SUCCESS;
2177
2178 fail:
2179                 ixgbe_i2c_bus_clear(hw);
2180                 retry++;
2181                 if (retry < max_retry)
2182                         DEBUGOUT("I2C byte write error - Retrying.\n");
2183                 else
2184                         DEBUGOUT("I2C byte write error.\n");
2185         } while (retry < max_retry);
2186
2187         if (lock)
2188                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2189
2190         return status;
2191 }
2192
2193 /**
2194  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2195  *  @hw: pointer to hardware structure
2196  *  @byte_offset: byte offset to write
2197  *  @data: value to write
2198  *
2199  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2200  *  a specified device address.
2201  **/
2202 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2203                                  u8 dev_addr, u8 data)
2204 {
2205         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2206                                                 data, TRUE);
2207 }
2208
2209 /**
2210  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2211  *  @hw: pointer to hardware structure
2212  *  @byte_offset: byte offset to write
2213  *  @data: value to write
2214  *
2215  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2216  *  a specified device address.
2217  **/
2218 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2219                                           u8 dev_addr, u8 data)
2220 {
2221         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2222                                                 data, FALSE);
2223 }
2224
2225 /**
2226  *  ixgbe_i2c_start - Sets I2C start condition
2227  *  @hw: pointer to hardware structure
2228  *
2229  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2230  *  Set bit-bang mode on X550 hardware.
2231  **/
2232 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2233 {
2234         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2235
2236         DEBUGFUNC("ixgbe_i2c_start");
2237
2238         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2239
2240         /* Start condition must begin with data and clock high */
2241         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2242         ixgbe_raise_i2c_clk(hw, &i2cctl);
2243
2244         /* Setup time for start condition (4.7us) */
2245         usec_delay(IXGBE_I2C_T_SU_STA);
2246
2247         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2248
2249         /* Hold time for start condition (4us) */
2250         usec_delay(IXGBE_I2C_T_HD_STA);
2251
2252         ixgbe_lower_i2c_clk(hw, &i2cctl);
2253
2254         /* Minimum low period of clock is 4.7 us */
2255         usec_delay(IXGBE_I2C_T_LOW);
2256
2257 }
2258
2259 /**
2260  *  ixgbe_i2c_stop - Sets I2C stop condition
2261  *  @hw: pointer to hardware structure
2262  *
2263  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2264  *  Disables bit-bang mode and negates data output enable on X550
2265  *  hardware.
2266  **/
2267 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2268 {
2269         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2270         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2271         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2272         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2273
2274         DEBUGFUNC("ixgbe_i2c_stop");
2275
2276         /* Stop condition must begin with data low and clock high */
2277         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2278         ixgbe_raise_i2c_clk(hw, &i2cctl);
2279
2280         /* Setup time for stop condition (4us) */
2281         usec_delay(IXGBE_I2C_T_SU_STO);
2282
2283         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2284
2285         /* bus free time between stop and start (4.7us)*/
2286         usec_delay(IXGBE_I2C_T_BUF);
2287
2288         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2289                 i2cctl &= ~bb_en_bit;
2290                 i2cctl |= data_oe_bit | clk_oe_bit;
2291                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2292                 IXGBE_WRITE_FLUSH(hw);
2293         }
2294 }
2295
2296 /**
2297  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2298  *  @hw: pointer to hardware structure
2299  *  @data: data byte to clock in
2300  *
2301  *  Clocks in one byte data via I2C data/clock
2302  **/
2303 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2304 {
2305         s32 i;
2306         bool bit = 0;
2307
2308         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2309
2310         *data = 0;
2311         for (i = 7; i >= 0; i--) {
2312                 ixgbe_clock_in_i2c_bit(hw, &bit);
2313                 *data |= bit << i;
2314         }
2315
2316         return IXGBE_SUCCESS;
2317 }
2318
2319 /**
2320  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2321  *  @hw: pointer to hardware structure
2322  *  @data: data byte clocked out
2323  *
2324  *  Clocks out one byte data via I2C data/clock
2325  **/
2326 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2327 {
2328         s32 status = IXGBE_SUCCESS;
2329         s32 i;
2330         u32 i2cctl;
2331         bool bit;
2332
2333         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2334
2335         for (i = 7; i >= 0; i--) {
2336                 bit = (data >> i) & 0x1;
2337                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2338
2339                 if (status != IXGBE_SUCCESS)
2340                         break;
2341         }
2342
2343         /* Release SDA line (set high) */
2344         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2345         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2346         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2347         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2348         IXGBE_WRITE_FLUSH(hw);
2349
2350         return status;
2351 }
2352
2353 /**
2354  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2355  *  @hw: pointer to hardware structure
2356  *
2357  *  Clocks in/out one bit via I2C data/clock
2358  **/
2359 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2360 {
2361         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2362         s32 status = IXGBE_SUCCESS;
2363         u32 i = 0;
2364         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2365         u32 timeout = 10;
2366         bool ack = 1;
2367
2368         DEBUGFUNC("ixgbe_get_i2c_ack");
2369
2370         if (data_oe_bit) {
2371                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2372                 i2cctl |= data_oe_bit;
2373                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2374                 IXGBE_WRITE_FLUSH(hw);
2375         }
2376         ixgbe_raise_i2c_clk(hw, &i2cctl);
2377
2378         /* Minimum high period of clock is 4us */
2379         usec_delay(IXGBE_I2C_T_HIGH);
2380
2381         /* Poll for ACK.  Note that ACK in I2C spec is
2382          * transition from 1 to 0 */
2383         for (i = 0; i < timeout; i++) {
2384                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2385                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2386
2387                 usec_delay(1);
2388                 if (!ack)
2389                         break;
2390         }
2391
2392         if (ack) {
2393                 DEBUGOUT("I2C ack was not received.\n");
2394                 status = IXGBE_ERR_I2C;
2395         }
2396
2397         ixgbe_lower_i2c_clk(hw, &i2cctl);
2398
2399         /* Minimum low period of clock is 4.7 us */
2400         usec_delay(IXGBE_I2C_T_LOW);
2401
2402         return status;
2403 }
2404
2405 /**
2406  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2407  *  @hw: pointer to hardware structure
2408  *  @data: read data value
2409  *
2410  *  Clocks in one bit via I2C data/clock
2411  **/
2412 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2413 {
2414         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2415         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2416
2417         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2418
2419         if (data_oe_bit) {
2420                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2421                 i2cctl |= data_oe_bit;
2422                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2423                 IXGBE_WRITE_FLUSH(hw);
2424         }
2425         ixgbe_raise_i2c_clk(hw, &i2cctl);
2426
2427         /* Minimum high period of clock is 4us */
2428         usec_delay(IXGBE_I2C_T_HIGH);
2429
2430         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2431         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2432
2433         ixgbe_lower_i2c_clk(hw, &i2cctl);
2434
2435         /* Minimum low period of clock is 4.7 us */
2436         usec_delay(IXGBE_I2C_T_LOW);
2437
2438         return IXGBE_SUCCESS;
2439 }
2440
2441 /**
2442  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2443  *  @hw: pointer to hardware structure
2444  *  @data: data value to write
2445  *
2446  *  Clocks out one bit via I2C data/clock
2447  **/
2448 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2449 {
2450         s32 status;
2451         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2452
2453         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2454
2455         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2456         if (status == IXGBE_SUCCESS) {
2457                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2458
2459                 /* Minimum high period of clock is 4us */
2460                 usec_delay(IXGBE_I2C_T_HIGH);
2461
2462                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2463
2464                 /* Minimum low period of clock is 4.7 us.
2465                  * This also takes care of the data hold time.
2466                  */
2467                 usec_delay(IXGBE_I2C_T_LOW);
2468         } else {
2469                 status = IXGBE_ERR_I2C;
2470                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2471                              "I2C data was not set to %X\n", data);
2472         }
2473
2474         return status;
2475 }
2476
2477 /**
2478  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2479  *  @hw: pointer to hardware structure
2480  *  @i2cctl: Current value of I2CCTL register
2481  *
2482  *  Raises the I2C clock line '0'->'1'
2483  *  Negates the I2C clock output enable on X550 hardware.
2484  **/
2485 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2486 {
2487         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2488         u32 i = 0;
2489         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2490         u32 i2cctl_r = 0;
2491
2492         DEBUGFUNC("ixgbe_raise_i2c_clk");
2493
2494         if (clk_oe_bit) {
2495                 *i2cctl |= clk_oe_bit;
2496                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2497         }
2498
2499         for (i = 0; i < timeout; i++) {
2500                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2501
2502                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2503                 IXGBE_WRITE_FLUSH(hw);
2504                 /* SCL rise time (1000ns) */
2505                 usec_delay(IXGBE_I2C_T_RISE);
2506
2507                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2508                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2509                         break;
2510         }
2511 }
2512
2513 /**
2514  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2515  *  @hw: pointer to hardware structure
2516  *  @i2cctl: Current value of I2CCTL register
2517  *
2518  *  Lowers the I2C clock line '1'->'0'
2519  *  Asserts the I2C clock output enable on X550 hardware.
2520  **/
2521 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2522 {
2523         DEBUGFUNC("ixgbe_lower_i2c_clk");
2524
2525         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2526         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2527
2528         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2529         IXGBE_WRITE_FLUSH(hw);
2530
2531         /* SCL fall time (300ns) */
2532         usec_delay(IXGBE_I2C_T_FALL);
2533 }
2534
2535 /**
2536  *  ixgbe_set_i2c_data - Sets the I2C data bit
2537  *  @hw: pointer to hardware structure
2538  *  @i2cctl: Current value of I2CCTL register
2539  *  @data: I2C data value (0 or 1) to set
2540  *
2541  *  Sets the I2C data bit
2542  *  Asserts the I2C data output enable on X550 hardware.
2543  **/
2544 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2545 {
2546         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2547         s32 status = IXGBE_SUCCESS;
2548
2549         DEBUGFUNC("ixgbe_set_i2c_data");
2550
2551         if (data)
2552                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2553         else
2554                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2555         *i2cctl &= ~data_oe_bit;
2556
2557         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2558         IXGBE_WRITE_FLUSH(hw);
2559
2560         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2561         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2562
2563         if (!data)      /* Can't verify data in this case */
2564                 return IXGBE_SUCCESS;
2565         if (data_oe_bit) {
2566                 *i2cctl |= data_oe_bit;
2567                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2568                 IXGBE_WRITE_FLUSH(hw);
2569         }
2570
2571         /* Verify data was set correctly */
2572         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2573         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2574                 status = IXGBE_ERR_I2C;
2575                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2576                              "Error - I2C data was not set to %X.\n",
2577                              data);
2578         }
2579
2580         return status;
2581 }
2582
2583 /**
2584  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2585  *  @hw: pointer to hardware structure
2586  *  @i2cctl: Current value of I2CCTL register
2587  *
2588  *  Returns the I2C data bit value
2589  *  Negates the I2C data output enable on X550 hardware.
2590  **/
2591 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2592 {
2593         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2594         bool data;
2595
2596         DEBUGFUNC("ixgbe_get_i2c_data");
2597
2598         if (data_oe_bit) {
2599                 *i2cctl |= data_oe_bit;
2600                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2601                 IXGBE_WRITE_FLUSH(hw);
2602                 usec_delay(IXGBE_I2C_T_FALL);
2603         }
2604
2605         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2606                 data = 1;
2607         else
2608                 data = 0;
2609
2610         return data;
2611 }
2612
2613 /**
2614  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2615  *  @hw: pointer to hardware structure
2616  *
2617  *  Clears the I2C bus by sending nine clock pulses.
2618  *  Used when data line is stuck low.
2619  **/
2620 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2621 {
2622         u32 i2cctl;
2623         u32 i;
2624
2625         DEBUGFUNC("ixgbe_i2c_bus_clear");
2626
2627         ixgbe_i2c_start(hw);
2628         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2629
2630         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2631
2632         for (i = 0; i < 9; i++) {
2633                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2634
2635                 /* Min high period of clock is 4us */
2636                 usec_delay(IXGBE_I2C_T_HIGH);
2637
2638                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2639
2640                 /* Min low period of clock is 4.7us*/
2641                 usec_delay(IXGBE_I2C_T_LOW);
2642         }
2643
2644         ixgbe_i2c_start(hw);
2645
2646         /* Put the i2c bus back to default state */
2647         ixgbe_i2c_stop(hw);
2648 }
2649
2650 /**
2651  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2652  *  @hw: pointer to hardware structure
2653  *
2654  *  Checks if the LASI temp alarm status was triggered due to overtemp
2655  **/
2656 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2657 {
2658         s32 status = IXGBE_SUCCESS;
2659         u16 phy_data = 0;
2660
2661         DEBUGFUNC("ixgbe_tn_check_overtemp");
2662
2663         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2664                 goto out;
2665
2666         /* Check that the LASI temp alarm status was triggered */
2667         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2668                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2669
2670         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2671                 goto out;
2672
2673         status = IXGBE_ERR_OVERTEMP;
2674         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2675 out:
2676         return status;
2677 }
2678
2679 /**
2680  * ixgbe_set_copper_phy_power - Control power for copper phy
2681  * @hw: pointer to hardware structure
2682  * @on: TRUE for on, FALSE for off
2683  */
2684 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2685 {
2686         u32 status;
2687         u16 reg;
2688
2689         if (!on && ixgbe_mng_present(hw))
2690                 return 0;
2691
2692         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2693                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2694                                       &reg);
2695         if (status)
2696                 return status;
2697
2698         if (on) {
2699                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2700         } else {
2701                 if (ixgbe_check_reset_blocked(hw))
2702                         return 0;
2703                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2704         }
2705
2706         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2707                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2708                                        reg);
2709         return status;
2710 }