1 /******************************************************************************
3 Copyright (c) 2013-2014, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #ifndef _I40E_ADMINQ_CMD_H_
36 #define _I40E_ADMINQ_CMD_H_
38 /* This header file defines the i40e Admin Queue commands and is shared between
39 * i40e Firmware and Software.
41 * This file needs to comply with the Linux Kernel coding style.
44 #define I40E_FW_API_VERSION_MAJOR 0x0001
45 #define I40E_FW_API_VERSION_MINOR 0x0002
71 /* Flags sub-structure
72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
76 /* command flags and offsets*/
77 #define I40E_AQ_FLAG_DD_SHIFT 0
78 #define I40E_AQ_FLAG_CMP_SHIFT 1
79 #define I40E_AQ_FLAG_ERR_SHIFT 2
80 #define I40E_AQ_FLAG_VFE_SHIFT 3
81 #define I40E_AQ_FLAG_LB_SHIFT 9
82 #define I40E_AQ_FLAG_RD_SHIFT 10
83 #define I40E_AQ_FLAG_VFC_SHIFT 11
84 #define I40E_AQ_FLAG_BUF_SHIFT 12
85 #define I40E_AQ_FLAG_SI_SHIFT 13
86 #define I40E_AQ_FLAG_EI_SHIFT 14
87 #define I40E_AQ_FLAG_FE_SHIFT 15
89 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
90 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
91 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
92 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
93 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
94 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
95 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
96 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
97 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
98 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
99 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
102 enum i40e_admin_queue_err {
103 I40E_AQ_RC_OK = 0, /* success */
104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
105 I40E_AQ_RC_ENOENT = 2, /* No such element */
106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
108 I40E_AQ_RC_EIO = 5, /* I/O error */
109 I40E_AQ_RC_ENXIO = 6, /* No such resource */
110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
111 I40E_AQ_RC_EAGAIN = 8, /* Try again */
112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
113 I40E_AQ_RC_EACCES = 10, /* Permission denied */
114 I40E_AQ_RC_EFAULT = 11, /* Bad address */
115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
116 I40E_AQ_RC_EEXIST = 13, /* object already exists */
117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
125 I40E_AQ_RC_EFBIG = 22, /* File too large */
128 /* Admin Queue command opcodes */
129 enum i40e_admin_queue_opc {
131 i40e_aqc_opc_get_version = 0x0001,
132 i40e_aqc_opc_driver_version = 0x0002,
133 i40e_aqc_opc_queue_shutdown = 0x0003,
134 i40e_aqc_opc_set_pf_context = 0x0004,
136 /* resource ownership */
137 i40e_aqc_opc_request_resource = 0x0008,
138 i40e_aqc_opc_release_resource = 0x0009,
140 i40e_aqc_opc_list_func_capabilities = 0x000A,
141 i40e_aqc_opc_list_dev_capabilities = 0x000B,
143 i40e_aqc_opc_set_cppm_configuration = 0x0103,
144 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
148 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
155 /* internal switch commands */
156 i40e_aqc_opc_get_switch_config = 0x0200,
157 i40e_aqc_opc_add_statistics = 0x0201,
158 i40e_aqc_opc_remove_statistics = 0x0202,
159 i40e_aqc_opc_set_port_parameters = 0x0203,
160 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
162 i40e_aqc_opc_add_vsi = 0x0210,
163 i40e_aqc_opc_update_vsi_parameters = 0x0211,
164 i40e_aqc_opc_get_vsi_parameters = 0x0212,
166 i40e_aqc_opc_add_pv = 0x0220,
167 i40e_aqc_opc_update_pv_parameters = 0x0221,
168 i40e_aqc_opc_get_pv_parameters = 0x0222,
170 i40e_aqc_opc_add_veb = 0x0230,
171 i40e_aqc_opc_update_veb_parameters = 0x0231,
172 i40e_aqc_opc_get_veb_parameters = 0x0232,
174 i40e_aqc_opc_delete_element = 0x0243,
176 i40e_aqc_opc_add_macvlan = 0x0250,
177 i40e_aqc_opc_remove_macvlan = 0x0251,
178 i40e_aqc_opc_add_vlan = 0x0252,
179 i40e_aqc_opc_remove_vlan = 0x0253,
180 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
181 i40e_aqc_opc_add_tag = 0x0255,
182 i40e_aqc_opc_remove_tag = 0x0256,
183 i40e_aqc_opc_add_multicast_etag = 0x0257,
184 i40e_aqc_opc_remove_multicast_etag = 0x0258,
185 i40e_aqc_opc_update_tag = 0x0259,
186 i40e_aqc_opc_add_control_packet_filter = 0x025A,
187 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
188 i40e_aqc_opc_add_cloud_filters = 0x025C,
189 i40e_aqc_opc_remove_cloud_filters = 0x025D,
191 i40e_aqc_opc_add_mirror_rule = 0x0260,
192 i40e_aqc_opc_delete_mirror_rule = 0x0261,
195 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
196 i40e_aqc_opc_dcb_updated = 0x0302,
199 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
200 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
201 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
202 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
203 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
204 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
206 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
207 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
208 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
209 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
210 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
211 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
212 i40e_aqc_opc_query_port_ets_config = 0x0419,
213 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
214 i40e_aqc_opc_suspend_port_tx = 0x041B,
215 i40e_aqc_opc_resume_port_tx = 0x041C,
216 i40e_aqc_opc_configure_partition_bw = 0x041D,
219 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
220 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
223 i40e_aqc_opc_get_phy_abilities = 0x0600,
224 i40e_aqc_opc_set_phy_config = 0x0601,
225 i40e_aqc_opc_set_mac_config = 0x0603,
226 i40e_aqc_opc_set_link_restart_an = 0x0605,
227 i40e_aqc_opc_get_link_status = 0x0607,
228 i40e_aqc_opc_set_phy_int_mask = 0x0613,
229 i40e_aqc_opc_get_local_advt_reg = 0x0614,
230 i40e_aqc_opc_set_local_advt_reg = 0x0615,
231 i40e_aqc_opc_get_partner_advt = 0x0616,
232 i40e_aqc_opc_set_lb_modes = 0x0618,
233 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
234 i40e_aqc_opc_set_phy_debug = 0x0622,
235 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
238 i40e_aqc_opc_nvm_read = 0x0701,
239 i40e_aqc_opc_nvm_erase = 0x0702,
240 i40e_aqc_opc_nvm_update = 0x0703,
241 i40e_aqc_opc_nvm_config_read = 0x0704,
242 i40e_aqc_opc_nvm_config_write = 0x0705,
244 /* virtualization commands */
245 i40e_aqc_opc_send_msg_to_pf = 0x0801,
246 i40e_aqc_opc_send_msg_to_vf = 0x0802,
247 i40e_aqc_opc_send_msg_to_peer = 0x0803,
249 /* alternate structure */
250 i40e_aqc_opc_alternate_write = 0x0900,
251 i40e_aqc_opc_alternate_write_indirect = 0x0901,
252 i40e_aqc_opc_alternate_read = 0x0902,
253 i40e_aqc_opc_alternate_read_indirect = 0x0903,
254 i40e_aqc_opc_alternate_write_done = 0x0904,
255 i40e_aqc_opc_alternate_set_mode = 0x0905,
256 i40e_aqc_opc_alternate_clear_port = 0x0906,
259 i40e_aqc_opc_lldp_get_mib = 0x0A00,
260 i40e_aqc_opc_lldp_update_mib = 0x0A01,
261 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
262 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
263 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
264 i40e_aqc_opc_lldp_stop = 0x0A05,
265 i40e_aqc_opc_lldp_start = 0x0A06,
267 /* Tunnel commands */
268 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
269 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
270 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
273 i40e_aqc_opc_event_lan_overflow = 0x1001,
276 i40e_aqc_opc_oem_parameter_change = 0xFE00,
277 i40e_aqc_opc_oem_device_status_change = 0xFE01,
280 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
281 i40e_aqc_opc_debug_set_mode = 0xFF01,
282 i40e_aqc_opc_debug_read_reg = 0xFF03,
283 i40e_aqc_opc_debug_write_reg = 0xFF04,
284 i40e_aqc_opc_debug_modify_reg = 0xFF07,
285 i40e_aqc_opc_debug_dump_internals = 0xFF08,
286 i40e_aqc_opc_debug_modify_internals = 0xFF09,
289 /* command structures and indirect data structures */
291 /* Structure naming conventions:
292 * - no suffix for direct command descriptor structures
293 * - _data for indirect sent data
294 * - _resp for indirect return data (data which is both will use _data)
295 * - _completion for direct return data
296 * - _element_ for repeated elements (may also be _data or _resp)
298 * Command structures are expected to overlay the params.raw member of the basic
299 * descriptor, and as such cannot exceed 16 bytes in length.
302 /* This macro is used to generate a compilation error if a structure
303 * is not exactly the correct length. It gives a divide by zero error if the
304 * structure is not of the correct size, otherwise it creates an enum that is
307 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
308 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
310 /* This macro is used extensively to ensure that command structures are 16
311 * bytes in length as they have to map to the raw array of that size.
313 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
315 /* internal (0x00XX) commands */
317 /* Get version (direct 0x0001) */
318 struct i40e_aqc_get_version {
327 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
329 /* Send driver version (indirect 0x0002) */
330 struct i40e_aqc_driver_version {
334 u8 driver_subbuild_ver;
340 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
342 /* Queue Shutdown (direct 0x0003) */
343 struct i40e_aqc_queue_shutdown {
344 __le32 driver_unloading;
345 #define I40E_AQ_DRIVER_UNLOADING 0x1
349 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
351 /* Set PF context (0x0004, direct) */
352 struct i40e_aqc_set_pf_context {
357 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
359 /* Request resource ownership (direct 0x0008)
360 * Release resource ownership (direct 0x0009)
362 #define I40E_AQ_RESOURCE_NVM 1
363 #define I40E_AQ_RESOURCE_SDP 2
364 #define I40E_AQ_RESOURCE_ACCESS_READ 1
365 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
366 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
367 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
369 struct i40e_aqc_request_resource {
373 __le32 resource_number;
377 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
379 /* Get function capabilities (indirect 0x000A)
380 * Get device capabilities (indirect 0x000B)
382 struct i40e_aqc_list_capabilites {
384 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
392 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
394 struct i40e_aqc_list_capabilities_element_resp {
406 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
407 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
408 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
409 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
410 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
411 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
412 #define I40E_AQ_CAP_ID_SRIOV 0x0012
413 #define I40E_AQ_CAP_ID_VF 0x0013
414 #define I40E_AQ_CAP_ID_VMDQ 0x0014
415 #define I40E_AQ_CAP_ID_8021QBG 0x0015
416 #define I40E_AQ_CAP_ID_8021QBR 0x0016
417 #define I40E_AQ_CAP_ID_VSI 0x0017
418 #define I40E_AQ_CAP_ID_DCB 0x0018
419 #define I40E_AQ_CAP_ID_FCOE 0x0021
420 #define I40E_AQ_CAP_ID_RSS 0x0040
421 #define I40E_AQ_CAP_ID_RXQ 0x0041
422 #define I40E_AQ_CAP_ID_TXQ 0x0042
423 #define I40E_AQ_CAP_ID_MSIX 0x0043
424 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
425 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
426 #define I40E_AQ_CAP_ID_1588 0x0046
427 #define I40E_AQ_CAP_ID_IWARP 0x0051
428 #define I40E_AQ_CAP_ID_LED 0x0061
429 #define I40E_AQ_CAP_ID_SDP 0x0062
430 #define I40E_AQ_CAP_ID_MDIO 0x0063
431 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
432 #define I40E_AQ_CAP_ID_CEM 0x00F2
434 /* Set CPPM Configuration (direct 0x0103) */
435 struct i40e_aqc_cppm_configuration {
436 __le16 command_flags;
437 #define I40E_AQ_CPPM_EN_LTRC 0x0800
438 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
439 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
440 #define I40E_AQ_CPPM_EN_HPTC 0x4000
441 #define I40E_AQ_CPPM_EN_DMARC 0x8000
450 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
452 /* Set ARP Proxy command / response (indirect 0x0104) */
453 struct i40e_aqc_arp_proxy_data {
454 __le16 command_flags;
455 #define I40E_AQ_ARP_INIT_IPV4 0x0008
456 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
457 #define I40E_AQ_ARP_ENA 0x0020
458 #define I40E_AQ_ARP_ADD_IPV4 0x0040
459 #define I40E_AQ_ARP_DEL_IPV4 0x0080
466 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
467 struct i40e_aqc_ns_proxy_data {
468 __le16 table_idx_mac_addr_0;
469 __le16 table_idx_mac_addr_1;
470 __le16 table_idx_ipv6_0;
471 __le16 table_idx_ipv6_1;
473 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
474 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
475 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
476 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
477 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
478 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
479 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
480 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
481 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
482 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
483 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
486 u8 local_mac_addr[6];
487 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
491 /* Manage LAA Command (0x0106) - obsolete */
492 struct i40e_aqc_mng_laa {
493 __le16 command_flags;
494 #define I40E_AQ_LAA_FLAG_WR 0x8000
501 /* Manage MAC Address Read Command (indirect 0x0107) */
502 struct i40e_aqc_mac_address_read {
503 __le16 command_flags;
504 #define I40E_AQC_LAN_ADDR_VALID 0x10
505 #define I40E_AQC_SAN_ADDR_VALID 0x20
506 #define I40E_AQC_PORT_ADDR_VALID 0x40
507 #define I40E_AQC_WOL_ADDR_VALID 0x80
508 #define I40E_AQC_ADDR_VALID_MASK 0xf0
514 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
516 struct i40e_aqc_mac_address_read_data {
523 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
525 /* Manage MAC Address Write Command (0x0108) */
526 struct i40e_aqc_mac_address_write {
527 __le16 command_flags;
528 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
529 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
530 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
531 #define I40E_AQC_WRITE_TYPE_MASK 0xc000
537 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
539 /* PXE commands (0x011x) */
541 /* Clear PXE Command and response (direct 0x0110) */
542 struct i40e_aqc_clear_pxe {
547 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
549 /* Switch configuration commands (0x02xx) */
551 /* Used by many indirect commands that only pass an seid and a buffer in the
554 struct i40e_aqc_switch_seid {
561 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
563 /* Get Switch Configuration command (indirect 0x0200)
564 * uses i40e_aqc_switch_seid for the descriptor
566 struct i40e_aqc_get_switch_config_header_resp {
572 struct i40e_aqc_switch_config_element_resp {
574 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
575 #define I40E_AQ_SW_ELEM_TYPE_PF 2
576 #define I40E_AQ_SW_ELEM_TYPE_VF 3
577 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
578 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
579 #define I40E_AQ_SW_ELEM_TYPE_PV 16
580 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
581 #define I40E_AQ_SW_ELEM_TYPE_PA 18
582 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
584 #define I40E_AQ_SW_ELEM_REV_1 1
587 __le16 downlink_seid;
590 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
591 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
592 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
597 /* Get Switch Configuration (indirect 0x0200)
598 * an array of elements are returned in the response buffer
599 * the first in the array is the header, remainder are elements
601 struct i40e_aqc_get_switch_config_resp {
602 struct i40e_aqc_get_switch_config_header_resp header;
603 struct i40e_aqc_switch_config_element_resp element[1];
606 /* Add Statistics (direct 0x0201)
607 * Remove Statistics (direct 0x0202)
609 struct i40e_aqc_add_remove_statistics {
616 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
618 /* Set Port Parameters command (direct 0x0203) */
619 struct i40e_aqc_set_port_parameters {
620 __le16 command_flags;
621 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
622 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
623 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
624 __le16 bad_frame_vsi;
625 __le16 default_seid; /* reserved for command */
629 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
631 /* Get Switch Resource Allocation (indirect 0x0204) */
632 struct i40e_aqc_get_switch_resource_alloc {
633 u8 num_entries; /* reserved for command */
639 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
641 /* expect an array of these structs in the response buffer */
642 struct i40e_aqc_switch_resource_alloc_element_resp {
644 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
645 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
646 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
647 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
648 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
649 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
650 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
651 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
652 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
653 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
654 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
655 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
656 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
657 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
658 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
659 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
660 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
661 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
662 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
667 __le16 total_unalloced;
671 /* Add VSI (indirect 0x0210)
672 * this indirect command uses struct i40e_aqc_vsi_properties_data
673 * as the indirect buffer (128 bytes)
675 * Update VSI (indirect 0x211)
676 * uses the same data structure as Add VSI
678 * Get VSI (indirect 0x0212)
679 * uses the same completion and data structure as Add VSI
681 struct i40e_aqc_add_get_update_vsi {
684 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
685 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
686 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
691 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
692 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
693 #define I40E_AQ_VSI_TYPE_VF 0x0
694 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
695 #define I40E_AQ_VSI_TYPE_PF 0x2
696 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
697 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
702 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
704 struct i40e_aqc_add_get_update_vsi_completion {
713 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
715 struct i40e_aqc_vsi_properties_data {
716 /* first 96 byte are written by SW */
717 __le16 valid_sections;
718 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
719 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
720 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
721 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
722 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
723 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
724 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
725 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
726 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
727 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
729 __le16 switch_id; /* 12bit id combined with flags below */
730 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
731 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
732 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
733 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
734 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
736 /* security section */
738 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
739 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
740 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
743 __le16 pvid; /* VLANS include priority bits */
746 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
747 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
748 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
749 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
750 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
751 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
752 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
753 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
754 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
755 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
756 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
757 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
758 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
759 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
760 u8 pvlan_reserved[3];
761 /* ingress egress up sections */
762 __le32 ingress_table; /* bitmap, 3 bits per up */
763 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
764 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
765 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
766 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
767 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
768 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
769 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
770 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
771 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
772 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
773 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
774 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
775 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
776 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
777 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
778 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
779 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
780 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
781 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
782 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
783 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
784 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
785 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
786 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
787 __le32 egress_table; /* same defines as for ingress table */
788 /* cascaded PV section */
791 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
792 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
793 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
794 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
795 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
796 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
797 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
798 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
799 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
801 /* queue mapping section */
802 __le16 mapping_flags;
803 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
804 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
805 __le16 queue_mapping[16];
806 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
807 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
808 __le16 tc_mapping[8];
809 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
810 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
811 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
812 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
813 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
814 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
815 /* queueing option section */
816 u8 queueing_opt_flags;
817 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
818 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
819 u8 queueing_opt_reserved[3];
820 /* scheduler section */
823 /* outer up section */
824 __le32 outer_up_table; /* same structure and defines as ingress table */
826 /* last 32 bytes are written by FW */
828 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
829 __le16 stat_counter_idx;
831 u8 resp_reserved[12];
834 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
836 /* Add Port Virtualizer (direct 0x0220)
837 * also used for update PV (direct 0x0221) but only flags are used
838 * (IS_CTRL_PORT only works on add PV)
840 struct i40e_aqc_add_update_pv {
841 __le16 command_flags;
842 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
843 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
844 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
845 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
847 __le16 connected_seid;
851 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
853 struct i40e_aqc_add_update_pv_completion {
854 /* reserved for update; for add also encodes error if rc == ENOSPC */
856 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
857 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
858 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
859 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
863 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
865 /* Get PV Params (direct 0x0222)
866 * uses i40e_aqc_switch_seid for the descriptor
869 struct i40e_aqc_get_pv_params_completion {
872 __le16 pv_flags; /* same flags as add_pv */
873 #define I40E_AQC_GET_PV_PV_TYPE 0x1
874 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
875 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
877 __le16 default_port_seid;
880 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
882 /* Add VEB (direct 0x0230) */
883 struct i40e_aqc_add_veb {
885 __le16 downlink_seid;
887 #define I40E_AQC_ADD_VEB_FLOATING 0x1
888 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
889 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
890 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
891 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
892 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
893 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
898 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
900 struct i40e_aqc_add_veb_completion {
903 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
905 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
906 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
907 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
908 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
909 __le16 statistic_index;
914 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
916 /* Get VEB Parameters (direct 0x0232)
917 * uses i40e_aqc_switch_seid for the descriptor
919 struct i40e_aqc_get_veb_parameters_completion {
922 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
923 __le16 statistic_index;
929 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
931 /* Delete Element (direct 0x0243)
932 * uses the generic i40e_aqc_switch_seid
935 /* Add MAC-VLAN (indirect 0x0250) */
937 /* used for the command for most vlan commands */
938 struct i40e_aqc_macvlan {
939 __le16 num_addresses;
941 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
942 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
943 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
944 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
949 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
951 /* indirect data for command and response */
952 struct i40e_aqc_add_macvlan_element_data {
956 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
957 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
958 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
959 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
961 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
962 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
963 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
964 /* response section */
966 #define I40E_AQC_MM_PERFECT_MATCH 0x01
967 #define I40E_AQC_MM_HASH_MATCH 0x02
968 #define I40E_AQC_MM_ERR_NO_RES 0xFF
972 struct i40e_aqc_add_remove_macvlan_completion {
973 __le16 perfect_mac_used;
974 __le16 perfect_mac_free;
975 __le16 unicast_hash_free;
976 __le16 multicast_hash_free;
981 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
983 /* Remove MAC-VLAN (indirect 0x0251)
984 * uses i40e_aqc_macvlan for the descriptor
985 * data points to an array of num_addresses of elements
988 struct i40e_aqc_remove_macvlan_element_data {
992 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
993 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
994 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
995 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
999 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1000 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1001 u8 reply_reserved[3];
1004 /* Add VLAN (indirect 0x0252)
1005 * Remove VLAN (indirect 0x0253)
1006 * use the generic i40e_aqc_macvlan for the command
1008 struct i40e_aqc_add_remove_vlan_element_data {
1011 /* flags for add VLAN */
1012 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1013 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1014 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1015 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1016 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1017 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1018 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1019 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1020 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1021 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1022 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1023 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1024 /* flags for remove VLAN */
1025 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1028 /* flags for add VLAN */
1029 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1030 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1031 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1032 /* flags for remove VLAN */
1033 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1034 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1038 struct i40e_aqc_add_remove_vlan_completion {
1046 /* Set VSI Promiscuous Modes (direct 0x0254) */
1047 struct i40e_aqc_set_vsi_promiscuous_modes {
1048 __le16 promiscuous_flags;
1050 /* flags used for both fields above */
1051 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1052 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1053 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1054 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1055 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1057 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1059 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1063 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1065 /* Add S/E-tag command (direct 0x0255)
1066 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1068 struct i40e_aqc_add_tag {
1070 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1072 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1073 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1074 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1076 __le16 queue_number;
1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1082 struct i40e_aqc_add_remove_tag_completion {
1088 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1090 /* Remove S/E-tag command (direct 0x0256)
1091 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1093 struct i40e_aqc_remove_tag {
1095 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1096 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1097 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1102 /* Add multicast E-Tag (direct 0x0257)
1103 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1104 * and no external data
1106 struct i40e_aqc_add_remove_mcast_etag {
1109 u8 num_unicast_etags;
1111 __le32 addr_high; /* address of array of 2-byte s-tags */
1115 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1117 struct i40e_aqc_add_remove_mcast_etag_completion {
1119 __le16 mcast_etags_used;
1120 __le16 mcast_etags_free;
1126 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1128 /* Update S/E-Tag (direct 0x0259) */
1129 struct i40e_aqc_update_tag {
1131 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1132 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1133 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1139 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1141 struct i40e_aqc_update_tag_completion {
1147 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1149 /* Add Control Packet filter (direct 0x025A)
1150 * Remove Control Packet filter (direct 0x025B)
1151 * uses the i40e_aqc_add_oveb_cloud,
1152 * and the generic direct completion structure
1154 struct i40e_aqc_add_remove_control_packet_filter {
1158 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1159 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1160 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1161 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1162 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1164 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1165 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1166 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1171 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1173 struct i40e_aqc_add_remove_control_packet_filter_completion {
1174 __le16 mac_etype_used;
1176 __le16 mac_etype_free;
1181 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1183 /* Add Cloud filters (indirect 0x025C)
1184 * Remove Cloud filters (indirect 0x025D)
1185 * uses the i40e_aqc_add_remove_cloud_filters,
1186 * and the generic indirect completion structure
1188 struct i40e_aqc_add_remove_cloud_filters {
1192 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1193 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1194 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1200 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1202 struct i40e_aqc_add_remove_cloud_filters_element_data {
1216 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1217 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1218 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1219 /* 0x0000 reserved */
1220 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1221 /* 0x0002 reserved */
1222 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1223 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1224 /* 0x0005 reserved */
1225 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1226 /* 0x0007 reserved */
1227 /* 0x0008 reserved */
1228 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1229 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1230 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1231 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1233 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1234 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1235 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1236 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1237 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1239 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1240 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1241 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1242 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1243 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1244 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1248 __le16 queue_number;
1249 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1250 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1251 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1253 /* response section */
1254 u8 allocation_result;
1255 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1256 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1257 u8 response_reserved[7];
1260 struct i40e_aqc_remove_cloud_filters_completion {
1261 __le16 perfect_ovlan_used;
1262 __le16 perfect_ovlan_free;
1269 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1271 /* Add Mirror Rule (indirect or direct 0x0260)
1272 * Delete Mirror Rule (indirect or direct 0x0261)
1273 * note: some rule types (4,5) do not use an external buffer.
1274 * take care to set the flags correctly.
1276 struct i40e_aqc_add_delete_mirror_rule {
1279 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1280 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1281 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1282 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1283 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1284 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1285 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1286 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1288 __le16 destination; /* VSI for add, rule id for delete */
1289 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1293 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1295 struct i40e_aqc_add_delete_mirror_rule_completion {
1297 __le16 rule_id; /* only used on add */
1298 __le16 mirror_rules_used;
1299 __le16 mirror_rules_free;
1304 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1308 /* PFC Ignore (direct 0x0301)
1309 * the command and response use the same descriptor structure
1311 struct i40e_aqc_pfc_ignore {
1313 u8 command_flags; /* unused on response */
1314 #define I40E_AQC_PFC_IGNORE_SET 0x80
1315 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1319 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1321 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1322 * with no parameters
1325 /* TX scheduler 0x04xx */
1327 /* Almost all the indirect commands use
1328 * this generic struct to pass the SEID in param0
1330 struct i40e_aqc_tx_sched_ind {
1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1339 /* Several commands respond with a set of queue set handles */
1340 struct i40e_aqc_qs_handles_resp {
1341 __le16 qs_handles[8];
1344 /* Configure VSI BW limits (direct 0x0400) */
1345 struct i40e_aqc_configure_vsi_bw_limit {
1350 u8 max_credit; /* 0-3, limit = 2^max */
1354 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1356 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1357 * responds with i40e_aqc_qs_handles_resp
1359 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1362 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1364 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1365 __le16 tc_bw_max[2];
1369 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1370 * responds with i40e_aqc_qs_handles_resp
1372 struct i40e_aqc_configure_vsi_tc_bw_data {
1375 u8 tc_bw_credits[8];
1377 __le16 qs_handles[8];
1380 /* Query vsi bw configuration (indirect 0x0408) */
1381 struct i40e_aqc_query_vsi_bw_config_resp {
1383 u8 tc_suspended_bits;
1385 __le16 qs_handles[8];
1387 __le16 port_bw_limit;
1389 u8 max_bw; /* 0-3, limit = 2^max */
1393 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1394 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1397 u8 share_credits[8];
1400 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1401 __le16 tc_bw_max[2];
1404 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1405 struct i40e_aqc_configure_switching_comp_bw_limit {
1410 u8 max_bw; /* 0-3, limit = 2^max */
1414 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1416 /* Enable Physical Port ETS (indirect 0x0413)
1417 * Modify Physical Port ETS (indirect 0x0414)
1418 * Disable Physical Port ETS (indirect 0x0415)
1420 struct i40e_aqc_configure_switching_comp_ets_data {
1424 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1425 u8 tc_strict_priority_flags;
1427 u8 tc_bw_share_credits[8];
1431 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1432 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1435 __le16 tc_bw_credit[8];
1437 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1438 __le16 tc_bw_max[2];
1442 /* Configure Switching Component Bandwidth Allocation per Tc
1445 struct i40e_aqc_configure_switching_comp_bw_config_data {
1448 u8 absolute_credits; /* bool */
1449 u8 tc_bw_share_credits[8];
1453 /* Query Switching Component Configuration (indirect 0x0418) */
1454 struct i40e_aqc_query_switching_comp_ets_config_resp {
1457 __le16 port_bw_limit;
1459 u8 tc_bw_max; /* 0-3, limit = 2^max */
1463 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1464 struct i40e_aqc_query_port_ets_config_resp {
1468 u8 tc_strict_priority_bits;
1470 u8 tc_bw_share_credits[8];
1471 __le16 tc_bw_limits[8];
1473 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1474 __le16 tc_bw_max[2];
1478 /* Query Switching Component Bandwidth Allocation per Traffic Type
1481 struct i40e_aqc_query_switching_comp_bw_config_resp {
1484 u8 absolute_credits_enable; /* bool */
1485 u8 tc_bw_share_credits[8];
1486 __le16 tc_bw_limits[8];
1488 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1489 __le16 tc_bw_max[2];
1492 /* Suspend/resume port TX traffic
1493 * (direct 0x041B and 0x041C) uses the generic SEID struct
1496 /* Configure partition BW
1499 struct i40e_aqc_configure_partition_bw_data {
1500 __le16 pf_valid_bits;
1501 u8 min_bw[16]; /* guaranteed bandwidth */
1502 u8 max_bw[16]; /* bandwidth limit */
1505 /* Get and set the active HMC resource profile and status.
1506 * (direct 0x0500) and (direct 0x0501)
1508 struct i40e_aq_get_set_hmc_resource_profile {
1514 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1516 enum i40e_aq_hmc_profile {
1517 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1518 I40E_HMC_PROFILE_DEFAULT = 1,
1519 I40E_HMC_PROFILE_FAVOR_VF = 2,
1520 I40E_HMC_PROFILE_EQUAL = 3,
1523 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1524 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1526 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1528 /* set in param0 for get phy abilities to report qualified modules */
1529 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1530 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1532 enum i40e_aq_phy_type {
1533 I40E_PHY_TYPE_SGMII = 0x0,
1534 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1535 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1536 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1537 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1538 I40E_PHY_TYPE_XAUI = 0x5,
1539 I40E_PHY_TYPE_XFI = 0x6,
1540 I40E_PHY_TYPE_SFI = 0x7,
1541 I40E_PHY_TYPE_XLAUI = 0x8,
1542 I40E_PHY_TYPE_XLPPI = 0x9,
1543 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1544 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1545 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1546 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1547 I40E_PHY_TYPE_100BASE_TX = 0x11,
1548 I40E_PHY_TYPE_1000BASE_T = 0x12,
1549 I40E_PHY_TYPE_10GBASE_T = 0x13,
1550 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1551 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1552 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1553 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1554 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1555 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1556 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1557 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1558 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1559 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1560 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1564 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1565 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1566 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1567 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1568 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1570 enum i40e_aq_link_speed {
1571 I40E_LINK_SPEED_UNKNOWN = 0,
1572 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1573 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1574 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1575 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1576 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1579 struct i40e_aqc_module_desc {
1587 struct i40e_aq_get_phy_abilities_resp {
1588 __le32 phy_type; /* bitmap using the above enum for offsets */
1589 u8 link_speed; /* bitmap using the above enum bit patterns */
1591 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1592 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1593 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1594 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1595 #define I40E_AQ_PHY_AN_ENABLED 0x10
1596 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1597 __le16 eee_capability;
1598 #define I40E_AQ_EEE_100BASE_TX 0x0002
1599 #define I40E_AQ_EEE_1000BASE_T 0x0004
1600 #define I40E_AQ_EEE_10GBASE_T 0x0008
1601 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1602 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1603 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1606 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1610 u8 qualified_module_count;
1611 #define I40E_AQ_PHY_MAX_QMS 16
1612 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1615 /* Set PHY Config (direct 0x0601) */
1616 struct i40e_aq_set_phy_config { /* same bits as above in all */
1620 /* bits 0-2 use the values from get_phy_abilities_resp */
1621 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1622 #define I40E_AQ_PHY_ENABLE_AN 0x10
1623 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1624 __le16 eee_capability;
1630 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1632 /* Set MAC Config command data structure (direct 0x0603) */
1633 struct i40e_aq_set_mac_config {
1634 __le16 max_frame_size;
1636 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1637 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1638 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1639 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1640 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1641 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1642 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1643 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1644 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1645 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1646 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1647 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1648 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1649 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1650 u8 tx_timer_priority; /* bitmap */
1651 __le16 tx_timer_value;
1652 __le16 fc_refresh_threshold;
1656 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1658 /* Restart Auto-Negotiation (direct 0x605) */
1659 struct i40e_aqc_set_link_restart_an {
1661 #define I40E_AQ_PHY_RESTART_AN 0x02
1662 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1666 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1668 /* Get Link Status cmd & response data structure (direct 0x0607) */
1669 struct i40e_aqc_get_link_status {
1670 __le16 command_flags; /* only field set on command */
1671 #define I40E_AQ_LSE_MASK 0x3
1672 #define I40E_AQ_LSE_NOP 0x0
1673 #define I40E_AQ_LSE_DISABLE 0x2
1674 #define I40E_AQ_LSE_ENABLE 0x3
1675 /* only response uses this flag */
1676 #define I40E_AQ_LSE_IS_ENABLED 0x1
1677 u8 phy_type; /* i40e_aq_phy_type */
1678 u8 link_speed; /* i40e_aq_link_speed */
1680 #define I40E_AQ_LINK_UP 0x01
1681 #define I40E_AQ_LINK_FAULT 0x02
1682 #define I40E_AQ_LINK_FAULT_TX 0x04
1683 #define I40E_AQ_LINK_FAULT_RX 0x08
1684 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1685 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1686 #define I40E_AQ_SIGNAL_DETECT 0x80
1688 #define I40E_AQ_AN_COMPLETED 0x01
1689 #define I40E_AQ_LP_AN_ABILITY 0x02
1690 #define I40E_AQ_PD_FAULT 0x04
1691 #define I40E_AQ_FEC_EN 0x08
1692 #define I40E_AQ_PHY_LOW_POWER 0x10
1693 #define I40E_AQ_LINK_PAUSE_TX 0x20
1694 #define I40E_AQ_LINK_PAUSE_RX 0x40
1695 #define I40E_AQ_QUALIFIED_MODULE 0x80
1697 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1698 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1699 #define I40E_AQ_LINK_TX_SHIFT 0x02
1700 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1701 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1702 #define I40E_AQ_LINK_TX_DRAINED 0x01
1703 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1704 #define I40E_AQ_LINK_FORCED_40G 0x10
1705 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1706 __le16 max_frame_size;
1708 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1709 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1713 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1715 /* Set event mask command (direct 0x613) */
1716 struct i40e_aqc_set_phy_int_mask {
1719 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1720 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1721 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1722 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1723 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1724 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1725 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1726 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1727 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1731 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1733 /* Get Local AN advt register (direct 0x0614)
1734 * Set Local AN advt register (direct 0x0615)
1735 * Get Link Partner AN advt register (direct 0x0616)
1737 struct i40e_aqc_an_advt_reg {
1738 __le32 local_an_reg0;
1739 __le16 local_an_reg1;
1743 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1745 /* Set Loopback mode (0x0618) */
1746 struct i40e_aqc_set_lb_mode {
1748 #define I40E_AQ_LB_PHY_LOCAL 0x01
1749 #define I40E_AQ_LB_PHY_REMOTE 0x02
1750 #define I40E_AQ_LB_MAC_LOCAL 0x04
1754 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1756 /* Set PHY Debug command (0x0622) */
1757 struct i40e_aqc_set_phy_debug {
1759 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1760 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1761 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1762 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1763 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1764 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1765 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1766 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1770 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1772 enum i40e_aq_phy_reg_type {
1773 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1774 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1775 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1778 /* NVM Read command (indirect 0x0701)
1779 * NVM Erase commands (direct 0x0702)
1780 * NVM Update commands (indirect 0x0703)
1782 struct i40e_aqc_nvm_update {
1784 #define I40E_AQ_NVM_LAST_CMD 0x01
1785 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1793 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1795 /* NVM Config Read (indirect 0x0704) */
1796 struct i40e_aqc_nvm_config_read {
1798 #define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1799 #define ANVM_READ_SINGLE_FEATURE 0
1800 #define ANVM_READ_MULTIPLE_FEATURES 1
1801 __le16 element_count;
1802 __le16 element_id; /* Feature/field ID */
1804 __le32 address_high;
1808 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1810 /* NVM Config Write (indirect 0x0705) */
1811 struct i40e_aqc_nvm_config_write {
1813 __le16 element_count;
1815 __le32 address_high;
1819 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1821 struct i40e_aqc_nvm_config_data_feature {
1824 __le16 feature_options;
1825 __le16 feature_selection;
1828 struct i40e_aqc_nvm_config_data_immediate_field {
1829 #define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
1832 __le16 field_options;
1836 /* Send to PF command (indirect 0x0801) id is only used by PF
1837 * Send to VF command (indirect 0x0802) id is only used by PF
1838 * Send to Peer PF command (indirect 0x0803)
1840 struct i40e_aqc_pf_vf_message {
1847 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1849 /* Alternate structure */
1851 /* Direct write (direct 0x0900)
1852 * Direct read (direct 0x0902)
1854 struct i40e_aqc_alternate_write {
1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1863 /* Indirect write (indirect 0x0901)
1864 * Indirect read (indirect 0x0903)
1867 struct i40e_aqc_alternate_ind_write {
1874 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1876 /* Done alternate write (direct 0x0904)
1879 struct i40e_aqc_alternate_write_done {
1881 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1882 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1883 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1884 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1888 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1890 /* Set OEM mode (direct 0x0905) */
1891 struct i40e_aqc_alternate_set_mode {
1893 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1894 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1898 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1900 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1902 /* async events 0x10xx */
1904 /* Lan Queue Overflow Event (direct, 0x1001) */
1905 struct i40e_aqc_lan_overflow {
1906 __le32 prtdcb_rupto;
1911 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1913 /* Get LLDP MIB (indirect 0x0A00) */
1914 struct i40e_aqc_lldp_get_mib {
1917 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1918 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1919 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1920 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1921 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1922 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1923 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1924 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1925 #define I40E_AQ_LLDP_TX_SHIFT 0x4
1926 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1927 /* TX pause flags use I40E_AQ_LINK_TX_* above */
1935 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1937 /* Configure LLDP MIB Change Event (direct 0x0A01)
1938 * also used for the event (with type in the command field)
1940 struct i40e_aqc_lldp_update_mib {
1942 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1943 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1949 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1951 /* Add LLDP TLV (indirect 0x0A02)
1952 * Delete LLDP TLV (indirect 0x0A04)
1954 struct i40e_aqc_lldp_add_tlv {
1955 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1963 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1965 /* Update LLDP TLV (indirect 0x0A03) */
1966 struct i40e_aqc_lldp_update_tlv {
1967 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1976 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1978 /* Stop LLDP (direct 0x0A05) */
1979 struct i40e_aqc_lldp_stop {
1981 #define I40E_AQ_LLDP_AGENT_STOP 0x0
1982 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1986 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1988 /* Start LLDP (direct 0x0A06) */
1990 struct i40e_aqc_lldp_start {
1992 #define I40E_AQ_LLDP_AGENT_START 0x1
1996 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1998 /* Apply MIB changes (0x0A07)
1999 * uses the generic struc as it contains no data
2002 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2003 struct i40e_aqc_add_udp_tunnel {
2007 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2008 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2009 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2013 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2015 struct i40e_aqc_add_udp_tunnel_completion {
2017 u8 filter_entry_index;
2019 #define I40E_AQC_SINGLE_PF 0x0
2020 #define I40E_AQC_MULTIPLE_PFS 0x1
2025 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2027 /* remove UDP Tunnel command (0x0B01) */
2028 struct i40e_aqc_remove_udp_tunnel {
2030 u8 index; /* 0 to 15 */
2034 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2036 struct i40e_aqc_del_udp_tunnel_completion {
2038 u8 index; /* 0 to 15 */
2040 u8 total_filters_used;
2044 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2046 /* tunnel key structure 0x0B10 */
2048 struct i40e_aqc_tunnel_key_structure {
2051 u8 key1_len; /* 0 to 15 */
2052 u8 key2_len; /* 0 to 15 */
2054 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2055 /* response flags */
2056 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2057 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2058 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2059 u8 network_key_index;
2060 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2061 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2062 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2063 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2067 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2069 /* OEM mode commands (direct 0xFE0x) */
2070 struct i40e_aqc_oem_param_change {
2072 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2073 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2074 #define I40E_AQ_OEM_PARAM_MAC 2
2075 __le32 param_value1;
2079 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2081 struct i40e_aqc_oem_state_change {
2083 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2084 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2088 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2090 /* debug commands */
2092 /* get device id (0xFF00) uses the generic structure */
2094 /* set test more (0xFF01, internal) */
2096 struct i40e_acq_set_test_mode {
2098 #define I40E_AQ_TEST_PARTIAL 0
2099 #define I40E_AQ_TEST_FULL 1
2100 #define I40E_AQ_TEST_NVM 2
2103 #define I40E_AQ_TEST_OPEN 0
2104 #define I40E_AQ_TEST_CLOSE 1
2105 #define I40E_AQ_TEST_INC 2
2107 __le32 address_high;
2111 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2113 /* Debug Read Register command (0xFF03)
2114 * Debug Write Register command (0xFF04)
2116 struct i40e_aqc_debug_reg_read_write {
2123 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2125 /* Scatter/gather Reg Read (indirect 0xFF05)
2126 * Scatter/gather Reg Write (indirect 0xFF06)
2129 /* i40e_aq_desc is used for the command */
2130 struct i40e_aqc_debug_reg_sg_element_data {
2135 /* Debug Modify register (direct 0xFF07) */
2136 struct i40e_aqc_debug_modify_reg {
2143 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2145 /* dump internal data (0xFF08, indirect) */
2147 #define I40E_AQ_CLUSTER_ID_AUX 0
2148 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2149 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2150 #define I40E_AQ_CLUSTER_ID_HMC 3
2151 #define I40E_AQ_CLUSTER_ID_MAC0 4
2152 #define I40E_AQ_CLUSTER_ID_MAC1 5
2153 #define I40E_AQ_CLUSTER_ID_MAC2 6
2154 #define I40E_AQ_CLUSTER_ID_MAC3 7
2155 #define I40E_AQ_CLUSTER_ID_DCB 8
2156 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2157 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2158 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2160 struct i40e_aqc_debug_dump_internals {
2165 __le32 address_high;
2169 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2171 struct i40e_aqc_debug_modify_internals {
2173 u8 cluster_specific_params[7];
2174 __le32 address_high;
2178 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);