1 /******************************************************************************
3 Copyright (c) 2013-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "i40e_virtchnl.h"
42 * i40e_set_mac_type - Sets MAC type
43 * @hw: pointer to the HW structure
45 * This function sets the mac type of the adapter based on the
46 * vendor ID and device ID stored in the hw structure.
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 enum i40e_status_code status = I40E_SUCCESS;
52 DEBUGFUNC("i40e_set_mac_type\n");
54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 switch (hw->device_id) {
56 case I40E_DEV_ID_SFP_XL710:
57 case I40E_DEV_ID_QEMU:
58 case I40E_DEV_ID_KX_A:
59 case I40E_DEV_ID_KX_B:
60 case I40E_DEV_ID_KX_C:
61 case I40E_DEV_ID_QSFP_A:
62 case I40E_DEV_ID_QSFP_B:
63 case I40E_DEV_ID_QSFP_C:
64 case I40E_DEV_ID_10G_BASE_T:
65 case I40E_DEV_ID_20G_KR2:
66 hw->mac.type = I40E_MAC_XL710;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
87 * @hw: debug mask related to admin queue
89 * @desc: pointer to admin queue descriptor
90 * @buffer: pointer to command buffer
91 * @buf_len: max length of buffer
93 * Dumps debug log about adminq command with descriptor contents.
95 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
96 void *buffer, u16 buf_len)
98 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
99 u16 len = LE16_TO_CPU(aq_desc->datalen);
100 u8 *buf = (u8 *)buffer;
103 if ((!(mask & hw->debug_mask)) || (desc == NULL))
107 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
108 LE16_TO_CPU(aq_desc->opcode),
109 LE16_TO_CPU(aq_desc->flags),
110 LE16_TO_CPU(aq_desc->datalen),
111 LE16_TO_CPU(aq_desc->retval));
112 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
113 LE32_TO_CPU(aq_desc->cookie_high),
114 LE32_TO_CPU(aq_desc->cookie_low));
115 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
116 LE32_TO_CPU(aq_desc->params.internal.param0),
117 LE32_TO_CPU(aq_desc->params.internal.param1));
118 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
119 LE32_TO_CPU(aq_desc->params.external.addr_high),
120 LE32_TO_CPU(aq_desc->params.external.addr_low));
122 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
123 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
126 /* write the full 16-byte chunks */
127 for (i = 0; i < (len - 16); i += 16)
129 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
130 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
131 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
132 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
133 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
134 /* write whatever's left over without overrunning the buffer */
139 memset(d_buf, 0, sizeof(d_buf));
140 j += sprintf(d_buf, "\t0x%04X ", i);
142 j += sprintf(&d_buf[j], " %02X", buf[i++]);
143 i40e_debug(hw, mask, "%s\n", d_buf);
149 * i40e_check_asq_alive
150 * @hw: pointer to the hw struct
152 * Returns TRUE if Queue is enabled else FALSE.
154 bool i40e_check_asq_alive(struct i40e_hw *hw)
157 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
163 * i40e_aq_queue_shutdown
164 * @hw: pointer to the hw struct
165 * @unloading: is the driver unloading itself
167 * Tell the Firmware that we're shutting down the AdminQ and whether
168 * or not the driver is unloading as well.
170 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
173 struct i40e_aq_desc desc;
174 struct i40e_aqc_queue_shutdown *cmd =
175 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
176 enum i40e_status_code status;
178 i40e_fill_default_direct_cmd_desc(&desc,
179 i40e_aqc_opc_queue_shutdown);
182 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
183 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
188 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
189 * hardware to a bit-field that can be used by SW to more easily determine the
192 * Macros are used to shorten the table lines and make this table human
195 * We store the PTYPE in the top byte of the bit field - this is just so that
196 * we can check that the table doesn't have a row missing, as the index into
197 * the table should be the PTYPE.
201 * IF NOT i40e_ptype_lookup[ptype].known
204 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
205 * Use the rest of the fields to look at the tunnels, inner protocols, etc
207 * Use the enum i40e_rx_l2_ptype to decode the packet type
211 /* macro to make the table lines short */
212 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
215 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
216 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
217 I40E_RX_PTYPE_##OUTER_FRAG, \
218 I40E_RX_PTYPE_TUNNEL_##T, \
219 I40E_RX_PTYPE_TUNNEL_END_##TE, \
220 I40E_RX_PTYPE_##TEF, \
221 I40E_RX_PTYPE_INNER_PROT_##I, \
222 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
224 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
225 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
227 /* shorter macros makes the table fit but are terse */
228 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
229 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
230 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
232 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
233 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
234 /* L2 Packet types */
235 I40E_PTT_UNUSED_ENTRY(0),
236 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
237 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
238 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
239 I40E_PTT_UNUSED_ENTRY(4),
240 I40E_PTT_UNUSED_ENTRY(5),
241 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
242 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT_UNUSED_ENTRY(8),
244 I40E_PTT_UNUSED_ENTRY(9),
245 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
246 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
247 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
258 /* Non Tunneled IPv4 */
259 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
260 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
262 I40E_PTT_UNUSED_ENTRY(25),
263 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
264 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
265 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
268 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(32),
272 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
277 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(39),
281 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
285 /* IPv4 --> GRE/NAT */
286 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
288 /* IPv4 --> GRE/NAT --> IPv4 */
289 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(47),
293 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
297 /* IPv4 --> GRE/NAT --> IPv6 */
298 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(54),
302 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
306 /* IPv4 --> GRE/NAT --> MAC */
307 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
309 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
310 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(62),
314 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
318 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
319 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(69),
323 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
327 /* IPv4 --> GRE/NAT --> MAC/VLAN */
328 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
330 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
331 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
332 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
333 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
334 I40E_PTT_UNUSED_ENTRY(77),
335 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
336 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
337 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
339 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
340 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
341 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
342 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
343 I40E_PTT_UNUSED_ENTRY(84),
344 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
345 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
346 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
348 /* Non Tunneled IPv6 */
349 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
350 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
352 I40E_PTT_UNUSED_ENTRY(91),
353 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
354 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
355 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
358 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(98),
362 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
367 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(105),
371 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
375 /* IPv6 --> GRE/NAT */
376 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
378 /* IPv6 --> GRE/NAT -> IPv4 */
379 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(113),
383 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
387 /* IPv6 --> GRE/NAT -> IPv6 */
388 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(120),
392 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
396 /* IPv6 --> GRE/NAT -> MAC */
397 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
399 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
400 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(128),
404 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
408 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
409 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(135),
413 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
417 /* IPv6 --> GRE/NAT -> MAC/VLAN */
418 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
420 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
421 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
422 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
423 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
424 I40E_PTT_UNUSED_ENTRY(143),
425 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
426 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
427 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
429 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
430 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
431 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
432 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
433 I40E_PTT_UNUSED_ENTRY(150),
434 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
435 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
436 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
439 I40E_PTT_UNUSED_ENTRY(154),
440 I40E_PTT_UNUSED_ENTRY(155),
441 I40E_PTT_UNUSED_ENTRY(156),
442 I40E_PTT_UNUSED_ENTRY(157),
443 I40E_PTT_UNUSED_ENTRY(158),
444 I40E_PTT_UNUSED_ENTRY(159),
446 I40E_PTT_UNUSED_ENTRY(160),
447 I40E_PTT_UNUSED_ENTRY(161),
448 I40E_PTT_UNUSED_ENTRY(162),
449 I40E_PTT_UNUSED_ENTRY(163),
450 I40E_PTT_UNUSED_ENTRY(164),
451 I40E_PTT_UNUSED_ENTRY(165),
452 I40E_PTT_UNUSED_ENTRY(166),
453 I40E_PTT_UNUSED_ENTRY(167),
454 I40E_PTT_UNUSED_ENTRY(168),
455 I40E_PTT_UNUSED_ENTRY(169),
457 I40E_PTT_UNUSED_ENTRY(170),
458 I40E_PTT_UNUSED_ENTRY(171),
459 I40E_PTT_UNUSED_ENTRY(172),
460 I40E_PTT_UNUSED_ENTRY(173),
461 I40E_PTT_UNUSED_ENTRY(174),
462 I40E_PTT_UNUSED_ENTRY(175),
463 I40E_PTT_UNUSED_ENTRY(176),
464 I40E_PTT_UNUSED_ENTRY(177),
465 I40E_PTT_UNUSED_ENTRY(178),
466 I40E_PTT_UNUSED_ENTRY(179),
468 I40E_PTT_UNUSED_ENTRY(180),
469 I40E_PTT_UNUSED_ENTRY(181),
470 I40E_PTT_UNUSED_ENTRY(182),
471 I40E_PTT_UNUSED_ENTRY(183),
472 I40E_PTT_UNUSED_ENTRY(184),
473 I40E_PTT_UNUSED_ENTRY(185),
474 I40E_PTT_UNUSED_ENTRY(186),
475 I40E_PTT_UNUSED_ENTRY(187),
476 I40E_PTT_UNUSED_ENTRY(188),
477 I40E_PTT_UNUSED_ENTRY(189),
479 I40E_PTT_UNUSED_ENTRY(190),
480 I40E_PTT_UNUSED_ENTRY(191),
481 I40E_PTT_UNUSED_ENTRY(192),
482 I40E_PTT_UNUSED_ENTRY(193),
483 I40E_PTT_UNUSED_ENTRY(194),
484 I40E_PTT_UNUSED_ENTRY(195),
485 I40E_PTT_UNUSED_ENTRY(196),
486 I40E_PTT_UNUSED_ENTRY(197),
487 I40E_PTT_UNUSED_ENTRY(198),
488 I40E_PTT_UNUSED_ENTRY(199),
490 I40E_PTT_UNUSED_ENTRY(200),
491 I40E_PTT_UNUSED_ENTRY(201),
492 I40E_PTT_UNUSED_ENTRY(202),
493 I40E_PTT_UNUSED_ENTRY(203),
494 I40E_PTT_UNUSED_ENTRY(204),
495 I40E_PTT_UNUSED_ENTRY(205),
496 I40E_PTT_UNUSED_ENTRY(206),
497 I40E_PTT_UNUSED_ENTRY(207),
498 I40E_PTT_UNUSED_ENTRY(208),
499 I40E_PTT_UNUSED_ENTRY(209),
501 I40E_PTT_UNUSED_ENTRY(210),
502 I40E_PTT_UNUSED_ENTRY(211),
503 I40E_PTT_UNUSED_ENTRY(212),
504 I40E_PTT_UNUSED_ENTRY(213),
505 I40E_PTT_UNUSED_ENTRY(214),
506 I40E_PTT_UNUSED_ENTRY(215),
507 I40E_PTT_UNUSED_ENTRY(216),
508 I40E_PTT_UNUSED_ENTRY(217),
509 I40E_PTT_UNUSED_ENTRY(218),
510 I40E_PTT_UNUSED_ENTRY(219),
512 I40E_PTT_UNUSED_ENTRY(220),
513 I40E_PTT_UNUSED_ENTRY(221),
514 I40E_PTT_UNUSED_ENTRY(222),
515 I40E_PTT_UNUSED_ENTRY(223),
516 I40E_PTT_UNUSED_ENTRY(224),
517 I40E_PTT_UNUSED_ENTRY(225),
518 I40E_PTT_UNUSED_ENTRY(226),
519 I40E_PTT_UNUSED_ENTRY(227),
520 I40E_PTT_UNUSED_ENTRY(228),
521 I40E_PTT_UNUSED_ENTRY(229),
523 I40E_PTT_UNUSED_ENTRY(230),
524 I40E_PTT_UNUSED_ENTRY(231),
525 I40E_PTT_UNUSED_ENTRY(232),
526 I40E_PTT_UNUSED_ENTRY(233),
527 I40E_PTT_UNUSED_ENTRY(234),
528 I40E_PTT_UNUSED_ENTRY(235),
529 I40E_PTT_UNUSED_ENTRY(236),
530 I40E_PTT_UNUSED_ENTRY(237),
531 I40E_PTT_UNUSED_ENTRY(238),
532 I40E_PTT_UNUSED_ENTRY(239),
534 I40E_PTT_UNUSED_ENTRY(240),
535 I40E_PTT_UNUSED_ENTRY(241),
536 I40E_PTT_UNUSED_ENTRY(242),
537 I40E_PTT_UNUSED_ENTRY(243),
538 I40E_PTT_UNUSED_ENTRY(244),
539 I40E_PTT_UNUSED_ENTRY(245),
540 I40E_PTT_UNUSED_ENTRY(246),
541 I40E_PTT_UNUSED_ENTRY(247),
542 I40E_PTT_UNUSED_ENTRY(248),
543 I40E_PTT_UNUSED_ENTRY(249),
545 I40E_PTT_UNUSED_ENTRY(250),
546 I40E_PTT_UNUSED_ENTRY(251),
547 I40E_PTT_UNUSED_ENTRY(252),
548 I40E_PTT_UNUSED_ENTRY(253),
549 I40E_PTT_UNUSED_ENTRY(254),
550 I40E_PTT_UNUSED_ENTRY(255)
555 * i40e_validate_mac_addr - Validate unicast MAC address
556 * @mac_addr: pointer to MAC address
558 * Tests a MAC address to ensure it is a valid Individual Address
560 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
562 enum i40e_status_code status = I40E_SUCCESS;
564 DEBUGFUNC("i40e_validate_mac_addr");
566 /* Broadcast addresses ARE multicast addresses
567 * Make sure it is not a multicast address
568 * Reject the zero address
570 if (I40E_IS_MULTICAST(mac_addr) ||
571 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
572 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
573 status = I40E_ERR_INVALID_MAC_ADDR;
579 * i40e_init_shared_code - Initialize the shared code
580 * @hw: pointer to hardware structure
582 * This assigns the MAC type and PHY code and inits the NVM.
583 * Does not touch the hardware. This function must be called prior to any
584 * other function in the shared code. The i40e_hw structure should be
585 * memset to 0 prior to calling this function. The following fields in
586 * hw structure should be filled in prior to calling this function:
587 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
588 * subsystem_vendor_id, and revision_id
590 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
592 enum i40e_status_code status = I40E_SUCCESS;
593 u32 port, ari, func_rid;
595 DEBUGFUNC("i40e_init_shared_code");
597 i40e_set_mac_type(hw);
599 switch (hw->mac.type) {
603 return I40E_ERR_DEVICE_NOT_SUPPORTED;
606 hw->phy.get_link_info = TRUE;
608 /* Determine port number and PF number*/
609 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
610 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
612 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
613 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
614 func_rid = rd32(hw, I40E_PF_FUNC_RID);
616 hw->pf_id = (u8)(func_rid & 0xff);
618 hw->pf_id = (u8)(func_rid & 0x7);
620 status = i40e_init_nvm(hw);
625 * i40e_aq_mac_address_read - Retrieve the MAC addresses
626 * @hw: pointer to the hw struct
627 * @flags: a return indicator of what addresses were added to the addr store
628 * @addrs: the requestor's mac addr store
629 * @cmd_details: pointer to command details structure or NULL
631 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
633 struct i40e_aqc_mac_address_read_data *addrs,
634 struct i40e_asq_cmd_details *cmd_details)
636 struct i40e_aq_desc desc;
637 struct i40e_aqc_mac_address_read *cmd_data =
638 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
639 enum i40e_status_code status;
641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
642 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
644 status = i40e_asq_send_command(hw, &desc, addrs,
645 sizeof(*addrs), cmd_details);
646 *flags = LE16_TO_CPU(cmd_data->command_flags);
652 * i40e_aq_mac_address_write - Change the MAC addresses
653 * @hw: pointer to the hw struct
654 * @flags: indicates which MAC to be written
655 * @mac_addr: address to write
656 * @cmd_details: pointer to command details structure or NULL
658 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
659 u16 flags, u8 *mac_addr,
660 struct i40e_asq_cmd_details *cmd_details)
662 struct i40e_aq_desc desc;
663 struct i40e_aqc_mac_address_write *cmd_data =
664 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
665 enum i40e_status_code status;
667 i40e_fill_default_direct_cmd_desc(&desc,
668 i40e_aqc_opc_mac_address_write);
669 cmd_data->command_flags = CPU_TO_LE16(flags);
670 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
671 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
672 ((u32)mac_addr[3] << 16) |
673 ((u32)mac_addr[4] << 8) |
676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
682 * i40e_get_mac_addr - get MAC address
683 * @hw: pointer to the HW structure
684 * @mac_addr: pointer to MAC address
686 * Reads the adapter's MAC address from register
688 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
690 struct i40e_aqc_mac_address_read_data addrs;
691 enum i40e_status_code status;
694 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
696 if (flags & I40E_AQC_LAN_ADDR_VALID)
697 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
703 * i40e_get_port_mac_addr - get Port MAC address
704 * @hw: pointer to the HW structure
705 * @mac_addr: pointer to Port MAC address
707 * Reads the adapter's Port MAC address
709 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
711 struct i40e_aqc_mac_address_read_data addrs;
712 enum i40e_status_code status;
715 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
719 if (flags & I40E_AQC_PORT_ADDR_VALID)
720 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
722 status = I40E_ERR_INVALID_MAC_ADDR;
728 * i40e_pre_tx_queue_cfg - pre tx queue configure
729 * @hw: pointer to the HW structure
730 * @queue: target pf queue index
731 * @enable: state change request
733 * Handles hw requirement to indicate intention to enable
734 * or disable target queue.
736 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
738 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
742 if (abs_queue_idx >= 128) {
743 reg_block = abs_queue_idx / 128;
744 abs_queue_idx %= 128;
747 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
748 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
749 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
752 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
754 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
756 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
760 * i40e_read_pba_string - Reads part number string from EEPROM
761 * @hw: pointer to hardware structure
762 * @pba_num: stores the part number string from the EEPROM
763 * @pba_num_size: part number string buffer length
765 * Reads the part number string from the EEPROM.
767 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
770 enum i40e_status_code status = I40E_SUCCESS;
776 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
777 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
778 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
782 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
783 if (status != I40E_SUCCESS) {
784 DEBUGOUT("Failed to read PBA Block pointer.\n");
788 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
789 if (status != I40E_SUCCESS) {
790 DEBUGOUT("Failed to read PBA Block size.\n");
794 /* Subtract one to get PBA word count (PBA Size word is included in
798 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
799 DEBUGOUT("Buffer to small for PBA data.\n");
800 return I40E_ERR_PARAM;
803 for (i = 0; i < pba_size; i++) {
804 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
805 if (status != I40E_SUCCESS) {
806 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
810 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
811 pba_num[(i * 2) + 1] = pba_word & 0xFF;
813 pba_num[(pba_size * 2)] = '\0';
819 * i40e_get_media_type - Gets media type
820 * @hw: pointer to the hardware structure
822 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
824 enum i40e_media_type media;
826 switch (hw->phy.link_info.phy_type) {
827 case I40E_PHY_TYPE_10GBASE_SR:
828 case I40E_PHY_TYPE_10GBASE_LR:
829 case I40E_PHY_TYPE_1000BASE_SX:
830 case I40E_PHY_TYPE_1000BASE_LX:
831 case I40E_PHY_TYPE_40GBASE_SR4:
832 case I40E_PHY_TYPE_40GBASE_LR4:
833 media = I40E_MEDIA_TYPE_FIBER;
835 case I40E_PHY_TYPE_100BASE_TX:
836 case I40E_PHY_TYPE_1000BASE_T:
837 case I40E_PHY_TYPE_10GBASE_T:
838 media = I40E_MEDIA_TYPE_BASET;
840 case I40E_PHY_TYPE_10GBASE_CR1_CU:
841 case I40E_PHY_TYPE_40GBASE_CR4_CU:
842 case I40E_PHY_TYPE_10GBASE_CR1:
843 case I40E_PHY_TYPE_40GBASE_CR4:
844 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
845 case I40E_PHY_TYPE_40GBASE_AOC:
846 case I40E_PHY_TYPE_10GBASE_AOC:
847 media = I40E_MEDIA_TYPE_DA;
849 case I40E_PHY_TYPE_1000BASE_KX:
850 case I40E_PHY_TYPE_10GBASE_KX4:
851 case I40E_PHY_TYPE_10GBASE_KR:
852 case I40E_PHY_TYPE_40GBASE_KR4:
853 case I40E_PHY_TYPE_20GBASE_KR2:
854 media = I40E_MEDIA_TYPE_BACKPLANE;
856 case I40E_PHY_TYPE_SGMII:
857 case I40E_PHY_TYPE_XAUI:
858 case I40E_PHY_TYPE_XFI:
859 case I40E_PHY_TYPE_XLAUI:
860 case I40E_PHY_TYPE_XLPPI:
862 media = I40E_MEDIA_TYPE_UNKNOWN;
869 #define I40E_PF_RESET_WAIT_COUNT 200
871 * i40e_pf_reset - Reset the PF
872 * @hw: pointer to the hardware structure
874 * Assuming someone else has triggered a global reset,
875 * assure the global reset is complete and then reset the PF
877 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
884 /* Poll for Global Reset steady state in case of recent GRST.
885 * The grst delay value is in 100ms units, and we'll wait a
886 * couple counts longer to be sure we don't just miss the end.
888 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
889 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
890 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
891 for (cnt = 0; cnt < grst_del + 2; cnt++) {
892 reg = rd32(hw, I40E_GLGEN_RSTAT);
893 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
895 i40e_msec_delay(100);
897 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
898 DEBUGOUT("Global reset polling failed to complete.\n");
899 return I40E_ERR_RESET_FAILED;
902 /* Now Wait for the FW to be ready */
903 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
904 reg = rd32(hw, I40E_GLNVM_ULD);
905 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
906 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
907 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
908 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
909 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
914 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
915 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
916 DEBUGOUT("wait for FW Reset complete timedout\n");
917 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
918 return I40E_ERR_RESET_FAILED;
921 /* If there was a Global Reset in progress when we got here,
922 * we don't need to do the PF Reset
925 reg = rd32(hw, I40E_PFGEN_CTRL);
926 wr32(hw, I40E_PFGEN_CTRL,
927 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
928 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
929 reg = rd32(hw, I40E_PFGEN_CTRL);
930 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
934 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
935 DEBUGOUT("PF reset polling failed to complete.\n");
936 return I40E_ERR_RESET_FAILED;
940 i40e_clear_pxe_mode(hw);
947 * i40e_clear_hw - clear out any left over hw state
948 * @hw: pointer to the hw struct
950 * Clear queues and interrupts, typically called at init time,
951 * but after the capabilities have been found so we know how many
952 * queues and msix vectors have been allocated.
954 void i40e_clear_hw(struct i40e_hw *hw)
956 u32 num_queues, base_queue;
964 /* get number of interrupts, queues, and vfs */
965 val = rd32(hw, I40E_GLPCI_CNF2);
966 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
967 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
968 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
969 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
971 val = rd32(hw, I40E_PFLAN_QALLOC);
972 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
973 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
974 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
975 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
976 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
977 num_queues = (j - base_queue) + 1;
981 val = rd32(hw, I40E_PF_VT_PFALLOC);
982 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
983 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
984 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
985 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
986 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
987 num_vfs = (j - i) + 1;
991 /* stop all the interrupts */
992 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
993 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
994 for (i = 0; i < num_pf_int - 2; i++)
995 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
997 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
998 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
999 wr32(hw, I40E_PFINT_LNKLST0, val);
1000 for (i = 0; i < num_pf_int - 2; i++)
1001 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1002 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1003 for (i = 0; i < num_vfs; i++)
1004 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1005 for (i = 0; i < num_vf_int - 2; i++)
1006 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1008 /* warn the HW of the coming Tx disables */
1009 for (i = 0; i < num_queues; i++) {
1010 u32 abs_queue_idx = base_queue + i;
1013 if (abs_queue_idx >= 128) {
1014 reg_block = abs_queue_idx / 128;
1015 abs_queue_idx %= 128;
1018 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1019 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1020 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1021 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1023 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1025 i40e_usec_delay(400);
1027 /* stop all the queues */
1028 for (i = 0; i < num_queues; i++) {
1029 wr32(hw, I40E_QINT_TQCTL(i), 0);
1030 wr32(hw, I40E_QTX_ENA(i), 0);
1031 wr32(hw, I40E_QINT_RQCTL(i), 0);
1032 wr32(hw, I40E_QRX_ENA(i), 0);
1035 /* short wait for all queue disables to settle */
1036 i40e_usec_delay(50);
1040 * i40e_clear_pxe_mode - clear pxe operations mode
1041 * @hw: pointer to the hw struct
1043 * Make sure all PXE mode settings are cleared, including things
1044 * like descriptor fetch/write-back mode.
1046 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1048 if (i40e_check_asq_alive(hw))
1049 i40e_aq_clear_pxe_mode(hw, NULL);
1053 * i40e_led_is_mine - helper to find matching led
1054 * @hw: pointer to the hw struct
1055 * @idx: index into GPIO registers
1057 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1059 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1064 if (!hw->func_caps.led[idx])
1067 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1068 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1069 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1071 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1072 * if it is not our port then ignore
1074 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1081 #define I40E_COMBINED_ACTIVITY 0xA
1082 #define I40E_FILTER_ACTIVITY 0xE
1083 #define I40E_LINK_ACTIVITY 0xC
1084 #define I40E_MAC_ACTIVITY 0xD
1085 #define I40E_LED0 22
1088 * i40e_led_get - return current on/off mode
1089 * @hw: pointer to the hw struct
1091 * The value returned is the 'mode' field as defined in the
1092 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1093 * values are variations of possible behaviors relating to
1094 * blink, link, and wire.
1096 u32 i40e_led_get(struct i40e_hw *hw)
1098 u32 current_mode = 0;
1102 /* as per the documentation GPIO 22-29 are the LED
1103 * GPIO pins named LED0..LED7
1105 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1106 u32 gpio_val = i40e_led_is_mine(hw, i);
1111 /* ignore gpio LED src mode entries related to the activity LEDs */
1112 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1113 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1114 switch (current_mode) {
1115 case I40E_COMBINED_ACTIVITY:
1116 case I40E_FILTER_ACTIVITY:
1117 case I40E_MAC_ACTIVITY:
1123 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1124 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1132 * i40e_led_set - set new on/off mode
1133 * @hw: pointer to the hw struct
1134 * @mode: 0=off, 0xf=on (else see manual for mode details)
1135 * @blink: TRUE if the LED should blink when on, FALSE if steady
1137 * if this function is used to turn on the blink it should
1138 * be used to disable the blink when restoring the original state.
1140 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1142 u32 current_mode = 0;
1145 if (mode & 0xfffffff0)
1146 DEBUGOUT1("invalid mode passed in %X\n", mode);
1148 /* as per the documentation GPIO 22-29 are the LED
1149 * GPIO pins named LED0..LED7
1151 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1152 u32 gpio_val = i40e_led_is_mine(hw, i);
1157 /* ignore gpio LED src mode entries related to the activity LEDs */
1158 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1159 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1160 switch (current_mode) {
1161 case I40E_COMBINED_ACTIVITY:
1162 case I40E_FILTER_ACTIVITY:
1163 case I40E_MAC_ACTIVITY:
1169 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1170 /* this & is a bit of paranoia, but serves as a range check */
1171 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1172 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1174 if (mode == I40E_LINK_ACTIVITY)
1178 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1180 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1182 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1187 /* Admin command wrappers */
1190 * i40e_aq_get_phy_capabilities
1191 * @hw: pointer to the hw struct
1192 * @abilities: structure for PHY capabilities to be filled
1193 * @qualified_modules: report Qualified Modules
1194 * @report_init: report init capabilities (active are default)
1195 * @cmd_details: pointer to command details structure or NULL
1197 * Returns the various PHY abilities supported on the Port.
1199 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1200 bool qualified_modules, bool report_init,
1201 struct i40e_aq_get_phy_abilities_resp *abilities,
1202 struct i40e_asq_cmd_details *cmd_details)
1204 struct i40e_aq_desc desc;
1205 enum i40e_status_code status;
1206 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1209 return I40E_ERR_PARAM;
1211 i40e_fill_default_direct_cmd_desc(&desc,
1212 i40e_aqc_opc_get_phy_abilities);
1214 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1215 if (abilities_size > I40E_AQ_LARGE_BUF)
1216 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1218 if (qualified_modules)
1219 desc.params.external.param0 |=
1220 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1223 desc.params.external.param0 |=
1224 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1226 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1229 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1230 status = I40E_ERR_UNKNOWN_PHY;
1236 * i40e_aq_set_phy_config
1237 * @hw: pointer to the hw struct
1238 * @config: structure with PHY configuration to be set
1239 * @cmd_details: pointer to command details structure or NULL
1241 * Set the various PHY configuration parameters
1242 * supported on the Port.One or more of the Set PHY config parameters may be
1243 * ignored in an MFP mode as the PF may not have the privilege to set some
1244 * of the PHY Config parameters. This status will be indicated by the
1247 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1248 struct i40e_aq_set_phy_config *config,
1249 struct i40e_asq_cmd_details *cmd_details)
1251 struct i40e_aq_desc desc;
1252 struct i40e_aq_set_phy_config *cmd =
1253 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1254 enum i40e_status_code status;
1257 return I40E_ERR_PARAM;
1259 i40e_fill_default_direct_cmd_desc(&desc,
1260 i40e_aqc_opc_set_phy_config);
1264 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1271 * @hw: pointer to the hw struct
1273 * Set the requested flow control mode using set_phy_config.
1275 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1276 bool atomic_restart)
1278 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1279 struct i40e_aq_get_phy_abilities_resp abilities;
1280 struct i40e_aq_set_phy_config config;
1281 enum i40e_status_code status;
1282 u8 pause_mask = 0x0;
1288 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1289 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1291 case I40E_FC_RX_PAUSE:
1292 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1294 case I40E_FC_TX_PAUSE:
1295 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1301 /* Get the current phy config */
1302 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1305 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1309 memset(&config, 0, sizeof(config));
1310 /* clear the old pause settings */
1311 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1312 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1313 /* set the new abilities */
1314 config.abilities |= pause_mask;
1315 /* If the abilities have changed, then set the new config */
1316 if (config.abilities != abilities.abilities) {
1317 /* Auto restart link so settings take effect */
1319 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1320 /* Copy over all the old settings */
1321 config.phy_type = abilities.phy_type;
1322 config.link_speed = abilities.link_speed;
1323 config.eee_capability = abilities.eee_capability;
1324 config.eeer = abilities.eeer_val;
1325 config.low_power_ctrl = abilities.d3_lpan;
1326 status = i40e_aq_set_phy_config(hw, &config, NULL);
1329 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1331 /* Update the link info */
1332 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1334 /* Wait a little bit (on 40G cards it sometimes takes a really
1335 * long time for link to come back from the atomic reset)
1338 i40e_msec_delay(1000);
1339 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1342 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1348 * i40e_aq_set_mac_config
1349 * @hw: pointer to the hw struct
1350 * @max_frame_size: Maximum Frame Size to be supported by the port
1351 * @crc_en: Tell HW to append a CRC to outgoing frames
1352 * @pacing: Pacing configurations
1353 * @cmd_details: pointer to command details structure or NULL
1355 * Configure MAC settings for frame size, jumbo frame support and the
1356 * addition of a CRC by the hardware.
1358 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1360 bool crc_en, u16 pacing,
1361 struct i40e_asq_cmd_details *cmd_details)
1363 struct i40e_aq_desc desc;
1364 struct i40e_aq_set_mac_config *cmd =
1365 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1366 enum i40e_status_code status;
1368 if (max_frame_size == 0)
1369 return I40E_ERR_PARAM;
1371 i40e_fill_default_direct_cmd_desc(&desc,
1372 i40e_aqc_opc_set_mac_config);
1374 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1375 cmd->params = ((u8)pacing & 0x0F) << 3;
1377 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1385 * i40e_aq_clear_pxe_mode
1386 * @hw: pointer to the hw struct
1387 * @cmd_details: pointer to command details structure or NULL
1389 * Tell the firmware that the driver is taking over from PXE
1391 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1392 struct i40e_asq_cmd_details *cmd_details)
1394 enum i40e_status_code status;
1395 struct i40e_aq_desc desc;
1396 struct i40e_aqc_clear_pxe *cmd =
1397 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1399 i40e_fill_default_direct_cmd_desc(&desc,
1400 i40e_aqc_opc_clear_pxe_mode);
1404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1406 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1412 * i40e_aq_set_link_restart_an
1413 * @hw: pointer to the hw struct
1414 * @enable_link: if TRUE: enable link, if FALSE: disable link
1415 * @cmd_details: pointer to command details structure or NULL
1417 * Sets up the link and restarts the Auto-Negotiation over the link.
1419 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1420 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1422 struct i40e_aq_desc desc;
1423 struct i40e_aqc_set_link_restart_an *cmd =
1424 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1425 enum i40e_status_code status;
1427 i40e_fill_default_direct_cmd_desc(&desc,
1428 i40e_aqc_opc_set_link_restart_an);
1430 cmd->command = I40E_AQ_PHY_RESTART_AN;
1432 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1434 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1436 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1442 * i40e_aq_get_link_info
1443 * @hw: pointer to the hw struct
1444 * @enable_lse: enable/disable LinkStatusEvent reporting
1445 * @link: pointer to link status structure - optional
1446 * @cmd_details: pointer to command details structure or NULL
1448 * Returns the link status of the adapter.
1450 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1451 bool enable_lse, struct i40e_link_status *link,
1452 struct i40e_asq_cmd_details *cmd_details)
1454 struct i40e_aq_desc desc;
1455 struct i40e_aqc_get_link_status *resp =
1456 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1457 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1458 enum i40e_status_code status;
1459 bool tx_pause, rx_pause;
1462 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1465 command_flags = I40E_AQ_LSE_ENABLE;
1467 command_flags = I40E_AQ_LSE_DISABLE;
1468 resp->command_flags = CPU_TO_LE16(command_flags);
1470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1472 if (status != I40E_SUCCESS)
1473 goto aq_get_link_info_exit;
1475 /* save off old link status information */
1476 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1477 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1479 /* update link status */
1480 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1481 hw->phy.media_type = i40e_get_media_type(hw);
1482 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1483 hw_link_info->link_info = resp->link_info;
1484 hw_link_info->an_info = resp->an_info;
1485 hw_link_info->ext_info = resp->ext_info;
1486 hw_link_info->loopback = resp->loopback;
1487 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1488 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1490 /* update fc info */
1491 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1492 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1493 if (tx_pause & rx_pause)
1494 hw->fc.current_mode = I40E_FC_FULL;
1496 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1498 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1500 hw->fc.current_mode = I40E_FC_NONE;
1502 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1503 hw_link_info->crc_enable = TRUE;
1505 hw_link_info->crc_enable = FALSE;
1507 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1508 hw_link_info->lse_enable = TRUE;
1510 hw_link_info->lse_enable = FALSE;
1512 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1513 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1514 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1516 /* save link status information */
1518 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1519 I40E_NONDMA_TO_NONDMA);
1521 /* flag cleared so helper functions don't call AQ again */
1522 hw->phy.get_link_info = FALSE;
1524 aq_get_link_info_exit:
1530 * i40e_aq_set_phy_int_mask
1531 * @hw: pointer to the hw struct
1532 * @mask: interrupt mask to be set
1533 * @cmd_details: pointer to command details structure or NULL
1535 * Set link interrupt mask.
1537 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1539 struct i40e_asq_cmd_details *cmd_details)
1541 struct i40e_aq_desc desc;
1542 struct i40e_aqc_set_phy_int_mask *cmd =
1543 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1544 enum i40e_status_code status;
1546 i40e_fill_default_direct_cmd_desc(&desc,
1547 i40e_aqc_opc_set_phy_int_mask);
1549 cmd->event_mask = CPU_TO_LE16(mask);
1551 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1557 * i40e_aq_get_local_advt_reg
1558 * @hw: pointer to the hw struct
1559 * @advt_reg: local AN advertisement register value
1560 * @cmd_details: pointer to command details structure or NULL
1562 * Get the Local AN advertisement register value.
1564 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1566 struct i40e_asq_cmd_details *cmd_details)
1568 struct i40e_aq_desc desc;
1569 struct i40e_aqc_an_advt_reg *resp =
1570 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1571 enum i40e_status_code status;
1573 i40e_fill_default_direct_cmd_desc(&desc,
1574 i40e_aqc_opc_get_local_advt_reg);
1576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1578 if (status != I40E_SUCCESS)
1579 goto aq_get_local_advt_reg_exit;
1581 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1582 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1584 aq_get_local_advt_reg_exit:
1589 * i40e_aq_set_local_advt_reg
1590 * @hw: pointer to the hw struct
1591 * @advt_reg: local AN advertisement register value
1592 * @cmd_details: pointer to command details structure or NULL
1594 * Get the Local AN advertisement register value.
1596 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1598 struct i40e_asq_cmd_details *cmd_details)
1600 struct i40e_aq_desc desc;
1601 struct i40e_aqc_an_advt_reg *cmd =
1602 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1603 enum i40e_status_code status;
1605 i40e_fill_default_direct_cmd_desc(&desc,
1606 i40e_aqc_opc_get_local_advt_reg);
1608 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1609 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1611 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1617 * i40e_aq_get_partner_advt
1618 * @hw: pointer to the hw struct
1619 * @advt_reg: AN partner advertisement register value
1620 * @cmd_details: pointer to command details structure or NULL
1622 * Get the link partner AN advertisement register value.
1624 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1626 struct i40e_asq_cmd_details *cmd_details)
1628 struct i40e_aq_desc desc;
1629 struct i40e_aqc_an_advt_reg *resp =
1630 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1631 enum i40e_status_code status;
1633 i40e_fill_default_direct_cmd_desc(&desc,
1634 i40e_aqc_opc_get_partner_advt);
1636 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1638 if (status != I40E_SUCCESS)
1639 goto aq_get_partner_advt_exit;
1641 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1642 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1644 aq_get_partner_advt_exit:
1649 * i40e_aq_set_lb_modes
1650 * @hw: pointer to the hw struct
1651 * @lb_modes: loopback mode to be set
1652 * @cmd_details: pointer to command details structure or NULL
1654 * Sets loopback modes.
1656 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1658 struct i40e_asq_cmd_details *cmd_details)
1660 struct i40e_aq_desc desc;
1661 struct i40e_aqc_set_lb_mode *cmd =
1662 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1663 enum i40e_status_code status;
1665 i40e_fill_default_direct_cmd_desc(&desc,
1666 i40e_aqc_opc_set_lb_modes);
1668 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1670 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1676 * i40e_aq_set_phy_debug
1677 * @hw: pointer to the hw struct
1678 * @cmd_flags: debug command flags
1679 * @cmd_details: pointer to command details structure or NULL
1681 * Reset the external PHY.
1683 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1684 struct i40e_asq_cmd_details *cmd_details)
1686 struct i40e_aq_desc desc;
1687 struct i40e_aqc_set_phy_debug *cmd =
1688 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1689 enum i40e_status_code status;
1691 i40e_fill_default_direct_cmd_desc(&desc,
1692 i40e_aqc_opc_set_phy_debug);
1694 cmd->command_flags = cmd_flags;
1696 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1703 * @hw: pointer to the hw struct
1704 * @vsi_ctx: pointer to a vsi context struct
1705 * @cmd_details: pointer to command details structure or NULL
1707 * Add a VSI context to the hardware.
1709 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1710 struct i40e_vsi_context *vsi_ctx,
1711 struct i40e_asq_cmd_details *cmd_details)
1713 struct i40e_aq_desc desc;
1714 struct i40e_aqc_add_get_update_vsi *cmd =
1715 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1716 struct i40e_aqc_add_get_update_vsi_completion *resp =
1717 (struct i40e_aqc_add_get_update_vsi_completion *)
1719 enum i40e_status_code status;
1721 i40e_fill_default_direct_cmd_desc(&desc,
1722 i40e_aqc_opc_add_vsi);
1724 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1725 cmd->connection_type = vsi_ctx->connection_type;
1726 cmd->vf_id = vsi_ctx->vf_num;
1727 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1729 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1731 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1732 sizeof(vsi_ctx->info), cmd_details);
1734 if (status != I40E_SUCCESS)
1735 goto aq_add_vsi_exit;
1737 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1738 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1739 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1740 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1747 * i40e_aq_set_default_vsi
1748 * @hw: pointer to the hw struct
1750 * @cmd_details: pointer to command details structure or NULL
1752 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1754 struct i40e_asq_cmd_details *cmd_details)
1756 struct i40e_aq_desc desc;
1757 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1758 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1760 enum i40e_status_code status;
1762 i40e_fill_default_direct_cmd_desc(&desc,
1763 i40e_aqc_opc_set_vsi_promiscuous_modes);
1765 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1766 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1767 cmd->seid = CPU_TO_LE16(seid);
1769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1775 * i40e_aq_set_vsi_unicast_promiscuous
1776 * @hw: pointer to the hw struct
1778 * @set: set unicast promiscuous enable/disable
1779 * @cmd_details: pointer to command details structure or NULL
1781 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1783 struct i40e_asq_cmd_details *cmd_details)
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1787 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1788 enum i40e_status_code status;
1791 i40e_fill_default_direct_cmd_desc(&desc,
1792 i40e_aqc_opc_set_vsi_promiscuous_modes);
1795 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1797 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1799 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1801 cmd->seid = CPU_TO_LE16(seid);
1802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1808 * i40e_aq_set_vsi_multicast_promiscuous
1809 * @hw: pointer to the hw struct
1811 * @set: set multicast promiscuous enable/disable
1812 * @cmd_details: pointer to command details structure or NULL
1814 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1815 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1817 struct i40e_aq_desc desc;
1818 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1819 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1820 enum i40e_status_code status;
1823 i40e_fill_default_direct_cmd_desc(&desc,
1824 i40e_aqc_opc_set_vsi_promiscuous_modes);
1827 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1829 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1831 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1833 cmd->seid = CPU_TO_LE16(seid);
1834 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1840 * i40e_aq_set_vsi_broadcast
1841 * @hw: pointer to the hw struct
1843 * @set_filter: TRUE to set filter, FALSE to clear filter
1844 * @cmd_details: pointer to command details structure or NULL
1846 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1848 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1849 u16 seid, bool set_filter,
1850 struct i40e_asq_cmd_details *cmd_details)
1852 struct i40e_aq_desc desc;
1853 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1854 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1855 enum i40e_status_code status;
1857 i40e_fill_default_direct_cmd_desc(&desc,
1858 i40e_aqc_opc_set_vsi_promiscuous_modes);
1861 cmd->promiscuous_flags
1862 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1864 cmd->promiscuous_flags
1865 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1867 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1868 cmd->seid = CPU_TO_LE16(seid);
1869 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1875 * i40e_get_vsi_params - get VSI configuration info
1876 * @hw: pointer to the hw struct
1877 * @vsi_ctx: pointer to a vsi context struct
1878 * @cmd_details: pointer to command details structure or NULL
1880 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1881 struct i40e_vsi_context *vsi_ctx,
1882 struct i40e_asq_cmd_details *cmd_details)
1884 struct i40e_aq_desc desc;
1885 struct i40e_aqc_add_get_update_vsi *cmd =
1886 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1887 struct i40e_aqc_add_get_update_vsi_completion *resp =
1888 (struct i40e_aqc_add_get_update_vsi_completion *)
1890 enum i40e_status_code status;
1892 i40e_fill_default_direct_cmd_desc(&desc,
1893 i40e_aqc_opc_get_vsi_parameters);
1895 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1897 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1899 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1900 sizeof(vsi_ctx->info), NULL);
1902 if (status != I40E_SUCCESS)
1903 goto aq_get_vsi_params_exit;
1905 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1906 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1907 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1908 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1910 aq_get_vsi_params_exit:
1915 * i40e_aq_update_vsi_params
1916 * @hw: pointer to the hw struct
1917 * @vsi_ctx: pointer to a vsi context struct
1918 * @cmd_details: pointer to command details structure or NULL
1920 * Update a VSI context.
1922 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1923 struct i40e_vsi_context *vsi_ctx,
1924 struct i40e_asq_cmd_details *cmd_details)
1926 struct i40e_aq_desc desc;
1927 struct i40e_aqc_add_get_update_vsi *cmd =
1928 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1929 enum i40e_status_code status;
1931 i40e_fill_default_direct_cmd_desc(&desc,
1932 i40e_aqc_opc_update_vsi_parameters);
1933 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1935 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1937 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1938 sizeof(vsi_ctx->info), cmd_details);
1944 * i40e_aq_get_switch_config
1945 * @hw: pointer to the hardware structure
1946 * @buf: pointer to the result buffer
1947 * @buf_size: length of input buffer
1948 * @start_seid: seid to start for the report, 0 == beginning
1949 * @cmd_details: pointer to command details structure or NULL
1951 * Fill the buf with switch configuration returned from AdminQ command
1953 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1954 struct i40e_aqc_get_switch_config_resp *buf,
1955 u16 buf_size, u16 *start_seid,
1956 struct i40e_asq_cmd_details *cmd_details)
1958 struct i40e_aq_desc desc;
1959 struct i40e_aqc_switch_seid *scfg =
1960 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1961 enum i40e_status_code status;
1963 i40e_fill_default_direct_cmd_desc(&desc,
1964 i40e_aqc_opc_get_switch_config);
1965 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1966 if (buf_size > I40E_AQ_LARGE_BUF)
1967 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1968 scfg->seid = CPU_TO_LE16(*start_seid);
1970 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1971 *start_seid = LE16_TO_CPU(scfg->seid);
1977 * i40e_aq_get_firmware_version
1978 * @hw: pointer to the hw struct
1979 * @fw_major_version: firmware major version
1980 * @fw_minor_version: firmware minor version
1981 * @fw_build: firmware build number
1982 * @api_major_version: major queue version
1983 * @api_minor_version: minor queue version
1984 * @cmd_details: pointer to command details structure or NULL
1986 * Get the firmware version from the admin queue commands
1988 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1989 u16 *fw_major_version, u16 *fw_minor_version,
1991 u16 *api_major_version, u16 *api_minor_version,
1992 struct i40e_asq_cmd_details *cmd_details)
1994 struct i40e_aq_desc desc;
1995 struct i40e_aqc_get_version *resp =
1996 (struct i40e_aqc_get_version *)&desc.params.raw;
1997 enum i40e_status_code status;
1999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2001 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003 if (status == I40E_SUCCESS) {
2004 if (fw_major_version != NULL)
2005 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2006 if (fw_minor_version != NULL)
2007 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2008 if (fw_build != NULL)
2009 *fw_build = LE32_TO_CPU(resp->fw_build);
2010 if (api_major_version != NULL)
2011 *api_major_version = LE16_TO_CPU(resp->api_major);
2012 if (api_minor_version != NULL)
2013 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2015 /* A workaround to fix the API version in SW */
2016 if (api_major_version && api_minor_version &&
2017 fw_major_version && fw_minor_version &&
2018 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2019 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2020 (*fw_major_version > 4)))
2021 *api_minor_version = 2;
2028 * i40e_aq_send_driver_version
2029 * @hw: pointer to the hw struct
2030 * @dv: driver's major, minor version
2031 * @cmd_details: pointer to command details structure or NULL
2033 * Send the driver version to the firmware
2035 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2036 struct i40e_driver_version *dv,
2037 struct i40e_asq_cmd_details *cmd_details)
2039 struct i40e_aq_desc desc;
2040 struct i40e_aqc_driver_version *cmd =
2041 (struct i40e_aqc_driver_version *)&desc.params.raw;
2042 enum i40e_status_code status;
2046 return I40E_ERR_PARAM;
2048 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2050 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2051 cmd->driver_major_ver = dv->major_version;
2052 cmd->driver_minor_ver = dv->minor_version;
2053 cmd->driver_build_ver = dv->build_version;
2054 cmd->driver_subbuild_ver = dv->subbuild_version;
2057 while (len < sizeof(dv->driver_string) &&
2058 (dv->driver_string[len] < 0x80) &&
2059 dv->driver_string[len])
2061 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2068 * i40e_get_link_status - get status of the HW network link
2069 * @hw: pointer to the hw struct
2071 * Returns TRUE if link is up, FALSE if link is down.
2073 * Side effect: LinkStatusEvent reporting becomes enabled
2075 bool i40e_get_link_status(struct i40e_hw *hw)
2077 enum i40e_status_code status = I40E_SUCCESS;
2078 bool link_status = FALSE;
2080 if (hw->phy.get_link_info) {
2081 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2083 if (status != I40E_SUCCESS)
2084 goto i40e_get_link_status_exit;
2087 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2089 i40e_get_link_status_exit:
2094 * i40e_get_link_speed
2095 * @hw: pointer to the hw struct
2097 * Returns the link speed of the adapter.
2099 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2101 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2102 enum i40e_status_code status = I40E_SUCCESS;
2104 if (hw->phy.get_link_info) {
2105 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2107 if (status != I40E_SUCCESS)
2108 goto i40e_link_speed_exit;
2111 speed = hw->phy.link_info.link_speed;
2113 i40e_link_speed_exit:
2118 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2119 * @hw: pointer to the hw struct
2120 * @uplink_seid: the MAC or other gizmo SEID
2121 * @downlink_seid: the VSI SEID
2122 * @enabled_tc: bitmap of TCs to be enabled
2123 * @default_port: TRUE for default port VSI, FALSE for control port
2124 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support
2125 * @veb_seid: pointer to where to put the resulting VEB SEID
2126 * @cmd_details: pointer to command details structure or NULL
2128 * This asks the FW to add a VEB between the uplink and downlink
2129 * elements. If the uplink SEID is 0, this will be a floating VEB.
2131 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2132 u16 downlink_seid, u8 enabled_tc,
2133 bool default_port, bool enable_l2_filtering,
2135 struct i40e_asq_cmd_details *cmd_details)
2137 struct i40e_aq_desc desc;
2138 struct i40e_aqc_add_veb *cmd =
2139 (struct i40e_aqc_add_veb *)&desc.params.raw;
2140 struct i40e_aqc_add_veb_completion *resp =
2141 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2142 enum i40e_status_code status;
2145 /* SEIDs need to either both be set or both be 0 for floating VEB */
2146 if (!!uplink_seid != !!downlink_seid)
2147 return I40E_ERR_PARAM;
2149 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2151 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2152 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2153 cmd->enable_tcs = enabled_tc;
2155 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2157 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2159 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2161 if (enable_l2_filtering)
2162 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2164 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2166 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2168 if (!status && veb_seid)
2169 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2175 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2176 * @hw: pointer to the hw struct
2177 * @veb_seid: the SEID of the VEB to query
2178 * @switch_id: the uplink switch id
2179 * @floating: set to TRUE if the VEB is floating
2180 * @statistic_index: index of the stats counter block for this VEB
2181 * @vebs_used: number of VEB's used by function
2182 * @vebs_free: total VEB's not reserved by any function
2183 * @cmd_details: pointer to command details structure or NULL
2185 * This retrieves the parameters for a particular VEB, specified by
2186 * uplink_seid, and returns them to the caller.
2188 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2189 u16 veb_seid, u16 *switch_id,
2190 bool *floating, u16 *statistic_index,
2191 u16 *vebs_used, u16 *vebs_free,
2192 struct i40e_asq_cmd_details *cmd_details)
2194 struct i40e_aq_desc desc;
2195 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2196 (struct i40e_aqc_get_veb_parameters_completion *)
2198 enum i40e_status_code status;
2201 return I40E_ERR_PARAM;
2203 i40e_fill_default_direct_cmd_desc(&desc,
2204 i40e_aqc_opc_get_veb_parameters);
2205 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2212 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2213 if (statistic_index)
2214 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2216 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2218 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2220 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2221 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2232 * i40e_aq_add_macvlan
2233 * @hw: pointer to the hw struct
2234 * @seid: VSI for the mac address
2235 * @mv_list: list of macvlans to be added
2236 * @count: length of the list
2237 * @cmd_details: pointer to command details structure or NULL
2239 * Add MAC/VLAN addresses to the HW filtering
2241 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2242 struct i40e_aqc_add_macvlan_element_data *mv_list,
2243 u16 count, struct i40e_asq_cmd_details *cmd_details)
2245 struct i40e_aq_desc desc;
2246 struct i40e_aqc_macvlan *cmd =
2247 (struct i40e_aqc_macvlan *)&desc.params.raw;
2248 enum i40e_status_code status;
2251 if (count == 0 || !mv_list || !hw)
2252 return I40E_ERR_PARAM;
2254 buf_size = count * sizeof(*mv_list);
2256 /* prep the rest of the request */
2257 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2258 cmd->num_addresses = CPU_TO_LE16(count);
2259 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2263 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2264 if (buf_size > I40E_AQ_LARGE_BUF)
2265 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2267 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2274 * i40e_aq_remove_macvlan
2275 * @hw: pointer to the hw struct
2276 * @seid: VSI for the mac address
2277 * @mv_list: list of macvlans to be removed
2278 * @count: length of the list
2279 * @cmd_details: pointer to command details structure or NULL
2281 * Remove MAC/VLAN addresses from the HW filtering
2283 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2284 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2285 u16 count, struct i40e_asq_cmd_details *cmd_details)
2287 struct i40e_aq_desc desc;
2288 struct i40e_aqc_macvlan *cmd =
2289 (struct i40e_aqc_macvlan *)&desc.params.raw;
2290 enum i40e_status_code status;
2293 if (count == 0 || !mv_list || !hw)
2294 return I40E_ERR_PARAM;
2296 buf_size = count * sizeof(*mv_list);
2298 /* prep the rest of the request */
2299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2300 cmd->num_addresses = CPU_TO_LE16(count);
2301 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2305 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2306 if (buf_size > I40E_AQ_LARGE_BUF)
2307 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2309 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2316 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2317 * @hw: pointer to the hw struct
2318 * @seid: VSI for the vlan filters
2319 * @v_list: list of vlan filters to be added
2320 * @count: length of the list
2321 * @cmd_details: pointer to command details structure or NULL
2323 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2324 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2325 u8 count, struct i40e_asq_cmd_details *cmd_details)
2327 struct i40e_aq_desc desc;
2328 struct i40e_aqc_macvlan *cmd =
2329 (struct i40e_aqc_macvlan *)&desc.params.raw;
2330 enum i40e_status_code status;
2333 if (count == 0 || !v_list || !hw)
2334 return I40E_ERR_PARAM;
2336 buf_size = count * sizeof(*v_list);
2338 /* prep the rest of the request */
2339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2340 cmd->num_addresses = CPU_TO_LE16(count);
2341 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2345 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2346 if (buf_size > I40E_AQ_LARGE_BUF)
2347 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2349 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2356 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2357 * @hw: pointer to the hw struct
2358 * @seid: VSI for the vlan filters
2359 * @v_list: list of macvlans to be removed
2360 * @count: length of the list
2361 * @cmd_details: pointer to command details structure or NULL
2363 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2364 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2365 u8 count, struct i40e_asq_cmd_details *cmd_details)
2367 struct i40e_aq_desc desc;
2368 struct i40e_aqc_macvlan *cmd =
2369 (struct i40e_aqc_macvlan *)&desc.params.raw;
2370 enum i40e_status_code status;
2373 if (count == 0 || !v_list || !hw)
2374 return I40E_ERR_PARAM;
2376 buf_size = count * sizeof(*v_list);
2378 /* prep the rest of the request */
2379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2380 cmd->num_addresses = CPU_TO_LE16(count);
2381 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2385 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2386 if (buf_size > I40E_AQ_LARGE_BUF)
2387 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2389 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2396 * i40e_aq_send_msg_to_vf
2397 * @hw: pointer to the hardware structure
2398 * @vfid: vf id to send msg
2399 * @v_opcode: opcodes for VF-PF communication
2400 * @v_retval: return error code
2401 * @msg: pointer to the msg buffer
2402 * @msglen: msg length
2403 * @cmd_details: pointer to command details
2407 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2408 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2409 struct i40e_asq_cmd_details *cmd_details)
2411 struct i40e_aq_desc desc;
2412 struct i40e_aqc_pf_vf_message *cmd =
2413 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2414 enum i40e_status_code status;
2416 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2417 cmd->id = CPU_TO_LE32(vfid);
2418 desc.cookie_high = CPU_TO_LE32(v_opcode);
2419 desc.cookie_low = CPU_TO_LE32(v_retval);
2420 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2422 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2424 if (msglen > I40E_AQ_LARGE_BUF)
2425 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2426 desc.datalen = CPU_TO_LE16(msglen);
2428 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2434 * i40e_aq_debug_read_register
2435 * @hw: pointer to the hw struct
2436 * @reg_addr: register address
2437 * @reg_val: register value
2438 * @cmd_details: pointer to command details structure or NULL
2440 * Read the register using the admin queue commands
2442 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2443 u32 reg_addr, u64 *reg_val,
2444 struct i40e_asq_cmd_details *cmd_details)
2446 struct i40e_aq_desc desc;
2447 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2448 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2449 enum i40e_status_code status;
2451 if (reg_val == NULL)
2452 return I40E_ERR_PARAM;
2454 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2456 cmd_resp->address = CPU_TO_LE32(reg_addr);
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2460 if (status == I40E_SUCCESS) {
2461 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2462 (u64)LE32_TO_CPU(cmd_resp->value_low);
2469 * i40e_aq_debug_write_register
2470 * @hw: pointer to the hw struct
2471 * @reg_addr: register address
2472 * @reg_val: register value
2473 * @cmd_details: pointer to command details structure or NULL
2475 * Write to a register using the admin queue commands
2477 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2478 u32 reg_addr, u64 reg_val,
2479 struct i40e_asq_cmd_details *cmd_details)
2481 struct i40e_aq_desc desc;
2482 struct i40e_aqc_debug_reg_read_write *cmd =
2483 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2484 enum i40e_status_code status;
2486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2488 cmd->address = CPU_TO_LE32(reg_addr);
2489 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2490 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 * i40e_aq_get_hmc_resource_profile
2499 * @hw: pointer to the hw struct
2500 * @profile: type of profile the HMC is to be set as
2501 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2502 * @cmd_details: pointer to command details structure or NULL
2504 * query the HMC profile of the device.
2506 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2507 enum i40e_aq_hmc_profile *profile,
2508 u8 *pe_vf_enabled_count,
2509 struct i40e_asq_cmd_details *cmd_details)
2511 struct i40e_aq_desc desc;
2512 struct i40e_aq_get_set_hmc_resource_profile *resp =
2513 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2514 enum i40e_status_code status;
2516 i40e_fill_default_direct_cmd_desc(&desc,
2517 i40e_aqc_opc_query_hmc_resource_profile);
2518 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2520 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2521 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2522 *pe_vf_enabled_count = resp->pe_vf_enabled &
2523 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2529 * i40e_aq_set_hmc_resource_profile
2530 * @hw: pointer to the hw struct
2531 * @profile: type of profile the HMC is to be set as
2532 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2533 * @cmd_details: pointer to command details structure or NULL
2535 * set the HMC profile of the device.
2537 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2538 enum i40e_aq_hmc_profile profile,
2539 u8 pe_vf_enabled_count,
2540 struct i40e_asq_cmd_details *cmd_details)
2542 struct i40e_aq_desc desc;
2543 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2544 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2545 enum i40e_status_code status;
2547 i40e_fill_default_direct_cmd_desc(&desc,
2548 i40e_aqc_opc_set_hmc_resource_profile);
2550 cmd->pm_profile = (u8)profile;
2551 cmd->pe_vf_enabled = pe_vf_enabled_count;
2553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559 * i40e_aq_request_resource
2560 * @hw: pointer to the hw struct
2561 * @resource: resource id
2562 * @access: access type
2563 * @sdp_number: resource number
2564 * @timeout: the maximum time in ms that the driver may hold the resource
2565 * @cmd_details: pointer to command details structure or NULL
2567 * requests common resource using the admin queue commands
2569 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2570 enum i40e_aq_resources_ids resource,
2571 enum i40e_aq_resource_access_type access,
2572 u8 sdp_number, u64 *timeout,
2573 struct i40e_asq_cmd_details *cmd_details)
2575 struct i40e_aq_desc desc;
2576 struct i40e_aqc_request_resource *cmd_resp =
2577 (struct i40e_aqc_request_resource *)&desc.params.raw;
2578 enum i40e_status_code status;
2580 DEBUGFUNC("i40e_aq_request_resource");
2582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2584 cmd_resp->resource_id = CPU_TO_LE16(resource);
2585 cmd_resp->access_type = CPU_TO_LE16(access);
2586 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2589 /* The completion specifies the maximum time in ms that the driver
2590 * may hold the resource in the Timeout field.
2591 * If the resource is held by someone else, the command completes with
2592 * busy return value and the timeout field indicates the maximum time
2593 * the current owner of the resource has to free it.
2595 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2596 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2602 * i40e_aq_release_resource
2603 * @hw: pointer to the hw struct
2604 * @resource: resource id
2605 * @sdp_number: resource number
2606 * @cmd_details: pointer to command details structure or NULL
2608 * release common resource using the admin queue commands
2610 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2611 enum i40e_aq_resources_ids resource,
2613 struct i40e_asq_cmd_details *cmd_details)
2615 struct i40e_aq_desc desc;
2616 struct i40e_aqc_request_resource *cmd =
2617 (struct i40e_aqc_request_resource *)&desc.params.raw;
2618 enum i40e_status_code status;
2620 DEBUGFUNC("i40e_aq_release_resource");
2622 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2624 cmd->resource_id = CPU_TO_LE16(resource);
2625 cmd->resource_number = CPU_TO_LE32(sdp_number);
2627 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2634 * @hw: pointer to the hw struct
2635 * @module_pointer: module pointer location in words from the NVM beginning
2636 * @offset: byte offset from the module beginning
2637 * @length: length of the section to be read (in bytes from the offset)
2638 * @data: command buffer (size [bytes] = length)
2639 * @last_command: tells if this is the last command in a series
2640 * @cmd_details: pointer to command details structure or NULL
2642 * Read the NVM using the admin queue commands
2644 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2645 u32 offset, u16 length, void *data,
2647 struct i40e_asq_cmd_details *cmd_details)
2649 struct i40e_aq_desc desc;
2650 struct i40e_aqc_nvm_update *cmd =
2651 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2652 enum i40e_status_code status;
2654 DEBUGFUNC("i40e_aq_read_nvm");
2656 /* In offset the highest byte must be zeroed. */
2657 if (offset & 0xFF000000) {
2658 status = I40E_ERR_PARAM;
2659 goto i40e_aq_read_nvm_exit;
2662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2664 /* If this is the last command in a series, set the proper flag. */
2666 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2667 cmd->module_pointer = module_pointer;
2668 cmd->offset = CPU_TO_LE32(offset);
2669 cmd->length = CPU_TO_LE16(length);
2671 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2672 if (length > I40E_AQ_LARGE_BUF)
2673 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2675 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2677 i40e_aq_read_nvm_exit:
2682 * i40e_aq_read_nvm_config - read an nvm config block
2683 * @hw: pointer to the hw struct
2684 * @cmd_flags: NVM access admin command bits
2685 * @field_id: field or feature id
2686 * @data: buffer for result
2687 * @buf_size: buffer size
2688 * @element_count: pointer to count of elements read by FW
2689 * @cmd_details: pointer to command details structure or NULL
2691 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2692 u8 cmd_flags, u32 field_id, void *data,
2693 u16 buf_size, u16 *element_count,
2694 struct i40e_asq_cmd_details *cmd_details)
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_nvm_config_read *cmd =
2698 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2699 enum i40e_status_code status;
2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2702 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2703 if (buf_size > I40E_AQ_LARGE_BUF)
2704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2706 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2707 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2708 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2709 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2711 cmd->element_id_msw = 0;
2713 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2715 if (!status && element_count)
2716 *element_count = LE16_TO_CPU(cmd->element_count);
2722 * i40e_aq_write_nvm_config - write an nvm config block
2723 * @hw: pointer to the hw struct
2724 * @cmd_flags: NVM access admin command bits
2725 * @data: buffer for result
2726 * @buf_size: buffer size
2727 * @element_count: count of elements to be written
2728 * @cmd_details: pointer to command details structure or NULL
2730 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2731 u8 cmd_flags, void *data, u16 buf_size,
2733 struct i40e_asq_cmd_details *cmd_details)
2735 struct i40e_aq_desc desc;
2736 struct i40e_aqc_nvm_config_write *cmd =
2737 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2738 enum i40e_status_code status;
2740 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2741 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2742 if (buf_size > I40E_AQ_LARGE_BUF)
2743 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2745 cmd->element_count = CPU_TO_LE16(element_count);
2746 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2747 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2754 * @hw: pointer to the hw struct
2755 * @module_pointer: module pointer location in words from the NVM beginning
2756 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2757 * @length: length of the section to be erased (expressed in 4 KB)
2758 * @last_command: tells if this is the last command in a series
2759 * @cmd_details: pointer to command details structure or NULL
2761 * Erase the NVM sector using the admin queue commands
2763 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2764 u32 offset, u16 length, bool last_command,
2765 struct i40e_asq_cmd_details *cmd_details)
2767 struct i40e_aq_desc desc;
2768 struct i40e_aqc_nvm_update *cmd =
2769 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2770 enum i40e_status_code status;
2772 DEBUGFUNC("i40e_aq_erase_nvm");
2774 /* In offset the highest byte must be zeroed. */
2775 if (offset & 0xFF000000) {
2776 status = I40E_ERR_PARAM;
2777 goto i40e_aq_erase_nvm_exit;
2780 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2782 /* If this is the last command in a series, set the proper flag. */
2784 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2785 cmd->module_pointer = module_pointer;
2786 cmd->offset = CPU_TO_LE32(offset);
2787 cmd->length = CPU_TO_LE16(length);
2789 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2791 i40e_aq_erase_nvm_exit:
2795 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2796 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2797 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2798 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2799 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2800 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2801 #define I40E_DEV_FUNC_CAP_VF 0x13
2802 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2803 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2804 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2805 #define I40E_DEV_FUNC_CAP_VSI 0x17
2806 #define I40E_DEV_FUNC_CAP_DCB 0x18
2807 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2808 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2809 #define I40E_DEV_FUNC_CAP_RSS 0x40
2810 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2811 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2812 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2813 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2814 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2815 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2816 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2817 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2818 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2819 #define I40E_DEV_FUNC_CAP_LED 0x61
2820 #define I40E_DEV_FUNC_CAP_SDP 0x62
2821 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2824 * i40e_parse_discover_capabilities
2825 * @hw: pointer to the hw struct
2826 * @buff: pointer to a buffer containing device/function capability records
2827 * @cap_count: number of capability records in the list
2828 * @list_type_opc: type of capabilities list to parse
2830 * Parse the device/function capabilities list.
2832 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2834 enum i40e_admin_queue_opc list_type_opc)
2836 struct i40e_aqc_list_capabilities_element_resp *cap;
2837 u32 valid_functions, num_functions;
2838 u32 number, logical_id, phys_id;
2839 struct i40e_hw_capabilities *p;
2843 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2845 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2846 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2847 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2848 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2852 for (i = 0; i < cap_count; i++, cap++) {
2853 id = LE16_TO_CPU(cap->id);
2854 number = LE32_TO_CPU(cap->number);
2855 logical_id = LE32_TO_CPU(cap->logical_id);
2856 phys_id = LE32_TO_CPU(cap->phys_id);
2859 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2860 p->switch_mode = number;
2862 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2863 p->management_mode = number;
2865 case I40E_DEV_FUNC_CAP_NPAR:
2866 p->npar_enable = number;
2868 case I40E_DEV_FUNC_CAP_OS2BMC:
2871 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2872 p->valid_functions = number;
2874 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2876 p->sr_iov_1_1 = TRUE;
2878 case I40E_DEV_FUNC_CAP_VF:
2879 p->num_vfs = number;
2880 p->vf_base_id = logical_id;
2882 case I40E_DEV_FUNC_CAP_VMDQ:
2886 case I40E_DEV_FUNC_CAP_802_1_QBG:
2888 p->evb_802_1_qbg = TRUE;
2890 case I40E_DEV_FUNC_CAP_802_1_QBH:
2892 p->evb_802_1_qbh = TRUE;
2894 case I40E_DEV_FUNC_CAP_VSI:
2895 p->num_vsis = number;
2897 case I40E_DEV_FUNC_CAP_DCB:
2900 p->enabled_tcmap = logical_id;
2904 case I40E_DEV_FUNC_CAP_FCOE:
2908 case I40E_DEV_FUNC_CAP_ISCSI:
2912 case I40E_DEV_FUNC_CAP_RSS:
2914 p->rss_table_size = number;
2915 p->rss_table_entry_width = logical_id;
2917 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2918 p->num_rx_qp = number;
2919 p->base_queue = phys_id;
2921 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2922 p->num_tx_qp = number;
2923 p->base_queue = phys_id;
2925 case I40E_DEV_FUNC_CAP_MSIX:
2926 p->num_msix_vectors = number;
2928 case I40E_DEV_FUNC_CAP_MSIX_VF:
2929 p->num_msix_vectors_vf = number;
2931 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2933 p->mfp_mode_1 = TRUE;
2935 case I40E_DEV_FUNC_CAP_CEM:
2939 case I40E_DEV_FUNC_CAP_IWARP:
2943 case I40E_DEV_FUNC_CAP_LED:
2944 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2945 p->led[phys_id] = TRUE;
2947 case I40E_DEV_FUNC_CAP_SDP:
2948 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2949 p->sdp[phys_id] = TRUE;
2951 case I40E_DEV_FUNC_CAP_MDIO:
2953 p->mdio_port_num = phys_id;
2954 p->mdio_port_mode = logical_id;
2957 case I40E_DEV_FUNC_CAP_IEEE_1588:
2959 p->ieee_1588 = TRUE;
2961 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2963 p->fd_filters_guaranteed = number;
2964 p->fd_filters_best_effort = logical_id;
2971 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2974 /* count the enabled ports (aka the "not disabled" ports) */
2976 for (i = 0; i < 4; i++) {
2977 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2980 /* use AQ read to get the physical register offset instead
2981 * of the port relative offset
2983 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2984 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2988 valid_functions = p->valid_functions;
2990 while (valid_functions) {
2991 if (valid_functions & 1)
2993 valid_functions >>= 1;
2996 /* partition id is 1-based, and functions are evenly spread
2997 * across the ports as partitions
2999 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3000 hw->num_partitions = num_functions / hw->num_ports;
3002 /* additional HW specific goodies that might
3003 * someday be HW version specific
3005 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3009 * i40e_aq_discover_capabilities
3010 * @hw: pointer to the hw struct
3011 * @buff: a virtual buffer to hold the capabilities
3012 * @buff_size: Size of the virtual buffer
3013 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3014 * @list_type_opc: capabilities type to discover - pass in the command opcode
3015 * @cmd_details: pointer to command details structure or NULL
3017 * Get the device capabilities descriptions from the firmware
3019 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3020 void *buff, u16 buff_size, u16 *data_size,
3021 enum i40e_admin_queue_opc list_type_opc,
3022 struct i40e_asq_cmd_details *cmd_details)
3024 struct i40e_aqc_list_capabilites *cmd;
3025 struct i40e_aq_desc desc;
3026 enum i40e_status_code status = I40E_SUCCESS;
3028 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3030 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3031 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3032 status = I40E_ERR_PARAM;
3036 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3038 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3039 if (buff_size > I40E_AQ_LARGE_BUF)
3040 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3042 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3043 *data_size = LE16_TO_CPU(desc.datalen);
3048 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3056 * i40e_aq_update_nvm
3057 * @hw: pointer to the hw struct
3058 * @module_pointer: module pointer location in words from the NVM beginning
3059 * @offset: byte offset from the module beginning
3060 * @length: length of the section to be written (in bytes from the offset)
3061 * @data: command buffer (size [bytes] = length)
3062 * @last_command: tells if this is the last command in a series
3063 * @cmd_details: pointer to command details structure or NULL
3065 * Update the NVM using the admin queue commands
3067 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3068 u32 offset, u16 length, void *data,
3070 struct i40e_asq_cmd_details *cmd_details)
3072 struct i40e_aq_desc desc;
3073 struct i40e_aqc_nvm_update *cmd =
3074 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3075 enum i40e_status_code status;
3077 DEBUGFUNC("i40e_aq_update_nvm");
3079 /* In offset the highest byte must be zeroed. */
3080 if (offset & 0xFF000000) {
3081 status = I40E_ERR_PARAM;
3082 goto i40e_aq_update_nvm_exit;
3085 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3087 /* If this is the last command in a series, set the proper flag. */
3089 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3090 cmd->module_pointer = module_pointer;
3091 cmd->offset = CPU_TO_LE32(offset);
3092 cmd->length = CPU_TO_LE16(length);
3094 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3095 if (length > I40E_AQ_LARGE_BUF)
3096 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3098 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3100 i40e_aq_update_nvm_exit:
3105 * i40e_aq_get_lldp_mib
3106 * @hw: pointer to the hw struct
3107 * @bridge_type: type of bridge requested
3108 * @mib_type: Local, Remote or both Local and Remote MIBs
3109 * @buff: pointer to a user supplied buffer to store the MIB block
3110 * @buff_size: size of the buffer (in bytes)
3111 * @local_len : length of the returned Local LLDP MIB
3112 * @remote_len: length of the returned Remote LLDP MIB
3113 * @cmd_details: pointer to command details structure or NULL
3115 * Requests the complete LLDP MIB (entire packet).
3117 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3118 u8 mib_type, void *buff, u16 buff_size,
3119 u16 *local_len, u16 *remote_len,
3120 struct i40e_asq_cmd_details *cmd_details)
3122 struct i40e_aq_desc desc;
3123 struct i40e_aqc_lldp_get_mib *cmd =
3124 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3125 struct i40e_aqc_lldp_get_mib *resp =
3126 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3127 enum i40e_status_code status;
3129 if (buff_size == 0 || !buff)
3130 return I40E_ERR_PARAM;
3132 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3133 /* Indirect Command */
3134 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3136 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3137 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3138 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3140 desc.datalen = CPU_TO_LE16(buff_size);
3142 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3143 if (buff_size > I40E_AQ_LARGE_BUF)
3144 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3146 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3148 if (local_len != NULL)
3149 *local_len = LE16_TO_CPU(resp->local_len);
3150 if (remote_len != NULL)
3151 *remote_len = LE16_TO_CPU(resp->remote_len);
3158 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3159 * @hw: pointer to the hw struct
3160 * @mib_type: Local, Remote or both Local and Remote MIBs
3161 * @buff: pointer to a user supplied buffer to store the MIB block
3162 * @buff_size: size of the buffer (in bytes)
3163 * @cmd_details: pointer to command details structure or NULL
3167 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3168 u8 mib_type, void *buff, u16 buff_size,
3169 struct i40e_asq_cmd_details *cmd_details)
3171 struct i40e_aq_desc desc;
3172 struct i40e_aqc_lldp_set_local_mib *cmd =
3173 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3174 enum i40e_status_code status;
3176 if (buff_size == 0 || !buff)
3177 return I40E_ERR_PARAM;
3179 i40e_fill_default_direct_cmd_desc(&desc,
3180 i40e_aqc_opc_lldp_set_local_mib);
3181 /* Indirect Command */
3182 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3183 if (buff_size > I40E_AQ_LARGE_BUF)
3184 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3185 desc.datalen = CPU_TO_LE16(buff_size);
3187 cmd->type = mib_type;
3188 cmd->length = CPU_TO_LE16(buff_size);
3189 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3190 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3192 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3197 * i40e_aq_cfg_lldp_mib_change_event
3198 * @hw: pointer to the hw struct
3199 * @enable_update: Enable or Disable event posting
3200 * @cmd_details: pointer to command details structure or NULL
3202 * Enable or Disable posting of an event on ARQ when LLDP MIB
3203 * associated with the interface changes
3205 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3207 struct i40e_asq_cmd_details *cmd_details)
3209 struct i40e_aq_desc desc;
3210 struct i40e_aqc_lldp_update_mib *cmd =
3211 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3212 enum i40e_status_code status;
3214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3217 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3225 * i40e_aq_add_lldp_tlv
3226 * @hw: pointer to the hw struct
3227 * @bridge_type: type of bridge
3228 * @buff: buffer with TLV to add
3229 * @buff_size: length of the buffer
3230 * @tlv_len: length of the TLV to be added
3231 * @mib_len: length of the LLDP MIB returned in response
3232 * @cmd_details: pointer to command details structure or NULL
3234 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3235 * it is responsibility of the caller to make sure that the TLV is not
3236 * already present in the LLDPDU.
3237 * In return firmware will write the complete LLDP MIB with the newly
3238 * added TLV in the response buffer.
3240 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3241 void *buff, u16 buff_size, u16 tlv_len,
3243 struct i40e_asq_cmd_details *cmd_details)
3245 struct i40e_aq_desc desc;
3246 struct i40e_aqc_lldp_add_tlv *cmd =
3247 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3248 enum i40e_status_code status;
3250 if (buff_size == 0 || !buff || tlv_len == 0)
3251 return I40E_ERR_PARAM;
3253 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3255 /* Indirect Command */
3256 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3257 if (buff_size > I40E_AQ_LARGE_BUF)
3258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3259 desc.datalen = CPU_TO_LE16(buff_size);
3261 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3262 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3263 cmd->len = CPU_TO_LE16(tlv_len);
3265 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3267 if (mib_len != NULL)
3268 *mib_len = LE16_TO_CPU(desc.datalen);
3275 * i40e_aq_update_lldp_tlv
3276 * @hw: pointer to the hw struct
3277 * @bridge_type: type of bridge
3278 * @buff: buffer with TLV to update
3279 * @buff_size: size of the buffer holding original and updated TLVs
3280 * @old_len: Length of the Original TLV
3281 * @new_len: Length of the Updated TLV
3282 * @offset: offset of the updated TLV in the buff
3283 * @mib_len: length of the returned LLDP MIB
3284 * @cmd_details: pointer to command details structure or NULL
3286 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3287 * Firmware will place the complete LLDP MIB in response buffer with the
3290 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3291 u8 bridge_type, void *buff, u16 buff_size,
3292 u16 old_len, u16 new_len, u16 offset,
3294 struct i40e_asq_cmd_details *cmd_details)
3296 struct i40e_aq_desc desc;
3297 struct i40e_aqc_lldp_update_tlv *cmd =
3298 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3299 enum i40e_status_code status;
3301 if (buff_size == 0 || !buff || offset == 0 ||
3302 old_len == 0 || new_len == 0)
3303 return I40E_ERR_PARAM;
3305 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3307 /* Indirect Command */
3308 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3309 if (buff_size > I40E_AQ_LARGE_BUF)
3310 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3311 desc.datalen = CPU_TO_LE16(buff_size);
3313 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3314 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3315 cmd->old_len = CPU_TO_LE16(old_len);
3316 cmd->new_offset = CPU_TO_LE16(offset);
3317 cmd->new_len = CPU_TO_LE16(new_len);
3319 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3321 if (mib_len != NULL)
3322 *mib_len = LE16_TO_CPU(desc.datalen);
3329 * i40e_aq_delete_lldp_tlv
3330 * @hw: pointer to the hw struct
3331 * @bridge_type: type of bridge
3332 * @buff: pointer to a user supplied buffer that has the TLV
3333 * @buff_size: length of the buffer
3334 * @tlv_len: length of the TLV to be deleted
3335 * @mib_len: length of the returned LLDP MIB
3336 * @cmd_details: pointer to command details structure or NULL
3338 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3339 * The firmware places the entire LLDP MIB in the response buffer.
3341 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3342 u8 bridge_type, void *buff, u16 buff_size,
3343 u16 tlv_len, u16 *mib_len,
3344 struct i40e_asq_cmd_details *cmd_details)
3346 struct i40e_aq_desc desc;
3347 struct i40e_aqc_lldp_add_tlv *cmd =
3348 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3349 enum i40e_status_code status;
3351 if (buff_size == 0 || !buff)
3352 return I40E_ERR_PARAM;
3354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3356 /* Indirect Command */
3357 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3358 if (buff_size > I40E_AQ_LARGE_BUF)
3359 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3360 desc.datalen = CPU_TO_LE16(buff_size);
3361 cmd->len = CPU_TO_LE16(tlv_len);
3362 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3363 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3365 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3367 if (mib_len != NULL)
3368 *mib_len = LE16_TO_CPU(desc.datalen);
3376 * @hw: pointer to the hw struct
3377 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3378 * @cmd_details: pointer to command details structure or NULL
3380 * Stop or Shutdown the embedded LLDP Agent
3382 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3383 struct i40e_asq_cmd_details *cmd_details)
3385 struct i40e_aq_desc desc;
3386 struct i40e_aqc_lldp_stop *cmd =
3387 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3388 enum i40e_status_code status;
3390 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3393 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3401 * i40e_aq_start_lldp
3402 * @hw: pointer to the hw struct
3403 * @cmd_details: pointer to command details structure or NULL
3405 * Start the embedded LLDP Agent on all ports.
3407 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3408 struct i40e_asq_cmd_details *cmd_details)
3410 struct i40e_aq_desc desc;
3411 struct i40e_aqc_lldp_start *cmd =
3412 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3413 enum i40e_status_code status;
3415 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3417 cmd->command = I40E_AQ_LLDP_AGENT_START;
3419 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3425 * i40e_aq_get_cee_dcb_config
3426 * @hw: pointer to the hw struct
3427 * @buff: response buffer that stores CEE operational configuration
3428 * @buff_size: size of the buffer passed
3429 * @cmd_details: pointer to command details structure or NULL
3431 * Get CEE DCBX mode operational configuration from firmware
3433 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3434 void *buff, u16 buff_size,
3435 struct i40e_asq_cmd_details *cmd_details)
3437 struct i40e_aq_desc desc;
3438 enum i40e_status_code status;
3440 if (buff_size == 0 || !buff)
3441 return I40E_ERR_PARAM;
3443 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3446 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3453 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3454 * @hw: pointer to the hw struct
3455 * @start_agent: True if DCBx Agent needs to be Started
3456 * False if DCBx Agent needs to be Stopped
3457 * @cmd_details: pointer to command details structure or NULL
3459 * Start/Stop the embedded dcbx Agent
3461 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3463 struct i40e_asq_cmd_details *cmd_details)
3465 struct i40e_aq_desc desc;
3466 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3467 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3469 enum i40e_status_code status;
3471 i40e_fill_default_direct_cmd_desc(&desc,
3472 i40e_aqc_opc_lldp_stop_start_spec_agent);
3475 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3477 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3483 * i40e_aq_add_udp_tunnel
3484 * @hw: pointer to the hw struct
3485 * @udp_port: the UDP port to add
3486 * @header_len: length of the tunneling header length in DWords
3487 * @protocol_index: protocol index type
3488 * @filter_index: pointer to filter index
3489 * @cmd_details: pointer to command details structure or NULL
3491 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3492 u16 udp_port, u8 protocol_index,
3494 struct i40e_asq_cmd_details *cmd_details)
3496 struct i40e_aq_desc desc;
3497 struct i40e_aqc_add_udp_tunnel *cmd =
3498 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3499 struct i40e_aqc_del_udp_tunnel_completion *resp =
3500 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3501 enum i40e_status_code status;
3503 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3505 cmd->udp_port = CPU_TO_LE16(udp_port);
3506 cmd->protocol_type = protocol_index;
3508 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3510 if (!status && filter_index)
3511 *filter_index = resp->index;
3517 * i40e_aq_del_udp_tunnel
3518 * @hw: pointer to the hw struct
3519 * @index: filter index
3520 * @cmd_details: pointer to command details structure or NULL
3522 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3523 struct i40e_asq_cmd_details *cmd_details)
3525 struct i40e_aq_desc desc;
3526 struct i40e_aqc_remove_udp_tunnel *cmd =
3527 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3528 enum i40e_status_code status;
3530 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3540 * i40e_aq_get_switch_resource_alloc (0x0204)
3541 * @hw: pointer to the hw struct
3542 * @num_entries: pointer to u8 to store the number of resource entries returned
3543 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3544 * to store the resource information for all resource types. Each
3545 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3546 * @count: size, in bytes, of the buffer provided
3547 * @cmd_details: pointer to command details structure or NULL
3549 * Query the resources allocated to a function.
3551 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3553 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3555 struct i40e_asq_cmd_details *cmd_details)
3557 struct i40e_aq_desc desc;
3558 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3559 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3560 enum i40e_status_code status;
3561 u16 length = count * sizeof(*buf);
3563 i40e_fill_default_direct_cmd_desc(&desc,
3564 i40e_aqc_opc_get_switch_resource_alloc);
3566 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3567 if (length > I40E_AQ_LARGE_BUF)
3568 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3570 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3572 if (!status && num_entries)
3573 *num_entries = cmd_resp->num_entries;
3579 * i40e_aq_delete_element - Delete switch element
3580 * @hw: pointer to the hw struct
3581 * @seid: the SEID to delete from the switch
3582 * @cmd_details: pointer to command details structure or NULL
3584 * This deletes a switch element from the switch.
3586 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3587 struct i40e_asq_cmd_details *cmd_details)
3589 struct i40e_aq_desc desc;
3590 struct i40e_aqc_switch_seid *cmd =
3591 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3592 enum i40e_status_code status;
3595 return I40E_ERR_PARAM;
3597 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3599 cmd->seid = CPU_TO_LE16(seid);
3601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3607 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3608 * @hw: pointer to the hw struct
3609 * @flags: component flags
3610 * @mac_seid: uplink seid (MAC SEID)
3611 * @vsi_seid: connected vsi seid
3612 * @ret_seid: seid of create pv component
3614 * This instantiates an i40e port virtualizer with specified flags.
3615 * Depending on specified flags the port virtualizer can act as a
3616 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3618 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3619 u16 mac_seid, u16 vsi_seid,
3622 struct i40e_aq_desc desc;
3623 struct i40e_aqc_add_update_pv *cmd =
3624 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3625 struct i40e_aqc_add_update_pv_completion *resp =
3626 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3627 enum i40e_status_code status;
3630 return I40E_ERR_PARAM;
3632 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3633 cmd->command_flags = CPU_TO_LE16(flags);
3634 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3635 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3637 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3638 if (!status && ret_seid)
3639 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3645 * i40e_aq_add_tag - Add an S/E-tag
3646 * @hw: pointer to the hw struct
3647 * @direct_to_queue: should s-tag direct flow to a specific queue
3648 * @vsi_seid: VSI SEID to use this tag
3649 * @tag: value of the tag
3650 * @queue_num: queue number, only valid is direct_to_queue is TRUE
3651 * @tags_used: return value, number of tags in use by this PF
3652 * @tags_free: return value, number of unallocated tags
3653 * @cmd_details: pointer to command details structure or NULL
3655 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3656 * the number of tags allocated by the PF, and the number of unallocated
3659 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3660 u16 vsi_seid, u16 tag, u16 queue_num,
3661 u16 *tags_used, u16 *tags_free,
3662 struct i40e_asq_cmd_details *cmd_details)
3664 struct i40e_aq_desc desc;
3665 struct i40e_aqc_add_tag *cmd =
3666 (struct i40e_aqc_add_tag *)&desc.params.raw;
3667 struct i40e_aqc_add_remove_tag_completion *resp =
3668 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3669 enum i40e_status_code status;
3672 return I40E_ERR_PARAM;
3674 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3676 cmd->seid = CPU_TO_LE16(vsi_seid);
3677 cmd->tag = CPU_TO_LE16(tag);
3678 if (direct_to_queue) {
3679 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3680 cmd->queue_number = CPU_TO_LE16(queue_num);
3683 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3686 if (tags_used != NULL)
3687 *tags_used = LE16_TO_CPU(resp->tags_used);
3688 if (tags_free != NULL)
3689 *tags_free = LE16_TO_CPU(resp->tags_free);
3696 * i40e_aq_remove_tag - Remove an S- or E-tag
3697 * @hw: pointer to the hw struct
3698 * @vsi_seid: VSI SEID this tag is associated with
3699 * @tag: value of the S-tag to delete
3700 * @tags_used: return value, number of tags in use by this PF
3701 * @tags_free: return value, number of unallocated tags
3702 * @cmd_details: pointer to command details structure or NULL
3704 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3705 * the number of tags allocated by the PF, and the number of unallocated
3708 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3709 u16 tag, u16 *tags_used, u16 *tags_free,
3710 struct i40e_asq_cmd_details *cmd_details)
3712 struct i40e_aq_desc desc;
3713 struct i40e_aqc_remove_tag *cmd =
3714 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3715 struct i40e_aqc_add_remove_tag_completion *resp =
3716 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3717 enum i40e_status_code status;
3720 return I40E_ERR_PARAM;
3722 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3724 cmd->seid = CPU_TO_LE16(vsi_seid);
3725 cmd->tag = CPU_TO_LE16(tag);
3727 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3730 if (tags_used != NULL)
3731 *tags_used = LE16_TO_CPU(resp->tags_used);
3732 if (tags_free != NULL)
3733 *tags_free = LE16_TO_CPU(resp->tags_free);
3740 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3741 * @hw: pointer to the hw struct
3742 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3743 * @etag: value of E-tag to add
3744 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3745 * @buf: address of indirect buffer
3746 * @tags_used: return value, number of E-tags in use by this port
3747 * @tags_free: return value, number of unallocated M-tags
3748 * @cmd_details: pointer to command details structure or NULL
3750 * This associates a multicast E-tag to a port virtualizer. It will return
3751 * the number of tags allocated by the PF, and the number of unallocated
3754 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3755 * num_tags_in_buf long.
3757 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3758 u16 etag, u8 num_tags_in_buf, void *buf,
3759 u16 *tags_used, u16 *tags_free,
3760 struct i40e_asq_cmd_details *cmd_details)
3762 struct i40e_aq_desc desc;
3763 struct i40e_aqc_add_remove_mcast_etag *cmd =
3764 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3765 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3766 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3767 enum i40e_status_code status;
3768 u16 length = sizeof(u16) * num_tags_in_buf;
3770 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3771 return I40E_ERR_PARAM;
3773 i40e_fill_default_direct_cmd_desc(&desc,
3774 i40e_aqc_opc_add_multicast_etag);
3776 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3777 cmd->etag = CPU_TO_LE16(etag);
3778 cmd->num_unicast_etags = num_tags_in_buf;
3780 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3781 if (length > I40E_AQ_LARGE_BUF)
3782 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3784 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3787 if (tags_used != NULL)
3788 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3789 if (tags_free != NULL)
3790 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3797 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3798 * @hw: pointer to the hw struct
3799 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3800 * @etag: value of the E-tag to remove
3801 * @tags_used: return value, number of tags in use by this port
3802 * @tags_free: return value, number of unallocated tags
3803 * @cmd_details: pointer to command details structure or NULL
3805 * This deletes an E-tag from the port virtualizer. It will return
3806 * the number of tags allocated by the port, and the number of unallocated
3809 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3810 u16 etag, u16 *tags_used, u16 *tags_free,
3811 struct i40e_asq_cmd_details *cmd_details)
3813 struct i40e_aq_desc desc;
3814 struct i40e_aqc_add_remove_mcast_etag *cmd =
3815 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3816 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3817 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3818 enum i40e_status_code status;
3822 return I40E_ERR_PARAM;
3824 i40e_fill_default_direct_cmd_desc(&desc,
3825 i40e_aqc_opc_remove_multicast_etag);
3827 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3828 cmd->etag = CPU_TO_LE16(etag);
3830 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3833 if (tags_used != NULL)
3834 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3835 if (tags_free != NULL)
3836 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3843 * i40e_aq_update_tag - Update an S/E-tag
3844 * @hw: pointer to the hw struct
3845 * @vsi_seid: VSI SEID using this S-tag
3846 * @old_tag: old tag value
3847 * @new_tag: new tag value
3848 * @tags_used: return value, number of tags in use by this PF
3849 * @tags_free: return value, number of unallocated tags
3850 * @cmd_details: pointer to command details structure or NULL
3852 * This updates the value of the tag currently attached to this VSI
3853 * in the switch complex. It will return the number of tags allocated
3854 * by the PF, and the number of unallocated tags available.
3856 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3857 u16 old_tag, u16 new_tag, u16 *tags_used,
3859 struct i40e_asq_cmd_details *cmd_details)
3861 struct i40e_aq_desc desc;
3862 struct i40e_aqc_update_tag *cmd =
3863 (struct i40e_aqc_update_tag *)&desc.params.raw;
3864 struct i40e_aqc_update_tag_completion *resp =
3865 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3866 enum i40e_status_code status;
3869 return I40E_ERR_PARAM;
3871 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3873 cmd->seid = CPU_TO_LE16(vsi_seid);
3874 cmd->old_tag = CPU_TO_LE16(old_tag);
3875 cmd->new_tag = CPU_TO_LE16(new_tag);
3877 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3880 if (tags_used != NULL)
3881 *tags_used = LE16_TO_CPU(resp->tags_used);
3882 if (tags_free != NULL)
3883 *tags_free = LE16_TO_CPU(resp->tags_free);
3890 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3891 * @hw: pointer to the hw struct
3892 * @tcmap: TC map for request/release any ignore PFC condition
3893 * @request: request or release ignore PFC condition
3894 * @tcmap_ret: return TCs for which PFC is currently ignored
3895 * @cmd_details: pointer to command details structure or NULL
3897 * This sends out request/release to ignore PFC condition for a TC.
3898 * It will return the TCs for which PFC is currently ignored.
3900 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3901 bool request, u8 *tcmap_ret,
3902 struct i40e_asq_cmd_details *cmd_details)
3904 struct i40e_aq_desc desc;
3905 struct i40e_aqc_pfc_ignore *cmd_resp =
3906 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3907 enum i40e_status_code status;
3909 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3912 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3914 cmd_resp->tc_bitmap = tcmap;
3916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3919 if (tcmap_ret != NULL)
3920 *tcmap_ret = cmd_resp->tc_bitmap;
3927 * i40e_aq_dcb_updated - DCB Updated Command
3928 * @hw: pointer to the hw struct
3929 * @cmd_details: pointer to command details structure or NULL
3931 * When LLDP is handled in PF this command is used by the PF
3932 * to notify EMP that a DCB setting is modified.
3933 * When LLDP is handled in EMP this command is used by the PF
3934 * to notify EMP whenever one of the following parameters get
3936 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3937 * - PCIRTT in PRTDCB_GENC.PCIRTT
3938 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3939 * EMP will return when the shared RPB settings have been
3940 * recomputed and modified. The retval field in the descriptor
3941 * will be set to 0 when RPB is modified.
3943 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3944 struct i40e_asq_cmd_details *cmd_details)
3946 struct i40e_aq_desc desc;
3947 enum i40e_status_code status;
3949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3951 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3957 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3958 * @hw: pointer to the hw struct
3959 * @seid: defines the SEID of the switch for which the stats are requested
3960 * @vlan_id: the VLAN ID for which the statistics are requested
3961 * @stat_index: index of the statistics counters block assigned to this VLAN
3962 * @cmd_details: pointer to command details structure or NULL
3964 * XL710 supports 128 smonVlanStats counters.This command is used to
3965 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3968 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3969 u16 vlan_id, u16 *stat_index,
3970 struct i40e_asq_cmd_details *cmd_details)
3972 struct i40e_aq_desc desc;
3973 struct i40e_aqc_add_remove_statistics *cmd_resp =
3974 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3975 enum i40e_status_code status;
3977 if ((seid == 0) || (stat_index == NULL))
3978 return I40E_ERR_PARAM;
3980 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3982 cmd_resp->seid = CPU_TO_LE16(seid);
3983 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
3985 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3987 if (!status && stat_index)
3988 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
3994 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
3995 * @hw: pointer to the hw struct
3996 * @seid: defines the SEID of the switch for which the stats are requested
3997 * @vlan_id: the VLAN ID for which the statistics are requested
3998 * @stat_index: index of the statistics counters block assigned to this VLAN
3999 * @cmd_details: pointer to command details structure or NULL
4001 * XL710 supports 128 smonVlanStats counters.This command is used to
4002 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4005 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4006 u16 vlan_id, u16 stat_index,
4007 struct i40e_asq_cmd_details *cmd_details)
4009 struct i40e_aq_desc desc;
4010 struct i40e_aqc_add_remove_statistics *cmd =
4011 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4012 enum i40e_status_code status;
4015 return I40E_ERR_PARAM;
4017 i40e_fill_default_direct_cmd_desc(&desc,
4018 i40e_aqc_opc_remove_statistics);
4020 cmd->seid = CPU_TO_LE16(seid);
4021 cmd->vlan = CPU_TO_LE16(vlan_id);
4022 cmd->stat_index = CPU_TO_LE16(stat_index);
4024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4030 * i40e_aq_set_port_parameters - set physical port parameters.
4031 * @hw: pointer to the hw struct
4032 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4033 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4034 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4035 * @double_vlan: if set double VLAN is enabled
4036 * @cmd_details: pointer to command details structure or NULL
4038 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4039 u16 bad_frame_vsi, bool save_bad_pac,
4040 bool pad_short_pac, bool double_vlan,
4041 struct i40e_asq_cmd_details *cmd_details)
4043 struct i40e_aqc_set_port_parameters *cmd;
4044 enum i40e_status_code status;
4045 struct i40e_aq_desc desc;
4046 u16 command_flags = 0;
4048 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4050 i40e_fill_default_direct_cmd_desc(&desc,
4051 i40e_aqc_opc_set_port_parameters);
4053 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4055 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4057 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4059 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4060 cmd->command_flags = CPU_TO_LE16(command_flags);
4062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4068 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4069 * @hw: pointer to the hw struct
4070 * @seid: seid for the physical port/switching component/vsi
4071 * @buff: Indirect buffer to hold data parameters and response
4072 * @buff_size: Indirect buffer size
4073 * @opcode: Tx scheduler AQ command opcode
4074 * @cmd_details: pointer to command details structure or NULL
4076 * Generic command handler for Tx scheduler AQ commands
4078 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4079 void *buff, u16 buff_size,
4080 enum i40e_admin_queue_opc opcode,
4081 struct i40e_asq_cmd_details *cmd_details)
4083 struct i40e_aq_desc desc;
4084 struct i40e_aqc_tx_sched_ind *cmd =
4085 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4086 enum i40e_status_code status;
4087 bool cmd_param_flag = FALSE;
4090 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4091 case i40e_aqc_opc_configure_vsi_tc_bw:
4092 case i40e_aqc_opc_enable_switching_comp_ets:
4093 case i40e_aqc_opc_modify_switching_comp_ets:
4094 case i40e_aqc_opc_disable_switching_comp_ets:
4095 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4096 case i40e_aqc_opc_configure_switching_comp_bw_config:
4097 cmd_param_flag = TRUE;
4099 case i40e_aqc_opc_query_vsi_bw_config:
4100 case i40e_aqc_opc_query_vsi_ets_sla_config:
4101 case i40e_aqc_opc_query_switching_comp_ets_config:
4102 case i40e_aqc_opc_query_port_ets_config:
4103 case i40e_aqc_opc_query_switching_comp_bw_config:
4104 cmd_param_flag = FALSE;
4107 return I40E_ERR_PARAM;
4110 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4112 /* Indirect command */
4113 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4116 if (buff_size > I40E_AQ_LARGE_BUF)
4117 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4119 desc.datalen = CPU_TO_LE16(buff_size);
4121 cmd->vsi_seid = CPU_TO_LE16(seid);
4123 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4129 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4130 * @hw: pointer to the hw struct
4132 * @credit: BW limit credits (0 = disabled)
4133 * @max_credit: Max BW limit credits
4134 * @cmd_details: pointer to command details structure or NULL
4136 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4137 u16 seid, u16 credit, u8 max_credit,
4138 struct i40e_asq_cmd_details *cmd_details)
4140 struct i40e_aq_desc desc;
4141 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4142 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4143 enum i40e_status_code status;
4145 i40e_fill_default_direct_cmd_desc(&desc,
4146 i40e_aqc_opc_configure_vsi_bw_limit);
4148 cmd->vsi_seid = CPU_TO_LE16(seid);
4149 cmd->credit = CPU_TO_LE16(credit);
4150 cmd->max_credit = max_credit;
4152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4158 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4159 * @hw: pointer to the hw struct
4160 * @seid: switching component seid
4161 * @credit: BW limit credits (0 = disabled)
4162 * @max_bw: Max BW limit credits
4163 * @cmd_details: pointer to command details structure or NULL
4165 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4166 u16 seid, u16 credit, u8 max_bw,
4167 struct i40e_asq_cmd_details *cmd_details)
4169 struct i40e_aq_desc desc;
4170 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4171 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4172 enum i40e_status_code status;
4174 i40e_fill_default_direct_cmd_desc(&desc,
4175 i40e_aqc_opc_configure_switching_comp_bw_limit);
4177 cmd->seid = CPU_TO_LE16(seid);
4178 cmd->credit = CPU_TO_LE16(credit);
4179 cmd->max_bw = max_bw;
4181 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4187 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4188 * @hw: pointer to the hw struct
4190 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4191 * @cmd_details: pointer to command details structure or NULL
4193 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4195 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4196 struct i40e_asq_cmd_details *cmd_details)
4198 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4199 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4204 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4205 * @hw: pointer to the hw struct
4207 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4208 * @cmd_details: pointer to command details structure or NULL
4210 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4212 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4213 struct i40e_asq_cmd_details *cmd_details)
4215 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4216 i40e_aqc_opc_configure_vsi_tc_bw,
4221 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4222 * @hw: pointer to the hw struct
4223 * @seid: seid of the switching component
4224 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4225 * @cmd_details: pointer to command details structure or NULL
4227 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4228 struct i40e_hw *hw, u16 seid,
4229 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4230 struct i40e_asq_cmd_details *cmd_details)
4232 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4233 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4238 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4239 * @hw: pointer to the hw struct
4240 * @seid: seid of the VSI
4241 * @bw_data: Buffer to hold VSI BW configuration
4242 * @cmd_details: pointer to command details structure or NULL
4244 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4246 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4247 struct i40e_asq_cmd_details *cmd_details)
4249 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4250 i40e_aqc_opc_query_vsi_bw_config,
4255 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4256 * @hw: pointer to the hw struct
4257 * @seid: seid of the VSI
4258 * @bw_data: Buffer to hold VSI BW configuration per TC
4259 * @cmd_details: pointer to command details structure or NULL
4261 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4263 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4264 struct i40e_asq_cmd_details *cmd_details)
4266 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4267 i40e_aqc_opc_query_vsi_ets_sla_config,
4272 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4273 * @hw: pointer to the hw struct
4274 * @seid: seid of the switching component
4275 * @bw_data: Buffer to hold switching component's per TC BW config
4276 * @cmd_details: pointer to command details structure or NULL
4278 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4280 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4281 struct i40e_asq_cmd_details *cmd_details)
4283 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4284 i40e_aqc_opc_query_switching_comp_ets_config,
4289 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4290 * @hw: pointer to the hw struct
4291 * @seid: seid of the VSI or switching component connected to Physical Port
4292 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4293 * @cmd_details: pointer to command details structure or NULL
4295 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4297 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4298 struct i40e_asq_cmd_details *cmd_details)
4300 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4301 i40e_aqc_opc_query_port_ets_config,
4306 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4307 * @hw: pointer to the hw struct
4308 * @seid: seid of the switching component
4309 * @bw_data: Buffer to hold switching component's BW configuration
4310 * @cmd_details: pointer to command details structure or NULL
4312 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4314 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4315 struct i40e_asq_cmd_details *cmd_details)
4317 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4318 i40e_aqc_opc_query_switching_comp_bw_config,
4323 * i40e_validate_filter_settings
4324 * @hw: pointer to the hardware structure
4325 * @settings: Filter control settings
4327 * Check and validate the filter control settings passed.
4328 * The function checks for the valid filter/context sizes being
4329 * passed for FCoE and PE.
4331 * Returns I40E_SUCCESS if the values passed are valid and within
4332 * range else returns an error.
4334 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4335 struct i40e_filter_control_settings *settings)
4337 u32 fcoe_cntx_size, fcoe_filt_size;
4338 u32 pe_cntx_size, pe_filt_size;
4343 /* Validate FCoE settings passed */
4344 switch (settings->fcoe_filt_num) {
4345 case I40E_HASH_FILTER_SIZE_1K:
4346 case I40E_HASH_FILTER_SIZE_2K:
4347 case I40E_HASH_FILTER_SIZE_4K:
4348 case I40E_HASH_FILTER_SIZE_8K:
4349 case I40E_HASH_FILTER_SIZE_16K:
4350 case I40E_HASH_FILTER_SIZE_32K:
4351 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4352 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4355 return I40E_ERR_PARAM;
4358 switch (settings->fcoe_cntx_num) {
4359 case I40E_DMA_CNTX_SIZE_512:
4360 case I40E_DMA_CNTX_SIZE_1K:
4361 case I40E_DMA_CNTX_SIZE_2K:
4362 case I40E_DMA_CNTX_SIZE_4K:
4363 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4364 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4367 return I40E_ERR_PARAM;
4370 /* Validate PE settings passed */
4371 switch (settings->pe_filt_num) {
4372 case I40E_HASH_FILTER_SIZE_1K:
4373 case I40E_HASH_FILTER_SIZE_2K:
4374 case I40E_HASH_FILTER_SIZE_4K:
4375 case I40E_HASH_FILTER_SIZE_8K:
4376 case I40E_HASH_FILTER_SIZE_16K:
4377 case I40E_HASH_FILTER_SIZE_32K:
4378 case I40E_HASH_FILTER_SIZE_64K:
4379 case I40E_HASH_FILTER_SIZE_128K:
4380 case I40E_HASH_FILTER_SIZE_256K:
4381 case I40E_HASH_FILTER_SIZE_512K:
4382 case I40E_HASH_FILTER_SIZE_1M:
4383 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4384 pe_filt_size <<= (u32)settings->pe_filt_num;
4387 return I40E_ERR_PARAM;
4390 switch (settings->pe_cntx_num) {
4391 case I40E_DMA_CNTX_SIZE_512:
4392 case I40E_DMA_CNTX_SIZE_1K:
4393 case I40E_DMA_CNTX_SIZE_2K:
4394 case I40E_DMA_CNTX_SIZE_4K:
4395 case I40E_DMA_CNTX_SIZE_8K:
4396 case I40E_DMA_CNTX_SIZE_16K:
4397 case I40E_DMA_CNTX_SIZE_32K:
4398 case I40E_DMA_CNTX_SIZE_64K:
4399 case I40E_DMA_CNTX_SIZE_128K:
4400 case I40E_DMA_CNTX_SIZE_256K:
4401 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4402 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4405 return I40E_ERR_PARAM;
4408 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4409 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4410 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4411 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4412 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4413 return I40E_ERR_INVALID_SIZE;
4415 return I40E_SUCCESS;
4419 * i40e_set_filter_control
4420 * @hw: pointer to the hardware structure
4421 * @settings: Filter control settings
4423 * Set the Queue Filters for PE/FCoE and enable filters required
4424 * for a single PF. It is expected that these settings are programmed
4425 * at the driver initialization time.
4427 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4428 struct i40e_filter_control_settings *settings)
4430 enum i40e_status_code ret = I40E_SUCCESS;
4431 u32 hash_lut_size = 0;
4435 return I40E_ERR_PARAM;
4437 /* Validate the input settings */
4438 ret = i40e_validate_filter_settings(hw, settings);
4442 /* Read the PF Queue Filter control register */
4443 val = rd32(hw, I40E_PFQF_CTL_0);
4445 /* Program required PE hash buckets for the PF */
4446 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4447 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4448 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4449 /* Program required PE contexts for the PF */
4450 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4451 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4452 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4454 /* Program required FCoE hash buckets for the PF */
4455 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4456 val |= ((u32)settings->fcoe_filt_num <<
4457 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4458 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4459 /* Program required FCoE DDP contexts for the PF */
4460 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4461 val |= ((u32)settings->fcoe_cntx_num <<
4462 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4463 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4465 /* Program Hash LUT size for the PF */
4466 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4467 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4469 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4470 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4472 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4473 if (settings->enable_fdir)
4474 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4475 if (settings->enable_ethtype)
4476 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4477 if (settings->enable_macvlan)
4478 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4480 wr32(hw, I40E_PFQF_CTL_0, val);
4482 return I40E_SUCCESS;
4486 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4487 * @hw: pointer to the hw struct
4488 * @mac_addr: MAC address to use in the filter
4489 * @ethtype: Ethertype to use in the filter
4490 * @flags: Flags that needs to be applied to the filter
4491 * @vsi_seid: seid of the control VSI
4492 * @queue: VSI queue number to send the packet to
4493 * @is_add: Add control packet filter if True else remove
4494 * @stats: Structure to hold information on control filter counts
4495 * @cmd_details: pointer to command details structure or NULL
4497 * This command will Add or Remove control packet filter for a control VSI.
4498 * In return it will update the total number of perfect filter count in
4501 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4502 u8 *mac_addr, u16 ethtype, u16 flags,
4503 u16 vsi_seid, u16 queue, bool is_add,
4504 struct i40e_control_filter_stats *stats,
4505 struct i40e_asq_cmd_details *cmd_details)
4507 struct i40e_aq_desc desc;
4508 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4509 (struct i40e_aqc_add_remove_control_packet_filter *)
4511 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4512 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4514 enum i40e_status_code status;
4517 return I40E_ERR_PARAM;
4520 i40e_fill_default_direct_cmd_desc(&desc,
4521 i40e_aqc_opc_add_control_packet_filter);
4522 cmd->queue = CPU_TO_LE16(queue);
4524 i40e_fill_default_direct_cmd_desc(&desc,
4525 i40e_aqc_opc_remove_control_packet_filter);
4529 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4530 I40E_NONDMA_TO_NONDMA);
4532 cmd->etype = CPU_TO_LE16(ethtype);
4533 cmd->flags = CPU_TO_LE16(flags);
4534 cmd->seid = CPU_TO_LE16(vsi_seid);
4536 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4538 if (!status && stats) {
4539 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4540 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4541 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4542 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4549 * i40e_aq_add_cloud_filters
4550 * @hw: pointer to the hardware structure
4551 * @seid: VSI seid to add cloud filters from
4552 * @filters: Buffer which contains the filters to be added
4553 * @filter_count: number of filters contained in the buffer
4555 * Set the cloud filters for a given VSI. The contents of the
4556 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4557 * in by the caller of the function.
4560 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4562 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4565 struct i40e_aq_desc desc;
4566 struct i40e_aqc_add_remove_cloud_filters *cmd =
4567 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4569 enum i40e_status_code status;
4571 i40e_fill_default_direct_cmd_desc(&desc,
4572 i40e_aqc_opc_add_cloud_filters);
4574 buff_len = filter_count * sizeof(*filters);
4575 desc.datalen = CPU_TO_LE16(buff_len);
4576 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4577 cmd->num_filters = filter_count;
4578 cmd->seid = CPU_TO_LE16(seid);
4580 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4586 * i40e_aq_remove_cloud_filters
4587 * @hw: pointer to the hardware structure
4588 * @seid: VSI seid to remove cloud filters from
4589 * @filters: Buffer which contains the filters to be removed
4590 * @filter_count: number of filters contained in the buffer
4592 * Remove the cloud filters for a given VSI. The contents of the
4593 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4594 * in by the caller of the function.
4597 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4599 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4602 struct i40e_aq_desc desc;
4603 struct i40e_aqc_add_remove_cloud_filters *cmd =
4604 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4605 enum i40e_status_code status;
4608 i40e_fill_default_direct_cmd_desc(&desc,
4609 i40e_aqc_opc_remove_cloud_filters);
4611 buff_len = filter_count * sizeof(*filters);
4612 desc.datalen = CPU_TO_LE16(buff_len);
4613 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4614 cmd->num_filters = filter_count;
4615 cmd->seid = CPU_TO_LE16(seid);
4617 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4623 * i40e_aq_alternate_write
4624 * @hw: pointer to the hardware structure
4625 * @reg_addr0: address of first dword to be read
4626 * @reg_val0: value to be written under 'reg_addr0'
4627 * @reg_addr1: address of second dword to be read
4628 * @reg_val1: value to be written under 'reg_addr1'
4630 * Write one or two dwords to alternate structure. Fields are indicated
4631 * by 'reg_addr0' and 'reg_addr1' register numbers.
4634 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4635 u32 reg_addr0, u32 reg_val0,
4636 u32 reg_addr1, u32 reg_val1)
4638 struct i40e_aq_desc desc;
4639 struct i40e_aqc_alternate_write *cmd_resp =
4640 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4641 enum i40e_status_code status;
4643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4644 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4645 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4646 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4647 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4649 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4655 * i40e_aq_alternate_write_indirect
4656 * @hw: pointer to the hardware structure
4657 * @addr: address of a first register to be modified
4658 * @dw_count: number of alternate structure fields to write
4659 * @buffer: pointer to the command buffer
4661 * Write 'dw_count' dwords from 'buffer' to alternate structure
4662 * starting at 'addr'.
4665 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4666 u32 addr, u32 dw_count, void *buffer)
4668 struct i40e_aq_desc desc;
4669 struct i40e_aqc_alternate_ind_write *cmd_resp =
4670 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4671 enum i40e_status_code status;
4674 return I40E_ERR_PARAM;
4676 /* Indirect command */
4677 i40e_fill_default_direct_cmd_desc(&desc,
4678 i40e_aqc_opc_alternate_write_indirect);
4680 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4681 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4682 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4683 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4685 cmd_resp->address = CPU_TO_LE32(addr);
4686 cmd_resp->length = CPU_TO_LE32(dw_count);
4687 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4688 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4690 status = i40e_asq_send_command(hw, &desc, buffer,
4691 I40E_LO_DWORD(4*dw_count), NULL);
4697 * i40e_aq_alternate_read
4698 * @hw: pointer to the hardware structure
4699 * @reg_addr0: address of first dword to be read
4700 * @reg_val0: pointer for data read from 'reg_addr0'
4701 * @reg_addr1: address of second dword to be read
4702 * @reg_val1: pointer for data read from 'reg_addr1'
4704 * Read one or two dwords from alternate structure. Fields are indicated
4705 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4706 * is not passed then only register at 'reg_addr0' is read.
4709 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4710 u32 reg_addr0, u32 *reg_val0,
4711 u32 reg_addr1, u32 *reg_val1)
4713 struct i40e_aq_desc desc;
4714 struct i40e_aqc_alternate_write *cmd_resp =
4715 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4716 enum i40e_status_code status;
4718 if (reg_val0 == NULL)
4719 return I40E_ERR_PARAM;
4721 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4722 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4723 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4725 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4727 if (status == I40E_SUCCESS) {
4728 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4730 if (reg_val1 != NULL)
4731 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4738 * i40e_aq_alternate_read_indirect
4739 * @hw: pointer to the hardware structure
4740 * @addr: address of the alternate structure field
4741 * @dw_count: number of alternate structure fields to read
4742 * @buffer: pointer to the command buffer
4744 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4745 * place them in 'buffer'. The buffer should be allocated by caller.
4748 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4749 u32 addr, u32 dw_count, void *buffer)
4751 struct i40e_aq_desc desc;
4752 struct i40e_aqc_alternate_ind_write *cmd_resp =
4753 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4754 enum i40e_status_code status;
4757 return I40E_ERR_PARAM;
4759 /* Indirect command */
4760 i40e_fill_default_direct_cmd_desc(&desc,
4761 i40e_aqc_opc_alternate_read_indirect);
4763 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4764 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4765 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4766 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4768 cmd_resp->address = CPU_TO_LE32(addr);
4769 cmd_resp->length = CPU_TO_LE32(dw_count);
4770 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4771 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4773 status = i40e_asq_send_command(hw, &desc, buffer,
4774 I40E_LO_DWORD(4*dw_count), NULL);
4780 * i40e_aq_alternate_clear
4781 * @hw: pointer to the HW structure.
4783 * Clear the alternate structures of the port from which the function
4787 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4789 struct i40e_aq_desc desc;
4790 enum i40e_status_code status;
4792 i40e_fill_default_direct_cmd_desc(&desc,
4793 i40e_aqc_opc_alternate_clear_port);
4795 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4801 * i40e_aq_alternate_write_done
4802 * @hw: pointer to the HW structure.
4803 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4804 * @reset_needed: indicates the SW should trigger GLOBAL reset
4806 * Indicates to the FW that alternate structures have been changed.
4809 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4810 u8 bios_mode, bool *reset_needed)
4812 struct i40e_aq_desc desc;
4813 struct i40e_aqc_alternate_write_done *cmd =
4814 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4815 enum i40e_status_code status;
4817 if (reset_needed == NULL)
4818 return I40E_ERR_PARAM;
4820 i40e_fill_default_direct_cmd_desc(&desc,
4821 i40e_aqc_opc_alternate_write_done);
4823 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4825 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4826 if (!status && reset_needed)
4827 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4828 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4834 * i40e_aq_set_oem_mode
4835 * @hw: pointer to the HW structure.
4836 * @oem_mode: the OEM mode to be used
4838 * Sets the device to a specific operating mode. Currently the only supported
4839 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4842 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4845 struct i40e_aq_desc desc;
4846 struct i40e_aqc_alternate_write_done *cmd =
4847 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4848 enum i40e_status_code status;
4850 i40e_fill_default_direct_cmd_desc(&desc,
4851 i40e_aqc_opc_alternate_set_mode);
4853 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4855 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4861 * i40e_aq_resume_port_tx
4862 * @hw: pointer to the hardware structure
4863 * @cmd_details: pointer to command details structure or NULL
4865 * Resume port's Tx traffic
4867 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4868 struct i40e_asq_cmd_details *cmd_details)
4870 struct i40e_aq_desc desc;
4871 enum i40e_status_code status;
4873 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4875 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4881 * i40e_set_pci_config_data - store PCI bus info
4882 * @hw: pointer to hardware structure
4883 * @link_status: the link status word from PCI config space
4885 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4887 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4889 hw->bus.type = i40e_bus_type_pci_express;
4891 switch (link_status & I40E_PCI_LINK_WIDTH) {
4892 case I40E_PCI_LINK_WIDTH_1:
4893 hw->bus.width = i40e_bus_width_pcie_x1;
4895 case I40E_PCI_LINK_WIDTH_2:
4896 hw->bus.width = i40e_bus_width_pcie_x2;
4898 case I40E_PCI_LINK_WIDTH_4:
4899 hw->bus.width = i40e_bus_width_pcie_x4;
4901 case I40E_PCI_LINK_WIDTH_8:
4902 hw->bus.width = i40e_bus_width_pcie_x8;
4905 hw->bus.width = i40e_bus_width_unknown;
4909 switch (link_status & I40E_PCI_LINK_SPEED) {
4910 case I40E_PCI_LINK_SPEED_2500:
4911 hw->bus.speed = i40e_bus_speed_2500;
4913 case I40E_PCI_LINK_SPEED_5000:
4914 hw->bus.speed = i40e_bus_speed_5000;
4916 case I40E_PCI_LINK_SPEED_8000:
4917 hw->bus.speed = i40e_bus_speed_8000;
4920 hw->bus.speed = i40e_bus_speed_unknown;
4926 * i40e_read_bw_from_alt_ram
4927 * @hw: pointer to the hardware structure
4928 * @max_bw: pointer for max_bw read
4929 * @min_bw: pointer for min_bw read
4930 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value
4931 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value
4933 * Read bw from the alternate ram for the given pf
4935 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4936 u32 *max_bw, u32 *min_bw,
4937 bool *min_valid, bool *max_valid)
4939 enum i40e_status_code status;
4940 u32 max_bw_addr, min_bw_addr;
4942 /* Calculate the address of the min/max bw registers */
4943 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4944 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4945 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4946 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4947 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4948 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4950 /* Read the bandwidths from alt ram */
4951 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4952 min_bw_addr, min_bw);
4954 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4959 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4968 * i40e_aq_configure_partition_bw
4969 * @hw: pointer to the hardware structure
4970 * @bw_data: Buffer holding valid pfs and bw limits
4971 * @cmd_details: pointer to command details
4973 * Configure partitions guaranteed/max bw
4975 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4976 struct i40e_aqc_configure_partition_bw_data *bw_data,
4977 struct i40e_asq_cmd_details *cmd_details)
4979 enum i40e_status_code status;
4980 struct i40e_aq_desc desc;
4981 u16 bwd_size = sizeof(*bw_data);
4983 i40e_fill_default_direct_cmd_desc(&desc,
4984 i40e_aqc_opc_configure_partition_bw);
4986 /* Indirect command */
4987 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4988 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4990 if (bwd_size > I40E_AQ_LARGE_BUF)
4991 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4993 desc.datalen = CPU_TO_LE16(bwd_size);
4995 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5001 * i40e_aq_send_msg_to_pf
5002 * @hw: pointer to the hardware structure
5003 * @v_opcode: opcodes for VF-PF communication
5004 * @v_retval: return error code
5005 * @msg: pointer to the msg buffer
5006 * @msglen: msg length
5007 * @cmd_details: pointer to command details
5009 * Send message to PF driver using admin queue. By default, this message
5010 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5011 * completion before returning.
5013 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5014 enum i40e_virtchnl_ops v_opcode,
5015 enum i40e_status_code v_retval,
5016 u8 *msg, u16 msglen,
5017 struct i40e_asq_cmd_details *cmd_details)
5019 struct i40e_aq_desc desc;
5020 struct i40e_asq_cmd_details details;
5021 enum i40e_status_code status;
5023 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5024 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5025 desc.cookie_high = CPU_TO_LE32(v_opcode);
5026 desc.cookie_low = CPU_TO_LE32(v_retval);
5028 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5029 | I40E_AQ_FLAG_RD));
5030 if (msglen > I40E_AQ_LARGE_BUF)
5031 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5032 desc.datalen = CPU_TO_LE16(msglen);
5035 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5036 details.async = TRUE;
5037 cmd_details = &details;
5039 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5040 msglen, cmd_details);
5045 * i40e_vf_parse_hw_config
5046 * @hw: pointer to the hardware structure
5047 * @msg: pointer to the virtual channel VF resource structure
5049 * Given a VF resource message from the PF, populate the hw struct
5050 * with appropriate information.
5052 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5053 struct i40e_virtchnl_vf_resource *msg)
5055 struct i40e_virtchnl_vsi_resource *vsi_res;
5058 vsi_res = &msg->vsi_res[0];
5060 hw->dev_caps.num_vsis = msg->num_vsis;
5061 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5062 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5063 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5064 hw->dev_caps.dcb = msg->vf_offload_flags &
5065 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5066 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5067 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5068 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5069 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5070 for (i = 0; i < msg->num_vsis; i++) {
5071 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5072 i40e_memcpy(hw->mac.perm_addr,
5073 vsi_res->default_mac_addr,
5074 I40E_ETH_LENGTH_OF_ADDRESS,
5075 I40E_NONDMA_TO_NONDMA);
5076 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5077 I40E_ETH_LENGTH_OF_ADDRESS,
5078 I40E_NONDMA_TO_NONDMA);
5086 * @hw: pointer to the hardware structure
5088 * Send a VF_RESET message to the PF. Does not wait for response from PF
5089 * as none will be forthcoming. Immediately after calling this function,
5090 * the admin queue should be shut down and (optionally) reinitialized.
5092 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5094 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5095 I40E_SUCCESS, NULL, 0, NULL);