1 /******************************************************************************
3 Copyright (c) 2013-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "i40e_virtchnl.h"
42 * i40e_set_mac_type - Sets MAC type
43 * @hw: pointer to the HW structure
45 * This function sets the mac type of the adapter based on the
46 * vendor ID and device ID stored in the hw structure.
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 enum i40e_status_code status = I40E_SUCCESS;
52 DEBUGFUNC("i40e_set_mac_type\n");
54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 switch (hw->device_id) {
56 case I40E_DEV_ID_SFP_XL710:
57 case I40E_DEV_ID_QEMU:
58 case I40E_DEV_ID_KX_A:
59 case I40E_DEV_ID_KX_B:
60 case I40E_DEV_ID_KX_C:
61 case I40E_DEV_ID_QSFP_A:
62 case I40E_DEV_ID_QSFP_B:
63 case I40E_DEV_ID_QSFP_C:
64 case I40E_DEV_ID_10G_BASE_T:
65 case I40E_DEV_ID_20G_KR2:
66 hw->mac.type = I40E_MAC_XL710;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
87 * @hw: debug mask related to admin queue
89 * @desc: pointer to admin queue descriptor
90 * @buffer: pointer to command buffer
91 * @buf_len: max length of buffer
93 * Dumps debug log about adminq command with descriptor contents.
95 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
96 void *buffer, u16 buf_len)
98 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
99 u16 len = LE16_TO_CPU(aq_desc->datalen);
100 u8 *buf = (u8 *)buffer;
103 if ((!(mask & hw->debug_mask)) || (desc == NULL))
107 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
108 LE16_TO_CPU(aq_desc->opcode),
109 LE16_TO_CPU(aq_desc->flags),
110 LE16_TO_CPU(aq_desc->datalen),
111 LE16_TO_CPU(aq_desc->retval));
112 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
113 LE32_TO_CPU(aq_desc->cookie_high),
114 LE32_TO_CPU(aq_desc->cookie_low));
115 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
116 LE32_TO_CPU(aq_desc->params.internal.param0),
117 LE32_TO_CPU(aq_desc->params.internal.param1));
118 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
119 LE32_TO_CPU(aq_desc->params.external.addr_high),
120 LE32_TO_CPU(aq_desc->params.external.addr_low));
122 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
123 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
126 /* write the full 16-byte chunks */
127 for (i = 0; i < (len - 16); i += 16)
129 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
130 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
131 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
132 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
133 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
134 /* write whatever's left over without overrunning the buffer */
139 memset(d_buf, 0, sizeof(d_buf));
140 j += sprintf(d_buf, "\t0x%04X ", i);
142 j += sprintf(&d_buf[j], " %02X", buf[i++]);
143 i40e_debug(hw, mask, "%s\n", d_buf);
149 * i40e_check_asq_alive
150 * @hw: pointer to the hw struct
152 * Returns TRUE if Queue is enabled else FALSE.
154 bool i40e_check_asq_alive(struct i40e_hw *hw)
157 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
163 * i40e_aq_queue_shutdown
164 * @hw: pointer to the hw struct
165 * @unloading: is the driver unloading itself
167 * Tell the Firmware that we're shutting down the AdminQ and whether
168 * or not the driver is unloading as well.
170 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
173 struct i40e_aq_desc desc;
174 struct i40e_aqc_queue_shutdown *cmd =
175 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
176 enum i40e_status_code status;
178 i40e_fill_default_direct_cmd_desc(&desc,
179 i40e_aqc_opc_queue_shutdown);
182 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
183 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
188 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
189 * hardware to a bit-field that can be used by SW to more easily determine the
192 * Macros are used to shorten the table lines and make this table human
195 * We store the PTYPE in the top byte of the bit field - this is just so that
196 * we can check that the table doesn't have a row missing, as the index into
197 * the table should be the PTYPE.
201 * IF NOT i40e_ptype_lookup[ptype].known
204 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
205 * Use the rest of the fields to look at the tunnels, inner protocols, etc
207 * Use the enum i40e_rx_l2_ptype to decode the packet type
211 /* macro to make the table lines short */
212 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
215 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
216 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
217 I40E_RX_PTYPE_##OUTER_FRAG, \
218 I40E_RX_PTYPE_TUNNEL_##T, \
219 I40E_RX_PTYPE_TUNNEL_END_##TE, \
220 I40E_RX_PTYPE_##TEF, \
221 I40E_RX_PTYPE_INNER_PROT_##I, \
222 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
224 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
225 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
227 /* shorter macros makes the table fit but are terse */
228 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
229 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
230 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
232 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
233 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
234 /* L2 Packet types */
235 I40E_PTT_UNUSED_ENTRY(0),
236 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
237 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
238 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
239 I40E_PTT_UNUSED_ENTRY(4),
240 I40E_PTT_UNUSED_ENTRY(5),
241 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
242 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
243 I40E_PTT_UNUSED_ENTRY(8),
244 I40E_PTT_UNUSED_ENTRY(9),
245 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
246 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
247 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
248 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
249 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
250 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
251 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
252 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
258 /* Non Tunneled IPv4 */
259 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
260 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
262 I40E_PTT_UNUSED_ENTRY(25),
263 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
264 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
265 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
268 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(32),
272 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
277 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(39),
281 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
285 /* IPv4 --> GRE/NAT */
286 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
288 /* IPv4 --> GRE/NAT --> IPv4 */
289 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(47),
293 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
297 /* IPv4 --> GRE/NAT --> IPv6 */
298 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(54),
302 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
306 /* IPv4 --> GRE/NAT --> MAC */
307 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
309 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
310 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(62),
314 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
318 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
319 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(69),
323 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
327 /* IPv4 --> GRE/NAT --> MAC/VLAN */
328 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
330 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
331 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
332 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
333 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
334 I40E_PTT_UNUSED_ENTRY(77),
335 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
336 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
337 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
339 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
340 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
341 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
342 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
343 I40E_PTT_UNUSED_ENTRY(84),
344 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
345 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
346 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
348 /* Non Tunneled IPv6 */
349 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
350 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
351 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
352 I40E_PTT_UNUSED_ENTRY(91),
353 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
354 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
355 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
358 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(98),
362 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
367 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(105),
371 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
375 /* IPv6 --> GRE/NAT */
376 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
378 /* IPv6 --> GRE/NAT -> IPv4 */
379 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(113),
383 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
387 /* IPv6 --> GRE/NAT -> IPv6 */
388 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(120),
392 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
396 /* IPv6 --> GRE/NAT -> MAC */
397 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
399 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
400 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(128),
404 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
408 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
409 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(135),
413 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
417 /* IPv6 --> GRE/NAT -> MAC/VLAN */
418 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
420 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
421 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
422 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
423 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
424 I40E_PTT_UNUSED_ENTRY(143),
425 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
426 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
427 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
429 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
430 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
431 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
432 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
433 I40E_PTT_UNUSED_ENTRY(150),
434 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
435 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
436 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
439 I40E_PTT_UNUSED_ENTRY(154),
440 I40E_PTT_UNUSED_ENTRY(155),
441 I40E_PTT_UNUSED_ENTRY(156),
442 I40E_PTT_UNUSED_ENTRY(157),
443 I40E_PTT_UNUSED_ENTRY(158),
444 I40E_PTT_UNUSED_ENTRY(159),
446 I40E_PTT_UNUSED_ENTRY(160),
447 I40E_PTT_UNUSED_ENTRY(161),
448 I40E_PTT_UNUSED_ENTRY(162),
449 I40E_PTT_UNUSED_ENTRY(163),
450 I40E_PTT_UNUSED_ENTRY(164),
451 I40E_PTT_UNUSED_ENTRY(165),
452 I40E_PTT_UNUSED_ENTRY(166),
453 I40E_PTT_UNUSED_ENTRY(167),
454 I40E_PTT_UNUSED_ENTRY(168),
455 I40E_PTT_UNUSED_ENTRY(169),
457 I40E_PTT_UNUSED_ENTRY(170),
458 I40E_PTT_UNUSED_ENTRY(171),
459 I40E_PTT_UNUSED_ENTRY(172),
460 I40E_PTT_UNUSED_ENTRY(173),
461 I40E_PTT_UNUSED_ENTRY(174),
462 I40E_PTT_UNUSED_ENTRY(175),
463 I40E_PTT_UNUSED_ENTRY(176),
464 I40E_PTT_UNUSED_ENTRY(177),
465 I40E_PTT_UNUSED_ENTRY(178),
466 I40E_PTT_UNUSED_ENTRY(179),
468 I40E_PTT_UNUSED_ENTRY(180),
469 I40E_PTT_UNUSED_ENTRY(181),
470 I40E_PTT_UNUSED_ENTRY(182),
471 I40E_PTT_UNUSED_ENTRY(183),
472 I40E_PTT_UNUSED_ENTRY(184),
473 I40E_PTT_UNUSED_ENTRY(185),
474 I40E_PTT_UNUSED_ENTRY(186),
475 I40E_PTT_UNUSED_ENTRY(187),
476 I40E_PTT_UNUSED_ENTRY(188),
477 I40E_PTT_UNUSED_ENTRY(189),
479 I40E_PTT_UNUSED_ENTRY(190),
480 I40E_PTT_UNUSED_ENTRY(191),
481 I40E_PTT_UNUSED_ENTRY(192),
482 I40E_PTT_UNUSED_ENTRY(193),
483 I40E_PTT_UNUSED_ENTRY(194),
484 I40E_PTT_UNUSED_ENTRY(195),
485 I40E_PTT_UNUSED_ENTRY(196),
486 I40E_PTT_UNUSED_ENTRY(197),
487 I40E_PTT_UNUSED_ENTRY(198),
488 I40E_PTT_UNUSED_ENTRY(199),
490 I40E_PTT_UNUSED_ENTRY(200),
491 I40E_PTT_UNUSED_ENTRY(201),
492 I40E_PTT_UNUSED_ENTRY(202),
493 I40E_PTT_UNUSED_ENTRY(203),
494 I40E_PTT_UNUSED_ENTRY(204),
495 I40E_PTT_UNUSED_ENTRY(205),
496 I40E_PTT_UNUSED_ENTRY(206),
497 I40E_PTT_UNUSED_ENTRY(207),
498 I40E_PTT_UNUSED_ENTRY(208),
499 I40E_PTT_UNUSED_ENTRY(209),
501 I40E_PTT_UNUSED_ENTRY(210),
502 I40E_PTT_UNUSED_ENTRY(211),
503 I40E_PTT_UNUSED_ENTRY(212),
504 I40E_PTT_UNUSED_ENTRY(213),
505 I40E_PTT_UNUSED_ENTRY(214),
506 I40E_PTT_UNUSED_ENTRY(215),
507 I40E_PTT_UNUSED_ENTRY(216),
508 I40E_PTT_UNUSED_ENTRY(217),
509 I40E_PTT_UNUSED_ENTRY(218),
510 I40E_PTT_UNUSED_ENTRY(219),
512 I40E_PTT_UNUSED_ENTRY(220),
513 I40E_PTT_UNUSED_ENTRY(221),
514 I40E_PTT_UNUSED_ENTRY(222),
515 I40E_PTT_UNUSED_ENTRY(223),
516 I40E_PTT_UNUSED_ENTRY(224),
517 I40E_PTT_UNUSED_ENTRY(225),
518 I40E_PTT_UNUSED_ENTRY(226),
519 I40E_PTT_UNUSED_ENTRY(227),
520 I40E_PTT_UNUSED_ENTRY(228),
521 I40E_PTT_UNUSED_ENTRY(229),
523 I40E_PTT_UNUSED_ENTRY(230),
524 I40E_PTT_UNUSED_ENTRY(231),
525 I40E_PTT_UNUSED_ENTRY(232),
526 I40E_PTT_UNUSED_ENTRY(233),
527 I40E_PTT_UNUSED_ENTRY(234),
528 I40E_PTT_UNUSED_ENTRY(235),
529 I40E_PTT_UNUSED_ENTRY(236),
530 I40E_PTT_UNUSED_ENTRY(237),
531 I40E_PTT_UNUSED_ENTRY(238),
532 I40E_PTT_UNUSED_ENTRY(239),
534 I40E_PTT_UNUSED_ENTRY(240),
535 I40E_PTT_UNUSED_ENTRY(241),
536 I40E_PTT_UNUSED_ENTRY(242),
537 I40E_PTT_UNUSED_ENTRY(243),
538 I40E_PTT_UNUSED_ENTRY(244),
539 I40E_PTT_UNUSED_ENTRY(245),
540 I40E_PTT_UNUSED_ENTRY(246),
541 I40E_PTT_UNUSED_ENTRY(247),
542 I40E_PTT_UNUSED_ENTRY(248),
543 I40E_PTT_UNUSED_ENTRY(249),
545 I40E_PTT_UNUSED_ENTRY(250),
546 I40E_PTT_UNUSED_ENTRY(251),
547 I40E_PTT_UNUSED_ENTRY(252),
548 I40E_PTT_UNUSED_ENTRY(253),
549 I40E_PTT_UNUSED_ENTRY(254),
550 I40E_PTT_UNUSED_ENTRY(255)
555 * i40e_validate_mac_addr - Validate unicast MAC address
556 * @mac_addr: pointer to MAC address
558 * Tests a MAC address to ensure it is a valid Individual Address
560 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
562 enum i40e_status_code status = I40E_SUCCESS;
564 DEBUGFUNC("i40e_validate_mac_addr");
566 /* Broadcast addresses ARE multicast addresses
567 * Make sure it is not a multicast address
568 * Reject the zero address
570 if (I40E_IS_MULTICAST(mac_addr) ||
571 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
572 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
573 status = I40E_ERR_INVALID_MAC_ADDR;
579 * i40e_init_shared_code - Initialize the shared code
580 * @hw: pointer to hardware structure
582 * This assigns the MAC type and PHY code and inits the NVM.
583 * Does not touch the hardware. This function must be called prior to any
584 * other function in the shared code. The i40e_hw structure should be
585 * memset to 0 prior to calling this function. The following fields in
586 * hw structure should be filled in prior to calling this function:
587 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
588 * subsystem_vendor_id, and revision_id
590 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
592 enum i40e_status_code status = I40E_SUCCESS;
593 u32 port, ari, func_rid;
595 DEBUGFUNC("i40e_init_shared_code");
597 i40e_set_mac_type(hw);
599 switch (hw->mac.type) {
603 return I40E_ERR_DEVICE_NOT_SUPPORTED;
606 hw->phy.get_link_info = TRUE;
608 /* Determine port number and PF number*/
609 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
610 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
612 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
613 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
614 func_rid = rd32(hw, I40E_PF_FUNC_RID);
616 hw->pf_id = (u8)(func_rid & 0xff);
618 hw->pf_id = (u8)(func_rid & 0x7);
620 status = i40e_init_nvm(hw);
625 * i40e_aq_mac_address_read - Retrieve the MAC addresses
626 * @hw: pointer to the hw struct
627 * @flags: a return indicator of what addresses were added to the addr store
628 * @addrs: the requestor's mac addr store
629 * @cmd_details: pointer to command details structure or NULL
631 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
633 struct i40e_aqc_mac_address_read_data *addrs,
634 struct i40e_asq_cmd_details *cmd_details)
636 struct i40e_aq_desc desc;
637 struct i40e_aqc_mac_address_read *cmd_data =
638 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
639 enum i40e_status_code status;
641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
642 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
644 status = i40e_asq_send_command(hw, &desc, addrs,
645 sizeof(*addrs), cmd_details);
646 *flags = LE16_TO_CPU(cmd_data->command_flags);
652 * i40e_aq_mac_address_write - Change the MAC addresses
653 * @hw: pointer to the hw struct
654 * @flags: indicates which MAC to be written
655 * @mac_addr: address to write
656 * @cmd_details: pointer to command details structure or NULL
658 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
659 u16 flags, u8 *mac_addr,
660 struct i40e_asq_cmd_details *cmd_details)
662 struct i40e_aq_desc desc;
663 struct i40e_aqc_mac_address_write *cmd_data =
664 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
665 enum i40e_status_code status;
667 i40e_fill_default_direct_cmd_desc(&desc,
668 i40e_aqc_opc_mac_address_write);
669 cmd_data->command_flags = CPU_TO_LE16(flags);
670 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
671 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
672 ((u32)mac_addr[3] << 16) |
673 ((u32)mac_addr[4] << 8) |
676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
682 * i40e_get_mac_addr - get MAC address
683 * @hw: pointer to the HW structure
684 * @mac_addr: pointer to MAC address
686 * Reads the adapter's MAC address from register
688 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
690 struct i40e_aqc_mac_address_read_data addrs;
691 enum i40e_status_code status;
694 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
696 if (flags & I40E_AQC_LAN_ADDR_VALID)
697 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
703 * i40e_get_port_mac_addr - get Port MAC address
704 * @hw: pointer to the HW structure
705 * @mac_addr: pointer to Port MAC address
707 * Reads the adapter's Port MAC address
709 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
711 struct i40e_aqc_mac_address_read_data addrs;
712 enum i40e_status_code status;
715 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
719 if (flags & I40E_AQC_PORT_ADDR_VALID)
720 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
722 status = I40E_ERR_INVALID_MAC_ADDR;
728 * i40e_pre_tx_queue_cfg - pre tx queue configure
729 * @hw: pointer to the HW structure
730 * @queue: target pf queue index
731 * @enable: state change request
733 * Handles hw requirement to indicate intention to enable
734 * or disable target queue.
736 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
738 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
742 if (abs_queue_idx >= 128) {
743 reg_block = abs_queue_idx / 128;
744 abs_queue_idx %= 128;
747 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
748 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
749 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
752 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
754 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
756 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
760 * i40e_read_pba_string - Reads part number string from EEPROM
761 * @hw: pointer to hardware structure
762 * @pba_num: stores the part number string from the EEPROM
763 * @pba_num_size: part number string buffer length
765 * Reads the part number string from the EEPROM.
767 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
770 enum i40e_status_code status = I40E_SUCCESS;
776 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
777 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
778 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
782 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
783 if (status != I40E_SUCCESS) {
784 DEBUGOUT("Failed to read PBA Block pointer.\n");
788 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
789 if (status != I40E_SUCCESS) {
790 DEBUGOUT("Failed to read PBA Block size.\n");
794 /* Subtract one to get PBA word count (PBA Size word is included in
798 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
799 DEBUGOUT("Buffer to small for PBA data.\n");
800 return I40E_ERR_PARAM;
803 for (i = 0; i < pba_size; i++) {
804 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
805 if (status != I40E_SUCCESS) {
806 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
810 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
811 pba_num[(i * 2) + 1] = pba_word & 0xFF;
813 pba_num[(pba_size * 2)] = '\0';
819 * i40e_get_media_type - Gets media type
820 * @hw: pointer to the hardware structure
822 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
824 enum i40e_media_type media;
826 switch (hw->phy.link_info.phy_type) {
827 case I40E_PHY_TYPE_10GBASE_SR:
828 case I40E_PHY_TYPE_10GBASE_LR:
829 case I40E_PHY_TYPE_1000BASE_SX:
830 case I40E_PHY_TYPE_1000BASE_LX:
831 case I40E_PHY_TYPE_40GBASE_SR4:
832 case I40E_PHY_TYPE_40GBASE_LR4:
833 media = I40E_MEDIA_TYPE_FIBER;
835 case I40E_PHY_TYPE_100BASE_TX:
836 case I40E_PHY_TYPE_1000BASE_T:
837 case I40E_PHY_TYPE_10GBASE_T:
838 media = I40E_MEDIA_TYPE_BASET;
840 case I40E_PHY_TYPE_10GBASE_CR1_CU:
841 case I40E_PHY_TYPE_40GBASE_CR4_CU:
842 case I40E_PHY_TYPE_10GBASE_CR1:
843 case I40E_PHY_TYPE_40GBASE_CR4:
844 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
845 case I40E_PHY_TYPE_40GBASE_AOC:
846 case I40E_PHY_TYPE_10GBASE_AOC:
847 media = I40E_MEDIA_TYPE_DA;
849 case I40E_PHY_TYPE_1000BASE_KX:
850 case I40E_PHY_TYPE_10GBASE_KX4:
851 case I40E_PHY_TYPE_10GBASE_KR:
852 case I40E_PHY_TYPE_40GBASE_KR4:
853 case I40E_PHY_TYPE_20GBASE_KR2:
854 media = I40E_MEDIA_TYPE_BACKPLANE;
856 case I40E_PHY_TYPE_SGMII:
857 case I40E_PHY_TYPE_XAUI:
858 case I40E_PHY_TYPE_XFI:
859 case I40E_PHY_TYPE_XLAUI:
860 case I40E_PHY_TYPE_XLPPI:
862 media = I40E_MEDIA_TYPE_UNKNOWN;
869 #define I40E_PF_RESET_WAIT_COUNT 110
871 * i40e_pf_reset - Reset the PF
872 * @hw: pointer to the hardware structure
874 * Assuming someone else has triggered a global reset,
875 * assure the global reset is complete and then reset the PF
877 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
884 /* Poll for Global Reset steady state in case of recent GRST.
885 * The grst delay value is in 100ms units, and we'll wait a
886 * couple counts longer to be sure we don't just miss the end.
888 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
889 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
890 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
891 for (cnt = 0; cnt < grst_del + 2; cnt++) {
892 reg = rd32(hw, I40E_GLGEN_RSTAT);
893 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
895 i40e_msec_delay(100);
897 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
898 DEBUGOUT("Global reset polling failed to complete.\n");
899 return I40E_ERR_RESET_FAILED;
902 /* Now Wait for the FW to be ready */
903 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
904 reg = rd32(hw, I40E_GLNVM_ULD);
905 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
906 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
907 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
908 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
909 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
914 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
915 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
916 DEBUGOUT("wait for FW Reset complete timedout\n");
917 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
918 return I40E_ERR_RESET_FAILED;
921 /* If there was a Global Reset in progress when we got here,
922 * we don't need to do the PF Reset
925 reg = rd32(hw, I40E_PFGEN_CTRL);
926 wr32(hw, I40E_PFGEN_CTRL,
927 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
928 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
929 reg = rd32(hw, I40E_PFGEN_CTRL);
930 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
934 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
935 DEBUGOUT("PF reset polling failed to complete.\n");
936 return I40E_ERR_RESET_FAILED;
940 i40e_clear_pxe_mode(hw);
947 * i40e_clear_hw - clear out any left over hw state
948 * @hw: pointer to the hw struct
950 * Clear queues and interrupts, typically called at init time,
951 * but after the capabilities have been found so we know how many
952 * queues and msix vectors have been allocated.
954 void i40e_clear_hw(struct i40e_hw *hw)
956 u32 num_queues, base_queue;
964 /* get number of interrupts, queues, and vfs */
965 val = rd32(hw, I40E_GLPCI_CNF2);
966 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
967 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
968 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
969 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
971 val = rd32(hw, I40E_PFLAN_QALLOC);
972 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
973 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
974 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
975 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
976 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
977 num_queues = (j - base_queue) + 1;
981 val = rd32(hw, I40E_PF_VT_PFALLOC);
982 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
983 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
984 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
985 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
986 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
987 num_vfs = (j - i) + 1;
991 /* stop all the interrupts */
992 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
993 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
994 for (i = 0; i < num_pf_int - 2; i++)
995 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
997 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
998 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
999 wr32(hw, I40E_PFINT_LNKLST0, val);
1000 for (i = 0; i < num_pf_int - 2; i++)
1001 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1002 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1003 for (i = 0; i < num_vfs; i++)
1004 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1005 for (i = 0; i < num_vf_int - 2; i++)
1006 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1008 /* warn the HW of the coming Tx disables */
1009 for (i = 0; i < num_queues; i++) {
1010 u32 abs_queue_idx = base_queue + i;
1013 if (abs_queue_idx >= 128) {
1014 reg_block = abs_queue_idx / 128;
1015 abs_queue_idx %= 128;
1018 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1019 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1020 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1021 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1023 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1025 i40e_usec_delay(400);
1027 /* stop all the queues */
1028 for (i = 0; i < num_queues; i++) {
1029 wr32(hw, I40E_QINT_TQCTL(i), 0);
1030 wr32(hw, I40E_QTX_ENA(i), 0);
1031 wr32(hw, I40E_QINT_RQCTL(i), 0);
1032 wr32(hw, I40E_QRX_ENA(i), 0);
1035 /* short wait for all queue disables to settle */
1036 i40e_usec_delay(50);
1040 * i40e_clear_pxe_mode - clear pxe operations mode
1041 * @hw: pointer to the hw struct
1043 * Make sure all PXE mode settings are cleared, including things
1044 * like descriptor fetch/write-back mode.
1046 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1048 if (i40e_check_asq_alive(hw))
1049 i40e_aq_clear_pxe_mode(hw, NULL);
1053 * i40e_led_is_mine - helper to find matching led
1054 * @hw: pointer to the hw struct
1055 * @idx: index into GPIO registers
1057 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1059 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1064 if (!hw->func_caps.led[idx])
1067 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1068 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1069 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1071 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1072 * if it is not our port then ignore
1074 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1081 #define I40E_COMBINED_ACTIVITY 0xA
1082 #define I40E_FILTER_ACTIVITY 0xE
1083 #define I40E_LINK_ACTIVITY 0xC
1084 #define I40E_MAC_ACTIVITY 0xD
1085 #define I40E_LED0 22
1088 * i40e_led_get - return current on/off mode
1089 * @hw: pointer to the hw struct
1091 * The value returned is the 'mode' field as defined in the
1092 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1093 * values are variations of possible behaviors relating to
1094 * blink, link, and wire.
1096 u32 i40e_led_get(struct i40e_hw *hw)
1098 u32 current_mode = 0;
1102 /* as per the documentation GPIO 22-29 are the LED
1103 * GPIO pins named LED0..LED7
1105 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1106 u32 gpio_val = i40e_led_is_mine(hw, i);
1111 /* ignore gpio LED src mode entries related to the activity
1114 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1115 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1116 switch (current_mode) {
1117 case I40E_COMBINED_ACTIVITY:
1118 case I40E_FILTER_ACTIVITY:
1119 case I40E_MAC_ACTIVITY:
1125 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1126 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1134 * i40e_led_set - set new on/off mode
1135 * @hw: pointer to the hw struct
1136 * @mode: 0=off, 0xf=on (else see manual for mode details)
1137 * @blink: TRUE if the LED should blink when on, FALSE if steady
1139 * if this function is used to turn on the blink it should
1140 * be used to disable the blink when restoring the original state.
1142 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1144 u32 current_mode = 0;
1147 if (mode & 0xfffffff0)
1148 DEBUGOUT1("invalid mode passed in %X\n", mode);
1150 /* as per the documentation GPIO 22-29 are the LED
1151 * GPIO pins named LED0..LED7
1153 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1154 u32 gpio_val = i40e_led_is_mine(hw, i);
1159 /* ignore gpio LED src mode entries related to the activity
1162 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1163 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1164 switch (current_mode) {
1165 case I40E_COMBINED_ACTIVITY:
1166 case I40E_FILTER_ACTIVITY:
1167 case I40E_MAC_ACTIVITY:
1173 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1174 /* this & is a bit of paranoia, but serves as a range check */
1175 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1176 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1178 if (mode == I40E_LINK_ACTIVITY)
1182 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1184 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1186 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1191 /* Admin command wrappers */
1194 * i40e_aq_get_phy_capabilities
1195 * @hw: pointer to the hw struct
1196 * @abilities: structure for PHY capabilities to be filled
1197 * @qualified_modules: report Qualified Modules
1198 * @report_init: report init capabilities (active are default)
1199 * @cmd_details: pointer to command details structure or NULL
1201 * Returns the various PHY abilities supported on the Port.
1203 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1204 bool qualified_modules, bool report_init,
1205 struct i40e_aq_get_phy_abilities_resp *abilities,
1206 struct i40e_asq_cmd_details *cmd_details)
1208 struct i40e_aq_desc desc;
1209 enum i40e_status_code status;
1210 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1213 return I40E_ERR_PARAM;
1215 i40e_fill_default_direct_cmd_desc(&desc,
1216 i40e_aqc_opc_get_phy_abilities);
1218 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1219 if (abilities_size > I40E_AQ_LARGE_BUF)
1220 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1222 if (qualified_modules)
1223 desc.params.external.param0 |=
1224 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1227 desc.params.external.param0 |=
1228 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1230 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1233 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1234 status = I40E_ERR_UNKNOWN_PHY;
1240 * i40e_aq_set_phy_config
1241 * @hw: pointer to the hw struct
1242 * @config: structure with PHY configuration to be set
1243 * @cmd_details: pointer to command details structure or NULL
1245 * Set the various PHY configuration parameters
1246 * supported on the Port.One or more of the Set PHY config parameters may be
1247 * ignored in an MFP mode as the PF may not have the privilege to set some
1248 * of the PHY Config parameters. This status will be indicated by the
1251 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1252 struct i40e_aq_set_phy_config *config,
1253 struct i40e_asq_cmd_details *cmd_details)
1255 struct i40e_aq_desc desc;
1256 struct i40e_aq_set_phy_config *cmd =
1257 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1258 enum i40e_status_code status;
1261 return I40E_ERR_PARAM;
1263 i40e_fill_default_direct_cmd_desc(&desc,
1264 i40e_aqc_opc_set_phy_config);
1268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1275 * @hw: pointer to the hw struct
1277 * Set the requested flow control mode using set_phy_config.
1279 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1280 bool atomic_restart)
1282 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1283 struct i40e_aq_get_phy_abilities_resp abilities;
1284 struct i40e_aq_set_phy_config config;
1285 enum i40e_status_code status;
1286 u8 pause_mask = 0x0;
1292 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1293 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1295 case I40E_FC_RX_PAUSE:
1296 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1298 case I40E_FC_TX_PAUSE:
1299 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1305 /* Get the current phy config */
1306 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1309 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1313 memset(&config, 0, sizeof(config));
1314 /* clear the old pause settings */
1315 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1316 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1317 /* set the new abilities */
1318 config.abilities |= pause_mask;
1319 /* If the abilities have changed, then set the new config */
1320 if (config.abilities != abilities.abilities) {
1321 /* Auto restart link so settings take effect */
1323 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1324 /* Copy over all the old settings */
1325 config.phy_type = abilities.phy_type;
1326 config.link_speed = abilities.link_speed;
1327 config.eee_capability = abilities.eee_capability;
1328 config.eeer = abilities.eeer_val;
1329 config.low_power_ctrl = abilities.d3_lpan;
1330 status = i40e_aq_set_phy_config(hw, &config, NULL);
1333 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1335 /* Update the link info */
1336 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1338 /* Wait a little bit (on 40G cards it sometimes takes a really
1339 * long time for link to come back from the atomic reset)
1342 i40e_msec_delay(1000);
1343 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1346 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1352 * i40e_aq_set_mac_config
1353 * @hw: pointer to the hw struct
1354 * @max_frame_size: Maximum Frame Size to be supported by the port
1355 * @crc_en: Tell HW to append a CRC to outgoing frames
1356 * @pacing: Pacing configurations
1357 * @cmd_details: pointer to command details structure or NULL
1359 * Configure MAC settings for frame size, jumbo frame support and the
1360 * addition of a CRC by the hardware.
1362 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1364 bool crc_en, u16 pacing,
1365 struct i40e_asq_cmd_details *cmd_details)
1367 struct i40e_aq_desc desc;
1368 struct i40e_aq_set_mac_config *cmd =
1369 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1370 enum i40e_status_code status;
1372 if (max_frame_size == 0)
1373 return I40E_ERR_PARAM;
1375 i40e_fill_default_direct_cmd_desc(&desc,
1376 i40e_aqc_opc_set_mac_config);
1378 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1379 cmd->params = ((u8)pacing & 0x0F) << 3;
1381 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1383 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1389 * i40e_aq_clear_pxe_mode
1390 * @hw: pointer to the hw struct
1391 * @cmd_details: pointer to command details structure or NULL
1393 * Tell the firmware that the driver is taking over from PXE
1395 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1396 struct i40e_asq_cmd_details *cmd_details)
1398 enum i40e_status_code status;
1399 struct i40e_aq_desc desc;
1400 struct i40e_aqc_clear_pxe *cmd =
1401 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1403 i40e_fill_default_direct_cmd_desc(&desc,
1404 i40e_aqc_opc_clear_pxe_mode);
1408 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1410 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1416 * i40e_aq_set_link_restart_an
1417 * @hw: pointer to the hw struct
1418 * @enable_link: if TRUE: enable link, if FALSE: disable link
1419 * @cmd_details: pointer to command details structure or NULL
1421 * Sets up the link and restarts the Auto-Negotiation over the link.
1423 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1424 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1426 struct i40e_aq_desc desc;
1427 struct i40e_aqc_set_link_restart_an *cmd =
1428 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1429 enum i40e_status_code status;
1431 i40e_fill_default_direct_cmd_desc(&desc,
1432 i40e_aqc_opc_set_link_restart_an);
1434 cmd->command = I40E_AQ_PHY_RESTART_AN;
1436 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1438 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1440 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1446 * i40e_aq_get_link_info
1447 * @hw: pointer to the hw struct
1448 * @enable_lse: enable/disable LinkStatusEvent reporting
1449 * @link: pointer to link status structure - optional
1450 * @cmd_details: pointer to command details structure or NULL
1452 * Returns the link status of the adapter.
1454 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1455 bool enable_lse, struct i40e_link_status *link,
1456 struct i40e_asq_cmd_details *cmd_details)
1458 struct i40e_aq_desc desc;
1459 struct i40e_aqc_get_link_status *resp =
1460 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1461 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1462 enum i40e_status_code status;
1463 bool tx_pause, rx_pause;
1466 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1469 command_flags = I40E_AQ_LSE_ENABLE;
1471 command_flags = I40E_AQ_LSE_DISABLE;
1472 resp->command_flags = CPU_TO_LE16(command_flags);
1474 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1476 if (status != I40E_SUCCESS)
1477 goto aq_get_link_info_exit;
1479 /* save off old link status information */
1480 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1481 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1483 /* update link status */
1484 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1485 hw->phy.media_type = i40e_get_media_type(hw);
1486 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1487 hw_link_info->link_info = resp->link_info;
1488 hw_link_info->an_info = resp->an_info;
1489 hw_link_info->ext_info = resp->ext_info;
1490 hw_link_info->loopback = resp->loopback;
1491 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1492 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1494 /* update fc info */
1495 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1496 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1497 if (tx_pause & rx_pause)
1498 hw->fc.current_mode = I40E_FC_FULL;
1500 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1502 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1504 hw->fc.current_mode = I40E_FC_NONE;
1506 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1507 hw_link_info->crc_enable = TRUE;
1509 hw_link_info->crc_enable = FALSE;
1511 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1512 hw_link_info->lse_enable = TRUE;
1514 hw_link_info->lse_enable = FALSE;
1516 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1517 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1518 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1520 /* save link status information */
1522 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1523 I40E_NONDMA_TO_NONDMA);
1525 /* flag cleared so helper functions don't call AQ again */
1526 hw->phy.get_link_info = FALSE;
1528 aq_get_link_info_exit:
1533 * i40e_aq_set_phy_int_mask
1534 * @hw: pointer to the hw struct
1535 * @mask: interrupt mask to be set
1536 * @cmd_details: pointer to command details structure or NULL
1538 * Set link interrupt mask.
1540 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1542 struct i40e_asq_cmd_details *cmd_details)
1544 struct i40e_aq_desc desc;
1545 struct i40e_aqc_set_phy_int_mask *cmd =
1546 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1547 enum i40e_status_code status;
1549 i40e_fill_default_direct_cmd_desc(&desc,
1550 i40e_aqc_opc_set_phy_int_mask);
1552 cmd->event_mask = CPU_TO_LE16(mask);
1554 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1560 * i40e_aq_get_local_advt_reg
1561 * @hw: pointer to the hw struct
1562 * @advt_reg: local AN advertisement register value
1563 * @cmd_details: pointer to command details structure or NULL
1565 * Get the Local AN advertisement register value.
1567 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1569 struct i40e_asq_cmd_details *cmd_details)
1571 struct i40e_aq_desc desc;
1572 struct i40e_aqc_an_advt_reg *resp =
1573 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1574 enum i40e_status_code status;
1576 i40e_fill_default_direct_cmd_desc(&desc,
1577 i40e_aqc_opc_get_local_advt_reg);
1579 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1581 if (status != I40E_SUCCESS)
1582 goto aq_get_local_advt_reg_exit;
1584 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1585 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1587 aq_get_local_advt_reg_exit:
1592 * i40e_aq_set_local_advt_reg
1593 * @hw: pointer to the hw struct
1594 * @advt_reg: local AN advertisement register value
1595 * @cmd_details: pointer to command details structure or NULL
1597 * Get the Local AN advertisement register value.
1599 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1601 struct i40e_asq_cmd_details *cmd_details)
1603 struct i40e_aq_desc desc;
1604 struct i40e_aqc_an_advt_reg *cmd =
1605 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1606 enum i40e_status_code status;
1608 i40e_fill_default_direct_cmd_desc(&desc,
1609 i40e_aqc_opc_get_local_advt_reg);
1611 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1612 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1614 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1620 * i40e_aq_get_partner_advt
1621 * @hw: pointer to the hw struct
1622 * @advt_reg: AN partner advertisement register value
1623 * @cmd_details: pointer to command details structure or NULL
1625 * Get the link partner AN advertisement register value.
1627 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1629 struct i40e_asq_cmd_details *cmd_details)
1631 struct i40e_aq_desc desc;
1632 struct i40e_aqc_an_advt_reg *resp =
1633 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1634 enum i40e_status_code status;
1636 i40e_fill_default_direct_cmd_desc(&desc,
1637 i40e_aqc_opc_get_partner_advt);
1639 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1641 if (status != I40E_SUCCESS)
1642 goto aq_get_partner_advt_exit;
1644 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1645 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1647 aq_get_partner_advt_exit:
1652 * i40e_aq_set_lb_modes
1653 * @hw: pointer to the hw struct
1654 * @lb_modes: loopback mode to be set
1655 * @cmd_details: pointer to command details structure or NULL
1657 * Sets loopback modes.
1659 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1661 struct i40e_asq_cmd_details *cmd_details)
1663 struct i40e_aq_desc desc;
1664 struct i40e_aqc_set_lb_mode *cmd =
1665 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1666 enum i40e_status_code status;
1668 i40e_fill_default_direct_cmd_desc(&desc,
1669 i40e_aqc_opc_set_lb_modes);
1671 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1673 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1679 * i40e_aq_set_phy_debug
1680 * @hw: pointer to the hw struct
1681 * @cmd_flags: debug command flags
1682 * @cmd_details: pointer to command details structure or NULL
1684 * Reset the external PHY.
1686 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1687 struct i40e_asq_cmd_details *cmd_details)
1689 struct i40e_aq_desc desc;
1690 struct i40e_aqc_set_phy_debug *cmd =
1691 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1692 enum i40e_status_code status;
1694 i40e_fill_default_direct_cmd_desc(&desc,
1695 i40e_aqc_opc_set_phy_debug);
1697 cmd->command_flags = cmd_flags;
1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1706 * @hw: pointer to the hw struct
1707 * @vsi_ctx: pointer to a vsi context struct
1708 * @cmd_details: pointer to command details structure or NULL
1710 * Add a VSI context to the hardware.
1712 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1713 struct i40e_vsi_context *vsi_ctx,
1714 struct i40e_asq_cmd_details *cmd_details)
1716 struct i40e_aq_desc desc;
1717 struct i40e_aqc_add_get_update_vsi *cmd =
1718 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1719 struct i40e_aqc_add_get_update_vsi_completion *resp =
1720 (struct i40e_aqc_add_get_update_vsi_completion *)
1722 enum i40e_status_code status;
1724 i40e_fill_default_direct_cmd_desc(&desc,
1725 i40e_aqc_opc_add_vsi);
1727 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1728 cmd->connection_type = vsi_ctx->connection_type;
1729 cmd->vf_id = vsi_ctx->vf_num;
1730 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1732 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1734 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1735 sizeof(vsi_ctx->info), cmd_details);
1737 if (status != I40E_SUCCESS)
1738 goto aq_add_vsi_exit;
1740 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1741 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1742 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1743 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1750 * i40e_aq_set_default_vsi
1751 * @hw: pointer to the hw struct
1753 * @cmd_details: pointer to command details structure or NULL
1755 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1757 struct i40e_asq_cmd_details *cmd_details)
1759 struct i40e_aq_desc desc;
1760 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1761 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1763 enum i40e_status_code status;
1765 i40e_fill_default_direct_cmd_desc(&desc,
1766 i40e_aqc_opc_set_vsi_promiscuous_modes);
1768 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1769 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1770 cmd->seid = CPU_TO_LE16(seid);
1772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1778 * i40e_aq_set_vsi_unicast_promiscuous
1779 * @hw: pointer to the hw struct
1781 * @set: set unicast promiscuous enable/disable
1782 * @cmd_details: pointer to command details structure or NULL
1784 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1786 struct i40e_asq_cmd_details *cmd_details)
1788 struct i40e_aq_desc desc;
1789 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1790 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1791 enum i40e_status_code status;
1794 i40e_fill_default_direct_cmd_desc(&desc,
1795 i40e_aqc_opc_set_vsi_promiscuous_modes);
1798 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1800 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1802 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1804 cmd->seid = CPU_TO_LE16(seid);
1805 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1811 * i40e_aq_set_vsi_multicast_promiscuous
1812 * @hw: pointer to the hw struct
1814 * @set: set multicast promiscuous enable/disable
1815 * @cmd_details: pointer to command details structure or NULL
1817 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1818 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1820 struct i40e_aq_desc desc;
1821 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1822 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1823 enum i40e_status_code status;
1826 i40e_fill_default_direct_cmd_desc(&desc,
1827 i40e_aqc_opc_set_vsi_promiscuous_modes);
1830 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1832 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1834 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1836 cmd->seid = CPU_TO_LE16(seid);
1837 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1843 * i40e_aq_set_vsi_broadcast
1844 * @hw: pointer to the hw struct
1846 * @set_filter: TRUE to set filter, FALSE to clear filter
1847 * @cmd_details: pointer to command details structure or NULL
1849 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1851 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1852 u16 seid, bool set_filter,
1853 struct i40e_asq_cmd_details *cmd_details)
1855 struct i40e_aq_desc desc;
1856 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1857 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1858 enum i40e_status_code status;
1860 i40e_fill_default_direct_cmd_desc(&desc,
1861 i40e_aqc_opc_set_vsi_promiscuous_modes);
1864 cmd->promiscuous_flags
1865 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1867 cmd->promiscuous_flags
1868 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1870 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1871 cmd->seid = CPU_TO_LE16(seid);
1872 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1878 * i40e_get_vsi_params - get VSI configuration info
1879 * @hw: pointer to the hw struct
1880 * @vsi_ctx: pointer to a vsi context struct
1881 * @cmd_details: pointer to command details structure or NULL
1883 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1884 struct i40e_vsi_context *vsi_ctx,
1885 struct i40e_asq_cmd_details *cmd_details)
1887 struct i40e_aq_desc desc;
1888 struct i40e_aqc_add_get_update_vsi *cmd =
1889 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1890 struct i40e_aqc_add_get_update_vsi_completion *resp =
1891 (struct i40e_aqc_add_get_update_vsi_completion *)
1893 enum i40e_status_code status;
1895 i40e_fill_default_direct_cmd_desc(&desc,
1896 i40e_aqc_opc_get_vsi_parameters);
1898 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1900 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1902 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1903 sizeof(vsi_ctx->info), NULL);
1905 if (status != I40E_SUCCESS)
1906 goto aq_get_vsi_params_exit;
1908 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1909 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1910 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1911 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1913 aq_get_vsi_params_exit:
1918 * i40e_aq_update_vsi_params
1919 * @hw: pointer to the hw struct
1920 * @vsi_ctx: pointer to a vsi context struct
1921 * @cmd_details: pointer to command details structure or NULL
1923 * Update a VSI context.
1925 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1926 struct i40e_vsi_context *vsi_ctx,
1927 struct i40e_asq_cmd_details *cmd_details)
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_add_get_update_vsi *cmd =
1931 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1932 enum i40e_status_code status;
1934 i40e_fill_default_direct_cmd_desc(&desc,
1935 i40e_aqc_opc_update_vsi_parameters);
1936 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1938 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1940 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1941 sizeof(vsi_ctx->info), cmd_details);
1947 * i40e_aq_get_switch_config
1948 * @hw: pointer to the hardware structure
1949 * @buf: pointer to the result buffer
1950 * @buf_size: length of input buffer
1951 * @start_seid: seid to start for the report, 0 == beginning
1952 * @cmd_details: pointer to command details structure or NULL
1954 * Fill the buf with switch configuration returned from AdminQ command
1956 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1957 struct i40e_aqc_get_switch_config_resp *buf,
1958 u16 buf_size, u16 *start_seid,
1959 struct i40e_asq_cmd_details *cmd_details)
1961 struct i40e_aq_desc desc;
1962 struct i40e_aqc_switch_seid *scfg =
1963 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1964 enum i40e_status_code status;
1966 i40e_fill_default_direct_cmd_desc(&desc,
1967 i40e_aqc_opc_get_switch_config);
1968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1969 if (buf_size > I40E_AQ_LARGE_BUF)
1970 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1971 scfg->seid = CPU_TO_LE16(*start_seid);
1973 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1974 *start_seid = LE16_TO_CPU(scfg->seid);
1980 * i40e_aq_get_firmware_version
1981 * @hw: pointer to the hw struct
1982 * @fw_major_version: firmware major version
1983 * @fw_minor_version: firmware minor version
1984 * @fw_build: firmware build number
1985 * @api_major_version: major queue version
1986 * @api_minor_version: minor queue version
1987 * @cmd_details: pointer to command details structure or NULL
1989 * Get the firmware version from the admin queue commands
1991 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1992 u16 *fw_major_version, u16 *fw_minor_version,
1994 u16 *api_major_version, u16 *api_minor_version,
1995 struct i40e_asq_cmd_details *cmd_details)
1997 struct i40e_aq_desc desc;
1998 struct i40e_aqc_get_version *resp =
1999 (struct i40e_aqc_get_version *)&desc.params.raw;
2000 enum i40e_status_code status;
2002 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2006 if (status == I40E_SUCCESS) {
2007 if (fw_major_version != NULL)
2008 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2009 if (fw_minor_version != NULL)
2010 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2011 if (fw_build != NULL)
2012 *fw_build = LE32_TO_CPU(resp->fw_build);
2013 if (api_major_version != NULL)
2014 *api_major_version = LE16_TO_CPU(resp->api_major);
2015 if (api_minor_version != NULL)
2016 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2018 /* A workaround to fix the API version in SW */
2019 if (api_major_version && api_minor_version &&
2020 fw_major_version && fw_minor_version &&
2021 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2022 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2023 (*fw_major_version > 4)))
2024 *api_minor_version = 2;
2031 * i40e_aq_send_driver_version
2032 * @hw: pointer to the hw struct
2033 * @dv: driver's major, minor version
2034 * @cmd_details: pointer to command details structure or NULL
2036 * Send the driver version to the firmware
2038 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2039 struct i40e_driver_version *dv,
2040 struct i40e_asq_cmd_details *cmd_details)
2042 struct i40e_aq_desc desc;
2043 struct i40e_aqc_driver_version *cmd =
2044 (struct i40e_aqc_driver_version *)&desc.params.raw;
2045 enum i40e_status_code status;
2049 return I40E_ERR_PARAM;
2051 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2053 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2054 cmd->driver_major_ver = dv->major_version;
2055 cmd->driver_minor_ver = dv->minor_version;
2056 cmd->driver_build_ver = dv->build_version;
2057 cmd->driver_subbuild_ver = dv->subbuild_version;
2060 while (len < sizeof(dv->driver_string) &&
2061 (dv->driver_string[len] < 0x80) &&
2062 dv->driver_string[len])
2064 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2071 * i40e_get_link_status - get status of the HW network link
2072 * @hw: pointer to the hw struct
2074 * Returns TRUE if link is up, FALSE if link is down.
2076 * Side effect: LinkStatusEvent reporting becomes enabled
2078 bool i40e_get_link_status(struct i40e_hw *hw)
2080 enum i40e_status_code status = I40E_SUCCESS;
2081 bool link_status = FALSE;
2083 if (hw->phy.get_link_info) {
2084 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2086 if (status != I40E_SUCCESS)
2087 goto i40e_get_link_status_exit;
2090 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2092 i40e_get_link_status_exit:
2097 * i40e_get_link_speed
2098 * @hw: pointer to the hw struct
2100 * Returns the link speed of the adapter.
2102 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2104 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2105 enum i40e_status_code status = I40E_SUCCESS;
2107 if (hw->phy.get_link_info) {
2108 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2110 if (status != I40E_SUCCESS)
2111 goto i40e_link_speed_exit;
2114 speed = hw->phy.link_info.link_speed;
2116 i40e_link_speed_exit:
2121 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2122 * @hw: pointer to the hw struct
2123 * @uplink_seid: the MAC or other gizmo SEID
2124 * @downlink_seid: the VSI SEID
2125 * @enabled_tc: bitmap of TCs to be enabled
2126 * @default_port: TRUE for default port VSI, FALSE for control port
2127 * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support
2128 * @veb_seid: pointer to where to put the resulting VEB SEID
2129 * @cmd_details: pointer to command details structure or NULL
2131 * This asks the FW to add a VEB between the uplink and downlink
2132 * elements. If the uplink SEID is 0, this will be a floating VEB.
2134 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2135 u16 downlink_seid, u8 enabled_tc,
2136 bool default_port, bool enable_l2_filtering,
2138 struct i40e_asq_cmd_details *cmd_details)
2140 struct i40e_aq_desc desc;
2141 struct i40e_aqc_add_veb *cmd =
2142 (struct i40e_aqc_add_veb *)&desc.params.raw;
2143 struct i40e_aqc_add_veb_completion *resp =
2144 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2145 enum i40e_status_code status;
2148 /* SEIDs need to either both be set or both be 0 for floating VEB */
2149 if (!!uplink_seid != !!downlink_seid)
2150 return I40E_ERR_PARAM;
2152 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2154 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2155 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2156 cmd->enable_tcs = enabled_tc;
2158 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2160 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2162 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2164 if (enable_l2_filtering)
2165 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2167 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2171 if (!status && veb_seid)
2172 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2178 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2179 * @hw: pointer to the hw struct
2180 * @veb_seid: the SEID of the VEB to query
2181 * @switch_id: the uplink switch id
2182 * @floating: set to TRUE if the VEB is floating
2183 * @statistic_index: index of the stats counter block for this VEB
2184 * @vebs_used: number of VEB's used by function
2185 * @vebs_free: total VEB's not reserved by any function
2186 * @cmd_details: pointer to command details structure or NULL
2188 * This retrieves the parameters for a particular VEB, specified by
2189 * uplink_seid, and returns them to the caller.
2191 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2192 u16 veb_seid, u16 *switch_id,
2193 bool *floating, u16 *statistic_index,
2194 u16 *vebs_used, u16 *vebs_free,
2195 struct i40e_asq_cmd_details *cmd_details)
2197 struct i40e_aq_desc desc;
2198 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2199 (struct i40e_aqc_get_veb_parameters_completion *)
2201 enum i40e_status_code status;
2204 return I40E_ERR_PARAM;
2206 i40e_fill_default_direct_cmd_desc(&desc,
2207 i40e_aqc_opc_get_veb_parameters);
2208 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2215 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2216 if (statistic_index)
2217 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2219 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2221 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2223 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2224 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2235 * i40e_aq_add_macvlan
2236 * @hw: pointer to the hw struct
2237 * @seid: VSI for the mac address
2238 * @mv_list: list of macvlans to be added
2239 * @count: length of the list
2240 * @cmd_details: pointer to command details structure or NULL
2242 * Add MAC/VLAN addresses to the HW filtering
2244 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2245 struct i40e_aqc_add_macvlan_element_data *mv_list,
2246 u16 count, struct i40e_asq_cmd_details *cmd_details)
2248 struct i40e_aq_desc desc;
2249 struct i40e_aqc_macvlan *cmd =
2250 (struct i40e_aqc_macvlan *)&desc.params.raw;
2251 enum i40e_status_code status;
2254 if (count == 0 || !mv_list || !hw)
2255 return I40E_ERR_PARAM;
2257 buf_size = count * sizeof(*mv_list);
2259 /* prep the rest of the request */
2260 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2261 cmd->num_addresses = CPU_TO_LE16(count);
2262 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2266 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2267 if (buf_size > I40E_AQ_LARGE_BUF)
2268 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2270 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2277 * i40e_aq_remove_macvlan
2278 * @hw: pointer to the hw struct
2279 * @seid: VSI for the mac address
2280 * @mv_list: list of macvlans to be removed
2281 * @count: length of the list
2282 * @cmd_details: pointer to command details structure or NULL
2284 * Remove MAC/VLAN addresses from the HW filtering
2286 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2287 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2288 u16 count, struct i40e_asq_cmd_details *cmd_details)
2290 struct i40e_aq_desc desc;
2291 struct i40e_aqc_macvlan *cmd =
2292 (struct i40e_aqc_macvlan *)&desc.params.raw;
2293 enum i40e_status_code status;
2296 if (count == 0 || !mv_list || !hw)
2297 return I40E_ERR_PARAM;
2299 buf_size = count * sizeof(*mv_list);
2301 /* prep the rest of the request */
2302 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2303 cmd->num_addresses = CPU_TO_LE16(count);
2304 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2308 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2309 if (buf_size > I40E_AQ_LARGE_BUF)
2310 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2312 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2319 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2320 * @hw: pointer to the hw struct
2321 * @seid: VSI for the vlan filters
2322 * @v_list: list of vlan filters to be added
2323 * @count: length of the list
2324 * @cmd_details: pointer to command details structure or NULL
2326 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2327 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2328 u8 count, struct i40e_asq_cmd_details *cmd_details)
2330 struct i40e_aq_desc desc;
2331 struct i40e_aqc_macvlan *cmd =
2332 (struct i40e_aqc_macvlan *)&desc.params.raw;
2333 enum i40e_status_code status;
2336 if (count == 0 || !v_list || !hw)
2337 return I40E_ERR_PARAM;
2339 buf_size = count * sizeof(*v_list);
2341 /* prep the rest of the request */
2342 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2343 cmd->num_addresses = CPU_TO_LE16(count);
2344 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2348 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2349 if (buf_size > I40E_AQ_LARGE_BUF)
2350 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2352 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2359 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2360 * @hw: pointer to the hw struct
2361 * @seid: VSI for the vlan filters
2362 * @v_list: list of macvlans to be removed
2363 * @count: length of the list
2364 * @cmd_details: pointer to command details structure or NULL
2366 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2367 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2368 u8 count, struct i40e_asq_cmd_details *cmd_details)
2370 struct i40e_aq_desc desc;
2371 struct i40e_aqc_macvlan *cmd =
2372 (struct i40e_aqc_macvlan *)&desc.params.raw;
2373 enum i40e_status_code status;
2376 if (count == 0 || !v_list || !hw)
2377 return I40E_ERR_PARAM;
2379 buf_size = count * sizeof(*v_list);
2381 /* prep the rest of the request */
2382 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2383 cmd->num_addresses = CPU_TO_LE16(count);
2384 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2388 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2389 if (buf_size > I40E_AQ_LARGE_BUF)
2390 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2392 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2399 * i40e_aq_send_msg_to_vf
2400 * @hw: pointer to the hardware structure
2401 * @vfid: vf id to send msg
2402 * @v_opcode: opcodes for VF-PF communication
2403 * @v_retval: return error code
2404 * @msg: pointer to the msg buffer
2405 * @msglen: msg length
2406 * @cmd_details: pointer to command details
2410 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2411 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2412 struct i40e_asq_cmd_details *cmd_details)
2414 struct i40e_aq_desc desc;
2415 struct i40e_aqc_pf_vf_message *cmd =
2416 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2417 enum i40e_status_code status;
2419 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2420 cmd->id = CPU_TO_LE32(vfid);
2421 desc.cookie_high = CPU_TO_LE32(v_opcode);
2422 desc.cookie_low = CPU_TO_LE32(v_retval);
2423 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2425 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2427 if (msglen > I40E_AQ_LARGE_BUF)
2428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2429 desc.datalen = CPU_TO_LE16(msglen);
2431 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2437 * i40e_aq_debug_read_register
2438 * @hw: pointer to the hw struct
2439 * @reg_addr: register address
2440 * @reg_val: register value
2441 * @cmd_details: pointer to command details structure or NULL
2443 * Read the register using the admin queue commands
2445 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2446 u32 reg_addr, u64 *reg_val,
2447 struct i40e_asq_cmd_details *cmd_details)
2449 struct i40e_aq_desc desc;
2450 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2451 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2452 enum i40e_status_code status;
2454 if (reg_val == NULL)
2455 return I40E_ERR_PARAM;
2457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2459 cmd_resp->address = CPU_TO_LE32(reg_addr);
2461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2463 if (status == I40E_SUCCESS) {
2464 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2465 (u64)LE32_TO_CPU(cmd_resp->value_low);
2472 * i40e_aq_debug_write_register
2473 * @hw: pointer to the hw struct
2474 * @reg_addr: register address
2475 * @reg_val: register value
2476 * @cmd_details: pointer to command details structure or NULL
2478 * Write to a register using the admin queue commands
2480 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2481 u32 reg_addr, u64 reg_val,
2482 struct i40e_asq_cmd_details *cmd_details)
2484 struct i40e_aq_desc desc;
2485 struct i40e_aqc_debug_reg_read_write *cmd =
2486 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2487 enum i40e_status_code status;
2489 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2491 cmd->address = CPU_TO_LE32(reg_addr);
2492 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2493 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2501 * i40e_aq_get_hmc_resource_profile
2502 * @hw: pointer to the hw struct
2503 * @profile: type of profile the HMC is to be set as
2504 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2505 * @cmd_details: pointer to command details structure or NULL
2507 * query the HMC profile of the device.
2509 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2510 enum i40e_aq_hmc_profile *profile,
2511 u8 *pe_vf_enabled_count,
2512 struct i40e_asq_cmd_details *cmd_details)
2514 struct i40e_aq_desc desc;
2515 struct i40e_aq_get_set_hmc_resource_profile *resp =
2516 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2517 enum i40e_status_code status;
2519 i40e_fill_default_direct_cmd_desc(&desc,
2520 i40e_aqc_opc_query_hmc_resource_profile);
2521 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2523 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2524 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2525 *pe_vf_enabled_count = resp->pe_vf_enabled &
2526 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2532 * i40e_aq_set_hmc_resource_profile
2533 * @hw: pointer to the hw struct
2534 * @profile: type of profile the HMC is to be set as
2535 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2536 * @cmd_details: pointer to command details structure or NULL
2538 * set the HMC profile of the device.
2540 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2541 enum i40e_aq_hmc_profile profile,
2542 u8 pe_vf_enabled_count,
2543 struct i40e_asq_cmd_details *cmd_details)
2545 struct i40e_aq_desc desc;
2546 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2547 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2548 enum i40e_status_code status;
2550 i40e_fill_default_direct_cmd_desc(&desc,
2551 i40e_aqc_opc_set_hmc_resource_profile);
2553 cmd->pm_profile = (u8)profile;
2554 cmd->pe_vf_enabled = pe_vf_enabled_count;
2556 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2562 * i40e_aq_request_resource
2563 * @hw: pointer to the hw struct
2564 * @resource: resource id
2565 * @access: access type
2566 * @sdp_number: resource number
2567 * @timeout: the maximum time in ms that the driver may hold the resource
2568 * @cmd_details: pointer to command details structure or NULL
2570 * requests common resource using the admin queue commands
2572 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2573 enum i40e_aq_resources_ids resource,
2574 enum i40e_aq_resource_access_type access,
2575 u8 sdp_number, u64 *timeout,
2576 struct i40e_asq_cmd_details *cmd_details)
2578 struct i40e_aq_desc desc;
2579 struct i40e_aqc_request_resource *cmd_resp =
2580 (struct i40e_aqc_request_resource *)&desc.params.raw;
2581 enum i40e_status_code status;
2583 DEBUGFUNC("i40e_aq_request_resource");
2585 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2587 cmd_resp->resource_id = CPU_TO_LE16(resource);
2588 cmd_resp->access_type = CPU_TO_LE16(access);
2589 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2591 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2592 /* The completion specifies the maximum time in ms that the driver
2593 * may hold the resource in the Timeout field.
2594 * If the resource is held by someone else, the command completes with
2595 * busy return value and the timeout field indicates the maximum time
2596 * the current owner of the resource has to free it.
2598 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2599 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2605 * i40e_aq_release_resource
2606 * @hw: pointer to the hw struct
2607 * @resource: resource id
2608 * @sdp_number: resource number
2609 * @cmd_details: pointer to command details structure or NULL
2611 * release common resource using the admin queue commands
2613 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2614 enum i40e_aq_resources_ids resource,
2616 struct i40e_asq_cmd_details *cmd_details)
2618 struct i40e_aq_desc desc;
2619 struct i40e_aqc_request_resource *cmd =
2620 (struct i40e_aqc_request_resource *)&desc.params.raw;
2621 enum i40e_status_code status;
2623 DEBUGFUNC("i40e_aq_release_resource");
2625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2627 cmd->resource_id = CPU_TO_LE16(resource);
2628 cmd->resource_number = CPU_TO_LE32(sdp_number);
2630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2637 * @hw: pointer to the hw struct
2638 * @module_pointer: module pointer location in words from the NVM beginning
2639 * @offset: byte offset from the module beginning
2640 * @length: length of the section to be read (in bytes from the offset)
2641 * @data: command buffer (size [bytes] = length)
2642 * @last_command: tells if this is the last command in a series
2643 * @cmd_details: pointer to command details structure or NULL
2645 * Read the NVM using the admin queue commands
2647 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2648 u32 offset, u16 length, void *data,
2650 struct i40e_asq_cmd_details *cmd_details)
2652 struct i40e_aq_desc desc;
2653 struct i40e_aqc_nvm_update *cmd =
2654 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2655 enum i40e_status_code status;
2657 DEBUGFUNC("i40e_aq_read_nvm");
2659 /* In offset the highest byte must be zeroed. */
2660 if (offset & 0xFF000000) {
2661 status = I40E_ERR_PARAM;
2662 goto i40e_aq_read_nvm_exit;
2665 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2667 /* If this is the last command in a series, set the proper flag. */
2669 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2670 cmd->module_pointer = module_pointer;
2671 cmd->offset = CPU_TO_LE32(offset);
2672 cmd->length = CPU_TO_LE16(length);
2674 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2675 if (length > I40E_AQ_LARGE_BUF)
2676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2678 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2680 i40e_aq_read_nvm_exit:
2685 * i40e_aq_read_nvm_config - read an nvm config block
2686 * @hw: pointer to the hw struct
2687 * @cmd_flags: NVM access admin command bits
2688 * @field_id: field or feature id
2689 * @data: buffer for result
2690 * @buf_size: buffer size
2691 * @element_count: pointer to count of elements read by FW
2692 * @cmd_details: pointer to command details structure or NULL
2694 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2695 u8 cmd_flags, u32 field_id, void *data,
2696 u16 buf_size, u16 *element_count,
2697 struct i40e_asq_cmd_details *cmd_details)
2699 struct i40e_aq_desc desc;
2700 struct i40e_aqc_nvm_config_read *cmd =
2701 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2702 enum i40e_status_code status;
2704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2705 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2706 if (buf_size > I40E_AQ_LARGE_BUF)
2707 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2709 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2710 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2711 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2712 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2714 cmd->element_id_msw = 0;
2716 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2718 if (!status && element_count)
2719 *element_count = LE16_TO_CPU(cmd->element_count);
2725 * i40e_aq_write_nvm_config - write an nvm config block
2726 * @hw: pointer to the hw struct
2727 * @cmd_flags: NVM access admin command bits
2728 * @data: buffer for result
2729 * @buf_size: buffer size
2730 * @element_count: count of elements to be written
2731 * @cmd_details: pointer to command details structure or NULL
2733 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2734 u8 cmd_flags, void *data, u16 buf_size,
2736 struct i40e_asq_cmd_details *cmd_details)
2738 struct i40e_aq_desc desc;
2739 struct i40e_aqc_nvm_config_write *cmd =
2740 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2741 enum i40e_status_code status;
2743 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2744 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2745 if (buf_size > I40E_AQ_LARGE_BUF)
2746 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2748 cmd->element_count = CPU_TO_LE16(element_count);
2749 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2750 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2757 * @hw: pointer to the hw struct
2758 * @module_pointer: module pointer location in words from the NVM beginning
2759 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2760 * @length: length of the section to be erased (expressed in 4 KB)
2761 * @last_command: tells if this is the last command in a series
2762 * @cmd_details: pointer to command details structure or NULL
2764 * Erase the NVM sector using the admin queue commands
2766 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2767 u32 offset, u16 length, bool last_command,
2768 struct i40e_asq_cmd_details *cmd_details)
2770 struct i40e_aq_desc desc;
2771 struct i40e_aqc_nvm_update *cmd =
2772 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2773 enum i40e_status_code status;
2775 DEBUGFUNC("i40e_aq_erase_nvm");
2777 /* In offset the highest byte must be zeroed. */
2778 if (offset & 0xFF000000) {
2779 status = I40E_ERR_PARAM;
2780 goto i40e_aq_erase_nvm_exit;
2783 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2785 /* If this is the last command in a series, set the proper flag. */
2787 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2788 cmd->module_pointer = module_pointer;
2789 cmd->offset = CPU_TO_LE32(offset);
2790 cmd->length = CPU_TO_LE16(length);
2792 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2794 i40e_aq_erase_nvm_exit:
2798 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2799 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2800 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2801 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2802 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2803 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2804 #define I40E_DEV_FUNC_CAP_VF 0x13
2805 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2806 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2807 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2808 #define I40E_DEV_FUNC_CAP_VSI 0x17
2809 #define I40E_DEV_FUNC_CAP_DCB 0x18
2810 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2811 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2812 #define I40E_DEV_FUNC_CAP_RSS 0x40
2813 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2814 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2815 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2816 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2817 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2818 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2819 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
2820 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2821 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2822 #define I40E_DEV_FUNC_CAP_LED 0x61
2823 #define I40E_DEV_FUNC_CAP_SDP 0x62
2824 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2825 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
2828 * i40e_parse_discover_capabilities
2829 * @hw: pointer to the hw struct
2830 * @buff: pointer to a buffer containing device/function capability records
2831 * @cap_count: number of capability records in the list
2832 * @list_type_opc: type of capabilities list to parse
2834 * Parse the device/function capabilities list.
2836 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2838 enum i40e_admin_queue_opc list_type_opc)
2840 struct i40e_aqc_list_capabilities_element_resp *cap;
2841 u32 valid_functions, num_functions;
2842 u32 number, logical_id, phys_id;
2844 struct i40e_hw_capabilities *p;
2848 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2850 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2851 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2852 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2853 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2857 for (i = 0; i < cap_count; i++, cap++) {
2858 id = LE16_TO_CPU(cap->id);
2859 number = LE32_TO_CPU(cap->number);
2860 logical_id = LE32_TO_CPU(cap->logical_id);
2861 phys_id = LE32_TO_CPU(cap->phys_id);
2862 major_rev = cap->major_rev;
2865 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2866 p->switch_mode = number;
2868 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2869 p->management_mode = number;
2871 case I40E_DEV_FUNC_CAP_NPAR:
2872 p->npar_enable = number;
2874 case I40E_DEV_FUNC_CAP_OS2BMC:
2877 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2878 p->valid_functions = number;
2880 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2882 p->sr_iov_1_1 = TRUE;
2884 case I40E_DEV_FUNC_CAP_VF:
2885 p->num_vfs = number;
2886 p->vf_base_id = logical_id;
2888 case I40E_DEV_FUNC_CAP_VMDQ:
2892 case I40E_DEV_FUNC_CAP_802_1_QBG:
2894 p->evb_802_1_qbg = TRUE;
2896 case I40E_DEV_FUNC_CAP_802_1_QBH:
2898 p->evb_802_1_qbh = TRUE;
2900 case I40E_DEV_FUNC_CAP_VSI:
2901 p->num_vsis = number;
2903 case I40E_DEV_FUNC_CAP_DCB:
2906 p->enabled_tcmap = logical_id;
2910 case I40E_DEV_FUNC_CAP_FCOE:
2914 case I40E_DEV_FUNC_CAP_ISCSI:
2918 case I40E_DEV_FUNC_CAP_RSS:
2920 p->rss_table_size = number;
2921 p->rss_table_entry_width = logical_id;
2923 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2924 p->num_rx_qp = number;
2925 p->base_queue = phys_id;
2927 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2928 p->num_tx_qp = number;
2929 p->base_queue = phys_id;
2931 case I40E_DEV_FUNC_CAP_MSIX:
2932 p->num_msix_vectors = number;
2934 case I40E_DEV_FUNC_CAP_MSIX_VF:
2935 p->num_msix_vectors_vf = number;
2937 case I40E_DEV_FUNC_CAP_FLEX10:
2938 if (major_rev == 1) {
2940 p->flex10_enable = TRUE;
2941 p->flex10_capable = TRUE;
2944 /* Capability revision >= 2 */
2946 p->flex10_enable = TRUE;
2948 p->flex10_capable = TRUE;
2950 p->flex10_mode = logical_id;
2951 p->flex10_status = phys_id;
2953 case I40E_DEV_FUNC_CAP_CEM:
2957 case I40E_DEV_FUNC_CAP_IWARP:
2961 case I40E_DEV_FUNC_CAP_LED:
2962 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2963 p->led[phys_id] = TRUE;
2965 case I40E_DEV_FUNC_CAP_SDP:
2966 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2967 p->sdp[phys_id] = TRUE;
2969 case I40E_DEV_FUNC_CAP_MDIO:
2971 p->mdio_port_num = phys_id;
2972 p->mdio_port_mode = logical_id;
2975 case I40E_DEV_FUNC_CAP_IEEE_1588:
2977 p->ieee_1588 = TRUE;
2979 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2981 p->fd_filters_guaranteed = number;
2982 p->fd_filters_best_effort = logical_id;
2984 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
2985 p->wr_csr_prot = (u64)number;
2986 p->wr_csr_prot |= (u64)logical_id << 32;
2994 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2996 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2999 /* count the enabled ports (aka the "not disabled" ports) */
3001 for (i = 0; i < 4; i++) {
3002 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3005 /* use AQ read to get the physical register offset instead
3006 * of the port relative offset
3008 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3009 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3013 valid_functions = p->valid_functions;
3015 while (valid_functions) {
3016 if (valid_functions & 1)
3018 valid_functions >>= 1;
3021 /* partition id is 1-based, and functions are evenly spread
3022 * across the ports as partitions
3024 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3025 hw->num_partitions = num_functions / hw->num_ports;
3027 /* additional HW specific goodies that might
3028 * someday be HW version specific
3030 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3034 * i40e_aq_discover_capabilities
3035 * @hw: pointer to the hw struct
3036 * @buff: a virtual buffer to hold the capabilities
3037 * @buff_size: Size of the virtual buffer
3038 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3039 * @list_type_opc: capabilities type to discover - pass in the command opcode
3040 * @cmd_details: pointer to command details structure or NULL
3042 * Get the device capabilities descriptions from the firmware
3044 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3045 void *buff, u16 buff_size, u16 *data_size,
3046 enum i40e_admin_queue_opc list_type_opc,
3047 struct i40e_asq_cmd_details *cmd_details)
3049 struct i40e_aqc_list_capabilites *cmd;
3050 struct i40e_aq_desc desc;
3051 enum i40e_status_code status = I40E_SUCCESS;
3053 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3055 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3056 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3057 status = I40E_ERR_PARAM;
3061 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3063 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3064 if (buff_size > I40E_AQ_LARGE_BUF)
3065 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3067 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3068 *data_size = LE16_TO_CPU(desc.datalen);
3073 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3081 * i40e_aq_update_nvm
3082 * @hw: pointer to the hw struct
3083 * @module_pointer: module pointer location in words from the NVM beginning
3084 * @offset: byte offset from the module beginning
3085 * @length: length of the section to be written (in bytes from the offset)
3086 * @data: command buffer (size [bytes] = length)
3087 * @last_command: tells if this is the last command in a series
3088 * @cmd_details: pointer to command details structure or NULL
3090 * Update the NVM using the admin queue commands
3092 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3093 u32 offset, u16 length, void *data,
3095 struct i40e_asq_cmd_details *cmd_details)
3097 struct i40e_aq_desc desc;
3098 struct i40e_aqc_nvm_update *cmd =
3099 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3100 enum i40e_status_code status;
3102 DEBUGFUNC("i40e_aq_update_nvm");
3104 /* In offset the highest byte must be zeroed. */
3105 if (offset & 0xFF000000) {
3106 status = I40E_ERR_PARAM;
3107 goto i40e_aq_update_nvm_exit;
3110 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3112 /* If this is the last command in a series, set the proper flag. */
3114 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3115 cmd->module_pointer = module_pointer;
3116 cmd->offset = CPU_TO_LE32(offset);
3117 cmd->length = CPU_TO_LE16(length);
3119 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3120 if (length > I40E_AQ_LARGE_BUF)
3121 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3123 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3125 i40e_aq_update_nvm_exit:
3130 * i40e_aq_get_lldp_mib
3131 * @hw: pointer to the hw struct
3132 * @bridge_type: type of bridge requested
3133 * @mib_type: Local, Remote or both Local and Remote MIBs
3134 * @buff: pointer to a user supplied buffer to store the MIB block
3135 * @buff_size: size of the buffer (in bytes)
3136 * @local_len : length of the returned Local LLDP MIB
3137 * @remote_len: length of the returned Remote LLDP MIB
3138 * @cmd_details: pointer to command details structure or NULL
3140 * Requests the complete LLDP MIB (entire packet).
3142 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3143 u8 mib_type, void *buff, u16 buff_size,
3144 u16 *local_len, u16 *remote_len,
3145 struct i40e_asq_cmd_details *cmd_details)
3147 struct i40e_aq_desc desc;
3148 struct i40e_aqc_lldp_get_mib *cmd =
3149 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3150 struct i40e_aqc_lldp_get_mib *resp =
3151 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3152 enum i40e_status_code status;
3154 if (buff_size == 0 || !buff)
3155 return I40E_ERR_PARAM;
3157 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3158 /* Indirect Command */
3159 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3161 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3162 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3163 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3165 desc.datalen = CPU_TO_LE16(buff_size);
3167 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3168 if (buff_size > I40E_AQ_LARGE_BUF)
3169 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3171 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3173 if (local_len != NULL)
3174 *local_len = LE16_TO_CPU(resp->local_len);
3175 if (remote_len != NULL)
3176 *remote_len = LE16_TO_CPU(resp->remote_len);
3183 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3184 * @hw: pointer to the hw struct
3185 * @mib_type: Local, Remote or both Local and Remote MIBs
3186 * @buff: pointer to a user supplied buffer to store the MIB block
3187 * @buff_size: size of the buffer (in bytes)
3188 * @cmd_details: pointer to command details structure or NULL
3192 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3193 u8 mib_type, void *buff, u16 buff_size,
3194 struct i40e_asq_cmd_details *cmd_details)
3196 struct i40e_aq_desc desc;
3197 struct i40e_aqc_lldp_set_local_mib *cmd =
3198 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3199 enum i40e_status_code status;
3201 if (buff_size == 0 || !buff)
3202 return I40E_ERR_PARAM;
3204 i40e_fill_default_direct_cmd_desc(&desc,
3205 i40e_aqc_opc_lldp_set_local_mib);
3206 /* Indirect Command */
3207 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3208 if (buff_size > I40E_AQ_LARGE_BUF)
3209 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3210 desc.datalen = CPU_TO_LE16(buff_size);
3212 cmd->type = mib_type;
3213 cmd->length = CPU_TO_LE16(buff_size);
3214 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3215 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3217 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3222 * i40e_aq_cfg_lldp_mib_change_event
3223 * @hw: pointer to the hw struct
3224 * @enable_update: Enable or Disable event posting
3225 * @cmd_details: pointer to command details structure or NULL
3227 * Enable or Disable posting of an event on ARQ when LLDP MIB
3228 * associated with the interface changes
3230 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3232 struct i40e_asq_cmd_details *cmd_details)
3234 struct i40e_aq_desc desc;
3235 struct i40e_aqc_lldp_update_mib *cmd =
3236 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3237 enum i40e_status_code status;
3239 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3242 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3244 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3250 * i40e_aq_add_lldp_tlv
3251 * @hw: pointer to the hw struct
3252 * @bridge_type: type of bridge
3253 * @buff: buffer with TLV to add
3254 * @buff_size: length of the buffer
3255 * @tlv_len: length of the TLV to be added
3256 * @mib_len: length of the LLDP MIB returned in response
3257 * @cmd_details: pointer to command details structure or NULL
3259 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3260 * it is responsibility of the caller to make sure that the TLV is not
3261 * already present in the LLDPDU.
3262 * In return firmware will write the complete LLDP MIB with the newly
3263 * added TLV in the response buffer.
3265 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3266 void *buff, u16 buff_size, u16 tlv_len,
3268 struct i40e_asq_cmd_details *cmd_details)
3270 struct i40e_aq_desc desc;
3271 struct i40e_aqc_lldp_add_tlv *cmd =
3272 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3273 enum i40e_status_code status;
3275 if (buff_size == 0 || !buff || tlv_len == 0)
3276 return I40E_ERR_PARAM;
3278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3280 /* Indirect Command */
3281 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3282 if (buff_size > I40E_AQ_LARGE_BUF)
3283 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3284 desc.datalen = CPU_TO_LE16(buff_size);
3286 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3287 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3288 cmd->len = CPU_TO_LE16(tlv_len);
3290 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3292 if (mib_len != NULL)
3293 *mib_len = LE16_TO_CPU(desc.datalen);
3300 * i40e_aq_update_lldp_tlv
3301 * @hw: pointer to the hw struct
3302 * @bridge_type: type of bridge
3303 * @buff: buffer with TLV to update
3304 * @buff_size: size of the buffer holding original and updated TLVs
3305 * @old_len: Length of the Original TLV
3306 * @new_len: Length of the Updated TLV
3307 * @offset: offset of the updated TLV in the buff
3308 * @mib_len: length of the returned LLDP MIB
3309 * @cmd_details: pointer to command details structure or NULL
3311 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3312 * Firmware will place the complete LLDP MIB in response buffer with the
3315 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3316 u8 bridge_type, void *buff, u16 buff_size,
3317 u16 old_len, u16 new_len, u16 offset,
3319 struct i40e_asq_cmd_details *cmd_details)
3321 struct i40e_aq_desc desc;
3322 struct i40e_aqc_lldp_update_tlv *cmd =
3323 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3324 enum i40e_status_code status;
3326 if (buff_size == 0 || !buff || offset == 0 ||
3327 old_len == 0 || new_len == 0)
3328 return I40E_ERR_PARAM;
3330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3332 /* Indirect Command */
3333 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3334 if (buff_size > I40E_AQ_LARGE_BUF)
3335 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3336 desc.datalen = CPU_TO_LE16(buff_size);
3338 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3339 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3340 cmd->old_len = CPU_TO_LE16(old_len);
3341 cmd->new_offset = CPU_TO_LE16(offset);
3342 cmd->new_len = CPU_TO_LE16(new_len);
3344 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3346 if (mib_len != NULL)
3347 *mib_len = LE16_TO_CPU(desc.datalen);
3354 * i40e_aq_delete_lldp_tlv
3355 * @hw: pointer to the hw struct
3356 * @bridge_type: type of bridge
3357 * @buff: pointer to a user supplied buffer that has the TLV
3358 * @buff_size: length of the buffer
3359 * @tlv_len: length of the TLV to be deleted
3360 * @mib_len: length of the returned LLDP MIB
3361 * @cmd_details: pointer to command details structure or NULL
3363 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3364 * The firmware places the entire LLDP MIB in the response buffer.
3366 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3367 u8 bridge_type, void *buff, u16 buff_size,
3368 u16 tlv_len, u16 *mib_len,
3369 struct i40e_asq_cmd_details *cmd_details)
3371 struct i40e_aq_desc desc;
3372 struct i40e_aqc_lldp_add_tlv *cmd =
3373 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3374 enum i40e_status_code status;
3376 if (buff_size == 0 || !buff)
3377 return I40E_ERR_PARAM;
3379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3381 /* Indirect Command */
3382 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3383 if (buff_size > I40E_AQ_LARGE_BUF)
3384 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3385 desc.datalen = CPU_TO_LE16(buff_size);
3386 cmd->len = CPU_TO_LE16(tlv_len);
3387 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3388 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3390 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3392 if (mib_len != NULL)
3393 *mib_len = LE16_TO_CPU(desc.datalen);
3401 * @hw: pointer to the hw struct
3402 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3403 * @cmd_details: pointer to command details structure or NULL
3405 * Stop or Shutdown the embedded LLDP Agent
3407 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3408 struct i40e_asq_cmd_details *cmd_details)
3410 struct i40e_aq_desc desc;
3411 struct i40e_aqc_lldp_stop *cmd =
3412 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3413 enum i40e_status_code status;
3415 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3418 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3420 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3426 * i40e_aq_start_lldp
3427 * @hw: pointer to the hw struct
3428 * @cmd_details: pointer to command details structure or NULL
3430 * Start the embedded LLDP Agent on all ports.
3432 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3433 struct i40e_asq_cmd_details *cmd_details)
3435 struct i40e_aq_desc desc;
3436 struct i40e_aqc_lldp_start *cmd =
3437 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3438 enum i40e_status_code status;
3440 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3442 cmd->command = I40E_AQ_LLDP_AGENT_START;
3444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3450 * i40e_aq_get_cee_dcb_config
3451 * @hw: pointer to the hw struct
3452 * @buff: response buffer that stores CEE operational configuration
3453 * @buff_size: size of the buffer passed
3454 * @cmd_details: pointer to command details structure or NULL
3456 * Get CEE DCBX mode operational configuration from firmware
3458 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3459 void *buff, u16 buff_size,
3460 struct i40e_asq_cmd_details *cmd_details)
3462 struct i40e_aq_desc desc;
3463 enum i40e_status_code status;
3465 if (buff_size == 0 || !buff)
3466 return I40E_ERR_PARAM;
3468 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3470 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3471 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3478 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3479 * @hw: pointer to the hw struct
3480 * @start_agent: True if DCBx Agent needs to be Started
3481 * False if DCBx Agent needs to be Stopped
3482 * @cmd_details: pointer to command details structure or NULL
3484 * Start/Stop the embedded dcbx Agent
3486 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3488 struct i40e_asq_cmd_details *cmd_details)
3490 struct i40e_aq_desc desc;
3491 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3492 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3494 enum i40e_status_code status;
3496 i40e_fill_default_direct_cmd_desc(&desc,
3497 i40e_aqc_opc_lldp_stop_start_spec_agent);
3500 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3508 * i40e_aq_add_udp_tunnel
3509 * @hw: pointer to the hw struct
3510 * @udp_port: the UDP port to add
3511 * @header_len: length of the tunneling header length in DWords
3512 * @protocol_index: protocol index type
3513 * @filter_index: pointer to filter index
3514 * @cmd_details: pointer to command details structure or NULL
3516 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3517 u16 udp_port, u8 protocol_index,
3519 struct i40e_asq_cmd_details *cmd_details)
3521 struct i40e_aq_desc desc;
3522 struct i40e_aqc_add_udp_tunnel *cmd =
3523 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3524 struct i40e_aqc_del_udp_tunnel_completion *resp =
3525 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3526 enum i40e_status_code status;
3528 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3530 cmd->udp_port = CPU_TO_LE16(udp_port);
3531 cmd->protocol_type = protocol_index;
3533 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3535 if (!status && filter_index)
3536 *filter_index = resp->index;
3542 * i40e_aq_del_udp_tunnel
3543 * @hw: pointer to the hw struct
3544 * @index: filter index
3545 * @cmd_details: pointer to command details structure or NULL
3547 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3548 struct i40e_asq_cmd_details *cmd_details)
3550 struct i40e_aq_desc desc;
3551 struct i40e_aqc_remove_udp_tunnel *cmd =
3552 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3553 enum i40e_status_code status;
3555 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3559 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3565 * i40e_aq_get_switch_resource_alloc (0x0204)
3566 * @hw: pointer to the hw struct
3567 * @num_entries: pointer to u8 to store the number of resource entries returned
3568 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3569 * to store the resource information for all resource types. Each
3570 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3571 * @count: size, in bytes, of the buffer provided
3572 * @cmd_details: pointer to command details structure or NULL
3574 * Query the resources allocated to a function.
3576 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3578 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3580 struct i40e_asq_cmd_details *cmd_details)
3582 struct i40e_aq_desc desc;
3583 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3584 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3585 enum i40e_status_code status;
3586 u16 length = count * sizeof(*buf);
3588 i40e_fill_default_direct_cmd_desc(&desc,
3589 i40e_aqc_opc_get_switch_resource_alloc);
3591 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3592 if (length > I40E_AQ_LARGE_BUF)
3593 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3595 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3597 if (!status && num_entries)
3598 *num_entries = cmd_resp->num_entries;
3604 * i40e_aq_delete_element - Delete switch element
3605 * @hw: pointer to the hw struct
3606 * @seid: the SEID to delete from the switch
3607 * @cmd_details: pointer to command details structure or NULL
3609 * This deletes a switch element from the switch.
3611 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3612 struct i40e_asq_cmd_details *cmd_details)
3614 struct i40e_aq_desc desc;
3615 struct i40e_aqc_switch_seid *cmd =
3616 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3617 enum i40e_status_code status;
3620 return I40E_ERR_PARAM;
3622 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3624 cmd->seid = CPU_TO_LE16(seid);
3626 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3632 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3633 * @hw: pointer to the hw struct
3634 * @flags: component flags
3635 * @mac_seid: uplink seid (MAC SEID)
3636 * @vsi_seid: connected vsi seid
3637 * @ret_seid: seid of create pv component
3639 * This instantiates an i40e port virtualizer with specified flags.
3640 * Depending on specified flags the port virtualizer can act as a
3641 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3643 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3644 u16 mac_seid, u16 vsi_seid,
3647 struct i40e_aq_desc desc;
3648 struct i40e_aqc_add_update_pv *cmd =
3649 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3650 struct i40e_aqc_add_update_pv_completion *resp =
3651 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3652 enum i40e_status_code status;
3655 return I40E_ERR_PARAM;
3657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3658 cmd->command_flags = CPU_TO_LE16(flags);
3659 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3660 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3662 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3663 if (!status && ret_seid)
3664 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3670 * i40e_aq_add_tag - Add an S/E-tag
3671 * @hw: pointer to the hw struct
3672 * @direct_to_queue: should s-tag direct flow to a specific queue
3673 * @vsi_seid: VSI SEID to use this tag
3674 * @tag: value of the tag
3675 * @queue_num: queue number, only valid is direct_to_queue is TRUE
3676 * @tags_used: return value, number of tags in use by this PF
3677 * @tags_free: return value, number of unallocated tags
3678 * @cmd_details: pointer to command details structure or NULL
3680 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3681 * the number of tags allocated by the PF, and the number of unallocated
3684 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3685 u16 vsi_seid, u16 tag, u16 queue_num,
3686 u16 *tags_used, u16 *tags_free,
3687 struct i40e_asq_cmd_details *cmd_details)
3689 struct i40e_aq_desc desc;
3690 struct i40e_aqc_add_tag *cmd =
3691 (struct i40e_aqc_add_tag *)&desc.params.raw;
3692 struct i40e_aqc_add_remove_tag_completion *resp =
3693 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3694 enum i40e_status_code status;
3697 return I40E_ERR_PARAM;
3699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3701 cmd->seid = CPU_TO_LE16(vsi_seid);
3702 cmd->tag = CPU_TO_LE16(tag);
3703 if (direct_to_queue) {
3704 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3705 cmd->queue_number = CPU_TO_LE16(queue_num);
3708 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3711 if (tags_used != NULL)
3712 *tags_used = LE16_TO_CPU(resp->tags_used);
3713 if (tags_free != NULL)
3714 *tags_free = LE16_TO_CPU(resp->tags_free);
3721 * i40e_aq_remove_tag - Remove an S- or E-tag
3722 * @hw: pointer to the hw struct
3723 * @vsi_seid: VSI SEID this tag is associated with
3724 * @tag: value of the S-tag to delete
3725 * @tags_used: return value, number of tags in use by this PF
3726 * @tags_free: return value, number of unallocated tags
3727 * @cmd_details: pointer to command details structure or NULL
3729 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3730 * the number of tags allocated by the PF, and the number of unallocated
3733 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3734 u16 tag, u16 *tags_used, u16 *tags_free,
3735 struct i40e_asq_cmd_details *cmd_details)
3737 struct i40e_aq_desc desc;
3738 struct i40e_aqc_remove_tag *cmd =
3739 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3740 struct i40e_aqc_add_remove_tag_completion *resp =
3741 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3742 enum i40e_status_code status;
3745 return I40E_ERR_PARAM;
3747 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3749 cmd->seid = CPU_TO_LE16(vsi_seid);
3750 cmd->tag = CPU_TO_LE16(tag);
3752 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3755 if (tags_used != NULL)
3756 *tags_used = LE16_TO_CPU(resp->tags_used);
3757 if (tags_free != NULL)
3758 *tags_free = LE16_TO_CPU(resp->tags_free);
3765 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3766 * @hw: pointer to the hw struct
3767 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3768 * @etag: value of E-tag to add
3769 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3770 * @buf: address of indirect buffer
3771 * @tags_used: return value, number of E-tags in use by this port
3772 * @tags_free: return value, number of unallocated M-tags
3773 * @cmd_details: pointer to command details structure or NULL
3775 * This associates a multicast E-tag to a port virtualizer. It will return
3776 * the number of tags allocated by the PF, and the number of unallocated
3779 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3780 * num_tags_in_buf long.
3782 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3783 u16 etag, u8 num_tags_in_buf, void *buf,
3784 u16 *tags_used, u16 *tags_free,
3785 struct i40e_asq_cmd_details *cmd_details)
3787 struct i40e_aq_desc desc;
3788 struct i40e_aqc_add_remove_mcast_etag *cmd =
3789 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3790 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3791 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3792 enum i40e_status_code status;
3793 u16 length = sizeof(u16) * num_tags_in_buf;
3795 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3796 return I40E_ERR_PARAM;
3798 i40e_fill_default_direct_cmd_desc(&desc,
3799 i40e_aqc_opc_add_multicast_etag);
3801 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3802 cmd->etag = CPU_TO_LE16(etag);
3803 cmd->num_unicast_etags = num_tags_in_buf;
3805 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3806 if (length > I40E_AQ_LARGE_BUF)
3807 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3809 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3812 if (tags_used != NULL)
3813 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3814 if (tags_free != NULL)
3815 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3822 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3823 * @hw: pointer to the hw struct
3824 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3825 * @etag: value of the E-tag to remove
3826 * @tags_used: return value, number of tags in use by this port
3827 * @tags_free: return value, number of unallocated tags
3828 * @cmd_details: pointer to command details structure or NULL
3830 * This deletes an E-tag from the port virtualizer. It will return
3831 * the number of tags allocated by the port, and the number of unallocated
3834 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3835 u16 etag, u16 *tags_used, u16 *tags_free,
3836 struct i40e_asq_cmd_details *cmd_details)
3838 struct i40e_aq_desc desc;
3839 struct i40e_aqc_add_remove_mcast_etag *cmd =
3840 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3841 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3842 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3843 enum i40e_status_code status;
3847 return I40E_ERR_PARAM;
3849 i40e_fill_default_direct_cmd_desc(&desc,
3850 i40e_aqc_opc_remove_multicast_etag);
3852 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3853 cmd->etag = CPU_TO_LE16(etag);
3855 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3858 if (tags_used != NULL)
3859 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3860 if (tags_free != NULL)
3861 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3868 * i40e_aq_update_tag - Update an S/E-tag
3869 * @hw: pointer to the hw struct
3870 * @vsi_seid: VSI SEID using this S-tag
3871 * @old_tag: old tag value
3872 * @new_tag: new tag value
3873 * @tags_used: return value, number of tags in use by this PF
3874 * @tags_free: return value, number of unallocated tags
3875 * @cmd_details: pointer to command details structure or NULL
3877 * This updates the value of the tag currently attached to this VSI
3878 * in the switch complex. It will return the number of tags allocated
3879 * by the PF, and the number of unallocated tags available.
3881 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3882 u16 old_tag, u16 new_tag, u16 *tags_used,
3884 struct i40e_asq_cmd_details *cmd_details)
3886 struct i40e_aq_desc desc;
3887 struct i40e_aqc_update_tag *cmd =
3888 (struct i40e_aqc_update_tag *)&desc.params.raw;
3889 struct i40e_aqc_update_tag_completion *resp =
3890 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3891 enum i40e_status_code status;
3894 return I40E_ERR_PARAM;
3896 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3898 cmd->seid = CPU_TO_LE16(vsi_seid);
3899 cmd->old_tag = CPU_TO_LE16(old_tag);
3900 cmd->new_tag = CPU_TO_LE16(new_tag);
3902 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3905 if (tags_used != NULL)
3906 *tags_used = LE16_TO_CPU(resp->tags_used);
3907 if (tags_free != NULL)
3908 *tags_free = LE16_TO_CPU(resp->tags_free);
3915 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3916 * @hw: pointer to the hw struct
3917 * @tcmap: TC map for request/release any ignore PFC condition
3918 * @request: request or release ignore PFC condition
3919 * @tcmap_ret: return TCs for which PFC is currently ignored
3920 * @cmd_details: pointer to command details structure or NULL
3922 * This sends out request/release to ignore PFC condition for a TC.
3923 * It will return the TCs for which PFC is currently ignored.
3925 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3926 bool request, u8 *tcmap_ret,
3927 struct i40e_asq_cmd_details *cmd_details)
3929 struct i40e_aq_desc desc;
3930 struct i40e_aqc_pfc_ignore *cmd_resp =
3931 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3932 enum i40e_status_code status;
3934 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3937 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3939 cmd_resp->tc_bitmap = tcmap;
3941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3944 if (tcmap_ret != NULL)
3945 *tcmap_ret = cmd_resp->tc_bitmap;
3952 * i40e_aq_dcb_updated - DCB Updated Command
3953 * @hw: pointer to the hw struct
3954 * @cmd_details: pointer to command details structure or NULL
3956 * When LLDP is handled in PF this command is used by the PF
3957 * to notify EMP that a DCB setting is modified.
3958 * When LLDP is handled in EMP this command is used by the PF
3959 * to notify EMP whenever one of the following parameters get
3961 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3962 * - PCIRTT in PRTDCB_GENC.PCIRTT
3963 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3964 * EMP will return when the shared RPB settings have been
3965 * recomputed and modified. The retval field in the descriptor
3966 * will be set to 0 when RPB is modified.
3968 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3969 struct i40e_asq_cmd_details *cmd_details)
3971 struct i40e_aq_desc desc;
3972 enum i40e_status_code status;
3974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3982 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3983 * @hw: pointer to the hw struct
3984 * @seid: defines the SEID of the switch for which the stats are requested
3985 * @vlan_id: the VLAN ID for which the statistics are requested
3986 * @stat_index: index of the statistics counters block assigned to this VLAN
3987 * @cmd_details: pointer to command details structure or NULL
3989 * XL710 supports 128 smonVlanStats counters.This command is used to
3990 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3993 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3994 u16 vlan_id, u16 *stat_index,
3995 struct i40e_asq_cmd_details *cmd_details)
3997 struct i40e_aq_desc desc;
3998 struct i40e_aqc_add_remove_statistics *cmd_resp =
3999 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4000 enum i40e_status_code status;
4002 if ((seid == 0) || (stat_index == NULL))
4003 return I40E_ERR_PARAM;
4005 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4007 cmd_resp->seid = CPU_TO_LE16(seid);
4008 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4010 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4012 if (!status && stat_index)
4013 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4019 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4020 * @hw: pointer to the hw struct
4021 * @seid: defines the SEID of the switch for which the stats are requested
4022 * @vlan_id: the VLAN ID for which the statistics are requested
4023 * @stat_index: index of the statistics counters block assigned to this VLAN
4024 * @cmd_details: pointer to command details structure or NULL
4026 * XL710 supports 128 smonVlanStats counters.This command is used to
4027 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4030 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4031 u16 vlan_id, u16 stat_index,
4032 struct i40e_asq_cmd_details *cmd_details)
4034 struct i40e_aq_desc desc;
4035 struct i40e_aqc_add_remove_statistics *cmd =
4036 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4037 enum i40e_status_code status;
4040 return I40E_ERR_PARAM;
4042 i40e_fill_default_direct_cmd_desc(&desc,
4043 i40e_aqc_opc_remove_statistics);
4045 cmd->seid = CPU_TO_LE16(seid);
4046 cmd->vlan = CPU_TO_LE16(vlan_id);
4047 cmd->stat_index = CPU_TO_LE16(stat_index);
4049 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4055 * i40e_aq_set_port_parameters - set physical port parameters.
4056 * @hw: pointer to the hw struct
4057 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4058 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4059 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4060 * @double_vlan: if set double VLAN is enabled
4061 * @cmd_details: pointer to command details structure or NULL
4063 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4064 u16 bad_frame_vsi, bool save_bad_pac,
4065 bool pad_short_pac, bool double_vlan,
4066 struct i40e_asq_cmd_details *cmd_details)
4068 struct i40e_aqc_set_port_parameters *cmd;
4069 enum i40e_status_code status;
4070 struct i40e_aq_desc desc;
4071 u16 command_flags = 0;
4073 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4075 i40e_fill_default_direct_cmd_desc(&desc,
4076 i40e_aqc_opc_set_port_parameters);
4078 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4080 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4082 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4084 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4085 cmd->command_flags = CPU_TO_LE16(command_flags);
4087 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4093 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4094 * @hw: pointer to the hw struct
4095 * @seid: seid for the physical port/switching component/vsi
4096 * @buff: Indirect buffer to hold data parameters and response
4097 * @buff_size: Indirect buffer size
4098 * @opcode: Tx scheduler AQ command opcode
4099 * @cmd_details: pointer to command details structure or NULL
4101 * Generic command handler for Tx scheduler AQ commands
4103 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4104 void *buff, u16 buff_size,
4105 enum i40e_admin_queue_opc opcode,
4106 struct i40e_asq_cmd_details *cmd_details)
4108 struct i40e_aq_desc desc;
4109 struct i40e_aqc_tx_sched_ind *cmd =
4110 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4111 enum i40e_status_code status;
4112 bool cmd_param_flag = FALSE;
4115 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4116 case i40e_aqc_opc_configure_vsi_tc_bw:
4117 case i40e_aqc_opc_enable_switching_comp_ets:
4118 case i40e_aqc_opc_modify_switching_comp_ets:
4119 case i40e_aqc_opc_disable_switching_comp_ets:
4120 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4121 case i40e_aqc_opc_configure_switching_comp_bw_config:
4122 cmd_param_flag = TRUE;
4124 case i40e_aqc_opc_query_vsi_bw_config:
4125 case i40e_aqc_opc_query_vsi_ets_sla_config:
4126 case i40e_aqc_opc_query_switching_comp_ets_config:
4127 case i40e_aqc_opc_query_port_ets_config:
4128 case i40e_aqc_opc_query_switching_comp_bw_config:
4129 cmd_param_flag = FALSE;
4132 return I40E_ERR_PARAM;
4135 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4137 /* Indirect command */
4138 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4140 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4141 if (buff_size > I40E_AQ_LARGE_BUF)
4142 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4144 desc.datalen = CPU_TO_LE16(buff_size);
4146 cmd->vsi_seid = CPU_TO_LE16(seid);
4148 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4154 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4155 * @hw: pointer to the hw struct
4157 * @credit: BW limit credits (0 = disabled)
4158 * @max_credit: Max BW limit credits
4159 * @cmd_details: pointer to command details structure or NULL
4161 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4162 u16 seid, u16 credit, u8 max_credit,
4163 struct i40e_asq_cmd_details *cmd_details)
4165 struct i40e_aq_desc desc;
4166 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4167 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4168 enum i40e_status_code status;
4170 i40e_fill_default_direct_cmd_desc(&desc,
4171 i40e_aqc_opc_configure_vsi_bw_limit);
4173 cmd->vsi_seid = CPU_TO_LE16(seid);
4174 cmd->credit = CPU_TO_LE16(credit);
4175 cmd->max_credit = max_credit;
4177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4183 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4184 * @hw: pointer to the hw struct
4185 * @seid: switching component seid
4186 * @credit: BW limit credits (0 = disabled)
4187 * @max_bw: Max BW limit credits
4188 * @cmd_details: pointer to command details structure or NULL
4190 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4191 u16 seid, u16 credit, u8 max_bw,
4192 struct i40e_asq_cmd_details *cmd_details)
4194 struct i40e_aq_desc desc;
4195 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4196 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4197 enum i40e_status_code status;
4199 i40e_fill_default_direct_cmd_desc(&desc,
4200 i40e_aqc_opc_configure_switching_comp_bw_limit);
4202 cmd->seid = CPU_TO_LE16(seid);
4203 cmd->credit = CPU_TO_LE16(credit);
4204 cmd->max_bw = max_bw;
4206 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4212 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4213 * @hw: pointer to the hw struct
4215 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4216 * @cmd_details: pointer to command details structure or NULL
4218 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4220 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4221 struct i40e_asq_cmd_details *cmd_details)
4223 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4224 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4229 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4230 * @hw: pointer to the hw struct
4232 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4233 * @cmd_details: pointer to command details structure or NULL
4235 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4237 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4238 struct i40e_asq_cmd_details *cmd_details)
4240 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4241 i40e_aqc_opc_configure_vsi_tc_bw,
4246 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4247 * @hw: pointer to the hw struct
4248 * @seid: seid of the switching component
4249 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4250 * @cmd_details: pointer to command details structure or NULL
4252 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4253 struct i40e_hw *hw, u16 seid,
4254 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4255 struct i40e_asq_cmd_details *cmd_details)
4257 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4258 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4263 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4264 * @hw: pointer to the hw struct
4265 * @seid: seid of the VSI
4266 * @bw_data: Buffer to hold VSI BW configuration
4267 * @cmd_details: pointer to command details structure or NULL
4269 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4271 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4272 struct i40e_asq_cmd_details *cmd_details)
4274 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4275 i40e_aqc_opc_query_vsi_bw_config,
4280 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4281 * @hw: pointer to the hw struct
4282 * @seid: seid of the VSI
4283 * @bw_data: Buffer to hold VSI BW configuration per TC
4284 * @cmd_details: pointer to command details structure or NULL
4286 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4288 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4289 struct i40e_asq_cmd_details *cmd_details)
4291 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4292 i40e_aqc_opc_query_vsi_ets_sla_config,
4297 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4298 * @hw: pointer to the hw struct
4299 * @seid: seid of the switching component
4300 * @bw_data: Buffer to hold switching component's per TC BW config
4301 * @cmd_details: pointer to command details structure or NULL
4303 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4305 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4306 struct i40e_asq_cmd_details *cmd_details)
4308 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4309 i40e_aqc_opc_query_switching_comp_ets_config,
4314 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4315 * @hw: pointer to the hw struct
4316 * @seid: seid of the VSI or switching component connected to Physical Port
4317 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4318 * @cmd_details: pointer to command details structure or NULL
4320 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4322 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4323 struct i40e_asq_cmd_details *cmd_details)
4325 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4326 i40e_aqc_opc_query_port_ets_config,
4331 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4332 * @hw: pointer to the hw struct
4333 * @seid: seid of the switching component
4334 * @bw_data: Buffer to hold switching component's BW configuration
4335 * @cmd_details: pointer to command details structure or NULL
4337 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4339 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4340 struct i40e_asq_cmd_details *cmd_details)
4342 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4343 i40e_aqc_opc_query_switching_comp_bw_config,
4348 * i40e_validate_filter_settings
4349 * @hw: pointer to the hardware structure
4350 * @settings: Filter control settings
4352 * Check and validate the filter control settings passed.
4353 * The function checks for the valid filter/context sizes being
4354 * passed for FCoE and PE.
4356 * Returns I40E_SUCCESS if the values passed are valid and within
4357 * range else returns an error.
4359 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4360 struct i40e_filter_control_settings *settings)
4362 u32 fcoe_cntx_size, fcoe_filt_size;
4363 u32 pe_cntx_size, pe_filt_size;
4368 /* Validate FCoE settings passed */
4369 switch (settings->fcoe_filt_num) {
4370 case I40E_HASH_FILTER_SIZE_1K:
4371 case I40E_HASH_FILTER_SIZE_2K:
4372 case I40E_HASH_FILTER_SIZE_4K:
4373 case I40E_HASH_FILTER_SIZE_8K:
4374 case I40E_HASH_FILTER_SIZE_16K:
4375 case I40E_HASH_FILTER_SIZE_32K:
4376 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4377 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4380 return I40E_ERR_PARAM;
4383 switch (settings->fcoe_cntx_num) {
4384 case I40E_DMA_CNTX_SIZE_512:
4385 case I40E_DMA_CNTX_SIZE_1K:
4386 case I40E_DMA_CNTX_SIZE_2K:
4387 case I40E_DMA_CNTX_SIZE_4K:
4388 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4389 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4392 return I40E_ERR_PARAM;
4395 /* Validate PE settings passed */
4396 switch (settings->pe_filt_num) {
4397 case I40E_HASH_FILTER_SIZE_1K:
4398 case I40E_HASH_FILTER_SIZE_2K:
4399 case I40E_HASH_FILTER_SIZE_4K:
4400 case I40E_HASH_FILTER_SIZE_8K:
4401 case I40E_HASH_FILTER_SIZE_16K:
4402 case I40E_HASH_FILTER_SIZE_32K:
4403 case I40E_HASH_FILTER_SIZE_64K:
4404 case I40E_HASH_FILTER_SIZE_128K:
4405 case I40E_HASH_FILTER_SIZE_256K:
4406 case I40E_HASH_FILTER_SIZE_512K:
4407 case I40E_HASH_FILTER_SIZE_1M:
4408 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4409 pe_filt_size <<= (u32)settings->pe_filt_num;
4412 return I40E_ERR_PARAM;
4415 switch (settings->pe_cntx_num) {
4416 case I40E_DMA_CNTX_SIZE_512:
4417 case I40E_DMA_CNTX_SIZE_1K:
4418 case I40E_DMA_CNTX_SIZE_2K:
4419 case I40E_DMA_CNTX_SIZE_4K:
4420 case I40E_DMA_CNTX_SIZE_8K:
4421 case I40E_DMA_CNTX_SIZE_16K:
4422 case I40E_DMA_CNTX_SIZE_32K:
4423 case I40E_DMA_CNTX_SIZE_64K:
4424 case I40E_DMA_CNTX_SIZE_128K:
4425 case I40E_DMA_CNTX_SIZE_256K:
4426 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4427 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4430 return I40E_ERR_PARAM;
4433 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4434 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4435 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4436 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4437 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4438 return I40E_ERR_INVALID_SIZE;
4440 return I40E_SUCCESS;
4444 * i40e_set_filter_control
4445 * @hw: pointer to the hardware structure
4446 * @settings: Filter control settings
4448 * Set the Queue Filters for PE/FCoE and enable filters required
4449 * for a single PF. It is expected that these settings are programmed
4450 * at the driver initialization time.
4452 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4453 struct i40e_filter_control_settings *settings)
4455 enum i40e_status_code ret = I40E_SUCCESS;
4456 u32 hash_lut_size = 0;
4460 return I40E_ERR_PARAM;
4462 /* Validate the input settings */
4463 ret = i40e_validate_filter_settings(hw, settings);
4467 /* Read the PF Queue Filter control register */
4468 val = rd32(hw, I40E_PFQF_CTL_0);
4470 /* Program required PE hash buckets for the PF */
4471 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4472 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4473 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4474 /* Program required PE contexts for the PF */
4475 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4476 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4477 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4479 /* Program required FCoE hash buckets for the PF */
4480 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4481 val |= ((u32)settings->fcoe_filt_num <<
4482 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4483 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4484 /* Program required FCoE DDP contexts for the PF */
4485 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4486 val |= ((u32)settings->fcoe_cntx_num <<
4487 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4488 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4490 /* Program Hash LUT size for the PF */
4491 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4492 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4494 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4495 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4497 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4498 if (settings->enable_fdir)
4499 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4500 if (settings->enable_ethtype)
4501 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4502 if (settings->enable_macvlan)
4503 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4505 wr32(hw, I40E_PFQF_CTL_0, val);
4507 return I40E_SUCCESS;
4511 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4512 * @hw: pointer to the hw struct
4513 * @mac_addr: MAC address to use in the filter
4514 * @ethtype: Ethertype to use in the filter
4515 * @flags: Flags that needs to be applied to the filter
4516 * @vsi_seid: seid of the control VSI
4517 * @queue: VSI queue number to send the packet to
4518 * @is_add: Add control packet filter if True else remove
4519 * @stats: Structure to hold information on control filter counts
4520 * @cmd_details: pointer to command details structure or NULL
4522 * This command will Add or Remove control packet filter for a control VSI.
4523 * In return it will update the total number of perfect filter count in
4526 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4527 u8 *mac_addr, u16 ethtype, u16 flags,
4528 u16 vsi_seid, u16 queue, bool is_add,
4529 struct i40e_control_filter_stats *stats,
4530 struct i40e_asq_cmd_details *cmd_details)
4532 struct i40e_aq_desc desc;
4533 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4534 (struct i40e_aqc_add_remove_control_packet_filter *)
4536 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4537 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4539 enum i40e_status_code status;
4542 return I40E_ERR_PARAM;
4545 i40e_fill_default_direct_cmd_desc(&desc,
4546 i40e_aqc_opc_add_control_packet_filter);
4547 cmd->queue = CPU_TO_LE16(queue);
4549 i40e_fill_default_direct_cmd_desc(&desc,
4550 i40e_aqc_opc_remove_control_packet_filter);
4554 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4555 I40E_NONDMA_TO_NONDMA);
4557 cmd->etype = CPU_TO_LE16(ethtype);
4558 cmd->flags = CPU_TO_LE16(flags);
4559 cmd->seid = CPU_TO_LE16(vsi_seid);
4561 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4563 if (!status && stats) {
4564 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4565 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4566 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4567 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4574 * i40e_aq_add_cloud_filters
4575 * @hw: pointer to the hardware structure
4576 * @seid: VSI seid to add cloud filters from
4577 * @filters: Buffer which contains the filters to be added
4578 * @filter_count: number of filters contained in the buffer
4580 * Set the cloud filters for a given VSI. The contents of the
4581 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4582 * in by the caller of the function.
4585 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4587 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4590 struct i40e_aq_desc desc;
4591 struct i40e_aqc_add_remove_cloud_filters *cmd =
4592 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4594 enum i40e_status_code status;
4596 i40e_fill_default_direct_cmd_desc(&desc,
4597 i40e_aqc_opc_add_cloud_filters);
4599 buff_len = filter_count * sizeof(*filters);
4600 desc.datalen = CPU_TO_LE16(buff_len);
4601 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4602 cmd->num_filters = filter_count;
4603 cmd->seid = CPU_TO_LE16(seid);
4605 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4611 * i40e_aq_remove_cloud_filters
4612 * @hw: pointer to the hardware structure
4613 * @seid: VSI seid to remove cloud filters from
4614 * @filters: Buffer which contains the filters to be removed
4615 * @filter_count: number of filters contained in the buffer
4617 * Remove the cloud filters for a given VSI. The contents of the
4618 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4619 * in by the caller of the function.
4622 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4624 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4627 struct i40e_aq_desc desc;
4628 struct i40e_aqc_add_remove_cloud_filters *cmd =
4629 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4630 enum i40e_status_code status;
4633 i40e_fill_default_direct_cmd_desc(&desc,
4634 i40e_aqc_opc_remove_cloud_filters);
4636 buff_len = filter_count * sizeof(*filters);
4637 desc.datalen = CPU_TO_LE16(buff_len);
4638 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4639 cmd->num_filters = filter_count;
4640 cmd->seid = CPU_TO_LE16(seid);
4642 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4648 * i40e_aq_alternate_write
4649 * @hw: pointer to the hardware structure
4650 * @reg_addr0: address of first dword to be read
4651 * @reg_val0: value to be written under 'reg_addr0'
4652 * @reg_addr1: address of second dword to be read
4653 * @reg_val1: value to be written under 'reg_addr1'
4655 * Write one or two dwords to alternate structure. Fields are indicated
4656 * by 'reg_addr0' and 'reg_addr1' register numbers.
4659 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4660 u32 reg_addr0, u32 reg_val0,
4661 u32 reg_addr1, u32 reg_val1)
4663 struct i40e_aq_desc desc;
4664 struct i40e_aqc_alternate_write *cmd_resp =
4665 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4666 enum i40e_status_code status;
4668 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4669 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4670 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4671 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4672 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4674 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4680 * i40e_aq_alternate_write_indirect
4681 * @hw: pointer to the hardware structure
4682 * @addr: address of a first register to be modified
4683 * @dw_count: number of alternate structure fields to write
4684 * @buffer: pointer to the command buffer
4686 * Write 'dw_count' dwords from 'buffer' to alternate structure
4687 * starting at 'addr'.
4690 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4691 u32 addr, u32 dw_count, void *buffer)
4693 struct i40e_aq_desc desc;
4694 struct i40e_aqc_alternate_ind_write *cmd_resp =
4695 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4696 enum i40e_status_code status;
4699 return I40E_ERR_PARAM;
4701 /* Indirect command */
4702 i40e_fill_default_direct_cmd_desc(&desc,
4703 i40e_aqc_opc_alternate_write_indirect);
4705 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4706 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4707 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4708 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4710 cmd_resp->address = CPU_TO_LE32(addr);
4711 cmd_resp->length = CPU_TO_LE32(dw_count);
4712 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4713 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4715 status = i40e_asq_send_command(hw, &desc, buffer,
4716 I40E_LO_DWORD(4*dw_count), NULL);
4722 * i40e_aq_alternate_read
4723 * @hw: pointer to the hardware structure
4724 * @reg_addr0: address of first dword to be read
4725 * @reg_val0: pointer for data read from 'reg_addr0'
4726 * @reg_addr1: address of second dword to be read
4727 * @reg_val1: pointer for data read from 'reg_addr1'
4729 * Read one or two dwords from alternate structure. Fields are indicated
4730 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4731 * is not passed then only register at 'reg_addr0' is read.
4734 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4735 u32 reg_addr0, u32 *reg_val0,
4736 u32 reg_addr1, u32 *reg_val1)
4738 struct i40e_aq_desc desc;
4739 struct i40e_aqc_alternate_write *cmd_resp =
4740 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4741 enum i40e_status_code status;
4743 if (reg_val0 == NULL)
4744 return I40E_ERR_PARAM;
4746 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4747 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4748 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4750 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4752 if (status == I40E_SUCCESS) {
4753 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4755 if (reg_val1 != NULL)
4756 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4763 * i40e_aq_alternate_read_indirect
4764 * @hw: pointer to the hardware structure
4765 * @addr: address of the alternate structure field
4766 * @dw_count: number of alternate structure fields to read
4767 * @buffer: pointer to the command buffer
4769 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4770 * place them in 'buffer'. The buffer should be allocated by caller.
4773 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4774 u32 addr, u32 dw_count, void *buffer)
4776 struct i40e_aq_desc desc;
4777 struct i40e_aqc_alternate_ind_write *cmd_resp =
4778 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4779 enum i40e_status_code status;
4782 return I40E_ERR_PARAM;
4784 /* Indirect command */
4785 i40e_fill_default_direct_cmd_desc(&desc,
4786 i40e_aqc_opc_alternate_read_indirect);
4788 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4789 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4790 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4791 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4793 cmd_resp->address = CPU_TO_LE32(addr);
4794 cmd_resp->length = CPU_TO_LE32(dw_count);
4795 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4796 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4798 status = i40e_asq_send_command(hw, &desc, buffer,
4799 I40E_LO_DWORD(4*dw_count), NULL);
4805 * i40e_aq_alternate_clear
4806 * @hw: pointer to the HW structure.
4808 * Clear the alternate structures of the port from which the function
4812 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4814 struct i40e_aq_desc desc;
4815 enum i40e_status_code status;
4817 i40e_fill_default_direct_cmd_desc(&desc,
4818 i40e_aqc_opc_alternate_clear_port);
4820 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4826 * i40e_aq_alternate_write_done
4827 * @hw: pointer to the HW structure.
4828 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4829 * @reset_needed: indicates the SW should trigger GLOBAL reset
4831 * Indicates to the FW that alternate structures have been changed.
4834 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4835 u8 bios_mode, bool *reset_needed)
4837 struct i40e_aq_desc desc;
4838 struct i40e_aqc_alternate_write_done *cmd =
4839 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4840 enum i40e_status_code status;
4842 if (reset_needed == NULL)
4843 return I40E_ERR_PARAM;
4845 i40e_fill_default_direct_cmd_desc(&desc,
4846 i40e_aqc_opc_alternate_write_done);
4848 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4850 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4851 if (!status && reset_needed)
4852 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4853 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4859 * i40e_aq_set_oem_mode
4860 * @hw: pointer to the HW structure.
4861 * @oem_mode: the OEM mode to be used
4863 * Sets the device to a specific operating mode. Currently the only supported
4864 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4867 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4870 struct i40e_aq_desc desc;
4871 struct i40e_aqc_alternate_write_done *cmd =
4872 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4873 enum i40e_status_code status;
4875 i40e_fill_default_direct_cmd_desc(&desc,
4876 i40e_aqc_opc_alternate_set_mode);
4878 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4880 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4886 * i40e_aq_resume_port_tx
4887 * @hw: pointer to the hardware structure
4888 * @cmd_details: pointer to command details structure or NULL
4890 * Resume port's Tx traffic
4892 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4893 struct i40e_asq_cmd_details *cmd_details)
4895 struct i40e_aq_desc desc;
4896 enum i40e_status_code status;
4898 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4900 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4906 * i40e_set_pci_config_data - store PCI bus info
4907 * @hw: pointer to hardware structure
4908 * @link_status: the link status word from PCI config space
4910 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4912 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4914 hw->bus.type = i40e_bus_type_pci_express;
4916 switch (link_status & I40E_PCI_LINK_WIDTH) {
4917 case I40E_PCI_LINK_WIDTH_1:
4918 hw->bus.width = i40e_bus_width_pcie_x1;
4920 case I40E_PCI_LINK_WIDTH_2:
4921 hw->bus.width = i40e_bus_width_pcie_x2;
4923 case I40E_PCI_LINK_WIDTH_4:
4924 hw->bus.width = i40e_bus_width_pcie_x4;
4926 case I40E_PCI_LINK_WIDTH_8:
4927 hw->bus.width = i40e_bus_width_pcie_x8;
4930 hw->bus.width = i40e_bus_width_unknown;
4934 switch (link_status & I40E_PCI_LINK_SPEED) {
4935 case I40E_PCI_LINK_SPEED_2500:
4936 hw->bus.speed = i40e_bus_speed_2500;
4938 case I40E_PCI_LINK_SPEED_5000:
4939 hw->bus.speed = i40e_bus_speed_5000;
4941 case I40E_PCI_LINK_SPEED_8000:
4942 hw->bus.speed = i40e_bus_speed_8000;
4945 hw->bus.speed = i40e_bus_speed_unknown;
4951 * i40e_aq_debug_dump
4952 * @hw: pointer to the hardware structure
4953 * @cluster_id: specific cluster to dump
4954 * @table_id: table id within cluster
4955 * @start_index: index of line in the block to read
4956 * @buff_size: dump buffer size
4957 * @buff: dump buffer
4958 * @ret_buff_size: actual buffer size returned
4959 * @ret_next_table: next block to read
4960 * @ret_next_index: next index to read
4962 * Dump internal FW/HW data for debug purposes.
4965 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4966 u8 table_id, u32 start_index, u16 buff_size,
4967 void *buff, u16 *ret_buff_size,
4968 u8 *ret_next_table, u32 *ret_next_index,
4969 struct i40e_asq_cmd_details *cmd_details)
4971 struct i40e_aq_desc desc;
4972 struct i40e_aqc_debug_dump_internals *cmd =
4973 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4974 struct i40e_aqc_debug_dump_internals *resp =
4975 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4976 enum i40e_status_code status;
4978 if (buff_size == 0 || !buff)
4979 return I40E_ERR_PARAM;
4981 i40e_fill_default_direct_cmd_desc(&desc,
4982 i40e_aqc_opc_debug_dump_internals);
4983 /* Indirect Command */
4984 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4985 if (buff_size > I40E_AQ_LARGE_BUF)
4986 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4988 cmd->cluster_id = cluster_id;
4989 cmd->table_id = table_id;
4990 cmd->idx = CPU_TO_LE32(start_index);
4992 desc.datalen = CPU_TO_LE16(buff_size);
4994 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4996 if (ret_buff_size != NULL)
4997 *ret_buff_size = LE16_TO_CPU(desc.datalen);
4998 if (ret_next_table != NULL)
4999 *ret_next_table = resp->table_id;
5000 if (ret_next_index != NULL)
5001 *ret_next_index = LE32_TO_CPU(resp->idx);
5008 * i40e_read_bw_from_alt_ram
5009 * @hw: pointer to the hardware structure
5010 * @max_bw: pointer for max_bw read
5011 * @min_bw: pointer for min_bw read
5012 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value
5013 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value
5015 * Read bw from the alternate ram for the given pf
5017 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5018 u32 *max_bw, u32 *min_bw,
5019 bool *min_valid, bool *max_valid)
5021 enum i40e_status_code status;
5022 u32 max_bw_addr, min_bw_addr;
5024 /* Calculate the address of the min/max bw registers */
5025 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5026 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5027 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5028 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5029 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5030 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5032 /* Read the bandwidths from alt ram */
5033 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5034 min_bw_addr, min_bw);
5036 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5041 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5050 * i40e_aq_configure_partition_bw
5051 * @hw: pointer to the hardware structure
5052 * @bw_data: Buffer holding valid pfs and bw limits
5053 * @cmd_details: pointer to command details
5055 * Configure partitions guaranteed/max bw
5057 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5058 struct i40e_aqc_configure_partition_bw_data *bw_data,
5059 struct i40e_asq_cmd_details *cmd_details)
5061 enum i40e_status_code status;
5062 struct i40e_aq_desc desc;
5063 u16 bwd_size = sizeof(*bw_data);
5065 i40e_fill_default_direct_cmd_desc(&desc,
5066 i40e_aqc_opc_configure_partition_bw);
5068 /* Indirect command */
5069 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5070 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5072 if (bwd_size > I40E_AQ_LARGE_BUF)
5073 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5075 desc.datalen = CPU_TO_LE16(bwd_size);
5077 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5083 * i40e_aq_send_msg_to_pf
5084 * @hw: pointer to the hardware structure
5085 * @v_opcode: opcodes for VF-PF communication
5086 * @v_retval: return error code
5087 * @msg: pointer to the msg buffer
5088 * @msglen: msg length
5089 * @cmd_details: pointer to command details
5091 * Send message to PF driver using admin queue. By default, this message
5092 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5093 * completion before returning.
5095 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5096 enum i40e_virtchnl_ops v_opcode,
5097 enum i40e_status_code v_retval,
5098 u8 *msg, u16 msglen,
5099 struct i40e_asq_cmd_details *cmd_details)
5101 struct i40e_aq_desc desc;
5102 struct i40e_asq_cmd_details details;
5103 enum i40e_status_code status;
5105 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5106 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5107 desc.cookie_high = CPU_TO_LE32(v_opcode);
5108 desc.cookie_low = CPU_TO_LE32(v_retval);
5110 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5111 | I40E_AQ_FLAG_RD));
5112 if (msglen > I40E_AQ_LARGE_BUF)
5113 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5114 desc.datalen = CPU_TO_LE16(msglen);
5117 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5118 details.async = TRUE;
5119 cmd_details = &details;
5121 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5122 msglen, cmd_details);
5127 * i40e_vf_parse_hw_config
5128 * @hw: pointer to the hardware structure
5129 * @msg: pointer to the virtual channel VF resource structure
5131 * Given a VF resource message from the PF, populate the hw struct
5132 * with appropriate information.
5134 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5135 struct i40e_virtchnl_vf_resource *msg)
5137 struct i40e_virtchnl_vsi_resource *vsi_res;
5140 vsi_res = &msg->vsi_res[0];
5142 hw->dev_caps.num_vsis = msg->num_vsis;
5143 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5144 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5145 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5146 hw->dev_caps.dcb = msg->vf_offload_flags &
5147 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5148 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5149 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5150 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5151 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5152 for (i = 0; i < msg->num_vsis; i++) {
5153 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5154 i40e_memcpy(hw->mac.perm_addr,
5155 vsi_res->default_mac_addr,
5156 I40E_ETH_LENGTH_OF_ADDRESS,
5157 I40E_NONDMA_TO_NONDMA);
5158 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5159 I40E_ETH_LENGTH_OF_ADDRESS,
5160 I40E_NONDMA_TO_NONDMA);
5168 * @hw: pointer to the hardware structure
5170 * Send a VF_RESET message to the PF. Does not wait for response from PF
5171 * as none will be forthcoming. Immediately after calling this function,
5172 * the admin queue should be shut down and (optionally) reinitialized.
5174 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5176 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5177 I40E_SUCCESS, NULL, 0, NULL);