sys/dev/ixl/i40e_type.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _I40E_TYPE_H_
  36 #define _I40E_TYPE_H_
  37
  38 #include "i40e_status.h"
  39 #include "i40e_osdep.h"
  40 #include "i40e_register.h"
  41 #include "i40e_adminq.h"
  42 #include "i40e_hmc.h"
  43 #include "i40e_lan_hmc.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46
  47 /* Vendor ID */
  48 #define I40E_INTEL_VENDOR_ID            0x8086
  49
  50 /* Device IDs */
  51 #define I40E_DEV_ID_SFP_XL710           0x1572
  52 #define I40E_DEV_ID_QEMU                0x1574
  53 #define I40E_DEV_ID_KX_A                0x157F
  54 #define I40E_DEV_ID_KX_B                0x1580
  55 #define I40E_DEV_ID_KX_C                0x1581
  56 #define I40E_DEV_ID_QSFP_A              0x1583
  57 #define I40E_DEV_ID_QSFP_B              0x1584
  58 #define I40E_DEV_ID_QSFP_C              0x1585
  59 #define I40E_DEV_ID_10G_BASE_T          0x1586
  60 #define I40E_DEV_ID_20G_KR2             0x1587
  61 #define I40E_DEV_ID_VF                  0x154C
  62 #define I40E_DEV_ID_VF_HV               0x1571
  63
  64 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  65                                          (d) == I40E_DEV_ID_QSFP_B  || \
  66                                          (d) == I40E_DEV_ID_QSFP_C)
  67
  68 #ifndef I40E_MASK
  69 /* I40E_MASK is a macro used on 32 bit registers */
  70 #define I40E_MASK(mask, shift) (mask << shift)
  71 #endif
  72
  73 #define I40E_MAX_PF                     16
  74 #define I40E_MAX_PF_VSI                 64
  75 #define I40E_MAX_PF_QP                  128
  76 #define I40E_MAX_VSI_QP                 16
  77 #define I40E_MAX_VF_VSI                 3
  78 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  79 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  80
  81 /* something less than 1 minute */
  82 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  83
  84 /* Max default timeout in ms, */
  85 #define I40E_MAX_NVM_TIMEOUT            18000
  86
  87 /* Check whether address is multicast. */
  88 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  89
  90 /* Check whether an address is broadcast. */
  91 #define I40E_IS_BROADCAST(address)      \
  92         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  93         (((u8 *)(address))[1] == ((u8)0xff)))
  94
  95 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  96 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  97
  98 /* forward declaration */
  99 struct i40e_hw;
 100 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
 101
 102 #define I40E_ETH_LENGTH_OF_ADDRESS      6
 103 /* Data type manipulation macros. */
 104 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 105 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 106
 107 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 108 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 109
 110 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 111 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 112
 113 /* Number of Transmit Descriptors must be a multiple of 8. */
 114 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 115 /* Number of Receive Descriptors must be a multiple of 32 if
 116  * the number of descriptors is greater than 32.
 117  */
 118 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 119
 120 #define I40E_DESC_UNUSED(R)     \
 121         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 122         (R)->next_to_clean - (R)->next_to_use - 1)
 123
 124 /* bitfields for Tx queue mapping in QTX_CTL */
 125 #define I40E_QTX_CTL_VF_QUEUE   0x0
 126 #define I40E_QTX_CTL_VM_QUEUE   0x1
 127 #define I40E_QTX_CTL_PF_QUEUE   0x2
 128
 129 /* debug masks - set these bits in hw->debug_mask to control output */
 130 enum i40e_debug_mask {
 131         I40E_DEBUG_INIT                 = 0x00000001,
 132         I40E_DEBUG_RELEASE              = 0x00000002,
 133
 134         I40E_DEBUG_LINK                 = 0x00000010,
 135         I40E_DEBUG_PHY                  = 0x00000020,
 136         I40E_DEBUG_HMC                  = 0x00000040,
 137         I40E_DEBUG_NVM                  = 0x00000080,
 138         I40E_DEBUG_LAN                  = 0x00000100,
 139         I40E_DEBUG_FLOW                 = 0x00000200,
 140         I40E_DEBUG_DCB                  = 0x00000400,
 141         I40E_DEBUG_DIAG                 = 0x00000800,
 142         I40E_DEBUG_FD                   = 0x00001000,
 143
 144         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 145         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 146         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 147         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 148         I40E_DEBUG_AQ                   = 0x0F000000,
 149
 150         I40E_DEBUG_USER                 = 0xF0000000,
 151
 152         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 153 };
 154
 155 /* PCI Bus Info */
 156 #define I40E_PCI_LINK_STATUS            0xB2
 157 #define I40E_PCI_LINK_WIDTH             0x3F0
 158 #define I40E_PCI_LINK_WIDTH_1           0x10
 159 #define I40E_PCI_LINK_WIDTH_2           0x20
 160 #define I40E_PCI_LINK_WIDTH_4           0x40
 161 #define I40E_PCI_LINK_WIDTH_8           0x80
 162 #define I40E_PCI_LINK_SPEED             0xF
 163 #define I40E_PCI_LINK_SPEED_2500        0x1
 164 #define I40E_PCI_LINK_SPEED_5000        0x2
 165 #define I40E_PCI_LINK_SPEED_8000        0x3
 166
 167 /* Memory types */
 168 enum i40e_memset_type {
 169         I40E_NONDMA_MEM = 0,
 170         I40E_DMA_MEM
 171 };
 172
 173 /* Memcpy types */
 174 enum i40e_memcpy_type {
 175         I40E_NONDMA_TO_NONDMA = 0,
 176         I40E_NONDMA_TO_DMA,
 177         I40E_DMA_TO_DMA,
 178         I40E_DMA_TO_NONDMA
 179 };
 180
 181 /* These are structs for managing the hardware information and the operations.
 182  * The structures of function pointers are filled out at init time when we
 183  * know for sure exactly which hardware we're working with.  This gives us the
 184  * flexibility of using the same main driver code but adapting to slightly
 185  * different hardware needs as new parts are developed.  For this architecture,
 186  * the Firmware and AdminQ are intended to insulate the driver from most of the
 187  * future changes, but these structures will also do part of the job.
 188  */
 189 enum i40e_mac_type {
 190         I40E_MAC_UNKNOWN = 0,
 191         I40E_MAC_X710,
 192         I40E_MAC_XL710,
 193         I40E_MAC_VF,
 194         I40E_MAC_GENERIC,
 195 };
 196
 197 enum i40e_media_type {
 198         I40E_MEDIA_TYPE_UNKNOWN = 0,
 199         I40E_MEDIA_TYPE_FIBER,
 200         I40E_MEDIA_TYPE_BASET,
 201         I40E_MEDIA_TYPE_BACKPLANE,
 202         I40E_MEDIA_TYPE_CX4,
 203         I40E_MEDIA_TYPE_DA,
 204         I40E_MEDIA_TYPE_VIRTUAL
 205 };
 206
 207 enum i40e_fc_mode {
 208         I40E_FC_NONE = 0,
 209         I40E_FC_RX_PAUSE,
 210         I40E_FC_TX_PAUSE,
 211         I40E_FC_FULL,
 212         I40E_FC_PFC,
 213         I40E_FC_DEFAULT
 214 };
 215
 216 enum i40e_set_fc_aq_failures {
 217         I40E_SET_FC_AQ_FAIL_NONE = 0,
 218         I40E_SET_FC_AQ_FAIL_GET = 1,
 219         I40E_SET_FC_AQ_FAIL_SET = 2,
 220         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 221         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 222 };
 223
 224 enum i40e_vsi_type {
 225         I40E_VSI_MAIN = 0,
 226         I40E_VSI_VMDQ1,
 227         I40E_VSI_VMDQ2,
 228         I40E_VSI_CTRL,
 229         I40E_VSI_FCOE,
 230         I40E_VSI_MIRROR,
 231         I40E_VSI_SRIOV,
 232         I40E_VSI_FDIR,
 233         I40E_VSI_TYPE_UNKNOWN
 234 };
 235
 236 enum i40e_queue_type {
 237         I40E_QUEUE_TYPE_RX = 0,
 238         I40E_QUEUE_TYPE_TX,
 239         I40E_QUEUE_TYPE_PE_CEQ,
 240         I40E_QUEUE_TYPE_UNKNOWN
 241 };
 242
 243 struct i40e_link_status {
 244         enum i40e_aq_phy_type phy_type;
 245         enum i40e_aq_link_speed link_speed;
 246         u8 link_info;
 247         u8 an_info;
 248         u8 ext_info;
 249         u8 loopback;
 250         /* is Link Status Event notification to SW enabled */
 251         bool lse_enable;
 252         u16 max_frame_size;
 253         bool crc_enable;
 254         u8 pacing;
 255         u8 requested_speeds;
 256 };
 257
 258 struct i40e_phy_info {
 259         struct i40e_link_status link_info;
 260         struct i40e_link_status link_info_old;
 261         u32 autoneg_advertised;
 262         u32 phy_id;
 263         u32 module_type;
 264         bool get_link_info;
 265         enum i40e_media_type media_type;
 266 };
 267
 268 #define I40E_HW_CAP_MAX_GPIO                    30
 269 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 270 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 271
 272 /* Capabilities of a PF or a VF or the whole device */
 273 struct i40e_hw_capabilities {
 274         u32  switch_mode;
 275 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 276 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 277 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 278
 279         u32  management_mode;
 280         u32  npar_enable;
 281         u32  os2bmc;
 282         u32  valid_functions;
 283         bool sr_iov_1_1;
 284         bool vmdq;
 285         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 286         bool evb_802_1_qbh; /* Bridge Port Extension */
 287         bool dcb;
 288         bool fcoe;
 289         bool iscsi; /* Indicates iSCSI enabled */
 290         bool mfp_mode_1;
 291         bool mgmt_cem;
 292         bool ieee_1588;
 293         bool iwarp;
 294         bool fd;
 295         u32 fd_filters_guaranteed;
 296         u32 fd_filters_best_effort;
 297         bool rss;
 298         u32 rss_table_size;
 299         u32 rss_table_entry_width;
 300         bool led[I40E_HW_CAP_MAX_GPIO];
 301         bool sdp[I40E_HW_CAP_MAX_GPIO];
 302         u32 nvm_image_type;
 303         u32 num_flow_director_filters;
 304         u32 num_vfs;
 305         u32 vf_base_id;
 306         u32 num_vsis;
 307         u32 num_rx_qp;
 308         u32 num_tx_qp;
 309         u32 base_queue;
 310         u32 num_msix_vectors;
 311         u32 num_msix_vectors_vf;
 312         u32 led_pin_num;
 313         u32 sdp_pin_num;
 314         u32 mdio_port_num;
 315         u32 mdio_port_mode;
 316         u8 rx_buf_chain_len;
 317         u32 enabled_tcmap;
 318         u32 maxtc;
 319 };
 320
 321 struct i40e_mac_info {
 322         enum i40e_mac_type type;
 323         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 324         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 325         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 326         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 327         u16 max_fcoeq;
 328 };
 329
 330 enum i40e_aq_resources_ids {
 331         I40E_NVM_RESOURCE_ID = 1
 332 };
 333
 334 enum i40e_aq_resource_access_type {
 335         I40E_RESOURCE_READ = 1,
 336         I40E_RESOURCE_WRITE
 337 };
 338
 339 struct i40e_nvm_info {
 340         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 341         u32 timeout;              /* [ms] */
 342         u16 sr_size;              /* Shadow RAM size in words */
 343         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 344         u16 version;              /* NVM package version */
 345         u32 eetrack;              /* NVM data version */
 346 };
 347
 348 /* definitions used in NVM update support */
 349
 350 enum i40e_nvmupd_cmd {
 351         I40E_NVMUPD_INVALID,
 352         I40E_NVMUPD_READ_CON,
 353         I40E_NVMUPD_READ_SNT,
 354         I40E_NVMUPD_READ_LCB,
 355         I40E_NVMUPD_READ_SA,
 356         I40E_NVMUPD_WRITE_ERA,
 357         I40E_NVMUPD_WRITE_CON,
 358         I40E_NVMUPD_WRITE_SNT,
 359         I40E_NVMUPD_WRITE_LCB,
 360         I40E_NVMUPD_WRITE_SA,
 361         I40E_NVMUPD_CSUM_CON,
 362         I40E_NVMUPD_CSUM_SA,
 363         I40E_NVMUPD_CSUM_LCB,
 364 };
 365
 366 enum i40e_nvmupd_state {
 367         I40E_NVMUPD_STATE_INIT,
 368         I40E_NVMUPD_STATE_READING,
 369         I40E_NVMUPD_STATE_WRITING
 370 };
 371
 372 /* nvm_access definition and its masks/shifts need to be accessible to
 373  * application, core driver, and shared code.  Where is the right file?
 374  */
 375 #define I40E_NVM_READ   0xB
 376 #define I40E_NVM_WRITE  0xC
 377
 378 #define I40E_NVM_MOD_PNT_MASK 0xFF
 379
 380 #define I40E_NVM_TRANS_SHIFT    8
 381 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 382 #define I40E_NVM_CON            0x0
 383 #define I40E_NVM_SNT            0x1
 384 #define I40E_NVM_LCB            0x2
 385 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 386 #define I40E_NVM_ERA            0x4
 387 #define I40E_NVM_CSUM           0x8
 388
 389 #define I40E_NVM_ADAPT_SHIFT    16
 390 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 391
 392 #define I40E_NVMUPD_MAX_DATA    4096
 393 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 394
 395 struct i40e_nvm_access {
 396         u32 command;
 397         u32 config;
 398         u32 offset;     /* in bytes */
 399         u32 data_size;  /* in bytes */
 400         u8 data[1];
 401 };
 402
 403 /* PCI bus types */
 404 enum i40e_bus_type {
 405         i40e_bus_type_unknown = 0,
 406         i40e_bus_type_pci,
 407         i40e_bus_type_pcix,
 408         i40e_bus_type_pci_express,
 409         i40e_bus_type_reserved
 410 };
 411
 412 /* PCI bus speeds */
 413 enum i40e_bus_speed {
 414         i40e_bus_speed_unknown  = 0,
 415         i40e_bus_speed_33       = 33,
 416         i40e_bus_speed_66       = 66,
 417         i40e_bus_speed_100      = 100,
 418         i40e_bus_speed_120      = 120,
 419         i40e_bus_speed_133      = 133,
 420         i40e_bus_speed_2500     = 2500,
 421         i40e_bus_speed_5000     = 5000,
 422         i40e_bus_speed_8000     = 8000,
 423         i40e_bus_speed_reserved
 424 };
 425
 426 /* PCI bus widths */
 427 enum i40e_bus_width {
 428         i40e_bus_width_unknown  = 0,
 429         i40e_bus_width_pcie_x1  = 1,
 430         i40e_bus_width_pcie_x2  = 2,
 431         i40e_bus_width_pcie_x4  = 4,
 432         i40e_bus_width_pcie_x8  = 8,
 433         i40e_bus_width_32       = 32,
 434         i40e_bus_width_64       = 64,
 435         i40e_bus_width_reserved
 436 };
 437
 438 /* Bus parameters */
 439 struct i40e_bus_info {
 440         enum i40e_bus_speed speed;
 441         enum i40e_bus_width width;
 442         enum i40e_bus_type type;
 443
 444         u16 func;
 445         u16 device;
 446         u16 lan_id;
 447 };
 448
 449 /* Flow control (FC) parameters */
 450 struct i40e_fc_info {
 451         enum i40e_fc_mode current_mode; /* FC mode in effect */
 452         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 453 };
 454
 455 #define I40E_MAX_TRAFFIC_CLASS          8
 456 #define I40E_MAX_USER_PRIORITY          8
 457 #define I40E_DCBX_MAX_APPS              32
 458 #define I40E_LLDPDU_SIZE                1500
 459 #define I40E_TLV_STATUS_OPER            0x1
 460 #define I40E_TLV_STATUS_SYNC            0x2
 461 #define I40E_TLV_STATUS_ERR             0x4
 462 #define I40E_CEE_OPER_MAX_APPS          3
 463 #define I40E_APP_PROTOID_FCOE           0x8906
 464 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 465 #define I40E_APP_PROTOID_FIP            0x8914
 466 #define I40E_APP_SEL_ETHTYPE            0x1
 467 #define I40E_APP_SEL_TCPIP              0x2
 468
 469 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 470 struct i40e_dcb_ets_config {
 471         u8 willing;
 472         u8 cbs;
 473         u8 maxtcs;
 474         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 475         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 476         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 477 };
 478
 479 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 480 struct i40e_dcb_pfc_config {
 481         u8 willing;
 482         u8 mbc;
 483         u8 pfccap;
 484         u8 pfcenable;
 485 };
 486
 487 /* CEE or IEEE 802.1Qaz Application Priority data */
 488 struct i40e_dcb_app_priority_table {
 489         u8  priority;
 490         u8  selector;
 491         u16 protocolid;
 492 };
 493
 494 struct i40e_dcbx_config {
 495         u8  dcbx_mode;
 496 #define I40E_DCBX_MODE_CEE      0x1
 497 #define I40E_DCBX_MODE_IEEE     0x2
 498         u32 numapps;
 499         struct i40e_dcb_ets_config etscfg;
 500         struct i40e_dcb_ets_config etsrec;
 501         struct i40e_dcb_pfc_config pfc;
 502         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 503 };
 504
 505 /* Port hardware description */
 506 struct i40e_hw {
 507         u8 *hw_addr;
 508         void *back;
 509
 510         /* subsystem structs */
 511         struct i40e_phy_info phy;
 512         struct i40e_mac_info mac;
 513         struct i40e_bus_info bus;
 514         struct i40e_nvm_info nvm;
 515         struct i40e_fc_info fc;
 516
 517         /* pci info */
 518         u16 device_id;
 519         u16 vendor_id;
 520         u16 subsystem_device_id;
 521         u16 subsystem_vendor_id;
 522         u8 revision_id;
 523         u8 port;
 524         bool adapter_stopped;
 525
 526         /* capabilities for entire device and PCI func */
 527         struct i40e_hw_capabilities dev_caps;
 528         struct i40e_hw_capabilities func_caps;
 529
 530         /* Flow Director shared filter space */
 531         u16 fdir_shared_filter_count;
 532
 533         /* device profile info */
 534         u8  pf_id;
 535         u16 main_vsi_seid;
 536
 537         /* for multi-function MACs */
 538         u16 partition_id;
 539         u16 num_partitions;
 540         u16 num_ports;
 541
 542         /* Closest numa node to the device */
 543         u16 numa_node;
 544
 545         /* Admin Queue info */
 546         struct i40e_adminq_info aq;
 547
 548         /* state of nvm update process */
 549         enum i40e_nvmupd_state nvmupd_state;
 550
 551         /* HMC info */
 552         struct i40e_hmc_info hmc; /* HMC info struct */
 553
 554         /* LLDP/DCBX Status */
 555         u16 dcbx_status;
 556
 557         /* DCBX info */
 558         struct i40e_dcbx_config local_dcbx_config;
 559         struct i40e_dcbx_config remote_dcbx_config;
 560
 561         /* debug mask */
 562         u32 debug_mask;
 563 };
 564
 565 static inline bool i40e_is_vf(struct i40e_hw *hw)
 566 {
 567         return hw->mac.type == I40E_MAC_VF;
 568 }
 569
 570 struct i40e_driver_version {
 571         u8 major_version;
 572         u8 minor_version;
 573         u8 build_version;
 574         u8 subbuild_version;
 575         u8 driver_string[32];
 576 };
 577
 578 /* RX Descriptors */
 579 union i40e_16byte_rx_desc {
 580         struct {
 581                 __le64 pkt_addr; /* Packet buffer address */
 582                 __le64 hdr_addr; /* Header buffer address */
 583         } read;
 584         struct {
 585                 struct {
 586                         struct {
 587                                 union {
 588                                         __le16 mirroring_status;
 589                                         __le16 fcoe_ctx_id;
 590                                 } mirr_fcoe;
 591                                 __le16 l2tag1;
 592                         } lo_dword;
 593                         union {
 594                                 __le32 rss; /* RSS Hash */
 595                                 __le32 fd_id; /* Flow director filter id */
 596                                 __le32 fcoe_param; /* FCoE DDP Context id */
 597                         } hi_dword;
 598                 } qword0;
 599                 struct {
 600                         /* ext status/error/pktype/length */
 601                         __le64 status_error_len;
 602                 } qword1;
 603         } wb;  /* writeback */
 604 };
 605
 606 union i40e_32byte_rx_desc {
 607         struct {
 608                 __le64  pkt_addr; /* Packet buffer address */
 609                 __le64  hdr_addr; /* Header buffer address */
 610                         /* bit 0 of hdr_buffer_addr is DD bit */
 611                 __le64  rsvd1;
 612                 __le64  rsvd2;
 613         } read;
 614         struct {
 615                 struct {
 616                         struct {
 617                                 union {
 618                                         __le16 mirroring_status;
 619                                         __le16 fcoe_ctx_id;
 620                                 } mirr_fcoe;
 621                                 __le16 l2tag1;
 622                         } lo_dword;
 623                         union {
 624                                 __le32 rss; /* RSS Hash */
 625                                 __le32 fcoe_param; /* FCoE DDP Context id */
 626                                 /* Flow director filter id in case of
 627                                  * Programming status desc WB
 628                                  */
 629                                 __le32 fd_id;
 630                         } hi_dword;
 631                 } qword0;
 632                 struct {
 633                         /* status/error/pktype/length */
 634                         __le64 status_error_len;
 635                 } qword1;
 636                 struct {
 637                         __le16 ext_status; /* extended status */
 638                         __le16 rsvd;
 639                         __le16 l2tag2_1;
 640                         __le16 l2tag2_2;
 641                 } qword2;
 642                 struct {
 643                         union {
 644                                 __le32 flex_bytes_lo;
 645                                 __le32 pe_status;
 646                         } lo_dword;
 647                         union {
 648                                 __le32 flex_bytes_hi;
 649                                 __le32 fd_id;
 650                         } hi_dword;
 651                 } qword3;
 652         } wb;  /* writeback */
 653 };
 654
 655 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 656 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 657                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 658 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 659 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 660                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 661
 662 enum i40e_rx_desc_status_bits {
 663         /* Note: These are predefined bit offsets */
 664         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 665         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 666         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 667         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 668         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 669         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 670         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 671         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 672
 673         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 674         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 675         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 676         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 677         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 678         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 679         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 680         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 681 };
 682
 683 #define I40E_RXD_QW1_STATUS_SHIFT       0
 684 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 685                                          I40E_RXD_QW1_STATUS_SHIFT)
 686
 687 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 688 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 689                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 690
 691 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 692 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 693                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 694
 695 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 696 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 697                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 698
 699 enum i40e_rx_desc_fltstat_values {
 700         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 701         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 702         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 703         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 704 };
 705
 706 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 707 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 708 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 709 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 710
 711 #define I40E_RXD_QW1_ERROR_SHIFT        19
 712 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 713
 714 enum i40e_rx_desc_error_bits {
 715         /* Note: These are predefined bit offsets */
 716         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 717         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 718         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 719         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 720         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 721         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 722         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 723         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 724         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 725 };
 726
 727 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 728         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 729         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 730         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 731         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 732         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 733 };
 734
 735 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 736 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 737
 738 /* Packet type non-ip values */
 739 enum i40e_rx_l2_ptype {
 740         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 741         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 742         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 743         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 744         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 745         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 746         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 747         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 748         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 749         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 750         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 751         I40E_RX_PTYPE_L2_ARP                            = 11,
 752         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 753         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 754         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 755         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 756         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 757         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 758         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 759         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 760         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 761         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 762         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 763         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 764         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 765         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 766 };
 767
 768 struct i40e_rx_ptype_decoded {
 769         u32 ptype:8;
 770         u32 known:1;
 771         u32 outer_ip:1;
 772         u32 outer_ip_ver:1;
 773         u32 outer_frag:1;
 774         u32 tunnel_type:3;
 775         u32 tunnel_end_prot:2;
 776         u32 tunnel_end_frag:1;
 777         u32 inner_prot:4;
 778         u32 payload_layer:3;
 779 };
 780
 781 enum i40e_rx_ptype_outer_ip {
 782         I40E_RX_PTYPE_OUTER_L2  = 0,
 783         I40E_RX_PTYPE_OUTER_IP  = 1
 784 };
 785
 786 enum i40e_rx_ptype_outer_ip_ver {
 787         I40E_RX_PTYPE_OUTER_NONE        = 0,
 788         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 789         I40E_RX_PTYPE_OUTER_IPV6        = 1
 790 };
 791
 792 enum i40e_rx_ptype_outer_fragmented {
 793         I40E_RX_PTYPE_NOT_FRAG  = 0,
 794         I40E_RX_PTYPE_FRAG      = 1
 795 };
 796
 797 enum i40e_rx_ptype_tunnel_type {
 798         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 799         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 800         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 801         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 802         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 803 };
 804
 805 enum i40e_rx_ptype_tunnel_end_prot {
 806         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 807         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 808         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 809 };
 810
 811 enum i40e_rx_ptype_inner_prot {
 812         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 813         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 814         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 815         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 816         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 817         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 818 };
 819
 820 enum i40e_rx_ptype_payload_layer {
 821         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 822         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 823         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 824         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 825 };
 826
 827 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 828 #define I40E_RX_PTYPE_SHIFT             56
 829
 830 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 831 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 832                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 833
 834 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 835 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 836                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 837
 838 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 839 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 840                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 841
 842 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 843 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 844
 845 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 846 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 847                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 848
 849 enum i40e_rx_desc_ext_status_bits {
 850         /* Note: These are predefined bit offsets */
 851         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 852         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 853         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 854         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 855         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 856         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 857         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 858 };
 859
 860 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 861 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 862
 863 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 864 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 865
 866 enum i40e_rx_desc_pe_status_bits {
 867         /* Note: These are predefined bit offsets */
 868         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 869         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 870         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 871         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 872         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 873         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 874         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 875         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 876         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 877 };
 878
 879 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 880 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 881
 882 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 883 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 884                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 885
 886 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 887 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 888                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 889
 890 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 891 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 892                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 893
 894 enum i40e_rx_prog_status_desc_status_bits {
 895         /* Note: These are predefined bit offsets */
 896         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 897         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 898 };
 899
 900 enum i40e_rx_prog_status_desc_prog_id_masks {
 901         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 902         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 903         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 904 };
 905
 906 enum i40e_rx_prog_status_desc_error_bits {
 907         /* Note: These are predefined bit offsets */
 908         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 909         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 910         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 911         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 912 };
 913
 914 #define I40E_TWO_BIT_MASK       0x3
 915 #define I40E_THREE_BIT_MASK     0x7
 916 #define I40E_FOUR_BIT_MASK      0xF
 917 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 918
 919 /* TX Descriptor */
 920 struct i40e_tx_desc {
 921         __le64 buffer_addr; /* Address of descriptor's data buf */
 922         __le64 cmd_type_offset_bsz;
 923 };
 924
 925 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 926 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 927
 928 enum i40e_tx_desc_dtype_value {
 929         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 930         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 931         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 932         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 933         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 934         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 935         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 936         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 937         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 938         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 939 };
 940
 941 #define I40E_TXD_QW1_CMD_SHIFT  4
 942 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 943
 944 enum i40e_tx_desc_cmd_bits {
 945         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 946         I40E_TX_DESC_CMD_RS                     = 0x0002,
 947         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 948         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 949         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 950         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 951         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 952         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 953         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 954         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 955         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 956         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 957         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 958         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 959         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 960         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 961         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 962         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 963 };
 964
 965 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 966 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 967                                          I40E_TXD_QW1_OFFSET_SHIFT)
 968
 969 enum i40e_tx_desc_length_fields {
 970         /* Note: These are predefined bit offsets */
 971         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 972         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 973         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 974 };
 975
 976 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 977 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 978 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 979 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 980
 981 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 982 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 983                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 984
 985 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 986 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 987
 988 /* Context descriptors */
 989 struct i40e_tx_context_desc {
 990         __le32 tunneling_params;
 991         __le16 l2tag2;
 992         __le16 rsvd;
 993         __le64 type_cmd_tso_mss;
 994 };
 995
 996 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 997 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 998
 999 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1000 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1001
1002 enum i40e_tx_ctx_desc_cmd_bits {
1003         I40E_TX_CTX_DESC_TSO            = 0x01,
1004         I40E_TX_CTX_DESC_TSYN           = 0x02,
1005         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1006         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1007         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1008         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1009         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1010         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1011         I40E_TX_CTX_DESC_SWPE           = 0x40
1012 };
1013
1014 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1015 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1016                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1017
1018 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1019 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1020                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1021
1022 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1023 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1024
1025 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1026 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1027                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1028
1029 enum i40e_tx_ctx_desc_eipt_offload {
1030         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1031         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1032         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1033         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1034 };
1035
1036 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1037 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1038                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1039
1040 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1041 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1042
1043 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1044 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1045
1046 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1047 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1048                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1049
1050 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1051
1052 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1053 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1054                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1055
1056 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1057 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1058                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1059
1060 struct i40e_nop_desc {
1061         __le64 rsvd;
1062         __le64 dtype_cmd;
1063 };
1064
1065 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1066 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1067
1068 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1069 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1070
1071 enum i40e_tx_nop_desc_cmd_bits {
1072         /* Note: These are predefined bit offsets */
1073         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1074         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1075         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1076 };
1077
1078 struct i40e_filter_program_desc {
1079         __le32 qindex_flex_ptype_vsi;
1080         __le32 rsvd;
1081         __le32 dtype_cmd_cntindex;
1082         __le32 fd_id;
1083 };
1084 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1085 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1086                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1087 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1088 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1089                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1090 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1091 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1092                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1093
1094 /* Packet Classifier Types for filters */
1095 enum i40e_filter_pctype {
1096         /* Note: Values 0-30 are reserved for future use */
1097         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1098         /* Note: Value 32 is reserved for future use */
1099         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1100         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1101         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1102         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1103         /* Note: Values 37-40 are reserved for future use */
1104         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1105         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1106         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1107         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1108         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1109         /* Note: Value 47 is reserved for future use */
1110         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1111         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1112         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1113         /* Note: Values 51-62 are reserved for future use */
1114         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1115 };
1116
1117 enum i40e_filter_program_desc_dest {
1118         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1119         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1120         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1121 };
1122
1123 enum i40e_filter_program_desc_fd_status {
1124         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1125         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1126         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1127         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1128 };
1129
1130 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1131 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1132                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1133
1134 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1135 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1136
1137 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1138 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1139                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1140
1141 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1142 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1143
1144 enum i40e_filter_program_desc_pcmd {
1145         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1146         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1147 };
1148
1149 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1150 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1151
1152 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1153 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1154                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1155
1156 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1157                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1158 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1159                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1160
1161 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1162 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1163                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1164
1165 enum i40e_filter_type {
1166         I40E_FLOW_DIRECTOR_FLTR = 0,
1167         I40E_PE_QUAD_HASH_FLTR = 1,
1168         I40E_ETHERTYPE_FLTR,
1169         I40E_FCOE_CTX_FLTR,
1170         I40E_MAC_VLAN_FLTR,
1171         I40E_HASH_FLTR
1172 };
1173
1174 struct i40e_vsi_context {
1175         u16 seid;
1176         u16 uplink_seid;
1177         u16 vsi_number;
1178         u16 vsis_allocated;
1179         u16 vsis_unallocated;
1180         u16 flags;
1181         u8 pf_num;
1182         u8 vf_num;
1183         u8 connection_type;
1184         struct i40e_aqc_vsi_properties_data info;
1185 };
1186
1187 struct i40e_veb_context {
1188         u16 seid;
1189         u16 uplink_seid;
1190         u16 veb_number;
1191         u16 vebs_allocated;
1192         u16 vebs_unallocated;
1193         u16 flags;
1194         struct i40e_aqc_get_veb_parameters_completion info;
1195 };
1196
1197 /* Statistics collected by each port, VSI, VEB, and S-channel */
1198 struct i40e_eth_stats {
1199         u64 rx_bytes;                   /* gorc */
1200         u64 rx_unicast;                 /* uprc */
1201         u64 rx_multicast;               /* mprc */
1202         u64 rx_broadcast;               /* bprc */
1203         u64 rx_discards;                /* rdpc */
1204         u64 rx_unknown_protocol;        /* rupp */
1205         u64 tx_bytes;                   /* gotc */
1206         u64 tx_unicast;                 /* uptc */
1207         u64 tx_multicast;               /* mptc */
1208         u64 tx_broadcast;               /* bptc */
1209         u64 tx_discards;                /* tdpc */
1210         u64 tx_errors;                  /* tepc */
1211 };
1212
1213 /* Statistics collected per VEB per TC */
1214 struct i40e_veb_tc_stats {
1215         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1216         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1217         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1218         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1219 };
1220
1221 /* Statistics collected by the MAC */
1222 struct i40e_hw_port_stats {
1223         /* eth stats collected by the port */
1224         struct i40e_eth_stats eth;
1225
1226         /* additional port specific stats */
1227         u64 tx_dropped_link_down;       /* tdold */
1228         u64 crc_errors;                 /* crcerrs */
1229         u64 illegal_bytes;              /* illerrc */
1230         u64 error_bytes;                /* errbc */
1231         u64 mac_local_faults;           /* mlfc */
1232         u64 mac_remote_faults;          /* mrfc */
1233         u64 rx_length_errors;           /* rlec */
1234         u64 link_xon_rx;                /* lxonrxc */
1235         u64 link_xoff_rx;               /* lxoffrxc */
1236         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1237         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1238         u64 link_xon_tx;                /* lxontxc */
1239         u64 link_xoff_tx;               /* lxofftxc */
1240         u64 priority_xon_tx[8];         /* pxontxc[8] */
1241         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1242         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1243         u64 rx_size_64;                 /* prc64 */
1244         u64 rx_size_127;                /* prc127 */
1245         u64 rx_size_255;                /* prc255 */
1246         u64 rx_size_511;                /* prc511 */
1247         u64 rx_size_1023;               /* prc1023 */
1248         u64 rx_size_1522;               /* prc1522 */
1249         u64 rx_size_big;                /* prc9522 */
1250         u64 rx_undersize;               /* ruc */
1251         u64 rx_fragments;               /* rfc */
1252         u64 rx_oversize;                /* roc */
1253         u64 rx_jabber;                  /* rjc */
1254         u64 tx_size_64;                 /* ptc64 */
1255         u64 tx_size_127;                /* ptc127 */
1256         u64 tx_size_255;                /* ptc255 */
1257         u64 tx_size_511;                /* ptc511 */
1258         u64 tx_size_1023;               /* ptc1023 */
1259         u64 tx_size_1522;               /* ptc1522 */
1260         u64 tx_size_big;                /* ptc9522 */
1261         u64 mac_short_packet_dropped;   /* mspdc */
1262         u64 checksum_error;             /* xec */
1263         /* flow director stats */
1264         u64 fd_atr_match;
1265         u64 fd_sb_match;
1266         /* EEE LPI */
1267         u32 tx_lpi_status;
1268         u32 rx_lpi_status;
1269         u64 tx_lpi_count;               /* etlpic */
1270         u64 rx_lpi_count;               /* erlpic */
1271 };
1272
1273 /* Checksum and Shadow RAM pointers */
1274 #define I40E_SR_NVM_CONTROL_WORD                0x00
1275 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1276 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1277 #define I40E_SR_OPTION_ROM_PTR                  0x05
1278 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1279 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1280 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1281 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1282 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1283 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1284 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1285 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1286 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1287 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1288 #define I40E_SR_PBA_FLAGS                       0x15
1289 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1290 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1291 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1292 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1293 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1294 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1295 #define I40E_SR_NVM_MAP_VERSION                 0x29
1296 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1297 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1298 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1299 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1300 #define I40E_SR_VPD_PTR                         0x2F
1301 #define I40E_SR_PXE_SETUP_PTR                   0x30
1302 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1303 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1304 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1305 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1306 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1307 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1308 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1309 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1310 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1311 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1312 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1313 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1314 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1315 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1316 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1317 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1318 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1319 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1320
1321 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1322 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1323 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1324 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1325 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1326
1327 /* Shadow RAM related */
1328 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1329 #define I40E_SR_BUF_ALIGNMENT           4096
1330 #define I40E_SR_WORDS_IN_1KB            512
1331 /* Checksum should be calculated such that after adding all the words,
1332  * including the checksum word itself, the sum should be 0xBABA.
1333  */
1334 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1335
1336 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1337
1338 enum i40e_switch_element_types {
1339         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1340         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1341         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1342         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1343         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1344         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1345         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1346         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1347         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1348 };
1349
1350 /* Supported EtherType filters */
1351 enum i40e_ether_type_index {
1352         I40E_ETHER_TYPE_1588            = 0,
1353         I40E_ETHER_TYPE_FIP             = 1,
1354         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1355         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1356         I40E_ETHER_TYPE_LLDP            = 4,
1357         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1358         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1359         I40E_ETHER_TYPE_QCN_CNM         = 7,
1360         I40E_ETHER_TYPE_8021X           = 8,
1361         I40E_ETHER_TYPE_ARP             = 9,
1362         I40E_ETHER_TYPE_RSV1            = 10,
1363         I40E_ETHER_TYPE_RSV2            = 11,
1364 };
1365
1366 /* Filter context base size is 1K */
1367 #define I40E_HASH_FILTER_BASE_SIZE      1024
1368 /* Supported Hash filter values */
1369 enum i40e_hash_filter_size {
1370         I40E_HASH_FILTER_SIZE_1K        = 0,
1371         I40E_HASH_FILTER_SIZE_2K        = 1,
1372         I40E_HASH_FILTER_SIZE_4K        = 2,
1373         I40E_HASH_FILTER_SIZE_8K        = 3,
1374         I40E_HASH_FILTER_SIZE_16K       = 4,
1375         I40E_HASH_FILTER_SIZE_32K       = 5,
1376         I40E_HASH_FILTER_SIZE_64K       = 6,
1377         I40E_HASH_FILTER_SIZE_128K      = 7,
1378         I40E_HASH_FILTER_SIZE_256K      = 8,
1379         I40E_HASH_FILTER_SIZE_512K      = 9,
1380         I40E_HASH_FILTER_SIZE_1M        = 10,
1381 };
1382
1383 /* DMA context base size is 0.5K */
1384 #define I40E_DMA_CNTX_BASE_SIZE         512
1385 /* Supported DMA context values */
1386 enum i40e_dma_cntx_size {
1387         I40E_DMA_CNTX_SIZE_512          = 0,
1388         I40E_DMA_CNTX_SIZE_1K           = 1,
1389         I40E_DMA_CNTX_SIZE_2K           = 2,
1390         I40E_DMA_CNTX_SIZE_4K           = 3,
1391         I40E_DMA_CNTX_SIZE_8K           = 4,
1392         I40E_DMA_CNTX_SIZE_16K          = 5,
1393         I40E_DMA_CNTX_SIZE_32K          = 6,
1394         I40E_DMA_CNTX_SIZE_64K          = 7,
1395         I40E_DMA_CNTX_SIZE_128K         = 8,
1396         I40E_DMA_CNTX_SIZE_256K         = 9,
1397 };
1398
1399 /* Supported Hash look up table (LUT) sizes */
1400 enum i40e_hash_lut_size {
1401         I40E_HASH_LUT_SIZE_128          = 0,
1402         I40E_HASH_LUT_SIZE_512          = 1,
1403 };
1404
1405 /* Structure to hold a per PF filter control settings */
1406 struct i40e_filter_control_settings {
1407         /* number of PE Quad Hash filter buckets */
1408         enum i40e_hash_filter_size pe_filt_num;
1409         /* number of PE Quad Hash contexts */
1410         enum i40e_dma_cntx_size pe_cntx_num;
1411         /* number of FCoE filter buckets */
1412         enum i40e_hash_filter_size fcoe_filt_num;
1413         /* number of FCoE DDP contexts */
1414         enum i40e_dma_cntx_size fcoe_cntx_num;
1415         /* size of the Hash LUT */
1416         enum i40e_hash_lut_size hash_lut_size;
1417         /* enable FDIR filters for PF and its VFs */
1418         bool enable_fdir;
1419         /* enable Ethertype filters for PF and its VFs */
1420         bool enable_ethtype;
1421         /* enable MAC/VLAN filters for PF and its VFs */
1422         bool enable_macvlan;
1423 };
1424
1425 /* Structure to hold device level control filter counts */
1426 struct i40e_control_filter_stats {
1427         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1428         u16 etype_used;       /* Used perfect EtherType filters */
1429         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1430         u16 etype_free;       /* Un-used perfect EtherType filters */
1431 };
1432
1433 enum i40e_reset_type {
1434         I40E_RESET_POR          = 0,
1435         I40E_RESET_CORER        = 1,
1436         I40E_RESET_GLOBR        = 2,
1437         I40E_RESET_EMPR         = 3,
1438 };
1439
1440 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1441 #define I40E_NVM_LLDP_CFG_PTR           0xD
1442 struct i40e_lldp_variables {
1443         u16 length;
1444         u16 adminstatus;
1445         u16 msgfasttx;
1446         u16 msgtxinterval;
1447         u16 txparams;
1448         u16 timers;
1449         u16 crc8;
1450 };
1451
1452 /* Offsets into Alternate Ram */
1453 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1454 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1455 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1456 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1457 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1458 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1459
1460 /* Alternate Ram Bandwidth Masks */
1461 #define I40E_ALT_BW_VALUE_MASK          0xFF
1462 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1463 #define I40E_ALT_BW_VALID_MASK          0x80000000
1464
1465 /* RSS Hash Table Size */
1466 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1467 #endif /* _I40E_TYPE_H_ */