sys/dev/ixl/i40e_type.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _I40E_TYPE_H_
  36 #define _I40E_TYPE_H_
  37
  38 #include "i40e_status.h"
  39 #include "i40e_osdep.h"
  40 #include "i40e_register.h"
  41 #include "i40e_adminq.h"
  42 #include "i40e_hmc.h"
  43 #include "i40e_lan_hmc.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46
  47 /* Vendor ID */
  48 #define I40E_INTEL_VENDOR_ID            0x8086
  49
  50 /* Device IDs */
  51 #define I40E_DEV_ID_SFP_XL710           0x1572
  52 #define I40E_DEV_ID_QEMU                0x1574
  53 #define I40E_DEV_ID_KX_A                0x157F
  54 #define I40E_DEV_ID_KX_B                0x1580
  55 #define I40E_DEV_ID_KX_C                0x1581
  56 #define I40E_DEV_ID_QSFP_A              0x1583
  57 #define I40E_DEV_ID_QSFP_B              0x1584
  58 #define I40E_DEV_ID_QSFP_C              0x1585
  59 #define I40E_DEV_ID_10G_BASE_T          0x1586
  60 #define I40E_DEV_ID_20G_KR2             0x1587
  61 #define I40E_DEV_ID_VF                  0x154C
  62 #define I40E_DEV_ID_VF_HV               0x1571
  63
  64 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  65                                          (d) == I40E_DEV_ID_QSFP_B  || \
  66                                          (d) == I40E_DEV_ID_QSFP_C)
  67
  68 #ifndef I40E_MASK
  69 /* I40E_MASK is a macro used on 32 bit registers */
  70 #define I40E_MASK(mask, shift) (mask << shift)
  71 #endif
  72
  73 #define I40E_MAX_PF                     16
  74 #define I40E_MAX_PF_VSI                 64
  75 #define I40E_MAX_PF_QP                  128
  76 #define I40E_MAX_VSI_QP                 16
  77 #define I40E_MAX_VF_VSI                 3
  78 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  79 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  80
  81 /* something less than 1 minute */
  82 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  83
  84 /* Max default timeout in ms, */
  85 #define I40E_MAX_NVM_TIMEOUT            18000
  86
  87 /* Check whether address is multicast. */
  88 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  89
  90 /* Check whether an address is broadcast. */
  91 #define I40E_IS_BROADCAST(address)      \
  92         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  93         (((u8 *)(address))[1] == ((u8)0xff)))
  94
  95 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  96 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  97
  98 /* forward declaration */
  99 struct i40e_hw;
 100 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
 101
 102 #define I40E_ETH_LENGTH_OF_ADDRESS      6
 103 /* Data type manipulation macros. */
 104 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 105 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 106
 107 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 108 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 109
 110 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 111 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 112
 113 /* Number of Transmit Descriptors must be a multiple of 8. */
 114 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 115 /* Number of Receive Descriptors must be a multiple of 32 if
 116  * the number of descriptors is greater than 32.
 117  */
 118 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 119
 120 #define I40E_DESC_UNUSED(R)     \
 121         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 122         (R)->next_to_clean - (R)->next_to_use - 1)
 123
 124 /* bitfields for Tx queue mapping in QTX_CTL */
 125 #define I40E_QTX_CTL_VF_QUEUE   0x0
 126 #define I40E_QTX_CTL_VM_QUEUE   0x1
 127 #define I40E_QTX_CTL_PF_QUEUE   0x2
 128
 129 /* debug masks - set these bits in hw->debug_mask to control output */
 130 enum i40e_debug_mask {
 131         I40E_DEBUG_INIT                 = 0x00000001,
 132         I40E_DEBUG_RELEASE              = 0x00000002,
 133
 134         I40E_DEBUG_LINK                 = 0x00000010,
 135         I40E_DEBUG_PHY                  = 0x00000020,
 136         I40E_DEBUG_HMC                  = 0x00000040,
 137         I40E_DEBUG_NVM                  = 0x00000080,
 138         I40E_DEBUG_LAN                  = 0x00000100,
 139         I40E_DEBUG_FLOW                 = 0x00000200,
 140         I40E_DEBUG_DCB                  = 0x00000400,
 141         I40E_DEBUG_DIAG                 = 0x00000800,
 142         I40E_DEBUG_FD                   = 0x00001000,
 143
 144         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 145         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 146         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 147         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 148         I40E_DEBUG_AQ                   = 0x0F000000,
 149
 150         I40E_DEBUG_USER                 = 0xF0000000,
 151
 152         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 153 };
 154
 155 /* PCI Bus Info */
 156 #define I40E_PCI_LINK_STATUS            0xB2
 157 #define I40E_PCI_LINK_WIDTH             0x3F0
 158 #define I40E_PCI_LINK_WIDTH_1           0x10
 159 #define I40E_PCI_LINK_WIDTH_2           0x20
 160 #define I40E_PCI_LINK_WIDTH_4           0x40
 161 #define I40E_PCI_LINK_WIDTH_8           0x80
 162 #define I40E_PCI_LINK_SPEED             0xF
 163 #define I40E_PCI_LINK_SPEED_2500        0x1
 164 #define I40E_PCI_LINK_SPEED_5000        0x2
 165 #define I40E_PCI_LINK_SPEED_8000        0x3
 166
 167 /* Memory types */
 168 enum i40e_memset_type {
 169         I40E_NONDMA_MEM = 0,
 170         I40E_DMA_MEM
 171 };
 172
 173 /* Memcpy types */
 174 enum i40e_memcpy_type {
 175         I40E_NONDMA_TO_NONDMA = 0,
 176         I40E_NONDMA_TO_DMA,
 177         I40E_DMA_TO_DMA,
 178         I40E_DMA_TO_NONDMA
 179 };
 180
 181 /* These are structs for managing the hardware information and the operations.
 182  * The structures of function pointers are filled out at init time when we
 183  * know for sure exactly which hardware we're working with.  This gives us the
 184  * flexibility of using the same main driver code but adapting to slightly
 185  * different hardware needs as new parts are developed.  For this architecture,
 186  * the Firmware and AdminQ are intended to insulate the driver from most of the
 187  * future changes, but these structures will also do part of the job.
 188  */
 189 enum i40e_mac_type {
 190         I40E_MAC_UNKNOWN = 0,
 191         I40E_MAC_X710,
 192         I40E_MAC_XL710,
 193         I40E_MAC_VF,
 194         I40E_MAC_GENERIC,
 195 };
 196
 197 enum i40e_media_type {
 198         I40E_MEDIA_TYPE_UNKNOWN = 0,
 199         I40E_MEDIA_TYPE_FIBER,
 200         I40E_MEDIA_TYPE_BASET,
 201         I40E_MEDIA_TYPE_BACKPLANE,
 202         I40E_MEDIA_TYPE_CX4,
 203         I40E_MEDIA_TYPE_DA,
 204         I40E_MEDIA_TYPE_VIRTUAL
 205 };
 206
 207 enum i40e_fc_mode {
 208         I40E_FC_NONE = 0,
 209         I40E_FC_RX_PAUSE,
 210         I40E_FC_TX_PAUSE,
 211         I40E_FC_FULL,
 212         I40E_FC_PFC,
 213         I40E_FC_DEFAULT
 214 };
 215
 216 enum i40e_set_fc_aq_failures {
 217         I40E_SET_FC_AQ_FAIL_NONE = 0,
 218         I40E_SET_FC_AQ_FAIL_GET = 1,
 219         I40E_SET_FC_AQ_FAIL_SET = 2,
 220         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 221         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 222 };
 223
 224 enum i40e_vsi_type {
 225         I40E_VSI_MAIN = 0,
 226         I40E_VSI_VMDQ1,
 227         I40E_VSI_VMDQ2,
 228         I40E_VSI_CTRL,
 229         I40E_VSI_FCOE,
 230         I40E_VSI_MIRROR,
 231         I40E_VSI_SRIOV,
 232         I40E_VSI_FDIR,
 233         I40E_VSI_TYPE_UNKNOWN
 234 };
 235
 236 enum i40e_queue_type {
 237         I40E_QUEUE_TYPE_RX = 0,
 238         I40E_QUEUE_TYPE_TX,
 239         I40E_QUEUE_TYPE_PE_CEQ,
 240         I40E_QUEUE_TYPE_UNKNOWN
 241 };
 242
 243 struct i40e_link_status {
 244         enum i40e_aq_phy_type phy_type;
 245         enum i40e_aq_link_speed link_speed;
 246         u8 link_info;
 247         u8 an_info;
 248         u8 ext_info;
 249         u8 loopback;
 250         /* is Link Status Event notification to SW enabled */
 251         bool lse_enable;
 252         u16 max_frame_size;
 253         bool crc_enable;
 254         u8 pacing;
 255         u8 requested_speeds;
 256 };
 257
 258 struct i40e_phy_info {
 259         struct i40e_link_status link_info;
 260         struct i40e_link_status link_info_old;
 261         u32 autoneg_advertised;
 262         u32 phy_id;
 263         u32 module_type;
 264         bool get_link_info;
 265         enum i40e_media_type media_type;
 266 };
 267
 268 #define I40E_HW_CAP_MAX_GPIO                    30
 269 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 270 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 271
 272 /* Capabilities of a PF or a VF or the whole device */
 273 struct i40e_hw_capabilities {
 274         u32  switch_mode;
 275 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 276 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 277 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 278
 279         u32  management_mode;
 280         u32  npar_enable;
 281         u32  os2bmc;
 282         u32  valid_functions;
 283         bool sr_iov_1_1;
 284         bool vmdq;
 285         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 286         bool evb_802_1_qbh; /* Bridge Port Extension */
 287         bool dcb;
 288         bool fcoe;
 289         bool iscsi; /* Indicates iSCSI enabled */
 290         bool flex10_enable;
 291         bool flex10_capable;
 292         u32  flex10_mode;
 293 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 294 #define I40E_FLEX10_MODE_DCC            0x1
 295 #define I40E_FLEX10_MODE_DCI            0x2
 296
 297         u32 flex10_status;
 298 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 299 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 300
 301         bool mgmt_cem;
 302         bool ieee_1588;
 303         bool iwarp;
 304         bool fd;
 305         u32 fd_filters_guaranteed;
 306         u32 fd_filters_best_effort;
 307         bool rss;
 308         u32 rss_table_size;
 309         u32 rss_table_entry_width;
 310         bool led[I40E_HW_CAP_MAX_GPIO];
 311         bool sdp[I40E_HW_CAP_MAX_GPIO];
 312         u32 nvm_image_type;
 313         u32 num_flow_director_filters;
 314         u32 num_vfs;
 315         u32 vf_base_id;
 316         u32 num_vsis;
 317         u32 num_rx_qp;
 318         u32 num_tx_qp;
 319         u32 base_queue;
 320         u32 num_msix_vectors;
 321         u32 num_msix_vectors_vf;
 322         u32 led_pin_num;
 323         u32 sdp_pin_num;
 324         u32 mdio_port_num;
 325         u32 mdio_port_mode;
 326         u8 rx_buf_chain_len;
 327         u32 enabled_tcmap;
 328         u32 maxtc;
 329         u64 wr_csr_prot;
 330 };
 331
 332 struct i40e_mac_info {
 333         enum i40e_mac_type type;
 334         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 335         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 336         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 337         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 338         u16 max_fcoeq;
 339 };
 340
 341 enum i40e_aq_resources_ids {
 342         I40E_NVM_RESOURCE_ID = 1
 343 };
 344
 345 enum i40e_aq_resource_access_type {
 346         I40E_RESOURCE_READ = 1,
 347         I40E_RESOURCE_WRITE
 348 };
 349
 350 struct i40e_nvm_info {
 351         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 352         u32 timeout;              /* [ms] */
 353         u16 sr_size;              /* Shadow RAM size in words */
 354         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 355         u16 version;              /* NVM package version */
 356         u32 eetrack;              /* NVM data version */
 357 };
 358
 359 /* definitions used in NVM update support */
 360
 361 enum i40e_nvmupd_cmd {
 362         I40E_NVMUPD_INVALID,
 363         I40E_NVMUPD_READ_CON,
 364         I40E_NVMUPD_READ_SNT,
 365         I40E_NVMUPD_READ_LCB,
 366         I40E_NVMUPD_READ_SA,
 367         I40E_NVMUPD_WRITE_ERA,
 368         I40E_NVMUPD_WRITE_CON,
 369         I40E_NVMUPD_WRITE_SNT,
 370         I40E_NVMUPD_WRITE_LCB,
 371         I40E_NVMUPD_WRITE_SA,
 372         I40E_NVMUPD_CSUM_CON,
 373         I40E_NVMUPD_CSUM_SA,
 374         I40E_NVMUPD_CSUM_LCB,
 375 };
 376
 377 enum i40e_nvmupd_state {
 378         I40E_NVMUPD_STATE_INIT,
 379         I40E_NVMUPD_STATE_READING,
 380         I40E_NVMUPD_STATE_WRITING
 381 };
 382
 383 /* nvm_access definition and its masks/shifts need to be accessible to
 384  * application, core driver, and shared code.  Where is the right file?
 385  */
 386 #define I40E_NVM_READ   0xB
 387 #define I40E_NVM_WRITE  0xC
 388
 389 #define I40E_NVM_MOD_PNT_MASK 0xFF
 390
 391 #define I40E_NVM_TRANS_SHIFT    8
 392 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 393 #define I40E_NVM_CON            0x0
 394 #define I40E_NVM_SNT            0x1
 395 #define I40E_NVM_LCB            0x2
 396 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 397 #define I40E_NVM_ERA            0x4
 398 #define I40E_NVM_CSUM           0x8
 399
 400 #define I40E_NVM_ADAPT_SHIFT    16
 401 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 402
 403 #define I40E_NVMUPD_MAX_DATA    4096
 404 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 405
 406 struct i40e_nvm_access {
 407         u32 command;
 408         u32 config;
 409         u32 offset;     /* in bytes */
 410         u32 data_size;  /* in bytes */
 411         u8 data[1];
 412 };
 413
 414 /* PCI bus types */
 415 enum i40e_bus_type {
 416         i40e_bus_type_unknown = 0,
 417         i40e_bus_type_pci,
 418         i40e_bus_type_pcix,
 419         i40e_bus_type_pci_express,
 420         i40e_bus_type_reserved
 421 };
 422
 423 /* PCI bus speeds */
 424 enum i40e_bus_speed {
 425         i40e_bus_speed_unknown  = 0,
 426         i40e_bus_speed_33       = 33,
 427         i40e_bus_speed_66       = 66,
 428         i40e_bus_speed_100      = 100,
 429         i40e_bus_speed_120      = 120,
 430         i40e_bus_speed_133      = 133,
 431         i40e_bus_speed_2500     = 2500,
 432         i40e_bus_speed_5000     = 5000,
 433         i40e_bus_speed_8000     = 8000,
 434         i40e_bus_speed_reserved
 435 };
 436
 437 /* PCI bus widths */
 438 enum i40e_bus_width {
 439         i40e_bus_width_unknown  = 0,
 440         i40e_bus_width_pcie_x1  = 1,
 441         i40e_bus_width_pcie_x2  = 2,
 442         i40e_bus_width_pcie_x4  = 4,
 443         i40e_bus_width_pcie_x8  = 8,
 444         i40e_bus_width_32       = 32,
 445         i40e_bus_width_64       = 64,
 446         i40e_bus_width_reserved
 447 };
 448
 449 /* Bus parameters */
 450 struct i40e_bus_info {
 451         enum i40e_bus_speed speed;
 452         enum i40e_bus_width width;
 453         enum i40e_bus_type type;
 454
 455         u16 func;
 456         u16 device;
 457         u16 lan_id;
 458 };
 459
 460 /* Flow control (FC) parameters */
 461 struct i40e_fc_info {
 462         enum i40e_fc_mode current_mode; /* FC mode in effect */
 463         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 464 };
 465
 466 #define I40E_MAX_TRAFFIC_CLASS          8
 467 #define I40E_MAX_USER_PRIORITY          8
 468 #define I40E_DCBX_MAX_APPS              32
 469 #define I40E_LLDPDU_SIZE                1500
 470 #define I40E_TLV_STATUS_OPER            0x1
 471 #define I40E_TLV_STATUS_SYNC            0x2
 472 #define I40E_TLV_STATUS_ERR             0x4
 473 #define I40E_CEE_OPER_MAX_APPS          3
 474 #define I40E_APP_PROTOID_FCOE           0x8906
 475 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 476 #define I40E_APP_PROTOID_FIP            0x8914
 477 #define I40E_APP_SEL_ETHTYPE            0x1
 478 #define I40E_APP_SEL_TCPIP              0x2
 479
 480 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 481 struct i40e_dcb_ets_config {
 482         u8 willing;
 483         u8 cbs;
 484         u8 maxtcs;
 485         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 486         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 487         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 488 };
 489
 490 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 491 struct i40e_dcb_pfc_config {
 492         u8 willing;
 493         u8 mbc;
 494         u8 pfccap;
 495         u8 pfcenable;
 496 };
 497
 498 /* CEE or IEEE 802.1Qaz Application Priority data */
 499 struct i40e_dcb_app_priority_table {
 500         u8  priority;
 501         u8  selector;
 502         u16 protocolid;
 503 };
 504
 505 struct i40e_dcbx_config {
 506         u8  dcbx_mode;
 507 #define I40E_DCBX_MODE_CEE      0x1
 508 #define I40E_DCBX_MODE_IEEE     0x2
 509         u32 numapps;
 510         struct i40e_dcb_ets_config etscfg;
 511         struct i40e_dcb_ets_config etsrec;
 512         struct i40e_dcb_pfc_config pfc;
 513         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 514 };
 515
 516 /* Port hardware description */
 517 struct i40e_hw {
 518         u8 *hw_addr;
 519         void *back;
 520
 521         /* subsystem structs */
 522         struct i40e_phy_info phy;
 523         struct i40e_mac_info mac;
 524         struct i40e_bus_info bus;
 525         struct i40e_nvm_info nvm;
 526         struct i40e_fc_info fc;
 527
 528         /* pci info */
 529         u16 device_id;
 530         u16 vendor_id;
 531         u16 subsystem_device_id;
 532         u16 subsystem_vendor_id;
 533         u8 revision_id;
 534         u8 port;
 535         bool adapter_stopped;
 536
 537         /* capabilities for entire device and PCI func */
 538         struct i40e_hw_capabilities dev_caps;
 539         struct i40e_hw_capabilities func_caps;
 540
 541         /* Flow Director shared filter space */
 542         u16 fdir_shared_filter_count;
 543
 544         /* device profile info */
 545         u8  pf_id;
 546         u16 main_vsi_seid;
 547
 548         /* for multi-function MACs */
 549         u16 partition_id;
 550         u16 num_partitions;
 551         u16 num_ports;
 552
 553         /* Closest numa node to the device */
 554         u16 numa_node;
 555
 556         /* Admin Queue info */
 557         struct i40e_adminq_info aq;
 558
 559         /* state of nvm update process */
 560         enum i40e_nvmupd_state nvmupd_state;
 561
 562         /* HMC info */
 563         struct i40e_hmc_info hmc; /* HMC info struct */
 564
 565         /* LLDP/DCBX Status */
 566         u16 dcbx_status;
 567
 568         /* DCBX info */
 569         struct i40e_dcbx_config local_dcbx_config;
 570         struct i40e_dcbx_config remote_dcbx_config;
 571
 572         /* debug mask */
 573         u32 debug_mask;
 574 };
 575
 576 static INLINE bool i40e_is_vf(struct i40e_hw *hw)
 577 {
 578         return hw->mac.type == I40E_MAC_VF;
 579 }
 580
 581 struct i40e_driver_version {
 582         u8 major_version;
 583         u8 minor_version;
 584         u8 build_version;
 585         u8 subbuild_version;
 586         u8 driver_string[32];
 587 };
 588
 589 /* RX Descriptors */
 590 union i40e_16byte_rx_desc {
 591         struct {
 592                 __le64 pkt_addr; /* Packet buffer address */
 593                 __le64 hdr_addr; /* Header buffer address */
 594         } read;
 595         struct {
 596                 struct {
 597                         struct {
 598                                 union {
 599                                         __le16 mirroring_status;
 600                                         __le16 fcoe_ctx_id;
 601                                 } mirr_fcoe;
 602                                 __le16 l2tag1;
 603                         } lo_dword;
 604                         union {
 605                                 __le32 rss; /* RSS Hash */
 606                                 __le32 fd_id; /* Flow director filter id */
 607                                 __le32 fcoe_param; /* FCoE DDP Context id */
 608                         } hi_dword;
 609                 } qword0;
 610                 struct {
 611                         /* ext status/error/pktype/length */
 612                         __le64 status_error_len;
 613                 } qword1;
 614         } wb;  /* writeback */
 615 };
 616
 617 union i40e_32byte_rx_desc {
 618         struct {
 619                 __le64  pkt_addr; /* Packet buffer address */
 620                 __le64  hdr_addr; /* Header buffer address */
 621                         /* bit 0 of hdr_buffer_addr is DD bit */
 622                 __le64  rsvd1;
 623                 __le64  rsvd2;
 624         } read;
 625         struct {
 626                 struct {
 627                         struct {
 628                                 union {
 629                                         __le16 mirroring_status;
 630                                         __le16 fcoe_ctx_id;
 631                                 } mirr_fcoe;
 632                                 __le16 l2tag1;
 633                         } lo_dword;
 634                         union {
 635                                 __le32 rss; /* RSS Hash */
 636                                 __le32 fcoe_param; /* FCoE DDP Context id */
 637                                 /* Flow director filter id in case of
 638                                  * Programming status desc WB
 639                                  */
 640                                 __le32 fd_id;
 641                         } hi_dword;
 642                 } qword0;
 643                 struct {
 644                         /* status/error/pktype/length */
 645                         __le64 status_error_len;
 646                 } qword1;
 647                 struct {
 648                         __le16 ext_status; /* extended status */
 649                         __le16 rsvd;
 650                         __le16 l2tag2_1;
 651                         __le16 l2tag2_2;
 652                 } qword2;
 653                 struct {
 654                         union {
 655                                 __le32 flex_bytes_lo;
 656                                 __le32 pe_status;
 657                         } lo_dword;
 658                         union {
 659                                 __le32 flex_bytes_hi;
 660                                 __le32 fd_id;
 661                         } hi_dword;
 662                 } qword3;
 663         } wb;  /* writeback */
 664 };
 665
 666 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 667 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 668                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 669 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 670 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 671                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 672
 673 enum i40e_rx_desc_status_bits {
 674         /* Note: These are predefined bit offsets */
 675         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 676         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 677         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 678         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 679         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 680         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 681         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 682         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 683
 684         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 685         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 686         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 687         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 688         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 689         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 690         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 691         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 692 };
 693
 694 #define I40E_RXD_QW1_STATUS_SHIFT       0
 695 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 696                                          I40E_RXD_QW1_STATUS_SHIFT)
 697
 698 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 699 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 700                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 701
 702 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 703 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 704                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 705
 706 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 707 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 708                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 709
 710 enum i40e_rx_desc_fltstat_values {
 711         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 712         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 713         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 714         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 715 };
 716
 717 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 718 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 719 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 720 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 721
 722 #define I40E_RXD_QW1_ERROR_SHIFT        19
 723 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 724
 725 enum i40e_rx_desc_error_bits {
 726         /* Note: These are predefined bit offsets */
 727         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 728         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 729         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 730         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 731         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 732         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 733         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 734         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 735         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 736 };
 737
 738 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 739         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 740         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 741         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 742         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 743         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 744 };
 745
 746 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 747 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 748
 749 /* Packet type non-ip values */
 750 enum i40e_rx_l2_ptype {
 751         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 752         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 753         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 754         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 755         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 756         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 757         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 758         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 759         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 760         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 761         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 762         I40E_RX_PTYPE_L2_ARP                            = 11,
 763         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 764         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 765         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 766         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 767         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 768         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 769         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 770         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 771         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 772         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 773         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 774         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 775         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 776         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 777 };
 778
 779 struct i40e_rx_ptype_decoded {
 780         u32 ptype:8;
 781         u32 known:1;
 782         u32 outer_ip:1;
 783         u32 outer_ip_ver:1;
 784         u32 outer_frag:1;
 785         u32 tunnel_type:3;
 786         u32 tunnel_end_prot:2;
 787         u32 tunnel_end_frag:1;
 788         u32 inner_prot:4;
 789         u32 payload_layer:3;
 790 };
 791
 792 enum i40e_rx_ptype_outer_ip {
 793         I40E_RX_PTYPE_OUTER_L2  = 0,
 794         I40E_RX_PTYPE_OUTER_IP  = 1
 795 };
 796
 797 enum i40e_rx_ptype_outer_ip_ver {
 798         I40E_RX_PTYPE_OUTER_NONE        = 0,
 799         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 800         I40E_RX_PTYPE_OUTER_IPV6        = 1
 801 };
 802
 803 enum i40e_rx_ptype_outer_fragmented {
 804         I40E_RX_PTYPE_NOT_FRAG  = 0,
 805         I40E_RX_PTYPE_FRAG      = 1
 806 };
 807
 808 enum i40e_rx_ptype_tunnel_type {
 809         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 810         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 811         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 812         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 813         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 814 };
 815
 816 enum i40e_rx_ptype_tunnel_end_prot {
 817         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 818         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 819         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 820 };
 821
 822 enum i40e_rx_ptype_inner_prot {
 823         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 824         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 825         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 826         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 827         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 828         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 829 };
 830
 831 enum i40e_rx_ptype_payload_layer {
 832         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 833         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 834         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 835         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 836 };
 837
 838 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 839 #define I40E_RX_PTYPE_SHIFT             56
 840
 841 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 842 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 843                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 844
 845 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 846 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 847                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 848
 849 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 850 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 851                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 852
 853 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 854 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 855
 856 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 857 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 858                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 859
 860 enum i40e_rx_desc_ext_status_bits {
 861         /* Note: These are predefined bit offsets */
 862         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 863         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 864         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 865         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 866         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 867         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 868         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 869 };
 870
 871 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 872 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 873
 874 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 875 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 876
 877 enum i40e_rx_desc_pe_status_bits {
 878         /* Note: These are predefined bit offsets */
 879         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 880         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 881         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 882         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 883         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 884         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 885         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 886         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 887         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 888 };
 889
 890 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 891 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 892
 893 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 894 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 895                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 896
 897 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 898 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 899                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 900
 901 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 902 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 903                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 904
 905 enum i40e_rx_prog_status_desc_status_bits {
 906         /* Note: These are predefined bit offsets */
 907         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 908         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 909 };
 910
 911 enum i40e_rx_prog_status_desc_prog_id_masks {
 912         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 913         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 914         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 915 };
 916
 917 enum i40e_rx_prog_status_desc_error_bits {
 918         /* Note: These are predefined bit offsets */
 919         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 920         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 921         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 922         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 923 };
 924
 925 #define I40E_TWO_BIT_MASK       0x3
 926 #define I40E_THREE_BIT_MASK     0x7
 927 #define I40E_FOUR_BIT_MASK      0xF
 928 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 929
 930 /* TX Descriptor */
 931 struct i40e_tx_desc {
 932         __le64 buffer_addr; /* Address of descriptor's data buf */
 933         __le64 cmd_type_offset_bsz;
 934 };
 935
 936 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 937 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 938
 939 enum i40e_tx_desc_dtype_value {
 940         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 941         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 942         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 943         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 944         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 945         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 946         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 947         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 948         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 949         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 950 };
 951
 952 #define I40E_TXD_QW1_CMD_SHIFT  4
 953 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 954
 955 enum i40e_tx_desc_cmd_bits {
 956         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 957         I40E_TX_DESC_CMD_RS                     = 0x0002,
 958         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 959         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 960         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 961         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 962         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 963         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 964         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 965         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 966         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 967         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 968         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 969         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 970         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 971         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 972         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 973         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 974 };
 975
 976 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 977 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 978                                          I40E_TXD_QW1_OFFSET_SHIFT)
 979
 980 enum i40e_tx_desc_length_fields {
 981         /* Note: These are predefined bit offsets */
 982         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 983         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 984         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 985 };
 986
 987 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 988 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 989 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 990 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 991
 992 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 993 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 994                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 995
 996 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 997 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 998
 999 /* Context descriptors */
1000 struct i40e_tx_context_desc {
1001         __le32 tunneling_params;
1002         __le16 l2tag2;
1003         __le16 rsvd;
1004         __le64 type_cmd_tso_mss;
1005 };
1006
1007 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1008 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1009
1010 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1011 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1012
1013 enum i40e_tx_ctx_desc_cmd_bits {
1014         I40E_TX_CTX_DESC_TSO            = 0x01,
1015         I40E_TX_CTX_DESC_TSYN           = 0x02,
1016         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1017         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1018         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1019         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1020         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1021         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1022         I40E_TX_CTX_DESC_SWPE           = 0x40
1023 };
1024
1025 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1026 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1027                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1028
1029 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1030 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1031                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1032
1033 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1034 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1035
1036 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1037 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1038                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1039
1040 enum i40e_tx_ctx_desc_eipt_offload {
1041         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1042         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1043         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1044         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1045 };
1046
1047 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1048 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1049                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1050
1051 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1052 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1053
1054 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1055 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1056
1057 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1058 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1059                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1060
1061 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1062
1063 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1064 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1065                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1066
1067 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1068 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1069                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1070
1071 struct i40e_nop_desc {
1072         __le64 rsvd;
1073         __le64 dtype_cmd;
1074 };
1075
1076 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1077 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1078
1079 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1080 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1081
1082 enum i40e_tx_nop_desc_cmd_bits {
1083         /* Note: These are predefined bit offsets */
1084         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1085         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1086         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1087 };
1088
1089 struct i40e_filter_program_desc {
1090         __le32 qindex_flex_ptype_vsi;
1091         __le32 rsvd;
1092         __le32 dtype_cmd_cntindex;
1093         __le32 fd_id;
1094 };
1095 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1096 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1097                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1098 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1099 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1100                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1101 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1102 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1103                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1104
1105 /* Packet Classifier Types for filters */
1106 enum i40e_filter_pctype {
1107         /* Note: Values 0-30 are reserved for future use */
1108         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1109         /* Note: Value 32 is reserved for future use */
1110         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1111         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1112         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1113         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1114         /* Note: Values 37-40 are reserved for future use */
1115         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1116         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1117         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1118         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1119         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1120         /* Note: Value 47 is reserved for future use */
1121         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1122         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1123         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1124         /* Note: Values 51-62 are reserved for future use */
1125         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1126 };
1127
1128 enum i40e_filter_program_desc_dest {
1129         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1130         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1131         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1132 };
1133
1134 enum i40e_filter_program_desc_fd_status {
1135         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1136         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1137         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1138         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1139 };
1140
1141 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1142 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1143                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1144
1145 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1146 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1147
1148 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1149 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1150                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1151
1152 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1153 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1154
1155 enum i40e_filter_program_desc_pcmd {
1156         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1157         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1158 };
1159
1160 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1161 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1162
1163 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1164 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1165                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1166
1167 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1168                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1169 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1170                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1171
1172 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1173 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1174                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1175
1176 enum i40e_filter_type {
1177         I40E_FLOW_DIRECTOR_FLTR = 0,
1178         I40E_PE_QUAD_HASH_FLTR = 1,
1179         I40E_ETHERTYPE_FLTR,
1180         I40E_FCOE_CTX_FLTR,
1181         I40E_MAC_VLAN_FLTR,
1182         I40E_HASH_FLTR
1183 };
1184
1185 struct i40e_vsi_context {
1186         u16 seid;
1187         u16 uplink_seid;
1188         u16 vsi_number;
1189         u16 vsis_allocated;
1190         u16 vsis_unallocated;
1191         u16 flags;
1192         u8 pf_num;
1193         u8 vf_num;
1194         u8 connection_type;
1195         struct i40e_aqc_vsi_properties_data info;
1196 };
1197
1198 struct i40e_veb_context {
1199         u16 seid;
1200         u16 uplink_seid;
1201         u16 veb_number;
1202         u16 vebs_allocated;
1203         u16 vebs_unallocated;
1204         u16 flags;
1205         struct i40e_aqc_get_veb_parameters_completion info;
1206 };
1207
1208 /* Statistics collected by each port, VSI, VEB, and S-channel */
1209 struct i40e_eth_stats {
1210         u64 rx_bytes;                   /* gorc */
1211         u64 rx_unicast;                 /* uprc */
1212         u64 rx_multicast;               /* mprc */
1213         u64 rx_broadcast;               /* bprc */
1214         u64 rx_discards;                /* rdpc */
1215         u64 rx_unknown_protocol;        /* rupp */
1216         u64 tx_bytes;                   /* gotc */
1217         u64 tx_unicast;                 /* uptc */
1218         u64 tx_multicast;               /* mptc */
1219         u64 tx_broadcast;               /* bptc */
1220         u64 tx_discards;                /* tdpc */
1221         u64 tx_errors;                  /* tepc */
1222 };
1223
1224 /* Statistics collected per VEB per TC */
1225 struct i40e_veb_tc_stats {
1226         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1227         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1228         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1229         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1230 };
1231
1232 /* Statistics collected by the MAC */
1233 struct i40e_hw_port_stats {
1234         /* eth stats collected by the port */
1235         struct i40e_eth_stats eth;
1236
1237         /* additional port specific stats */
1238         u64 tx_dropped_link_down;       /* tdold */
1239         u64 crc_errors;                 /* crcerrs */
1240         u64 illegal_bytes;              /* illerrc */
1241         u64 error_bytes;                /* errbc */
1242         u64 mac_local_faults;           /* mlfc */
1243         u64 mac_remote_faults;          /* mrfc */
1244         u64 rx_length_errors;           /* rlec */
1245         u64 link_xon_rx;                /* lxonrxc */
1246         u64 link_xoff_rx;               /* lxoffrxc */
1247         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1248         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1249         u64 link_xon_tx;                /* lxontxc */
1250         u64 link_xoff_tx;               /* lxofftxc */
1251         u64 priority_xon_tx[8];         /* pxontxc[8] */
1252         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1253         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1254         u64 rx_size_64;                 /* prc64 */
1255         u64 rx_size_127;                /* prc127 */
1256         u64 rx_size_255;                /* prc255 */
1257         u64 rx_size_511;                /* prc511 */
1258         u64 rx_size_1023;               /* prc1023 */
1259         u64 rx_size_1522;               /* prc1522 */
1260         u64 rx_size_big;                /* prc9522 */
1261         u64 rx_undersize;               /* ruc */
1262         u64 rx_fragments;               /* rfc */
1263         u64 rx_oversize;                /* roc */
1264         u64 rx_jabber;                  /* rjc */
1265         u64 tx_size_64;                 /* ptc64 */
1266         u64 tx_size_127;                /* ptc127 */
1267         u64 tx_size_255;                /* ptc255 */
1268         u64 tx_size_511;                /* ptc511 */
1269         u64 tx_size_1023;               /* ptc1023 */
1270         u64 tx_size_1522;               /* ptc1522 */
1271         u64 tx_size_big;                /* ptc9522 */
1272         u64 mac_short_packet_dropped;   /* mspdc */
1273         u64 checksum_error;             /* xec */
1274         /* flow director stats */
1275         u64 fd_atr_match;
1276         u64 fd_sb_match;
1277         u64 fd_atr_tunnel_match;
1278         u32 fd_atr_status;
1279         u32 fd_sb_status;
1280         /* EEE LPI */
1281         u32 tx_lpi_status;
1282         u32 rx_lpi_status;
1283         u64 tx_lpi_count;               /* etlpic */
1284         u64 rx_lpi_count;               /* erlpic */
1285 };
1286
1287 /* Checksum and Shadow RAM pointers */
1288 #define I40E_SR_NVM_CONTROL_WORD                0x00
1289 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1290 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1291 #define I40E_SR_OPTION_ROM_PTR                  0x05
1292 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1293 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1294 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1295 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1296 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1297 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1298 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1299 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1300 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1301 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1302 #define I40E_SR_PBA_FLAGS                       0x15
1303 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1304 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1305 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1306 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1307 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1308 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1309 #define I40E_SR_NVM_MAP_VERSION                 0x29
1310 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1311 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1312 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1313 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1314 #define I40E_SR_VPD_PTR                         0x2F
1315 #define I40E_SR_PXE_SETUP_PTR                   0x30
1316 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1317 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1318 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1319 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1320 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1321 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1322 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1323 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1324 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1325 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1326 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1327 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1328 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1329 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1330 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1331 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1332 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1333 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1334
1335 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1336 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1337 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1338 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1339 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1340
1341 /* Shadow RAM related */
1342 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1343 #define I40E_SR_BUF_ALIGNMENT           4096
1344 #define I40E_SR_WORDS_IN_1KB            512
1345 /* Checksum should be calculated such that after adding all the words,
1346  * including the checksum word itself, the sum should be 0xBABA.
1347  */
1348 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1349
1350 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1351
1352 enum i40e_switch_element_types {
1353         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1354         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1355         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1356         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1357         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1358         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1359         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1360         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1361         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1362 };
1363
1364 /* Supported EtherType filters */
1365 enum i40e_ether_type_index {
1366         I40E_ETHER_TYPE_1588            = 0,
1367         I40E_ETHER_TYPE_FIP             = 1,
1368         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1369         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1370         I40E_ETHER_TYPE_LLDP            = 4,
1371         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1372         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1373         I40E_ETHER_TYPE_QCN_CNM         = 7,
1374         I40E_ETHER_TYPE_8021X           = 8,
1375         I40E_ETHER_TYPE_ARP             = 9,
1376         I40E_ETHER_TYPE_RSV1            = 10,
1377         I40E_ETHER_TYPE_RSV2            = 11,
1378 };
1379
1380 /* Filter context base size is 1K */
1381 #define I40E_HASH_FILTER_BASE_SIZE      1024
1382 /* Supported Hash filter values */
1383 enum i40e_hash_filter_size {
1384         I40E_HASH_FILTER_SIZE_1K        = 0,
1385         I40E_HASH_FILTER_SIZE_2K        = 1,
1386         I40E_HASH_FILTER_SIZE_4K        = 2,
1387         I40E_HASH_FILTER_SIZE_8K        = 3,
1388         I40E_HASH_FILTER_SIZE_16K       = 4,
1389         I40E_HASH_FILTER_SIZE_32K       = 5,
1390         I40E_HASH_FILTER_SIZE_64K       = 6,
1391         I40E_HASH_FILTER_SIZE_128K      = 7,
1392         I40E_HASH_FILTER_SIZE_256K      = 8,
1393         I40E_HASH_FILTER_SIZE_512K      = 9,
1394         I40E_HASH_FILTER_SIZE_1M        = 10,
1395 };
1396
1397 /* DMA context base size is 0.5K */
1398 #define I40E_DMA_CNTX_BASE_SIZE         512
1399 /* Supported DMA context values */
1400 enum i40e_dma_cntx_size {
1401         I40E_DMA_CNTX_SIZE_512          = 0,
1402         I40E_DMA_CNTX_SIZE_1K           = 1,
1403         I40E_DMA_CNTX_SIZE_2K           = 2,
1404         I40E_DMA_CNTX_SIZE_4K           = 3,
1405         I40E_DMA_CNTX_SIZE_8K           = 4,
1406         I40E_DMA_CNTX_SIZE_16K          = 5,
1407         I40E_DMA_CNTX_SIZE_32K          = 6,
1408         I40E_DMA_CNTX_SIZE_64K          = 7,
1409         I40E_DMA_CNTX_SIZE_128K         = 8,
1410         I40E_DMA_CNTX_SIZE_256K         = 9,
1411 };
1412
1413 /* Supported Hash look up table (LUT) sizes */
1414 enum i40e_hash_lut_size {
1415         I40E_HASH_LUT_SIZE_128          = 0,
1416         I40E_HASH_LUT_SIZE_512          = 1,
1417 };
1418
1419 /* Structure to hold a per PF filter control settings */
1420 struct i40e_filter_control_settings {
1421         /* number of PE Quad Hash filter buckets */
1422         enum i40e_hash_filter_size pe_filt_num;
1423         /* number of PE Quad Hash contexts */
1424         enum i40e_dma_cntx_size pe_cntx_num;
1425         /* number of FCoE filter buckets */
1426         enum i40e_hash_filter_size fcoe_filt_num;
1427         /* number of FCoE DDP contexts */
1428         enum i40e_dma_cntx_size fcoe_cntx_num;
1429         /* size of the Hash LUT */
1430         enum i40e_hash_lut_size hash_lut_size;
1431         /* enable FDIR filters for PF and its VFs */
1432         bool enable_fdir;
1433         /* enable Ethertype filters for PF and its VFs */
1434         bool enable_ethtype;
1435         /* enable MAC/VLAN filters for PF and its VFs */
1436         bool enable_macvlan;
1437 };
1438
1439 /* Structure to hold device level control filter counts */
1440 struct i40e_control_filter_stats {
1441         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1442         u16 etype_used;       /* Used perfect EtherType filters */
1443         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1444         u16 etype_free;       /* Un-used perfect EtherType filters */
1445 };
1446
1447 enum i40e_reset_type {
1448         I40E_RESET_POR          = 0,
1449         I40E_RESET_CORER        = 1,
1450         I40E_RESET_GLOBR        = 2,
1451         I40E_RESET_EMPR         = 3,
1452 };
1453
1454 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1455 #define I40E_NVM_LLDP_CFG_PTR           0xD
1456 struct i40e_lldp_variables {
1457         u16 length;
1458         u16 adminstatus;
1459         u16 msgfasttx;
1460         u16 msgtxinterval;
1461         u16 txparams;
1462         u16 timers;
1463         u16 crc8;
1464 };
1465
1466 /* Offsets into Alternate Ram */
1467 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1468 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1469 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1470 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1471 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1472 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1473
1474 /* Alternate Ram Bandwidth Masks */
1475 #define I40E_ALT_BW_VALUE_MASK          0xFF
1476 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1477 #define I40E_ALT_BW_VALID_MASK          0x80000000
1478
1479 /* RSS Hash Table Size */
1480 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1481 #endif /* _I40E_TYPE_H_ */