2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include <machine/atomic.h>
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
71 #include <dev/jme/if_jmereg.h>
72 #include <dev/jme/if_jmevar.h>
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
77 /* Define the following to disable printing Rx errors. */
78 #undef JME_SHOW_ERRORS
80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(jme, pci, 1, 1, 1);
83 MODULE_DEPEND(jme, ether, 1, 1, 1);
84 MODULE_DEPEND(jme, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static struct jme_dev {
96 uint16_t jme_vendorid;
97 uint16_t jme_deviceid;
100 { VENDORID_JMICRON, DEVICEID_JMC250,
101 "JMicron Inc, JMC250 Gigabit Ethernet" },
102 { VENDORID_JMICRON, DEVICEID_JMC260,
103 "JMicron Inc, JMC260 Fast Ethernet" },
106 static int jme_miibus_readreg(device_t, int, int);
107 static int jme_miibus_writereg(device_t, int, int, int);
108 static void jme_miibus_statchg(device_t);
109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
110 static int jme_mediachange(struct ifnet *);
111 static int jme_probe(device_t);
112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
113 static int jme_eeprom_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_map_intr_vector(struct jme_softc *);
116 static int jme_attach(device_t);
117 static int jme_detach(device_t);
118 static void jme_sysctl_node(struct jme_softc *);
119 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
120 static int jme_dma_alloc(struct jme_softc *);
121 static void jme_dma_free(struct jme_softc *);
122 static int jme_shutdown(device_t);
123 static void jme_setlinkspeed(struct jme_softc *);
124 static void jme_setwol(struct jme_softc *);
125 static int jme_suspend(device_t);
126 static int jme_resume(device_t);
127 static int jme_encap(struct jme_softc *, struct mbuf **);
128 static void jme_tx_task(void *, int);
129 static void jme_start(struct ifnet *);
130 static void jme_watchdog(struct jme_softc *);
131 static int jme_ioctl(struct ifnet *, u_long, caddr_t);
132 static void jme_mac_config(struct jme_softc *);
133 static void jme_link_task(void *, int);
134 static int jme_intr(void *);
135 static void jme_int_task(void *, int);
136 static void jme_txeof(struct jme_softc *);
137 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
138 static void jme_rxeof(struct jme_softc *);
139 static int jme_rxintr(struct jme_softc *, int);
140 static void jme_tick(void *);
141 static void jme_reset(struct jme_softc *);
142 static void jme_init(void *);
143 static void jme_init_locked(struct jme_softc *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_stop_tx(struct jme_softc *);
146 static void jme_stop_rx(struct jme_softc *);
147 static int jme_init_rx_ring(struct jme_softc *);
148 static void jme_init_tx_ring(struct jme_softc *);
149 static void jme_init_ssb(struct jme_softc *);
150 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
151 static void jme_set_vlan(struct jme_softc *);
152 static void jme_set_filter(struct jme_softc *);
153 static void jme_stats_clear(struct jme_softc *);
154 static void jme_stats_save(struct jme_softc *);
155 static void jme_stats_update(struct jme_softc *);
156 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
157 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
158 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
159 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
160 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
164 static device_method_t jme_methods[] = {
165 /* Device interface. */
166 DEVMETHOD(device_probe, jme_probe),
167 DEVMETHOD(device_attach, jme_attach),
168 DEVMETHOD(device_detach, jme_detach),
169 DEVMETHOD(device_shutdown, jme_shutdown),
170 DEVMETHOD(device_suspend, jme_suspend),
171 DEVMETHOD(device_resume, jme_resume),
174 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
175 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
176 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
181 static driver_t jme_driver = {
184 sizeof(struct jme_softc)
187 static devclass_t jme_devclass;
189 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0);
190 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
192 static struct resource_spec jme_res_spec_mem[] = {
193 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
197 static struct resource_spec jme_irq_spec_legacy[] = {
198 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
202 static struct resource_spec jme_irq_spec_msi[] = {
203 { SYS_RES_IRQ, 1, RF_ACTIVE },
204 { SYS_RES_IRQ, 2, RF_ACTIVE },
205 { SYS_RES_IRQ, 3, RF_ACTIVE },
206 { SYS_RES_IRQ, 4, RF_ACTIVE },
207 { SYS_RES_IRQ, 5, RF_ACTIVE },
208 { SYS_RES_IRQ, 6, RF_ACTIVE },
209 { SYS_RES_IRQ, 7, RF_ACTIVE },
210 { SYS_RES_IRQ, 8, RF_ACTIVE },
215 * Read a PHY register on the MII of the JMC250.
218 jme_miibus_readreg(device_t dev, int phy, int reg)
220 struct jme_softc *sc;
224 sc = device_get_softc(dev);
226 /* For FPGA version, PHY address 0 should be ignored. */
227 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
230 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
231 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
232 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
234 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
239 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
243 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
247 * Write a PHY register on the MII of the JMC250.
250 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
252 struct jme_softc *sc;
255 sc = device_get_softc(dev);
257 /* For FPGA version, PHY address 0 should be ignored. */
258 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
261 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
262 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
263 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
264 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
266 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
271 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
277 * Callback from MII layer when media changes.
280 jme_miibus_statchg(device_t dev)
282 struct jme_softc *sc;
284 sc = device_get_softc(dev);
285 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
289 * Get the current interface media status.
292 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
294 struct jme_softc *sc;
295 struct mii_data *mii;
299 if ((ifp->if_flags & IFF_UP) == 0) {
303 mii = device_get_softc(sc->jme_miibus);
306 ifmr->ifm_status = mii->mii_media_status;
307 ifmr->ifm_active = mii->mii_media_active;
312 * Set hardware to newly-selected media.
315 jme_mediachange(struct ifnet *ifp)
317 struct jme_softc *sc;
318 struct mii_data *mii;
319 struct mii_softc *miisc;
324 mii = device_get_softc(sc->jme_miibus);
325 if (mii->mii_instance != 0) {
326 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
327 mii_phy_reset(miisc);
329 error = mii_mediachg(mii);
336 jme_probe(device_t dev)
340 uint16_t vendor, devid;
342 vendor = pci_get_vendor(dev);
343 devid = pci_get_device(dev);
345 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]);
347 if (vendor == sp->jme_vendorid &&
348 devid == sp->jme_deviceid) {
349 device_set_desc(dev, sp->jme_name);
350 return (BUS_PROBE_DEFAULT);
358 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
364 for (i = JME_TIMEOUT; i > 0; i--) {
365 reg = CSR_READ_4(sc, JME_SMBCSR);
366 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
372 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
376 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
377 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
378 for (i = JME_TIMEOUT; i > 0; i--) {
380 reg = CSR_READ_4(sc, JME_SMBINTF);
381 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
386 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
390 reg = CSR_READ_4(sc, JME_SMBINTF);
391 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
397 jme_eeprom_macaddr(struct jme_softc *sc)
399 uint8_t eaddr[ETHER_ADDR_LEN];
400 uint8_t fup, reg, val;
405 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
406 fup != JME_EEPROM_SIG0)
408 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
409 fup != JME_EEPROM_SIG1)
413 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
415 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
416 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
417 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
419 if (reg >= JME_PAR0 &&
420 reg < JME_PAR0 + ETHER_ADDR_LEN) {
421 if (jme_eeprom_read_byte(sc, offset + 2,
424 eaddr[reg - JME_PAR0] = val;
428 /* Check for the end of EEPROM descriptor. */
429 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
431 /* Try next eeprom descriptor. */
432 offset += JME_EEPROM_DESC_BYTES;
433 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
435 if (match == ETHER_ADDR_LEN) {
436 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
444 jme_reg_macaddr(struct jme_softc *sc)
448 /* Read station address. */
449 par0 = CSR_READ_4(sc, JME_PAR0);
450 par1 = CSR_READ_4(sc, JME_PAR1);
452 if ((par0 == 0 && par1 == 0) ||
453 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
454 device_printf(sc->jme_dev,
455 "generating fake ethernet address.\n");
457 /* Set OUI to JMicron. */
458 sc->jme_eaddr[0] = 0x02; /* U/L bit set. */
459 sc->jme_eaddr[1] = 0x1B;
460 sc->jme_eaddr[2] = 0x8C;
461 sc->jme_eaddr[3] = (par0 >> 16) & 0xff;
462 sc->jme_eaddr[4] = (par0 >> 8) & 0xff;
463 sc->jme_eaddr[5] = par0 & 0xff;
465 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
466 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
467 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
468 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
469 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
470 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
475 jme_map_intr_vector(struct jme_softc *sc)
477 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
479 bzero(map, sizeof(map));
481 /* Map Tx interrupts source to MSI/MSIX vector 2. */
482 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
483 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
484 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
485 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
486 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
487 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
488 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
489 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
490 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
491 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
492 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
493 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
494 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
495 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
496 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
497 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
498 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
499 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
500 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
501 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
503 /* Map Rx interrupts source to MSI/MSIX vector 1. */
504 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
505 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
506 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
507 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
508 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
509 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
510 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
511 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
512 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
513 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
514 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
515 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
516 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
517 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
518 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
519 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
520 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
521 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
522 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
523 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
524 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
525 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
526 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
527 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
528 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
529 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
530 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
531 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
532 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
533 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
534 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
535 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
537 /* Map all other interrupts source to MSI/MSIX vector 0. */
538 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
539 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
540 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
541 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
545 jme_attach(device_t dev)
547 struct jme_softc *sc;
549 struct mii_softc *miisc;
550 struct mii_data *mii;
553 int error, i, msic, msixc, pmc;
556 sc = device_get_softc(dev);
559 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
561 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
562 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
563 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
566 * Map the device. JMC250 supports both memory mapped and I/O
567 * register space access. Because I/O register access should
568 * use different BARs to access registers it's waste of time
569 * to use I/O register spce access. JMC250 uses 16K to map
570 * entire memory space.
572 pci_enable_busmaster(dev);
573 sc->jme_res_spec = jme_res_spec_mem;
574 sc->jme_irq_spec = jme_irq_spec_legacy;
575 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
577 device_printf(dev, "cannot allocate memory resources.\n");
581 /* Allocate IRQ resources. */
582 msixc = pci_msix_count(dev);
583 msic = pci_msi_count(dev);
585 device_printf(dev, "MSIX count : %d\n", msixc);
586 device_printf(dev, "MSI count : %d\n", msic);
589 /* Prefer MSIX over MSI. */
590 if (msix_disable == 0 || msi_disable == 0) {
591 if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES &&
592 pci_alloc_msix(dev, &msixc) == 0) {
593 if (msic == JME_MSIX_MESSAGES) {
594 device_printf(dev, "Using %d MSIX messages.\n",
596 sc->jme_flags |= JME_FLAG_MSIX;
597 sc->jme_irq_spec = jme_irq_spec_msi;
599 pci_release_msi(dev);
601 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
602 msic == JME_MSI_MESSAGES &&
603 pci_alloc_msi(dev, &msic) == 0) {
604 if (msic == JME_MSI_MESSAGES) {
605 device_printf(dev, "Using %d MSI messages.\n",
607 sc->jme_flags |= JME_FLAG_MSI;
608 sc->jme_irq_spec = jme_irq_spec_msi;
610 pci_release_msi(dev);
612 /* Map interrupt vector 0, 1 and 2. */
613 if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
614 (sc->jme_flags & JME_FLAG_MSIX) != 0)
615 jme_map_intr_vector(sc);
618 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
620 device_printf(dev, "cannot allocate IRQ resources.\n");
624 sc->jme_rev = pci_get_device(dev);
625 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
626 sc->jme_flags |= JME_FLAG_FASTETH;
627 sc->jme_flags |= JME_FLAG_NOJUMBO;
629 reg = CSR_READ_4(sc, JME_CHIPMODE);
630 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
631 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
633 sc->jme_flags |= JME_FLAG_FPGA;
635 device_printf(dev, "PCI device revision : 0x%04x\n",
637 device_printf(dev, "Chip revision : 0x%02x\n",
639 if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
640 device_printf(dev, "FPGA revision : 0x%04x\n",
641 (reg & CHIPMODE_FPGA_REV_MASK) >>
642 CHIPMODE_FPGA_REV_SHIFT);
644 if (sc->jme_chip_rev == 0xFF) {
645 device_printf(dev, "Unknown chip revision : 0x%02x\n",
651 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
652 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
653 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
654 sc->jme_flags |= JME_FLAG_DMA32BIT;
655 sc->jme_flags |= JME_FLAG_TXCLK;
656 sc->jme_flags |= JME_FLAG_HWMIB;
659 /* Reset the ethernet controller. */
662 /* Get station address. */
663 reg = CSR_READ_4(sc, JME_SMBCSR);
664 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
665 error = jme_eeprom_macaddr(sc);
666 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
667 if (error != 0 && (bootverbose))
668 device_printf(sc->jme_dev,
669 "ethernet hardware address not found in EEPROM.\n");
675 * Integrated JR0211 has fixed PHY address whereas FPGA version
676 * requires PHY probing to get correct PHY address.
678 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
679 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
680 GPREG0_PHY_ADDR_MASK;
682 device_printf(dev, "PHY is at address %d.\n",
687 /* Set max allowable DMA size. */
688 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
689 sc->jme_flags |= JME_FLAG_PCIE;
690 burst = pci_read_config(dev, i + 0x08, 2);
692 device_printf(dev, "Read request size : %d bytes.\n",
693 128 << ((burst >> 12) & 0x07));
694 device_printf(dev, "TLP payload size : %d bytes.\n",
695 128 << ((burst >> 5) & 0x07));
697 switch ((burst >> 12) & 0x07) {
699 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
702 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
705 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
708 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
710 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
711 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
713 /* Create coalescing sysctl node. */
715 if ((error = jme_dma_alloc(sc) != 0))
718 ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
720 device_printf(dev, "cannot allocate ifnet structure.\n");
726 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
727 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
728 ifp->if_ioctl = jme_ioctl;
729 ifp->if_start = jme_start;
730 ifp->if_init = jme_init;
731 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1;
732 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
733 IFQ_SET_READY(&ifp->if_snd);
734 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */
735 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
736 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
737 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
738 sc->jme_flags |= JME_FLAG_PMCAP;
739 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
741 ifp->if_capenable = ifp->if_capabilities;
743 /* Set up MII bus. */
744 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
745 jme_mediastatus, BMSR_DEFCAPMASK, sc->jme_phyaddr, MII_OFFSET_ANY,
748 device_printf(dev, "attaching PHYs failed\n");
753 * Force PHY to FPGA mode.
755 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
756 mii = device_get_softc(sc->jme_miibus);
757 if (mii->mii_instance != 0) {
758 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
759 if (miisc->mii_phy != 0) {
760 sc->jme_phyaddr = miisc->mii_phy;
764 if (sc->jme_phyaddr != 0) {
765 device_printf(sc->jme_dev,
766 "FPGA PHY is at %d\n", sc->jme_phyaddr);
768 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
774 ether_ifattach(ifp, sc->jme_eaddr);
776 /* VLAN capability setup */
777 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
778 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
779 ifp->if_capenable = ifp->if_capabilities;
781 /* Tell the upper layer(s) we support long frames. */
782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
784 /* Create local taskq. */
785 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp);
786 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
787 taskqueue_thread_enqueue, &sc->jme_tq);
788 if (sc->jme_tq == NULL) {
789 device_printf(dev, "could not create taskqueue.\n");
794 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
795 device_get_nameunit(sc->jme_dev));
797 if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
798 msic = JME_MSIX_MESSAGES;
799 else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
800 msic = JME_MSI_MESSAGES;
803 for (i = 0; i < msic; i++) {
804 error = bus_setup_intr(dev, sc->jme_irq[i],
805 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
806 &sc->jme_intrhand[i]);
812 device_printf(dev, "could not set up interrupt handler.\n");
813 taskqueue_free(sc->jme_tq);
827 jme_detach(device_t dev)
829 struct jme_softc *sc;
833 sc = device_get_softc(dev);
836 if (device_is_attached(dev)) {
838 sc->jme_flags |= JME_FLAG_DETACH;
841 callout_drain(&sc->jme_tick_ch);
842 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
843 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
844 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
848 if (sc->jme_tq != NULL) {
849 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
850 taskqueue_free(sc->jme_tq);
854 if (sc->jme_miibus != NULL) {
855 device_delete_child(dev, sc->jme_miibus);
856 sc->jme_miibus = NULL;
858 bus_generic_detach(dev);
867 if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
868 msic = JME_MSIX_MESSAGES;
869 else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
870 msic = JME_MSI_MESSAGES;
873 for (i = 0; i < msic; i++) {
874 if (sc->jme_intrhand[i] != NULL) {
875 bus_teardown_intr(dev, sc->jme_irq[i],
876 sc->jme_intrhand[i]);
877 sc->jme_intrhand[i] = NULL;
881 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
882 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
883 pci_release_msi(dev);
884 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
885 mtx_destroy(&sc->jme_mtx);
890 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \
891 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
894 jme_sysctl_node(struct jme_softc *sc)
896 struct sysctl_ctx_list *ctx;
897 struct sysctl_oid_list *child, *parent;
898 struct sysctl_oid *tree;
899 struct jme_hw_stats *stats;
902 stats = &sc->jme_stats;
903 ctx = device_get_sysctl_ctx(sc->jme_dev);
904 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
906 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
907 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
908 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
910 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
911 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
912 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
914 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
915 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
916 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
918 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
919 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
920 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
922 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
923 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
924 sysctl_hw_jme_proc_limit, "I",
925 "max number of Rx events to process");
927 /* Pull in device tunables. */
928 sc->jme_process_limit = JME_PROC_DEFAULT;
929 error = resource_int_value(device_get_name(sc->jme_dev),
930 device_get_unit(sc->jme_dev), "process_limit",
931 &sc->jme_process_limit);
933 if (sc->jme_process_limit < JME_PROC_MIN ||
934 sc->jme_process_limit > JME_PROC_MAX) {
935 device_printf(sc->jme_dev,
936 "process_limit value out of range; "
937 "using default: %d\n", JME_PROC_DEFAULT);
938 sc->jme_process_limit = JME_PROC_DEFAULT;
942 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
943 error = resource_int_value(device_get_name(sc->jme_dev),
944 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
946 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
947 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
948 device_printf(sc->jme_dev,
949 "tx_coal_to value out of range; "
950 "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
951 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
955 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
956 error = resource_int_value(device_get_name(sc->jme_dev),
957 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
959 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
960 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
961 device_printf(sc->jme_dev,
962 "tx_coal_pkt value out of range; "
963 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
964 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
968 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
969 error = resource_int_value(device_get_name(sc->jme_dev),
970 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
972 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
973 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
974 device_printf(sc->jme_dev,
975 "rx_coal_to value out of range; "
976 "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
977 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
981 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
982 error = resource_int_value(device_get_name(sc->jme_dev),
983 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
985 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
986 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
987 device_printf(sc->jme_dev,
988 "tx_coal_pkt value out of range; "
989 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
990 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
994 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
997 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
998 NULL, "JME statistics");
999 parent = SYSCTL_CHILDREN(tree);
1001 /* Rx statistics. */
1002 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1003 NULL, "Rx MAC statistics");
1004 child = SYSCTL_CHILDREN(tree);
1005 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1006 &stats->rx_good_frames, "Good frames");
1007 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1008 &stats->rx_crc_errs, "CRC errors");
1009 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
1010 &stats->rx_mii_errs, "MII errors");
1011 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1012 &stats->rx_fifo_oflows, "FIFO overflows");
1013 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
1014 &stats->rx_desc_empty, "Descriptor empty");
1015 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1016 &stats->rx_bad_frames, "Bad frames");
1018 /* Tx statistics. */
1019 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1020 NULL, "Tx MAC statistics");
1021 child = SYSCTL_CHILDREN(tree);
1022 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1023 &stats->tx_good_frames, "Good frames");
1024 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1025 &stats->tx_bad_frames, "Bad frames");
1028 #undef JME_SYSCTL_STAT_ADD32
1030 struct jme_dmamap_arg {
1031 bus_addr_t jme_busaddr;
1035 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1037 struct jme_dmamap_arg *ctx;
1042 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1044 ctx = (struct jme_dmamap_arg *)arg;
1045 ctx->jme_busaddr = segs[0].ds_addr;
1049 jme_dma_alloc(struct jme_softc *sc)
1051 struct jme_dmamap_arg ctx;
1052 struct jme_txdesc *txd;
1053 struct jme_rxdesc *rxd;
1054 bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1057 lowaddr = BUS_SPACE_MAXADDR;
1058 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1059 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1062 /* Create parent ring tag. */
1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1064 1, 0, /* algnmnt, boundary */
1065 lowaddr, /* lowaddr */
1066 BUS_SPACE_MAXADDR, /* highaddr */
1067 NULL, NULL, /* filter, filterarg */
1068 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1070 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1072 NULL, NULL, /* lockfunc, lockarg */
1073 &sc->jme_cdata.jme_ring_tag);
1075 device_printf(sc->jme_dev,
1076 "could not create parent ring DMA tag.\n");
1079 /* Create tag for Tx ring. */
1080 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1081 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
1082 BUS_SPACE_MAXADDR, /* lowaddr */
1083 BUS_SPACE_MAXADDR, /* highaddr */
1084 NULL, NULL, /* filter, filterarg */
1085 JME_TX_RING_SIZE, /* maxsize */
1087 JME_TX_RING_SIZE, /* maxsegsize */
1089 NULL, NULL, /* lockfunc, lockarg */
1090 &sc->jme_cdata.jme_tx_ring_tag);
1092 device_printf(sc->jme_dev,
1093 "could not allocate Tx ring DMA tag.\n");
1097 /* Create tag for Rx ring. */
1098 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1099 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1100 lowaddr, /* lowaddr */
1101 BUS_SPACE_MAXADDR, /* highaddr */
1102 NULL, NULL, /* filter, filterarg */
1103 JME_RX_RING_SIZE, /* maxsize */
1105 JME_RX_RING_SIZE, /* maxsegsize */
1107 NULL, NULL, /* lockfunc, lockarg */
1108 &sc->jme_cdata.jme_rx_ring_tag);
1110 device_printf(sc->jme_dev,
1111 "could not allocate Rx ring DMA tag.\n");
1115 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1116 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1117 (void **)&sc->jme_rdata.jme_tx_ring,
1118 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1119 &sc->jme_cdata.jme_tx_ring_map);
1121 device_printf(sc->jme_dev,
1122 "could not allocate DMA'able memory for Tx ring.\n");
1126 ctx.jme_busaddr = 0;
1127 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1128 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1129 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1130 if (error != 0 || ctx.jme_busaddr == 0) {
1131 device_printf(sc->jme_dev,
1132 "could not load DMA'able memory for Tx ring.\n");
1135 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1137 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1138 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1139 (void **)&sc->jme_rdata.jme_rx_ring,
1140 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1141 &sc->jme_cdata.jme_rx_ring_map);
1143 device_printf(sc->jme_dev,
1144 "could not allocate DMA'able memory for Rx ring.\n");
1148 ctx.jme_busaddr = 0;
1149 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1150 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1151 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1152 if (error != 0 || ctx.jme_busaddr == 0) {
1153 device_printf(sc->jme_dev,
1154 "could not load DMA'able memory for Rx ring.\n");
1157 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1159 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1160 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1161 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1163 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1165 if ((JME_ADDR_HI(tx_ring_end) !=
1166 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1167 (JME_ADDR_HI(rx_ring_end) !=
1168 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1169 device_printf(sc->jme_dev, "4GB boundary crossed, "
1170 "switching to 32bit DMA address mode.\n");
1172 /* Limit DMA address space to 32bit and try again. */
1173 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1178 lowaddr = BUS_SPACE_MAXADDR;
1179 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1180 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1181 /* Create parent buffer tag. */
1182 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1183 1, 0, /* algnmnt, boundary */
1184 lowaddr, /* lowaddr */
1185 BUS_SPACE_MAXADDR, /* highaddr */
1186 NULL, NULL, /* filter, filterarg */
1187 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1189 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1191 NULL, NULL, /* lockfunc, lockarg */
1192 &sc->jme_cdata.jme_buffer_tag);
1194 device_printf(sc->jme_dev,
1195 "could not create parent buffer DMA tag.\n");
1199 /* Create shadow status block tag. */
1200 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1201 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1202 BUS_SPACE_MAXADDR, /* lowaddr */
1203 BUS_SPACE_MAXADDR, /* highaddr */
1204 NULL, NULL, /* filter, filterarg */
1205 JME_SSB_SIZE, /* maxsize */
1207 JME_SSB_SIZE, /* maxsegsize */
1209 NULL, NULL, /* lockfunc, lockarg */
1210 &sc->jme_cdata.jme_ssb_tag);
1212 device_printf(sc->jme_dev,
1213 "could not create shared status block DMA tag.\n");
1217 /* Create tag for Tx buffers. */
1218 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1219 1, 0, /* algnmnt, boundary */
1220 BUS_SPACE_MAXADDR, /* lowaddr */
1221 BUS_SPACE_MAXADDR, /* highaddr */
1222 NULL, NULL, /* filter, filterarg */
1223 JME_TSO_MAXSIZE, /* maxsize */
1224 JME_MAXTXSEGS, /* nsegments */
1225 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1227 NULL, NULL, /* lockfunc, lockarg */
1228 &sc->jme_cdata.jme_tx_tag);
1230 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1234 /* Create tag for Rx buffers. */
1235 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1236 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1237 BUS_SPACE_MAXADDR, /* lowaddr */
1238 BUS_SPACE_MAXADDR, /* highaddr */
1239 NULL, NULL, /* filter, filterarg */
1240 MCLBYTES, /* maxsize */
1242 MCLBYTES, /* maxsegsize */
1244 NULL, NULL, /* lockfunc, lockarg */
1245 &sc->jme_cdata.jme_rx_tag);
1247 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1252 * Allocate DMA'able memory and load the DMA map for shared
1255 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1256 (void **)&sc->jme_rdata.jme_ssb_block,
1257 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1258 &sc->jme_cdata.jme_ssb_map);
1260 device_printf(sc->jme_dev, "could not allocate DMA'able "
1261 "memory for shared status block.\n");
1265 ctx.jme_busaddr = 0;
1266 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1267 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1268 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1269 if (error != 0 || ctx.jme_busaddr == 0) {
1270 device_printf(sc->jme_dev, "could not load DMA'able memory "
1271 "for shared status block.\n");
1274 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1276 /* Create DMA maps for Tx buffers. */
1277 for (i = 0; i < JME_TX_RING_CNT; i++) {
1278 txd = &sc->jme_cdata.jme_txdesc[i];
1280 txd->tx_dmamap = NULL;
1281 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1284 device_printf(sc->jme_dev,
1285 "could not create Tx dmamap.\n");
1289 /* Create DMA maps for Rx buffers. */
1290 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1291 &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1292 device_printf(sc->jme_dev,
1293 "could not create spare Rx dmamap.\n");
1296 for (i = 0; i < JME_RX_RING_CNT; i++) {
1297 rxd = &sc->jme_cdata.jme_rxdesc[i];
1299 rxd->rx_dmamap = NULL;
1300 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1303 device_printf(sc->jme_dev,
1304 "could not create Rx dmamap.\n");
1314 jme_dma_free(struct jme_softc *sc)
1316 struct jme_txdesc *txd;
1317 struct jme_rxdesc *rxd;
1321 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1322 if (sc->jme_cdata.jme_tx_ring_map)
1323 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1324 sc->jme_cdata.jme_tx_ring_map);
1325 if (sc->jme_cdata.jme_tx_ring_map &&
1326 sc->jme_rdata.jme_tx_ring)
1327 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1328 sc->jme_rdata.jme_tx_ring,
1329 sc->jme_cdata.jme_tx_ring_map);
1330 sc->jme_rdata.jme_tx_ring = NULL;
1331 sc->jme_cdata.jme_tx_ring_map = NULL;
1332 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1333 sc->jme_cdata.jme_tx_ring_tag = NULL;
1336 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1337 if (sc->jme_cdata.jme_rx_ring_map)
1338 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1339 sc->jme_cdata.jme_rx_ring_map);
1340 if (sc->jme_cdata.jme_rx_ring_map &&
1341 sc->jme_rdata.jme_rx_ring)
1342 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1343 sc->jme_rdata.jme_rx_ring,
1344 sc->jme_cdata.jme_rx_ring_map);
1345 sc->jme_rdata.jme_rx_ring = NULL;
1346 sc->jme_cdata.jme_rx_ring_map = NULL;
1347 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1348 sc->jme_cdata.jme_rx_ring_tag = NULL;
1351 if (sc->jme_cdata.jme_tx_tag != NULL) {
1352 for (i = 0; i < JME_TX_RING_CNT; i++) {
1353 txd = &sc->jme_cdata.jme_txdesc[i];
1354 if (txd->tx_dmamap != NULL) {
1355 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1357 txd->tx_dmamap = NULL;
1360 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1361 sc->jme_cdata.jme_tx_tag = NULL;
1364 if (sc->jme_cdata.jme_rx_tag != NULL) {
1365 for (i = 0; i < JME_RX_RING_CNT; i++) {
1366 rxd = &sc->jme_cdata.jme_rxdesc[i];
1367 if (rxd->rx_dmamap != NULL) {
1368 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1370 rxd->rx_dmamap = NULL;
1373 if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1374 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1375 sc->jme_cdata.jme_rx_sparemap);
1376 sc->jme_cdata.jme_rx_sparemap = NULL;
1378 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1379 sc->jme_cdata.jme_rx_tag = NULL;
1382 /* Shared status block. */
1383 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1384 if (sc->jme_cdata.jme_ssb_map)
1385 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1386 sc->jme_cdata.jme_ssb_map);
1387 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block)
1388 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1389 sc->jme_rdata.jme_ssb_block,
1390 sc->jme_cdata.jme_ssb_map);
1391 sc->jme_rdata.jme_ssb_block = NULL;
1392 sc->jme_cdata.jme_ssb_map = NULL;
1393 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1394 sc->jme_cdata.jme_ssb_tag = NULL;
1397 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1398 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1399 sc->jme_cdata.jme_buffer_tag = NULL;
1401 if (sc->jme_cdata.jme_ring_tag != NULL) {
1402 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1403 sc->jme_cdata.jme_ring_tag = NULL;
1408 * Make sure the interface is stopped at reboot time.
1411 jme_shutdown(device_t dev)
1414 return (jme_suspend(dev));
1418 * Unlike other ethernet controllers, JMC250 requires
1419 * explicit resetting link speed to 10/100Mbps as gigabit
1420 * link will cunsume more power than 375mA.
1421 * Note, we reset the link speed to 10/100Mbps with
1422 * auto-negotiation but we don't know whether that operation
1423 * would succeed or not as we have no control after powering
1424 * off. If the renegotiation fail WOL may not work. Running
1425 * at 1Gbps draws more power than 375mA at 3.3V which is
1426 * specified in PCI specification and that would result in
1427 * complete shutdowning power to ethernet controller.
1430 * Save current negotiated media speed/duplex/flow-control
1431 * to softc and restore the same link again after resuming.
1432 * PHY handling such as power down/resetting to 100Mbps
1433 * may be better handled in suspend method in phy driver.
1436 jme_setlinkspeed(struct jme_softc *sc)
1438 struct mii_data *mii;
1441 JME_LOCK_ASSERT(sc);
1443 mii = device_get_softc(sc->jme_miibus);
1446 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1447 switch IFM_SUBTYPE(mii->mii_media_active) {
1457 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1458 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1459 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1460 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1461 BMCR_AUTOEN | BMCR_STARTNEG);
1464 /* Poll link state until jme(4) get a 10/100 link. */
1465 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1467 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1468 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1478 pause("jmelnk", hz);
1481 if (i == MII_ANEGTICKS_GIGE)
1482 device_printf(sc->jme_dev, "establishing link failed, "
1483 "WOL may not work!");
1486 * No link, force MAC to have 100Mbps, full-duplex link.
1487 * This is the last resort and may/may not work.
1489 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1490 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1495 jme_setwol(struct jme_softc *sc)
1502 JME_LOCK_ASSERT(sc);
1504 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1505 /* Remove Tx MAC/offload clock to save more power. */
1506 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1507 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1508 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1509 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1510 /* No PME capability, PHY power down. */
1511 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1512 MII_BMCR, BMCR_PDOWN);
1517 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1518 pmcs = CSR_READ_4(sc, JME_PMCS);
1519 pmcs &= ~PMCS_WOL_ENB_MASK;
1520 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1521 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1522 /* Enable PME message. */
1523 gpr |= GPREG0_PME_ENB;
1524 /* For gigabit controllers, reset link speed to 10/100. */
1525 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1526 jme_setlinkspeed(sc);
1529 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1530 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1531 /* Remove Tx MAC/offload clock to save more power. */
1532 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1533 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1534 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1535 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1537 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1538 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1539 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1540 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1541 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1542 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1543 /* No WOL, PHY power down. */
1544 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1545 MII_BMCR, BMCR_PDOWN);
1550 jme_suspend(device_t dev)
1552 struct jme_softc *sc;
1554 sc = device_get_softc(dev);
1565 jme_resume(device_t dev)
1567 struct jme_softc *sc;
1572 sc = device_get_softc(dev);
1575 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1576 pmstat = pci_read_config(sc->jme_dev,
1577 pmc + PCIR_POWER_STATUS, 2);
1578 /* Disable PME clear PME status. */
1579 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1580 pci_write_config(sc->jme_dev,
1581 pmc + PCIR_POWER_STATUS, pmstat, 2);
1584 if ((ifp->if_flags & IFF_UP) != 0) {
1585 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1586 jme_init_locked(sc);
1595 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1597 struct jme_txdesc *txd;
1598 struct jme_desc *desc;
1600 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1601 int error, i, nsegs, prod;
1602 uint32_t cflags, tso_segsz;
1604 JME_LOCK_ASSERT(sc);
1606 M_ASSERTPKTHDR((*m_head));
1608 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1610 * Due to the adherence to NDIS specification JMC250
1611 * assumes upper stack computed TCP pseudo checksum
1612 * without including payload length. This breaks
1613 * checksum offload for TSO case so recompute TCP
1614 * pseudo checksum for JMC250. Hopefully this wouldn't
1615 * be much burden on modern CPUs.
1617 struct ether_header *eh;
1620 uint32_t ip_off, poff;
1622 if (M_WRITABLE(*m_head) == 0) {
1623 /* Get a writable copy. */
1624 m = m_dup(*m_head, M_DONTWAIT);
1632 ip_off = sizeof(struct ether_header);
1633 m = m_pullup(*m_head, ip_off);
1638 eh = mtod(m, struct ether_header *);
1639 /* Check the existence of VLAN tag. */
1640 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1641 ip_off = sizeof(struct ether_vlan_header);
1642 m = m_pullup(m, ip_off);
1648 m = m_pullup(m, ip_off + sizeof(struct ip));
1653 ip = (struct ip *)(mtod(m, char *) + ip_off);
1654 poff = ip_off + (ip->ip_hl << 2);
1655 m = m_pullup(m, poff + sizeof(struct tcphdr));
1661 * Reset IP checksum and recompute TCP pseudo
1662 * checksum that NDIS specification requires.
1664 ip = (struct ip *)(mtod(m, char *) + ip_off);
1665 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1667 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1668 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1670 htons((tcp->th_off << 2) + IPPROTO_TCP));
1671 /* No need to TSO, force IP checksum offload. */
1672 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1673 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1675 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1676 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1680 prod = sc->jme_cdata.jme_tx_prod;
1681 txd = &sc->jme_cdata.jme_txdesc[prod];
1683 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1684 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1685 if (error == EFBIG) {
1686 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS);
1693 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1694 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1700 } else if (error != 0)
1709 * Check descriptor overrun. Leave one free descriptor.
1710 * Since we always use 64bit address mode for transmitting,
1711 * each Tx request requires one more dummy descriptor.
1713 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1714 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1721 /* Configure checksum offload and TSO. */
1722 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1723 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1725 cflags |= JME_TD_TSO;
1727 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1728 cflags |= JME_TD_IPCSUM;
1729 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1730 cflags |= JME_TD_TCPCSUM;
1731 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1732 cflags |= JME_TD_UDPCSUM;
1734 /* Configure VLAN. */
1735 if ((m->m_flags & M_VLANTAG) != 0) {
1736 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1737 cflags |= JME_TD_VLAN_TAG;
1740 desc = &sc->jme_rdata.jme_tx_ring[prod];
1741 desc->flags = htole32(cflags);
1742 desc->buflen = htole32(tso_segsz);
1743 desc->addr_hi = htole32(m->m_pkthdr.len);
1745 sc->jme_cdata.jme_tx_cnt++;
1746 JME_DESC_INC(prod, JME_TX_RING_CNT);
1747 for (i = 0; i < nsegs; i++) {
1748 desc = &sc->jme_rdata.jme_tx_ring[prod];
1749 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1750 desc->buflen = htole32(txsegs[i].ds_len);
1751 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1752 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1753 sc->jme_cdata.jme_tx_cnt++;
1754 JME_DESC_INC(prod, JME_TX_RING_CNT);
1757 /* Update producer index. */
1758 sc->jme_cdata.jme_tx_prod = prod;
1760 * Finally request interrupt and give the first descriptor
1761 * owenership to hardware.
1763 desc = txd->tx_desc;
1764 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1767 txd->tx_ndesc = nsegs + 1;
1769 /* Sync descriptors. */
1770 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1771 BUS_DMASYNC_PREWRITE);
1772 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1773 sc->jme_cdata.jme_tx_ring_map,
1774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1780 jme_tx_task(void *arg, int pending)
1784 ifp = (struct ifnet *)arg;
1789 jme_start(struct ifnet *ifp)
1791 struct jme_softc *sc;
1792 struct mbuf *m_head;
1799 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1802 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1803 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) {
1808 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1809 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1813 * Pack the data into the transmit ring. If we
1814 * don't have room, set the OACTIVE flag and wait
1815 * for the NIC to drain the ring.
1817 if (jme_encap(sc, &m_head)) {
1820 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1821 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1827 * If there's a BPF listener, bounce a copy of this frame
1830 ETHER_BPF_MTAP(ifp, m_head);
1835 * Reading TXCSR takes very long time under heavy load
1836 * so cache TXCSR value and writes the ORed value with
1837 * the kick command to the TXCSR. This saves one register
1840 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1841 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1842 /* Set a timeout in case the chip goes out to lunch. */
1843 sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1850 jme_watchdog(struct jme_softc *sc)
1854 JME_LOCK_ASSERT(sc);
1856 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1860 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1861 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1863 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1864 jme_init_locked(sc);
1868 if (sc->jme_cdata.jme_tx_cnt == 0) {
1869 if_printf(sc->jme_ifp,
1870 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1871 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1872 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1876 if_printf(sc->jme_ifp, "watchdog timeout\n");
1878 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1879 jme_init_locked(sc);
1880 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1881 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1885 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1887 struct jme_softc *sc;
1889 struct mii_data *mii;
1894 ifr = (struct ifreq *)data;
1898 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1899 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1900 ifr->ifr_mtu > JME_MAX_MTU)) {
1905 if (ifp->if_mtu != ifr->ifr_mtu) {
1907 * No special configuration is required when interface
1908 * MTU is changed but availability of TSO/Tx checksum
1909 * offload should be chcked against new MTU size as
1910 * FIFO size is just 2K.
1913 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1914 ifp->if_capenable &=
1915 ~(IFCAP_TXCSUM | IFCAP_TSO4);
1917 ~(JME_CSUM_FEATURES | CSUM_TSO);
1918 VLAN_CAPABILITIES(ifp);
1920 ifp->if_mtu = ifr->ifr_mtu;
1921 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1922 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1923 jme_init_locked(sc);
1930 if ((ifp->if_flags & IFF_UP) != 0) {
1931 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1932 if (((ifp->if_flags ^ sc->jme_if_flags)
1933 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1936 if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
1937 jme_init_locked(sc);
1940 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1943 sc->jme_if_flags = ifp->if_flags;
1949 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1955 mii = device_get_softc(sc->jme_miibus);
1956 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1960 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1961 if ((mask & IFCAP_TXCSUM) != 0 &&
1962 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1963 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1964 ifp->if_capenable ^= IFCAP_TXCSUM;
1965 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1966 ifp->if_hwassist |= JME_CSUM_FEATURES;
1968 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1971 if ((mask & IFCAP_RXCSUM) != 0 &&
1972 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1973 ifp->if_capenable ^= IFCAP_RXCSUM;
1974 reg = CSR_READ_4(sc, JME_RXMAC);
1975 reg &= ~RXMAC_CSUM_ENB;
1976 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1977 reg |= RXMAC_CSUM_ENB;
1978 CSR_WRITE_4(sc, JME_RXMAC, reg);
1980 if ((mask & IFCAP_TSO4) != 0 &&
1981 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1982 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1983 ifp->if_capenable ^= IFCAP_TSO4;
1984 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1985 ifp->if_hwassist |= CSUM_TSO;
1987 ifp->if_hwassist &= ~CSUM_TSO;
1990 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1991 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0)
1992 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1993 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1994 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1995 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1996 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1997 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1998 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1999 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2000 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
2001 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2005 VLAN_CAPABILITIES(ifp);
2008 error = ether_ioctl(ifp, cmd, data);
2016 jme_mac_config(struct jme_softc *sc)
2018 struct mii_data *mii;
2019 uint32_t ghc, gpreg, rxmac, txmac, txpause;
2022 JME_LOCK_ASSERT(sc);
2024 mii = device_get_softc(sc->jme_miibus);
2026 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2028 CSR_WRITE_4(sc, JME_GHC, 0);
2031 rxmac = CSR_READ_4(sc, JME_RXMAC);
2032 rxmac &= ~RXMAC_FC_ENB;
2033 txmac = CSR_READ_4(sc, JME_TXMAC);
2034 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2035 txpause = CSR_READ_4(sc, JME_TXPFC);
2036 txpause &= ~TXPFC_PAUSE_ENB;
2037 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2038 ghc |= GHC_FULL_DUPLEX;
2039 rxmac &= ~RXMAC_COLL_DET_ENB;
2040 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2041 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2044 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2045 txpause |= TXPFC_PAUSE_ENB;
2046 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2047 rxmac |= RXMAC_FC_ENB;
2049 /* Disable retry transmit timer/retry limit. */
2050 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2051 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2053 rxmac |= RXMAC_COLL_DET_ENB;
2054 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2055 /* Enable retry transmit timer/retry limit. */
2056 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2057 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2059 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2060 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2062 ghc |= GHC_SPEED_10;
2063 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2066 ghc |= GHC_SPEED_100;
2067 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2070 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2072 ghc |= GHC_SPEED_1000;
2073 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2074 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2075 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2080 if (sc->jme_rev == DEVICEID_JMC250 &&
2081 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2083 * Workaround occasional packet loss issue of JMC250 A2
2084 * when it runs on half-duplex media.
2086 gpreg = CSR_READ_4(sc, JME_GPREG1);
2087 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2088 gpreg &= ~GPREG1_HDPX_FIX;
2090 gpreg |= GPREG1_HDPX_FIX;
2091 CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2092 /* Workaround CRC errors at 100Mbps on JMC250 A2. */
2093 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2094 /* Extend interface FIFO depth. */
2095 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2098 /* Select default interface FIFO depth. */
2099 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2103 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2105 CSR_WRITE_4(sc, JME_GHC, ghc);
2106 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2107 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2108 CSR_WRITE_4(sc, JME_TXPFC, txpause);
2112 jme_link_task(void *arg, int pending)
2114 struct jme_softc *sc;
2115 struct mii_data *mii;
2117 struct jme_txdesc *txd;
2121 sc = (struct jme_softc *)arg;
2124 mii = device_get_softc(sc->jme_miibus);
2126 if (mii == NULL || ifp == NULL ||
2127 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2132 sc->jme_flags &= ~JME_FLAG_LINK;
2133 if ((mii->mii_media_status & IFM_AVALID) != 0) {
2134 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2137 sc->jme_flags |= JME_FLAG_LINK;
2140 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2142 sc->jme_flags |= JME_FLAG_LINK;
2150 * Disabling Rx/Tx MACs have a side-effect of resetting
2151 * JME_TXNDA/JME_RXNDA register to the first address of
2152 * Tx/Rx descriptor address. So driver should reset its
2153 * internal procucer/consumer pointer and reclaim any
2154 * allocated resources. Note, just saving the value of
2155 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2156 * and restoring JME_TXNDA/JME_RXNDA register is not
2157 * sufficient to make sure correct MAC state because
2158 * stopping MAC operation can take a while and hardware
2159 * might have updated JME_TXNDA/JME_RXNDA registers
2160 * during the stop operation.
2162 /* Block execution of task. */
2163 taskqueue_block(sc->jme_tq);
2164 /* Disable interrupts and stop driver. */
2165 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2166 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2167 callout_stop(&sc->jme_tick_ch);
2168 sc->jme_watchdog_timer = 0;
2170 /* Stop receiver/transmitter. */
2174 /* XXX Drain all queued tasks. */
2176 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2177 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
2180 jme_rxintr(sc, JME_RX_RING_CNT);
2181 if (sc->jme_cdata.jme_rxhead != NULL)
2182 m_freem(sc->jme_cdata.jme_rxhead);
2183 JME_RXCHAIN_RESET(sc);
2185 if (sc->jme_cdata.jme_tx_cnt != 0) {
2186 /* Remove queued packets for transmit. */
2187 for (i = 0; i < JME_TX_RING_CNT; i++) {
2188 txd = &sc->jme_cdata.jme_txdesc[i];
2189 if (txd->tx_m != NULL) {
2191 sc->jme_cdata.jme_tx_tag,
2193 BUS_DMASYNC_POSTWRITE);
2195 sc->jme_cdata.jme_tx_tag,
2206 * Reuse configured Rx descriptors and reset
2207 * procuder/consumer index.
2209 sc->jme_cdata.jme_rx_cons = 0;
2210 atomic_set_int(&sc->jme_morework, 0);
2211 jme_init_tx_ring(sc);
2212 /* Initialize shadow status block. */
2215 /* Program MAC with resolved speed/duplex/flow-control. */
2216 if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2218 jme_stats_clear(sc);
2220 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2221 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2223 /* Set Tx ring address to the hardware. */
2224 paddr = JME_TX_RING_ADDR(sc, 0);
2225 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2226 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2228 /* Set Rx ring address to the hardware. */
2229 paddr = JME_RX_RING_ADDR(sc, 0);
2230 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2231 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2233 /* Restart receiver/transmitter. */
2234 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2236 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2239 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2240 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2241 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2242 /* Unblock execution of task. */
2243 taskqueue_unblock(sc->jme_tq);
2244 /* Reenable interrupts. */
2245 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2253 struct jme_softc *sc;
2256 sc = (struct jme_softc *)arg;
2258 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2259 if (status == 0 || status == 0xFFFFFFFF)
2260 return (FILTER_STRAY);
2261 /* Disable interrupts. */
2262 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2263 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2265 return (FILTER_HANDLED);
2269 jme_int_task(void *arg, int pending)
2271 struct jme_softc *sc;
2276 sc = (struct jme_softc *)arg;
2279 status = CSR_READ_4(sc, JME_INTR_STATUS);
2280 more = atomic_readandclear_int(&sc->jme_morework);
2282 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2285 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2287 /* Reset PCC counter/timer and Ack interrupts. */
2288 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2289 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2290 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2291 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2292 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2293 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2295 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2296 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2297 more = jme_rxintr(sc, sc->jme_process_limit);
2299 atomic_set_int(&sc->jme_morework, 1);
2301 if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2303 * Notify hardware availability of new Rx
2305 * Reading RXCSR takes very long time under
2306 * heavy load so cache RXCSR value and writes
2307 * the ORed value with the kick command to
2308 * the RXCSR. This saves one register access
2311 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2312 RXCSR_RX_ENB | RXCSR_RXQ_START);
2315 * Reclaiming Tx buffers are deferred to make jme(4) run
2316 * without locks held.
2318 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2319 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
2322 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2323 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2327 /* Reenable interrupts. */
2328 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2332 jme_txeof(struct jme_softc *sc)
2335 struct jme_txdesc *txd;
2339 JME_LOCK_ASSERT(sc);
2343 cons = sc->jme_cdata.jme_tx_cons;
2344 if (cons == sc->jme_cdata.jme_tx_prod)
2347 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2348 sc->jme_cdata.jme_tx_ring_map,
2349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2352 * Go through our Tx list and free mbufs for those
2353 * frames which have been transmitted.
2355 for (; cons != sc->jme_cdata.jme_tx_prod;) {
2356 txd = &sc->jme_cdata.jme_txdesc[cons];
2357 status = le32toh(txd->tx_desc->flags);
2358 if ((status & JME_TD_OWN) == JME_TD_OWN)
2361 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2365 if ((status & JME_TD_COLLISION) != 0)
2366 ifp->if_collisions +=
2367 le32toh(txd->tx_desc->buflen) &
2368 JME_TD_BUF_LEN_MASK;
2371 * Only the first descriptor of multi-descriptor
2372 * transmission is updated so driver have to skip entire
2373 * chained buffers for the transmiited frame. In other
2374 * words, JME_TD_OWN bit is valid only at the first
2375 * descriptor of a multi-descriptor transmission.
2377 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2378 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2379 JME_DESC_INC(cons, JME_TX_RING_CNT);
2382 /* Reclaim transferred mbufs. */
2383 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2384 BUS_DMASYNC_POSTWRITE);
2385 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2387 KASSERT(txd->tx_m != NULL,
2388 ("%s: freeing NULL mbuf!\n", __func__));
2391 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2392 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2393 ("%s: Active Tx desc counter was garbled\n", __func__));
2395 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2397 sc->jme_cdata.jme_tx_cons = cons;
2398 /* Unarm watchog timer when there is no pending descriptors in queue. */
2399 if (sc->jme_cdata.jme_tx_cnt == 0)
2400 sc->jme_watchdog_timer = 0;
2402 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2403 sc->jme_cdata.jme_tx_ring_map,
2404 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2407 static __inline void
2408 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2410 struct jme_desc *desc;
2412 desc = &sc->jme_rdata.jme_rx_ring[cons];
2413 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2414 desc->buflen = htole32(MCLBYTES);
2417 /* Receive a frame. */
2419 jme_rxeof(struct jme_softc *sc)
2422 struct jme_desc *desc;
2423 struct jme_rxdesc *rxd;
2424 struct mbuf *mp, *m;
2425 uint32_t flags, status;
2426 int cons, count, nsegs;
2430 cons = sc->jme_cdata.jme_rx_cons;
2431 desc = &sc->jme_rdata.jme_rx_ring[cons];
2432 flags = le32toh(desc->flags);
2433 status = le32toh(desc->buflen);
2434 nsegs = JME_RX_NSEGS(status);
2435 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2436 if ((status & JME_RX_ERR_STAT) != 0) {
2438 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2439 #ifdef JME_SHOW_ERRORS
2440 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2441 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2443 sc->jme_cdata.jme_rx_cons += nsegs;
2444 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2448 for (count = 0; count < nsegs; count++,
2449 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2450 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2452 /* Add a new receive buffer to the ring. */
2453 if (jme_newbuf(sc, rxd) != 0) {
2456 for (; count < nsegs; count++) {
2457 jme_discard_rxbuf(sc, cons);
2458 JME_DESC_INC(cons, JME_RX_RING_CNT);
2460 if (sc->jme_cdata.jme_rxhead != NULL) {
2461 m_freem(sc->jme_cdata.jme_rxhead);
2462 JME_RXCHAIN_RESET(sc);
2468 * Assume we've received a full sized frame.
2469 * Actual size is fixed when we encounter the end of
2470 * multi-segmented frame.
2472 mp->m_len = MCLBYTES;
2474 /* Chain received mbufs. */
2475 if (sc->jme_cdata.jme_rxhead == NULL) {
2476 sc->jme_cdata.jme_rxhead = mp;
2477 sc->jme_cdata.jme_rxtail = mp;
2480 * Receive processor can receive a maximum frame
2481 * size of 65535 bytes.
2483 mp->m_flags &= ~M_PKTHDR;
2484 sc->jme_cdata.jme_rxtail->m_next = mp;
2485 sc->jme_cdata.jme_rxtail = mp;
2488 if (count == nsegs - 1) {
2489 /* Last desc. for this frame. */
2490 m = sc->jme_cdata.jme_rxhead;
2491 m->m_flags |= M_PKTHDR;
2492 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2494 /* Set first mbuf size. */
2495 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2496 /* Set last mbuf size. */
2497 mp->m_len = sc->jme_cdata.jme_rxlen -
2498 ((MCLBYTES - JME_RX_PAD_BYTES) +
2499 (MCLBYTES * (nsegs - 2)));
2501 m->m_len = sc->jme_cdata.jme_rxlen;
2502 m->m_pkthdr.rcvif = ifp;
2505 * Account for 10bytes auto padding which is used
2506 * to align IP header on 32bit boundary. Also note,
2507 * CRC bytes is automatically removed by the
2510 m->m_data += JME_RX_PAD_BYTES;
2512 /* Set checksum information. */
2513 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2514 (flags & JME_RD_IPV4) != 0) {
2515 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2516 if ((flags & JME_RD_IPCSUM) != 0)
2517 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2518 if (((flags & JME_RD_MORE_FRAG) == 0) &&
2519 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2520 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2521 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2522 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2523 m->m_pkthdr.csum_flags |=
2524 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2525 m->m_pkthdr.csum_data = 0xffff;
2529 /* Check for VLAN tagged packets. */
2530 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2531 (flags & JME_RD_VLAN_TAG) != 0) {
2532 m->m_pkthdr.ether_vtag =
2533 flags & JME_RD_VLAN_MASK;
2534 m->m_flags |= M_VLANTAG;
2539 (*ifp->if_input)(ifp, m);
2541 /* Reset mbuf chains. */
2542 JME_RXCHAIN_RESET(sc);
2546 sc->jme_cdata.jme_rx_cons += nsegs;
2547 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2551 jme_rxintr(struct jme_softc *sc, int count)
2553 struct jme_desc *desc;
2554 int nsegs, prog, pktlen;
2556 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2557 sc->jme_cdata.jme_rx_ring_map,
2558 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2560 for (prog = 0; count > 0; prog++) {
2561 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2562 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2564 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2566 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2568 * Check number of segments against received bytes.
2569 * Non-matching value would indicate that hardware
2570 * is still trying to update Rx descriptors. I'm not
2571 * sure whether this check is needed.
2573 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2574 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES))
2577 /* Received a frame. */
2583 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2584 sc->jme_cdata.jme_rx_ring_map,
2585 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2587 return (count > 0 ? 0 : EAGAIN);
2593 struct jme_softc *sc;
2594 struct mii_data *mii;
2596 sc = (struct jme_softc *)arg;
2598 JME_LOCK_ASSERT(sc);
2600 mii = device_get_softc(sc->jme_miibus);
2603 * Reclaim Tx buffers that have been completed. It's not
2604 * needed here but it would release allocated mbuf chains
2605 * faster and limit the maximum delay to a hz.
2608 jme_stats_update(sc);
2610 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2614 jme_reset(struct jme_softc *sc)
2617 /* Stop receiver, transmitter. */
2620 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2622 CSR_WRITE_4(sc, JME_GHC, 0);
2628 struct jme_softc *sc;
2630 sc = (struct jme_softc *)xsc;
2632 jme_init_locked(sc);
2637 jme_init_locked(struct jme_softc *sc)
2640 struct mii_data *mii;
2641 uint8_t eaddr[ETHER_ADDR_LEN];
2646 JME_LOCK_ASSERT(sc);
2649 mii = device_get_softc(sc->jme_miibus);
2651 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2654 * Cancel any pending I/O.
2659 * Reset the chip to a known state.
2663 /* Init descriptors. */
2664 error = jme_init_rx_ring(sc);
2666 device_printf(sc->jme_dev,
2667 "%s: initialization failed: no memory for Rx buffers.\n",
2672 jme_init_tx_ring(sc);
2673 /* Initialize shadow status block. */
2676 /* Reprogram the station address. */
2677 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2678 CSR_WRITE_4(sc, JME_PAR0,
2679 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2680 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2683 * Configure Tx queue.
2684 * Tx priority queue weight value : 0
2685 * Tx FIFO threshold for processing next packet : 16QW
2686 * Maximum Tx DMA length : 512
2687 * Allow Tx DMA burst.
2689 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2690 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2691 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2692 sc->jme_txcsr |= sc->jme_tx_dma_size;
2693 sc->jme_txcsr |= TXCSR_DMA_BURST;
2694 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2696 /* Set Tx descriptor counter. */
2697 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2699 /* Set Tx ring address to the hardware. */
2700 paddr = JME_TX_RING_ADDR(sc, 0);
2701 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2702 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2704 /* Configure TxMAC parameters. */
2705 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2706 reg |= TXMAC_THRESH_1_PKT;
2707 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2708 CSR_WRITE_4(sc, JME_TXMAC, reg);
2711 * Configure Rx queue.
2712 * FIFO full threshold for transmitting Tx pause packet : 128T
2713 * FIFO threshold for processing next packet : 128QW
2715 * Max Rx DMA length : 128
2716 * Rx descriptor retry : 32
2717 * Rx descriptor retry time gap : 256ns
2718 * Don't receive runt/bad frame.
2720 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2722 * Since Rx FIFO size is 4K bytes, receiving frames larger
2723 * than 4K bytes will suffer from Rx FIFO overruns. So
2724 * decrease FIFO threshold to reduce the FIFO overruns for
2725 * frames larger than 4000 bytes.
2726 * For best performance of standard MTU sized frames use
2727 * maximum allowable FIFO threshold, 128QW. Note these do
2728 * not hold on chip full mask verion >=2. For these
2729 * controllers 64QW and 128QW are not valid value.
2731 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2732 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2734 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2735 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2736 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2738 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2740 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2741 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2742 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2743 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2745 /* Set Rx descriptor counter. */
2746 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2748 /* Set Rx ring address to the hardware. */
2749 paddr = JME_RX_RING_ADDR(sc, 0);
2750 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2751 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2753 /* Clear receive filter. */
2754 CSR_WRITE_4(sc, JME_RXMAC, 0);
2755 /* Set up the receive filter. */
2760 * Disable all WOL bits as WOL can interfere normal Rx
2761 * operation. Also clear WOL detection status bits.
2763 reg = CSR_READ_4(sc, JME_PMCS);
2764 reg &= ~PMCS_WOL_ENB_MASK;
2765 CSR_WRITE_4(sc, JME_PMCS, reg);
2767 reg = CSR_READ_4(sc, JME_RXMAC);
2769 * Pad 10bytes right before received frame. This will greatly
2770 * help Rx performance on strict-alignment architectures as
2771 * it does not need to copy the frame to align the payload.
2773 reg |= RXMAC_PAD_10BYTES;
2774 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2775 reg |= RXMAC_CSUM_ENB;
2776 CSR_WRITE_4(sc, JME_RXMAC, reg);
2778 /* Configure general purpose reg0 */
2779 reg = CSR_READ_4(sc, JME_GPREG0);
2780 reg &= ~GPREG0_PCC_UNIT_MASK;
2781 /* Set PCC timer resolution to micro-seconds unit. */
2782 reg |= GPREG0_PCC_UNIT_US;
2784 * Disable all shadow register posting as we have to read
2785 * JME_INTR_STATUS register in jme_int_task. Also it seems
2786 * that it's hard to synchronize interrupt status between
2787 * hardware and software with shadow posting due to
2788 * requirements of bus_dmamap_sync(9).
2790 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2791 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2792 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2793 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2794 /* Disable posting of DW0. */
2795 reg &= ~GPREG0_POST_DW0_ENB;
2796 /* Clear PME message. */
2797 reg &= ~GPREG0_PME_ENB;
2798 /* Set PHY address. */
2799 reg &= ~GPREG0_PHY_ADDR_MASK;
2800 reg |= sc->jme_phyaddr;
2801 CSR_WRITE_4(sc, JME_GPREG0, reg);
2803 /* Configure Tx queue 0 packet completion coalescing. */
2804 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2806 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2807 PCCTX_COAL_PKT_MASK;
2808 reg |= PCCTX_COAL_TXQ0;
2809 CSR_WRITE_4(sc, JME_PCCTX, reg);
2811 /* Configure Rx queue 0 packet completion coalescing. */
2812 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2814 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2815 PCCRX_COAL_PKT_MASK;
2816 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2818 /* Configure shadow status block but don't enable posting. */
2819 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2820 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2821 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2823 /* Disable Timer 1 and Timer 2. */
2824 CSR_WRITE_4(sc, JME_TIMER1, 0);
2825 CSR_WRITE_4(sc, JME_TIMER2, 0);
2827 /* Configure retry transmit period, retry limit value. */
2828 CSR_WRITE_4(sc, JME_TXTRHD,
2829 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2830 TXTRHD_RT_PERIOD_MASK) |
2831 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2832 TXTRHD_RT_LIMIT_SHIFT));
2835 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2837 /* Initialize the interrupt mask. */
2838 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2839 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2842 * Enabling Tx/Rx DMA engines and Rx queue processing is
2843 * done after detection of valid link in jme_link_task.
2846 sc->jme_flags &= ~JME_FLAG_LINK;
2847 /* Set the current media. */
2850 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2852 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2853 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2857 jme_stop(struct jme_softc *sc)
2860 struct jme_txdesc *txd;
2861 struct jme_rxdesc *rxd;
2864 JME_LOCK_ASSERT(sc);
2866 * Mark the interface down and cancel the watchdog timer.
2869 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2870 sc->jme_flags &= ~JME_FLAG_LINK;
2871 callout_stop(&sc->jme_tick_ch);
2872 sc->jme_watchdog_timer = 0;
2875 * Disable interrupts.
2877 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2878 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2880 /* Disable updating shadow status block. */
2881 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2882 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2884 /* Stop receiver, transmitter. */
2888 /* Reclaim Rx/Tx buffers that have been completed. */
2889 jme_rxintr(sc, JME_RX_RING_CNT);
2890 if (sc->jme_cdata.jme_rxhead != NULL)
2891 m_freem(sc->jme_cdata.jme_rxhead);
2892 JME_RXCHAIN_RESET(sc);
2895 * Free RX and TX mbufs still in the queues.
2897 for (i = 0; i < JME_RX_RING_CNT; i++) {
2898 rxd = &sc->jme_cdata.jme_rxdesc[i];
2899 if (rxd->rx_m != NULL) {
2900 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
2901 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2902 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2908 for (i = 0; i < JME_TX_RING_CNT; i++) {
2909 txd = &sc->jme_cdata.jme_txdesc[i];
2910 if (txd->tx_m != NULL) {
2911 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
2912 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2913 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2920 jme_stats_update(sc);
2925 jme_stop_tx(struct jme_softc *sc)
2930 reg = CSR_READ_4(sc, JME_TXCSR);
2931 if ((reg & TXCSR_TX_ENB) == 0)
2933 reg &= ~TXCSR_TX_ENB;
2934 CSR_WRITE_4(sc, JME_TXCSR, reg);
2935 for (i = JME_TIMEOUT; i > 0; i--) {
2937 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2941 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2945 jme_stop_rx(struct jme_softc *sc)
2950 reg = CSR_READ_4(sc, JME_RXCSR);
2951 if ((reg & RXCSR_RX_ENB) == 0)
2953 reg &= ~RXCSR_RX_ENB;
2954 CSR_WRITE_4(sc, JME_RXCSR, reg);
2955 for (i = JME_TIMEOUT; i > 0; i--) {
2957 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2961 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2965 jme_init_tx_ring(struct jme_softc *sc)
2967 struct jme_ring_data *rd;
2968 struct jme_txdesc *txd;
2971 sc->jme_cdata.jme_tx_prod = 0;
2972 sc->jme_cdata.jme_tx_cons = 0;
2973 sc->jme_cdata.jme_tx_cnt = 0;
2975 rd = &sc->jme_rdata;
2976 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2977 for (i = 0; i < JME_TX_RING_CNT; i++) {
2978 txd = &sc->jme_cdata.jme_txdesc[i];
2980 txd->tx_desc = &rd->jme_tx_ring[i];
2984 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2985 sc->jme_cdata.jme_tx_ring_map,
2986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2990 jme_init_ssb(struct jme_softc *sc)
2992 struct jme_ring_data *rd;
2994 rd = &sc->jme_rdata;
2995 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2996 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3001 jme_init_rx_ring(struct jme_softc *sc)
3003 struct jme_ring_data *rd;
3004 struct jme_rxdesc *rxd;
3007 sc->jme_cdata.jme_rx_cons = 0;
3008 JME_RXCHAIN_RESET(sc);
3009 atomic_set_int(&sc->jme_morework, 0);
3011 rd = &sc->jme_rdata;
3012 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
3013 for (i = 0; i < JME_RX_RING_CNT; i++) {
3014 rxd = &sc->jme_cdata.jme_rxdesc[i];
3016 rxd->rx_desc = &rd->jme_rx_ring[i];
3017 if (jme_newbuf(sc, rxd) != 0)
3021 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3022 sc->jme_cdata.jme_rx_ring_map,
3023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3029 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3031 struct jme_desc *desc;
3033 bus_dma_segment_t segs[1];
3037 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3041 * JMC250 has 64bit boundary alignment limitation so jme(4)
3042 * takes advantage of 10 bytes padding feature of hardware
3043 * in order not to copy entire frame to align IP header on
3046 m->m_len = m->m_pkthdr.len = MCLBYTES;
3048 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3049 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3053 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3055 if (rxd->rx_m != NULL) {
3056 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3057 BUS_DMASYNC_POSTREAD);
3058 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3060 map = rxd->rx_dmamap;
3061 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3062 sc->jme_cdata.jme_rx_sparemap = map;
3063 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3064 BUS_DMASYNC_PREREAD);
3067 desc = rxd->rx_desc;
3068 desc->buflen = htole32(segs[0].ds_len);
3069 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3070 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3071 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3077 jme_set_vlan(struct jme_softc *sc)
3082 JME_LOCK_ASSERT(sc);
3085 reg = CSR_READ_4(sc, JME_RXMAC);
3086 reg &= ~RXMAC_VLAN_ENB;
3087 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3088 reg |= RXMAC_VLAN_ENB;
3089 CSR_WRITE_4(sc, JME_RXMAC, reg);
3093 jme_set_filter(struct jme_softc *sc)
3096 struct ifmultiaddr *ifma;
3101 JME_LOCK_ASSERT(sc);
3105 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3106 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3108 /* Always accept frames destined to our station address. */
3109 rxcfg |= RXMAC_UNICAST;
3110 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3111 rxcfg |= RXMAC_BROADCAST;
3112 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3113 if ((ifp->if_flags & IFF_PROMISC) != 0)
3114 rxcfg |= RXMAC_PROMISC;
3115 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3116 rxcfg |= RXMAC_ALLMULTI;
3117 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3118 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3119 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3124 * Set up the multicast address filter by passing all multicast
3125 * addresses through a CRC generator, and then using the low-order
3126 * 6 bits as an index into the 64 bit multicast hash table. The
3127 * high order bits select the register, while the rest of the bits
3128 * select the bit within the register.
3130 rxcfg |= RXMAC_MULTICAST;
3131 bzero(mchash, sizeof(mchash));
3133 if_maddr_rlock(ifp);
3134 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
3135 if (ifma->ifma_addr->sa_family != AF_LINK)
3137 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3138 ifma->ifma_addr), ETHER_ADDR_LEN);
3140 /* Just want the 6 least significant bits. */
3143 /* Set the corresponding bit in the hash table. */
3144 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3146 if_maddr_runlock(ifp);
3148 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3149 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3150 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3154 jme_stats_clear(struct jme_softc *sc)
3157 JME_LOCK_ASSERT(sc);
3159 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3162 /* Disable and clear counters. */
3163 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3164 /* Activate hw counters. */
3165 CSR_WRITE_4(sc, JME_STATCSR, 0);
3166 CSR_READ_4(sc, JME_STATCSR);
3167 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3171 jme_stats_save(struct jme_softc *sc)
3174 JME_LOCK_ASSERT(sc);
3176 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3178 /* Save current counters. */
3179 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3180 /* Disable and clear counters. */
3181 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3185 jme_stats_update(struct jme_softc *sc)
3187 struct jme_hw_stats *stat, *ostat;
3190 JME_LOCK_ASSERT(sc);
3192 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3194 stat = &sc->jme_stats;
3195 ostat = &sc->jme_ostats;
3196 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3197 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3198 reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3199 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3200 STAT_RX_CRC_ERR_SHIFT;
3201 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3202 STAT_RX_MII_ERR_SHIFT;
3203 reg = CSR_READ_4(sc, JME_STAT_RXERR);
3204 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3205 STAT_RXERR_OFLOW_SHIFT;
3206 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3207 STAT_RXERR_MPTY_SHIFT;
3208 reg = CSR_READ_4(sc, JME_STAT_FAIL);
3209 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3210 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3212 /* Account for previous counters. */
3213 stat->rx_good_frames += ostat->rx_good_frames;
3214 stat->rx_crc_errs += ostat->rx_crc_errs;
3215 stat->rx_mii_errs += ostat->rx_mii_errs;
3216 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3217 stat->rx_desc_empty += ostat->rx_desc_empty;
3218 stat->rx_bad_frames += ostat->rx_bad_frames;
3219 stat->tx_good_frames += ostat->tx_good_frames;
3220 stat->tx_bad_frames += ostat->tx_bad_frames;
3224 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3230 value = *(int *)arg1;
3231 error = sysctl_handle_int(oidp, &value, 0, req);
3232 if (error || req->newptr == NULL)
3234 if (value < low || value > high)
3236 *(int *)arg1 = value;
3242 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3244 return (sysctl_int_range(oidp, arg1, arg2, req,
3245 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3249 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3251 return (sysctl_int_range(oidp, arg1, arg2, req,
3252 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3256 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3258 return (sysctl_int_range(oidp, arg1, arg2, req,
3259 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3263 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3265 return (sysctl_int_range(oidp, arg1, arg2, req,
3266 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3270 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3272 return (sysctl_int_range(oidp, arg1, arg2, req,
3273 JME_PROC_MIN, JME_PROC_MAX));