2 * Copyright (c) 2007 Marvell Semiconductor, Inc.
3 * Copyright (c) 2007 Sam Leffler, Errno Consulting
4 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
35 * Definitions for the Marvell 88W8335 Wireless LAN controller.
40 #include <net80211/ieee80211_radiotap.h>
41 #include <dev/malo/if_malohal.h>
42 #include <dev/malo/if_maloioctl.h>
45 #define MALO_TXBUF 256 /* number of TX descriptors/buffers */
48 #define MALO_RXBUF 256 /* number of RX descriptors/buffers */
51 #define MALO_TXDESC 1 /* max tx descriptors/segments */
53 #define MALO_RXSIZE PAGE_SIZE
54 #define MALO_RSSI_DUMMY_MARKER 127
55 #define MALO_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
57 #define MALO_REG_INT_CODE 0x00000C14
58 /* From host to ARM */
59 #define MALO_REG_H2A_INTERRUPT_EVENTS 0x00000C18
61 /* bit definitions for MALO_REG_H2A_INTERRUPT_CAUSE */
62 #define MALO_H2ARIC_BIT_PPA_READY 0x00000001
63 #define MALO_H2ARIC_BIT_DOOR_BELL 0x00000002 /* bit 1 */
64 #define MALO_H2ARIC_BIT_PS 0x00000004
65 #define MALO_H2ARIC_BIT_PSPOLL 0x00000008 /* bit 3 */
67 /* From ARM to host */
68 #define MALO_REG_A2H_INTERRUPT_CAUSE 0x00000C30
69 #define MALO_REG_A2H_INTERRUPT_MASK 0x00000C34
70 #define MALO_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38
71 #define MALO_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C
73 /* bit definitions for MALO_REG_A2H_INTERRUPT_CAUSE */
74 #define MALO_A2HRIC_BIT_TX_DONE 0x00000001 /* bit 0 */
75 #define MALO_A2HRIC_BIT_RX_RDY 0x00000002 /* bit 1 */
76 #define MALO_A2HRIC_BIT_OPC_DONE 0x00000004
77 #define MALO_A2HRIC_BIT_MAC_EVENT 0x00000008
78 #define MALO_A2HRIC_BIT_RX_PROBLEM 0x00000010
79 #define MALO_A2HRIC_BIT_RADIO_OFF 0x00000020 /* bit 5 */
80 #define MALO_A2HRIC_BIT_RADIO_ON 0x00000040
81 #define MALO_A2HRIC_BIT_RADAR_DETECT 0x00000080
82 #define MALO_A2HRIC_BIT_ICV_ERROR 0x00000100
83 #define MALO_A2HRIC_BIT_MIC_ERROR 0x00000200 /* bit 9 */
84 #define MALO_A2HRIC_BIT_QUEUE_EMPTY 0x00000400
85 #define MALO_A2HRIC_BIT_QUEUE_FULL 0x00000800
86 #define MALO_A2HRIC_BIT_CHAN_SWITCH 0x00001000
87 #define MALO_A2HRIC_BIT_TX_WATCHDOG 0x00002000
88 #define MALO_A2HRIC_BIT_BA_WATCHDOG 0x00004000
90 #define MALO_ISR_SRC_BITS \
91 (MALO_A2HRIC_BIT_RX_RDY | \
92 MALO_A2HRIC_BIT_TX_DONE | \
93 MALO_A2HRIC_BIT_OPC_DONE | \
94 MALO_A2HRIC_BIT_MAC_EVENT | \
95 MALO_A2HRIC_BIT_MIC_ERROR | \
96 MALO_A2HRIC_BIT_ICV_ERROR | \
97 MALO_A2HRIC_BIT_RADAR_DETECT | \
98 MALO_A2HRIC_BIT_CHAN_SWITCH | \
99 MALO_A2HRIC_BIT_TX_WATCHDOG | \
100 MALO_A2HRIC_BIT_QUEUE_EMPTY)
101 #define MALO_ISR_RESET (1<<15)
103 #define MALO_A2HRIC_BIT_MASK MALO_ISR_SRC_BITS
105 /* map to 0x80000000 on BAR1 */
106 #define MALO_REG_GEN_PTR 0x00000C10
107 #define MALO_REG_INT_CODE 0x00000C14
108 #define MALO_REG_SCRATCH 0x00000C40
111 * define OpMode for SoftAP/Station mode
113 * the following mode signature has to be written to PCI scratch register#0
114 * right after successfully downloading the last block of firmware and
115 * before waiting for firmware ready signature
117 #define MALO_HOSTCMD_STA_MODE 0x5A
118 #define MALO_HOSTCMD_STA_FWRDY_SIGNATURE 0xF0F1F2F4
121 * 16 bit host command code
123 #define MALO_HOSTCMD_NONE 0x0000
124 #define MALO_HOSTCMD_CODE_DNLD 0x0001
125 #define MALO_HOSTCMD_GET_HW_SPEC 0x0003
126 #define MALO_HOSTCMD_SET_HW_SPEC 0x0004
127 #define MALO_HOSTCMD_MAC_MULTICAST_ADR 0x0010
128 #define MALO_HOSTCMD_SET_WEPKEY 0x0013
129 #define MALO_HOSTCMD_802_11_RADIO_CONTROL 0x001c
130 #define MALO_HOSTCMD_802_11_RF_TX_POWER 0x001e
131 #define MALO_HOSTCMD_802_11_RF_ANTENNA 0x0020
132 #define MALO_HOSTCMD_SET_PRE_SCAN 0x0107
133 #define MALO_HOSTCMD_SET_POST_SCAN 0x0108
134 #define MALO_HOSTCMD_SET_RF_CHANNEL 0x010a
135 #define MALO_HOSTCMD_SET_AID 0x010d
136 #define MALO_HOSTCMD_SET_RATE 0x0110
137 #define MALO_HOSTCMD_SET_SLOT 0x0114
138 /* define DFS lab commands */
139 #define MALO_HOSTCMD_SET_FIXED_RATE 0x0126
140 #define MALO_HOSTCMD_SET_REGION_POWER 0x0128
141 #define MALO_HOSTCMD_GET_CALTABLE 0x1134
144 * definition of action or option for each command.
146 /* define general purpose action */
147 #define MALO_HOSTCMD_ACT_GEN_GET 0x0000
148 #define MALO_HOSTCMD_ACT_GEN_SET 0x0001
149 #define MALO_HOSTCMD_ACT_GEN_SET_LIST 0x0002
151 /* define action or option for HostCmd_FW_USE_FIXED_RATE */
152 #define MALO_HOSTCMD_ACT_USE_FIXED_RATE 0x0001
153 #define MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002
155 /* INT code register event definition */
156 #define MALO_INT_CODE_CMD_FINISHED 0x00000005
158 struct malo_cmd_header {
165 struct malo_cmd_caltable {
166 struct malo_cmd_header cmdhdr;
171 #define MALO_CAL_TBL_SIZE 160
172 uint8_t caltbl[MALO_CAL_TBL_SIZE];
175 struct malo_cmd_get_hwspec {
176 struct malo_cmd_header cmdhdr;
177 u_int8_t version; /* version of the HW */
178 u_int8_t hostif; /* host interface */
179 /* Max. number of WCB FW can handle */
181 /* MaxNbr of MC addresses FW can handle */
182 u_int16_t num_mcastaddr;
183 /* MAC address programmed in HW */
184 u_int8_t permaddr[6];
185 u_int16_t regioncode;
186 /* Number of antenna used */
187 u_int16_t num_antenna;
188 /* 4 byte of FW release number */
189 u_int32_t fw_releasenum;
191 u_int32_t rxpdwr_ptr;
192 u_int32_t rxpdrd_ptr;
193 u_int32_t ul_fw_awakecookie;
199 struct malo_cmd_set_hwspec {
200 struct malo_cmd_header cmdhdr;
201 uint8_t version; /* HW revision */
202 uint8_t hostif; /* Host interface */
203 /* Max. number of Multicast address FW can handle */
204 uint16_t num_mcastaddr;
205 uint8_t permaddr[6]; /* MAC address */
206 uint16_t regioncode; /* Region Code */
207 /* 4 byte of FW release number */
208 uint32_t fwreleasenum;
209 /* Firmware awake cookie */
210 uint32_t ul_fw_awakecookie;
211 /* Device capabilities (see above) */
213 uint32_t rxpdwrptr; /* Rx shared memory queue */
214 /* # TX queues in WcbBase array */
215 uint32_t num_txqueues;
217 uint32_t wcbbase[MALO_MAX_TXWCB_QUEUES];
219 uint32_t txwcbnum_per_queue;
220 uint32_t total_rxwcb;
224 struct malo_cmd_rf_antenna {
225 struct malo_cmd_header cmdhdr;
227 /* Number of antennas or 0xffff (diversity) */
231 struct malo_cmd_radio_control {
232 struct malo_cmd_header cmdhdr;
235 * bit 0 : 1 = on, 0 = off
236 * bit 1 : 1 = long, 0 = short
237 * bit 2 : 1 = auto, 0 = fix
243 struct malo_cmd_fw_set_wmmmode {
244 struct malo_cmd_header cmdhdr;
245 uint16_t action; /* 0 -> unset, 1 -> set */
248 struct malo_cmd_fw_set_rf_channel {
249 struct malo_cmd_header cmdhdr;
251 uint8_t cur_channel; /* channel # */
254 #define MALO_TX_POWER_LEVEL_TOTAL 8
255 struct malo_cmd_rf_tx_power {
256 struct malo_cmd_header cmdhdr;
258 uint16_t support_txpower_level;
259 uint16_t current_txpower_level;
261 uint16_t power_levellist[MALO_TX_POWER_LEVEL_TOTAL];
264 struct malo_fixrate_flag {
265 /* lower rate after the retry count. 0 = legacy, 1 = HT */
267 /* 0: retry count is not valid, 1: use retry count specified */
268 uint32_t retrycount_valid;
271 struct malo_fixed_rate_entry {
272 struct malo_fixrate_flag typeflags;
273 /* legacy rate(not index) or an MCS code. */
278 struct malo_cmd_fw_use_fixed_rate {
279 struct malo_cmd_header cmdhdr;
281 * MALO_HOSTCMD_ACT_GEN_GET 0x0000
282 * MALO_HOSTCMD_ACT_GEN_SET 0x0001
283 * MALO_HOSTCMD_ACT_NOT_USE_FIXED_RATE 0x0002
286 /* use fixed rate specified but firmware can drop to */
287 uint32_t allowratedrop;
289 struct malo_fixed_rate_entry fixedrate_table[4];
290 uint8_t multicast_rate;
291 uint8_t multirate_txtype;
292 uint8_t management_rate;
295 #define MALO_RATE_INDEX_MAX_ARRAY 14
297 struct malo_cmd_fw_set_aid {
298 struct malo_cmd_header cmdhdr;
300 uint8_t macaddr[6]; /* AP's Mac Address(BSSID) */
301 uint32_t gprotection;
302 uint8_t aprates[MALO_RATE_INDEX_MAX_ARRAY];
305 struct malo_cmd_prescan {
306 struct malo_cmd_header cmdhdr;
309 struct malo_cmd_postscan {
310 struct malo_cmd_header cmdhdr;
315 struct malo_cmd_fw_setslot {
316 struct malo_cmd_header cmdhdr;
318 /* slot = 0 if regular, slot = 1 if short. */
322 struct malo_cmd_set_rate {
323 struct malo_cmd_header cmdhdr;
324 uint8_t dataratetype;
329 struct malo_cmd_wepkey {
330 struct malo_cmd_header cmdhdr;
335 uint8_t value[IEEE80211_KEYBUF_SIZE];
336 uint8_t txmickey[IEEE80211_WEP_MICLEN];
337 uint8_t rxmickey[IEEE80211_WEP_MICLEN];
342 struct malo_cmd_mcast {
343 struct malo_cmd_header cmdhdr;
346 #define MALO_HAL_MCAST_MAX 32
347 uint8_t maclist[6*32];
351 * DMA state for tx/rx descriptors.
355 * Common "base class" for tx/rx descriptor resources
356 * allocated using the bus dma api.
358 struct malo_descdma {
360 void *dd_desc; /* descriptors */
361 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
362 bus_size_t dd_desc_len; /* size of dd_desc */
363 bus_dma_segment_t dd_dseg;
364 int dd_dnseg; /* number of segments */
365 bus_dma_tag_t dd_dmat; /* bus DMA tag */
366 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
367 void *dd_bufptr; /* associated buffers */
371 * Hardware tx/rx descriptors.
373 * NB: tx descriptor size must match f/w expected size
374 * because f/w prefetch's the next descriptor linearly
375 * and doesn't chase the next pointer.
379 #define MALO_TXD_STATUS_IDLE 0x00000000
380 #define MALO_TXD_STATUS_USED 0x00000001
381 #define MALO_TXD_STATUS_OK 0x00000001
382 #define MALO_TXD_STATUS_OK_RETRY 0x00000002
383 #define MALO_TXD_STATUS_OK_MORE_RETRY 0x00000004
384 #define MALO_TXD_STATUS_MULTICAST_TX 0x00000008
385 #define MALO_TXD_STATUS_BROADCAST_TX 0x00000010
386 #define MALO_TXD_STATUS_FAILED_LINK_ERROR 0x00000020
387 #define MALO_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040
388 #define MALO_TXD_STATUS_FAILED_XRETRY MALO_TXD_STATUS_FAILED_EXCEED_LIMIT
389 #define MALO_TXD_STATUS_FAILED_AGING 0x00000080
390 #define MALO_TXD_STATUS_FW_OWNED 0x80000000
398 uint32_t sap_pktinfo;
400 #define MALO_TXD_FORMAT 0x0001 /* frame format/rate */
401 #define MALO_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */
402 #define MALO_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */
403 #define MALO_TXD_RATE_S 3
404 /* NB: 3 is reserved */
405 #define MALO_TXD_ANTENNA 0x1800 /* antenna select */
406 #define MALO_TXD_ANTENNA_S 11
407 uint16_t pad; /* align to 4-byte boundary */
410 #define MALO_TXDESC_SYNC(txq, ds, how) do { \
411 bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \
415 uint8_t rxcontrol; /* control element */
416 #define MALO_RXD_CTRL_DRIVER_OWN 0x00
417 #define MALO_RXD_CTRL_OS_OWN 0x04
418 #define MALO_RXD_CTRL_DMA_OWN 0x80
419 uint8_t snr; /* signal to noise ratio */
420 uint8_t status; /* status field w/ USED bit */
421 #define MALO_RXD_STATUS_IDLE 0x00
422 #define MALO_RXD_STATUS_OK 0x01
423 #define MALO_RXD_STATUS_MULTICAST_RX 0x02
424 #define MALO_RXD_STATUS_BROADCAST_RX 0x04
425 #define MALO_RXD_STATUS_FRAGMENT_RX 0x08
426 #define MALO_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff
427 #define MALO_RXD_STATUS_DECRYPT_ERR_MASK 0x80
428 #define MALO_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02
429 #define MALO_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04
430 #define MALO_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08
431 uint8_t channel; /* channel # pkt received on */
432 uint16_t pktlen; /* total length of received data */
433 uint8_t nf; /* noise floor */
434 uint8_t rate; /* received data rate */
435 uint32_t physbuffdata; /* physical address of payload data */
436 uint32_t physnext; /* physical address of next RX desc */
437 uint16_t qosctrl; /* received QosCtrl field variable */
438 uint16_t htsig2; /* like name states */
441 #define MALO_RXDESC_SYNC(sc, ds, how) do { \
442 bus_dmamap_sync((sc)->malo_rxdma.dd_dmat, \
443 (sc)->malo_rxdma.dd_dmamap, how); \
447 STAILQ_ENTRY(malo_rxbuf) bf_list;
448 void *bf_desc; /* h/w descriptor */
449 bus_addr_t bf_daddr; /* physical addr of desc */
450 bus_dmamap_t bf_dmamap;
451 bus_addr_t bf_data; /* physical addr of rx data */
452 struct mbuf *bf_m; /* jumbo mbuf */
454 typedef STAILQ_HEAD(, malo_rxbuf) malo_rxbufhead;
457 * Software backed version of tx/rx descriptors. We keep
458 * the software state out of the h/w descriptor structure
459 * so that may be allocated in uncached memory w/o paying
463 STAILQ_ENTRY(malo_txbuf) bf_list;
464 void *bf_desc; /* h/w descriptor */
465 bus_addr_t bf_daddr; /* physical addr of desc */
466 bus_dmamap_t bf_dmamap; /* DMA map for descriptors */
468 bus_dma_segment_t bf_segs[MALO_TXDESC];
470 struct ieee80211_node *bf_node;
471 struct malo_txq *bf_txq; /* backpointer to tx q/ring */
473 typedef STAILQ_HEAD(, malo_txbuf) malo_txbufhead;
476 * TX/RX ring definitions. There are 4 tx rings, one
477 * per AC, and 1 rx ring. Note carefully that transmit
478 * descriptors are treated as a contiguous chunk and the
479 * firmware pre-fetches descriptors. This means that we
480 * must preserve order when moving descriptors between
481 * the active+free lists; otherwise we may stall transmit.
484 struct malo_descdma dma; /* bus dma resources */
485 struct mtx lock; /* tx q lock */
486 char name[12]; /* e.g. "malo0_txq4" */
487 int qnum; /* f/w q number */
488 int txpri; /* f/w tx priority */
489 int nfree; /* # buffers on free list */
490 malo_txbufhead free; /* queue of free buffers */
491 malo_txbufhead active; /* queue of active buffers */
494 #define MALO_TXQ_LOCK_INIT(_sc, _tq) do { \
495 snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \
496 device_get_nameunit((_sc)->malo_dev), (_tq)->qnum); \
497 mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \
499 #define MALO_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->lock)
500 #define MALO_TXQ_LOCK(_tq) mtx_lock(&(_tq)->lock)
501 #define MALO_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->lock)
502 #define MALO_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED)
505 * Each packet has fixed front matter: a 2-byte length
506 * of the payload, followed by a 4-address 802.11 header
507 * (regardless of the actual header and always w/o any
508 * QoS header). The payload then follows.
512 struct ieee80211_frame_addr4 wh;
516 struct ieee80211vap malo_vap;
517 int (*malo_newstate)(struct ieee80211vap *,
518 enum ieee80211_state, int);
520 #define MALO_VAP(vap) ((struct malo_vap *)(vap))
524 struct ifnet *malo_ifp; /* interface common */
525 struct mtx malo_mtx; /* master lock (recursive) */
526 struct taskqueue *malo_tq; /* private task queue */
528 bus_dma_tag_t malo_dmat; /* bus DMA tag */
529 bus_space_handle_t malo_io0h; /* BAR 0 */
530 bus_space_tag_t malo_io0t;
531 bus_space_handle_t malo_io1h; /* BAR 1 */
532 bus_space_tag_t malo_io1t;
534 unsigned int malo_invalid : 1,/* disable hardware accesses */
535 malo_recvsetup : 1, /* recv setup */
536 malo_fixedrate: 1; /* use fixed tx rate */
538 struct malo_hal *malo_mh; /* h/w access layer */
539 struct malo_hal_hwspec malo_hwspecs; /* h/w capabilities */
540 struct malo_hal_txrxdma malo_hwdma; /* h/w dma setup */
541 uint32_t malo_imask; /* interrupt mask copy */
542 struct malo_hal_channel malo_curchan;
543 u_int16_t malo_rxantenna; /* rx antenna */
544 u_int16_t malo_txantenna; /* tx antenna */
546 struct malo_descdma malo_rxdma; /* rx bus dma resources */
547 malo_rxbufhead malo_rxbuf; /* rx buffers */
548 struct malo_rxbuf *malo_rxnext; /* next rx buffer to process */
549 struct task malo_rxtask; /* rx int processing */
551 struct malo_txq malo_txq[MALO_NUM_TX_QUEUES];
552 struct task malo_txtask; /* tx int processing */
553 struct callout malo_watchdog_timer;
556 struct malo_tx_radiotap_header malo_tx_th;
557 struct malo_rx_radiotap_header malo_rx_th;
559 struct malo_stats malo_stats; /* interface statistics */
563 #define MALO_LOCK_INIT(_sc) \
564 mtx_init(&(_sc)->malo_mtx, device_get_nameunit((_sc)->malo_dev), \
565 NULL, MTX_DEF | MTX_RECURSE)
566 #define MALO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->malo_mtx)
567 #define MALO_LOCK(_sc) mtx_lock(&(_sc)->malo_mtx)
568 #define MALO_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_mtx)
569 #define MALO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->malo_mtx, MA_OWNED)
571 #define MALO_RXFREE_INIT(_sc) \
572 mtx_init(&(_sc)->malo_rxlock, device_get_nameunit((_sc)->malo_dev), \
574 #define MALO_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->malo_rxlock)
575 #define MALO_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->malo_rxlock)
576 #define MALO_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_rxlock)
577 #define MALO_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->malo_rxlock, \
580 int malo_attach(uint16_t, struct malo_softc *);
581 int malo_intr(void *);
582 int malo_detach(struct malo_softc *);
583 void malo_shutdown(struct malo_softc *);
584 void malo_suspend(struct malo_softc *);
585 void malo_resume(struct malo_softc *);