sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int mii_oui;
  72         int mii_model;
  73         int mii_rev;
  74         int serdes_flags;       /* Keeps track of the serdes type used */
  75 #define BRGPHY_5706S    0x0001
  76 #define BRGPHY_5708S    0x0002
  77         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  78 };
  79
  80 static device_method_t brgphy_methods[] = {
  81         /* device interface */
  82         DEVMETHOD(device_probe,         brgphy_probe),
  83         DEVMETHOD(device_attach,        brgphy_attach),
  84         DEVMETHOD(device_detach,        mii_phy_detach),
  85         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  86         { 0, 0 }
  87 };
  88
  89 static devclass_t brgphy_devclass;
  90
  91 static driver_t brgphy_driver = {
  92         "brgphy",
  93         brgphy_methods,
  94         sizeof(struct brgphy_softc)
  95 };
  96
  97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
  98
  99 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 100 static void     brgphy_setmedia(struct mii_softc *, int, int);
 101 static void     brgphy_status(struct mii_softc *);
 102 static void     brgphy_mii_phy_auto(struct mii_softc *);
 103 static void     brgphy_reset(struct mii_softc *);
 104 static void     brgphy_enable_loopback(struct mii_softc *);
 105 static void     bcm5401_load_dspcode(struct mii_softc *);
 106 static void     bcm5411_load_dspcode(struct mii_softc *);
 107 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 108 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 109 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 110 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 111 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 113 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 114 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 115
 116 static const struct mii_phydesc brgphys[] = {
 117         MII_PHY_DESC(xxBROADCOM, BCM5400),
 118         MII_PHY_DESC(xxBROADCOM, BCM5401),
 119         MII_PHY_DESC(xxBROADCOM, BCM5411),
 120         MII_PHY_DESC(xxBROADCOM, BCM5701),
 121         MII_PHY_DESC(xxBROADCOM, BCM5703),
 122         MII_PHY_DESC(xxBROADCOM, BCM5704),
 123         MII_PHY_DESC(xxBROADCOM, BCM5705),
 124         MII_PHY_DESC(xxBROADCOM, BCM5706),
 125         MII_PHY_DESC(xxBROADCOM, BCM5714),
 126         MII_PHY_DESC(xxBROADCOM, BCM5750),
 127         MII_PHY_DESC(xxBROADCOM, BCM5752),
 128         MII_PHY_DESC(xxBROADCOM, BCM5754),
 129         MII_PHY_DESC(xxBROADCOM, BCM5780),
 130         MII_PHY_DESC(xxBROADCOM, BCM5708C),
 131         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
 132         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
 133         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
 134         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
 135         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
 136         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
 137         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
 138         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
 139         MII_PHY_DESC(BROADCOM2, BCM5906),
 140         MII_PHY_END
 141 };
 142
 143
 144 /* Search for our PHY in the list of known PHYs */
 145 static int
 146 brgphy_probe(device_t dev)
 147 {
 148         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 149 }
 150
 151 /* Attach the PHY to the MII bus */
 152 static int
 153 brgphy_attach(device_t dev)
 154 {
 155         struct brgphy_softc *bsc;
 156         struct bge_softc *bge_sc = NULL;
 157         struct bce_softc *bce_sc = NULL;
 158         struct mii_softc *sc;
 159         struct mii_attach_args *ma;
 160         struct mii_data *mii;
 161         struct ifnet *ifp;
 162         int fast_ether;
 163
 164         bsc = device_get_softc(dev);
 165         sc = &bsc->mii_sc;
 166         ma = device_get_ivars(dev);
 167         sc->mii_dev = device_get_parent(dev);
 168         mii = device_get_softc(sc->mii_dev);
 169         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 170
 171         /* Initialize mii_softc structure */
 172         sc->mii_inst = mii->mii_instance;
 173         sc->mii_phy = ma->mii_phyno;
 174         sc->mii_service = brgphy_service;
 175         sc->mii_pdata = mii;
 176         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 177         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
 178         mii->mii_instance++;
 179
 180         /* Initialize brgphy_softc structure */
 181         bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
 182         bsc->mii_model = MII_MODEL(ma->mii_id2);
 183         bsc->mii_rev = MII_REV(ma->mii_id2);
 184         bsc->serdes_flags = 0;
 185
 186         fast_ether = 0;
 187
 188         if (bootverbose)
 189                 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
 190                     bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
 191
 192         /* Handle any special cases based on the PHY ID */
 193         switch (bsc->mii_oui) {
 194         case MII_OUI_BROADCOM:
 195         case MII_OUI_BROADCOM2:
 196                 break;
 197         case MII_OUI_xxBROADCOM:
 198                 switch (bsc->mii_model) {
 199                         case MII_MODEL_xxBROADCOM_BCM5706:
 200                         case MII_MODEL_xxBROADCOM_BCM5714:
 201                                 /*
 202                                  * The 5464 PHY used in the 5706 supports both copper
 203                                  * and fiber interfaces over GMII.  Need to check the
 204                                  * shadow registers to see which mode is actually
 205                                  * in effect, and therefore whether we have 5706C or
 206                                  * 5706S.
 207                                  */
 208                                 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 209                                         BRGPHY_SHADOW_1C_MODE_CTRL);
 210                                 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 211                                         BRGPHY_SHADOW_1C_ENA_1000X) {
 212                                         bsc->serdes_flags |= BRGPHY_5706S;
 213                                         sc->mii_flags |= MIIF_HAVEFIBER;
 214                                 }
 215                                 break;
 216                 } break;
 217         case MII_OUI_xxBROADCOM_ALT1:
 218                 switch (bsc->mii_model) {
 219                         case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
 220                                 bsc->serdes_flags |= BRGPHY_5708S;
 221                                 sc->mii_flags |= MIIF_HAVEFIBER;
 222                                 break;
 223                 } break;
 224         default:
 225                 device_printf(dev, "Unrecognized OUI for PHY!\n");
 226         }
 227
 228         ifp = sc->mii_pdata->mii_ifp;
 229
 230         /* Find the MAC driver associated with this PHY. */
 231         if (strcmp(ifp->if_dname, "bge") == 0)  {
 232                 bge_sc = ifp->if_softc;
 233         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 234                 bce_sc = ifp->if_softc;
 235         }
 236
 237         /* Todo: Need to add additional controllers such as 5906 & 5787F */
 238         /* The 590x chips are 10/100 only. */
 239         if (bge_sc &&
 240             pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
 241             (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
 242             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
 243             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
 244             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
 245                 fast_ether = 1;
 246                 sc->mii_anegticks = MII_ANEGTICKS;
 247         }
 248
 249         brgphy_reset(sc);
 250
 251         /* Read the PHY's capabilities. */
 252         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 253         if (sc->mii_capabilities & BMSR_EXTSTAT)
 254                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 255         device_printf(dev, " ");
 256
 257 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 258
 259         /* Create an instance of Ethernet media. */
 260         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO);
 261
 262         /* Add the supported media types */
 263         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 264                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
 265                         BRGPHY_S10);
 266                 printf("10baseT, ");
 267                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
 268                         BRGPHY_S10 | BRGPHY_BMCR_FDX);
 269                 printf("10baseT-FDX, ");
 270                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
 271                         BRGPHY_S100);
 272                 printf("100baseTX, ");
 273                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
 274                         BRGPHY_S100 | BRGPHY_BMCR_FDX);
 275                 printf("100baseTX-FDX, ");
 276                 if (fast_ether == 0) {
 277                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
 278                                 BRGPHY_S1000);
 279                         printf("1000baseT, ");
 280                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
 281                                 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 282                         printf("1000baseT-FDX, ");
 283                 }
 284         } else {
 285                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 286                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 287                 printf("1000baseSX-FDX, ");
 288                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 289                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 290                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 291                         printf("2500baseSX-FDX, ");
 292                 }
 293         }
 294
 295         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 296         printf("auto\n");
 297
 298 #undef ADD
 299         MIIBUS_MEDIAINIT(sc->mii_dev);
 300         return (0);
 301 }
 302
 303 static int
 304 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 305 {
 306         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 307         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 308         int error = 0;
 309         int val;
 310
 311         switch (cmd) {
 312         case MII_POLLSTAT:
 313                 /* If we're not polling our PHY instance, just return. */
 314                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 315                         goto brgphy_service_exit;
 316                 break;
 317         case MII_MEDIACHG:
 318                 /*
 319                  * If the media indicates a different PHY instance,
 320                  * isolate ourselves.
 321                  */
 322                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 323                         PHY_WRITE(sc, MII_BMCR,
 324                             PHY_READ(sc, MII_BMCR) | BMCR_ISO);
 325                         goto brgphy_service_exit;
 326                 }
 327
 328                 /* If the interface is not up, don't do anything. */
 329                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 330                         break;
 331
 332                 /* Todo: Why is this here?  Is it really needed? */
 333                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 334
 335                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 336                 case IFM_AUTO:
 337                         brgphy_mii_phy_auto(sc);
 338                         break;
 339                 case IFM_2500_SX:
 340                 case IFM_1000_SX:
 341                 case IFM_1000_T:
 342                 case IFM_100_TX:
 343                 case IFM_10_T:
 344                         brgphy_setmedia(sc, ife->ifm_media,
 345                             mii->mii_ifp->if_flags & IFF_LINK0);
 346                         break;
 347                 default:
 348                         error = EINVAL;
 349                         goto brgphy_service_exit;
 350                 }
 351                 break;
 352         case MII_TICK:
 353                 /* Bail if we're not currently selected. */
 354                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 355                         goto brgphy_service_exit;
 356
 357                 /* Bail if the interface isn't up. */
 358                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 359                         goto brgphy_service_exit;
 360
 361
 362                 /* Bail if autoneg isn't in process. */
 363                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 364                         sc->mii_ticks = 0;
 365                         break;
 366                 }
 367
 368                 /*
 369                  * Check to see if we have link.  If we do, we don't
 370                  * need to restart the autonegotiation process.
 371                  */
 372                 val     = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 373                 if (val & BMSR_LINK) {
 374                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 375                         break;
 376                 }
 377
 378                 /* Announce link loss right after it happens. */
 379                 if (sc->mii_ticks++ == 0)
 380                         break;
 381
 382                 /* Only retry autonegotiation every mii_anegticks seconds. */
 383                 if (sc->mii_ticks <= sc->mii_anegticks)
 384                         break;
 385
 386
 387                 /* Retry autonegotiation */
 388                 sc->mii_ticks = 0;
 389                 brgphy_mii_phy_auto(sc);
 390                 break;
 391         }
 392
 393         /* Update the media status. */
 394         brgphy_status(sc);
 395
 396         /*
 397          * Callback if something changed. Note that we need to poke
 398          * the DSP on the Broadcom PHYs if the media changes.
 399          */
 400         if (sc->mii_media_active != mii->mii_media_active ||
 401             sc->mii_media_status != mii->mii_media_status ||
 402             cmd == MII_MEDIACHG) {
 403                 switch (bsc->mii_oui) {
 404                 case MII_OUI_BROADCOM:
 405                         break;
 406                 case MII_OUI_xxBROADCOM:
 407                         switch (bsc->mii_model) {
 408                         case MII_MODEL_xxBROADCOM_BCM5400:
 409                                 bcm5401_load_dspcode(sc);
 410                                 break;
 411                         case MII_MODEL_xxBROADCOM_BCM5401:
 412                                 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 413                                         bcm5401_load_dspcode(sc);
 414                                 break;
 415                         case MII_MODEL_xxBROADCOM_BCM5411:
 416                                 bcm5411_load_dspcode(sc);
 417                                 break;
 418                         }
 419                         break;
 420                 case MII_OUI_xxBROADCOM_ALT1:
 421                         break;
 422                 }
 423         }
 424         mii_phy_update(sc, cmd);
 425 brgphy_service_exit:
 426         return (error);
 427 }
 428
 429
 430 /****************************************************************************/
 431 /* Sets the PHY link speed.                                                 */
 432 /*                                                                          */
 433 /* Returns:                                                                 */
 434 /*   None                                                                   */
 435 /****************************************************************************/
 436 static void
 437 brgphy_setmedia(struct mii_softc *sc, int media, int master)
 438 {
 439         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 440         int bmcr = 0, gig;
 441
 442         /* Calculate the value for the BMCR register. */
 443         switch (IFM_SUBTYPE(media)) {
 444         case IFM_2500_SX:
 445                 break;
 446         case IFM_1000_SX:
 447         case IFM_1000_T:
 448                 bmcr = BRGPHY_S1000;
 449                 break;
 450         case IFM_100_TX:
 451                 bmcr = BRGPHY_S100;
 452                 break;
 453         case IFM_10_T:
 454         default:
 455                 bmcr = BRGPHY_S10;
 456                 break;
 457         }
 458
 459         /* Calculate duplex settings for 1000BasetT/1000BaseX. */
 460         if ((media & IFM_GMASK) == IFM_FDX) {
 461                 bmcr |= BRGPHY_BMCR_FDX;
 462                 gig = BRGPHY_1000CTL_AFD;
 463         } else {
 464                 gig = BRGPHY_1000CTL_AHD;
 465         }
 466
 467         /* Force loopback to disconnect PHY for Ethernet medium. */
 468         brgphy_enable_loopback(sc);
 469
 470         /* Disable 1000BaseT advertisements. */
 471         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 472         /* Disable 10/100 advertisements. */
 473         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 474         /* Write forced link speed. */
 475         PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 476
 477         /* If 10/100 only then configuration is complete. */
 478         if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
 479                 goto brgphy_setmedia_exit;
 480
 481         /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */
 482         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 483         /* Restart auto-negotiation for 1000BaseT/1000BaseX. */
 484         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 485             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 486
 487         /* If not 5701 PHY then configuration is complete. */
 488         if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 489                 goto brgphy_setmedia_exit;
 490
 491         /*
 492          * When setting the link manually, one side must be the master and
 493          * the other the slave. However ifmedia doesn't give us a good way
 494          * to specify this, so we fake it by using one of the LINK flags.
 495          * If LINK0 is set, we program the PHY to be a master, otherwise
 496          * it's a slave.
 497          */
 498         if (master) {
 499                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 500                     gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
 501         } else {
 502                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 503                     gig | BRGPHY_1000CTL_MSE);
 504         }
 505
 506 brgphy_setmedia_exit:
 507         return;
 508 }
 509
 510 /****************************************************************************/
 511 /* Set the media status based on the PHY settings.                          */
 512 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled)                   */
 513 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled)                   */
 514 /*                                                                          */
 515 /* Returns:                                                                 */
 516 /*   None                                                                   */
 517 /****************************************************************************/
 518 static void
 519 brgphy_status(struct mii_softc *sc)
 520 {
 521         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 522         struct mii_data *mii = sc->mii_pdata;
 523         int aux, bmcr, bmsr, anar, anlpar, xstat, val;
 524
 525
 526         mii->mii_media_status = IFM_AVALID;
 527         mii->mii_media_active = IFM_ETHER;
 528
 529         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 530         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 531         anar = PHY_READ(sc, BRGPHY_MII_ANAR);
 532         anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
 533
 534         /* Loopback is enabled. */
 535         if (bmcr & BRGPHY_BMCR_LOOP) {
 536
 537                 mii->mii_media_active |= IFM_LOOP;
 538         }
 539
 540         /* Autoneg is still in progress. */
 541         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 542             (bmsr & BRGPHY_BMSR_ACOMP) == 0) {
 543                 /* Erg, still trying, I guess... */
 544                 mii->mii_media_active |= IFM_NONE;
 545                 goto brgphy_status_exit;
 546         }
 547
 548         /* Autoneg is enabled and complete, link should be up. */
 549         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 550                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 551
 552                 /* If copper link is up, get the negotiated speed/duplex. */
 553                 if (aux & BRGPHY_AUXSTS_LINK) {
 554                         mii->mii_media_status |= IFM_ACTIVE;
 555                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 556                         case BRGPHY_RES_1000FD:
 557                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 558                         case BRGPHY_RES_1000HD:
 559                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 560                         case BRGPHY_RES_100FD:
 561                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 562                         case BRGPHY_RES_100T4:
 563                                 mii->mii_media_active |= IFM_100_T4; break;
 564                         case BRGPHY_RES_100HD:
 565                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 566                         case BRGPHY_RES_10FD:
 567                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 568                         case BRGPHY_RES_10HD:
 569                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 570                         default:
 571                                 mii->mii_media_active |= IFM_NONE; break;
 572                         }
 573                 }
 574         } else {
 575                 /* If serdes link is up, get the negotiated speed/duplex. */
 576                 if (bmsr & BRGPHY_BMSR_LINK) {
 577                         mii->mii_media_status |= IFM_ACTIVE;
 578                 }
 579
 580                 /* Check the link speed/duplex based on the PHY type. */
 581                 if (bsc->serdes_flags & BRGPHY_5706S) {
 582                         mii->mii_media_active |= IFM_1000_SX;
 583
 584                         /* If autoneg enabled, read negotiated duplex settings */
 585                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 586                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 587                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 588                                         mii->mii_media_active |= IFM_FDX;
 589                                 else
 590                                         mii->mii_media_active |= IFM_HDX;
 591                         }
 592
 593                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 594                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 595                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 596
 597                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 598                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 599                                 mii->mii_media_active |= IFM_10_FL; break;
 600                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 601                                 mii->mii_media_active |= IFM_100_FX; break;
 602                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 603                                 mii->mii_media_active |= IFM_1000_SX; break;
 604                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 605                                 mii->mii_media_active |= IFM_2500_SX; break;
 606                         }
 607
 608                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 609                                 mii->mii_media_active |= IFM_FDX;
 610                         else
 611                                 mii->mii_media_active |= IFM_HDX;
 612                 }
 613         }
 614
 615 #if 0
 616         /* Todo: Change bge/bce to use these settings. */
 617
 618         /* Fetch flow control settings from the PHY */
 619         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 620                 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */
 621                 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
 622                         mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
 623                 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
 624                     (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 625                         mii->mii_media_active |= IFM_FLAG1;
 626                 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
 627                     !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 628                         mii->mii_media_active |= IFM_FLAG0;
 629                 }
 630         }
 631
 632         /* Todo: Add support for fiber settings too. */
 633 #endif
 634
 635
 636 brgphy_status_exit:
 637         return;
 638 }
 639
 640 static void
 641 brgphy_mii_phy_auto(struct mii_softc *sc)
 642 {
 643         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 644         int ktcr = 0;
 645
 646         brgphy_reset(sc);
 647
 648         /* Enable flow control in the advertisement register. */
 649         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 650                 /* Pause capability advertisement (pause capable & asymmetric) */
 651                 PHY_WRITE(sc, BRGPHY_MII_ANAR,
 652                 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
 653                 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
 654         } else {
 655                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 656                         BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
 657         }
 658
 659         /* Enable speed in the 1000baseT control register */
 660         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 661         if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 662                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 663         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 664         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 665
 666         /* Start autonegotiation */
 667         PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 668         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 669
 670 }
 671
 672
 673 /* Enable loopback to force the link down. */
 674 static void
 675 brgphy_enable_loopback(struct mii_softc *sc)
 676 {
 677         int i;
 678
 679         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 680         for (i = 0; i < 15000; i++) {
 681                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 682                         break;
 683                 DELAY(10);
 684         }
 685 }
 686
 687 /* Turn off tap power management on 5401. */
 688 static void
 689 bcm5401_load_dspcode(struct mii_softc *sc)
 690 {
 691         static const struct {
 692                 int             reg;
 693                 uint16_t        val;
 694         } dspcode[] = {
 695                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 696                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 697                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 698                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 699                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 700                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 701                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 702                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 703                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 704                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 705                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 706                 { 0,                            0 },
 707         };
 708         int i;
 709
 710         for (i = 0; dspcode[i].reg != 0; i++)
 711                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 712         DELAY(40);
 713 }
 714
 715 static void
 716 bcm5411_load_dspcode(struct mii_softc *sc)
 717 {
 718         static const struct {
 719                 int             reg;
 720                 uint16_t        val;
 721         } dspcode[] = {
 722                 { 0x1c,                         0x8c23 },
 723                 { 0x1c,                         0x8ca3 },
 724                 { 0x1c,                         0x8c23 },
 725                 { 0,                            0 },
 726         };
 727         int i;
 728
 729         for (i = 0; dspcode[i].reg != 0; i++)
 730                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 731 }
 732
 733 static void
 734 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 735 {
 736         static const struct {
 737                 int             reg;
 738                 uint16_t        val;
 739         } dspcode[] = {
 740                 { 0x1c,                         0x8d68 },
 741                 { 0x1c,                         0x8d68 },
 742                 { 0,                            0 },
 743         };
 744         int i;
 745
 746         for (i = 0; dspcode[i].reg != 0; i++)
 747                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 748 }
 749
 750 static void
 751 brgphy_fixup_adc_bug(struct mii_softc *sc)
 752 {
 753         static const struct {
 754                 int             reg;
 755                 uint16_t        val;
 756         } dspcode[] = {
 757                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 758                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 759                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 760                 { 0,                            0 },
 761         };
 762         int i;
 763
 764         for (i = 0; dspcode[i].reg != 0; i++)
 765                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 766 }
 767
 768 static void
 769 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 770 {
 771         static const struct {
 772                 int             reg;
 773                 uint16_t        val;
 774         } dspcode[] = {
 775                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 776                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 777                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 778                 { BRGPHY_MII_TEST1,                     0x0014 },
 779                 { BRGPHY_MII_AUXCTL,            0x0400 },
 780                 { 0,                            0 },
 781         };
 782         int i;
 783
 784         for (i = 0; dspcode[i].reg != 0; i++)
 785                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 786 }
 787
 788 static void
 789 brgphy_fixup_ber_bug(struct mii_softc *sc)
 790 {
 791         static const struct {
 792                 int             reg;
 793                 uint16_t        val;
 794         } dspcode[] = {
 795                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 796                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 797                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 798                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 799                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 800                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 801                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 802                 { BRGPHY_MII_AUXCTL,            0x0400 },
 803                 { 0,                            0 },
 804         };
 805         int i;
 806
 807         for (i = 0; dspcode[i].reg != 0; i++)
 808                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 809 }
 810
 811 static void
 812 brgphy_fixup_crc_bug(struct mii_softc *sc)
 813 {
 814         static const struct {
 815                 int             reg;
 816                 uint16_t        val;
 817         } dspcode[] = {
 818                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 819                 { 0x1c,                         0x8c68 },
 820                 { 0x1c,                         0x8d68 },
 821                 { 0x1c,                         0x8c68 },
 822                 { 0,                            0 },
 823         };
 824         int i;
 825
 826         for (i = 0; dspcode[i].reg != 0; i++)
 827                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 828 }
 829
 830 static void
 831 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 832 {
 833         static const struct {
 834                 int             reg;
 835                 uint16_t        val;
 836         } dspcode[] = {
 837                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 838                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 839                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 840                 { BRGPHY_MII_AUXCTL,            0x0400 },
 841                 { 0,                            0 },
 842         };
 843         int i;
 844
 845         for (i = 0; dspcode[i].reg != 0; i++)
 846                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 847 }
 848
 849
 850 static void
 851 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 852 {
 853         uint32_t val;
 854
 855         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 856         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 857         val &= ~(1 << 8);
 858         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 859
 860 }
 861
 862
 863 static void
 864 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 865 {
 866         uint32_t        val;
 867
 868         /* Enable Ethernet@WireSpeed. */
 869         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 870         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 871         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 872 }
 873
 874
 875 static void
 876 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 877 {
 878         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 879         uint32_t        val;
 880
 881         /* Set or clear jumbo frame settings in the PHY. */
 882         if (mtu > ETHER_MAX_LEN) {
 883                 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 884                         /* BCM5401 PHY cannot read-modify-write. */
 885                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 886                 } else {
 887                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 888                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 889                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 890                             val | BRGPHY_AUXCTL_LONG_PKT);
 891                 }
 892
 893                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 894                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 895                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 896         } else {
 897                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 898                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 899                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 900                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 901
 902                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 903                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 904                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 905         }
 906 }
 907
 908 static void
 909 brgphy_reset(struct mii_softc *sc)
 910 {
 911         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 912         struct bge_softc *bge_sc = NULL;
 913         struct bce_softc *bce_sc = NULL;
 914         struct ifnet *ifp;
 915
 916         /* Perform a standard PHY reset. */
 917         mii_phy_reset(sc);
 918
 919         /* Handle any PHY specific procedures following the reset. */
 920         switch (bsc->mii_oui) {
 921         case MII_OUI_BROADCOM:
 922                 break;
 923         case MII_OUI_xxBROADCOM:
 924                 switch (bsc->mii_model) {
 925                 case MII_MODEL_xxBROADCOM_BCM5400:
 926                         bcm5401_load_dspcode(sc);
 927                         break;
 928                 case MII_MODEL_xxBROADCOM_BCM5401:
 929                         if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 930                                 bcm5401_load_dspcode(sc);
 931                         break;
 932                 case MII_MODEL_xxBROADCOM_BCM5411:
 933                         bcm5411_load_dspcode(sc);
 934                         break;
 935                 }
 936                 break;
 937         case MII_OUI_xxBROADCOM_ALT1:
 938                 break;
 939         }
 940
 941         ifp = sc->mii_pdata->mii_ifp;
 942
 943         /* Find the driver associated with this PHY. */
 944         if (strcmp(ifp->if_dname, "bge") == 0)  {
 945                 bge_sc = ifp->if_softc;
 946         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 947                 bce_sc = ifp->if_softc;
 948         }
 949
 950         /* Handle any bge (NetXtreme/NetLink) workarounds. */
 951         if (bge_sc) {
 952                 /* Fix up various bugs */
 953                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
 954                         brgphy_fixup_5704_a0_bug(sc);
 955                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
 956                         brgphy_fixup_adc_bug(sc);
 957                 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
 958                         brgphy_fixup_adjust_trim(sc);
 959                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
 960                         brgphy_fixup_ber_bug(sc);
 961                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
 962                         brgphy_fixup_crc_bug(sc);
 963                 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
 964                         brgphy_fixup_jitter_bug(sc);
 965
 966                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 967
 968                 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
 969                         brgphy_ethernet_wirespeed(sc);
 970
 971                 /* Enable Link LED on Dell boxes */
 972                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
 973                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 974                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 975                             ~BRGPHY_PHY_EXTCTL_3_LED);
 976                 }
 977
 978                 /* Adjust output voltage (From Linux driver) */
 979                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 980                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 981
 982         /* Handle any bce (NetXtreme II) workarounds. */
 983         } else if (bce_sc) {
 984
 985                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 986                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
 987
 988                         /* Store autoneg capabilities/results in digital block (Page 0) */
 989                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 990                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 991                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
 992                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 993
 994                         /* Enable fiber mode and autodetection */
 995                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
 996                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
 997                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
 998                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
 999
1000                         /* Enable parallel detection */
1001                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1002                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1003                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1004
1005                         /* Advertise 2.5G support through next page during autoneg */
1006                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1007                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1008                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1009                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1010
1011                         /* Increase TX signal amplitude */
1012                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1013                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1014                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1015                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1016                                         BRGPHY_5708S_TX_MISC_PG5);
1017                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1018                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1019                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1020                                         BRGPHY_5708S_DIG_PG0);
1021                         }
1022
1023                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1024                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1025                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1026                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1027                                                 BRGPHY_5708S_TX_MISC_PG5);
1028                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1029                                                 bce_sc->bce_port_hw_cfg &
1030                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1031                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1032                                                 BRGPHY_5708S_DIG_PG0);
1033                         }
1034                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1035                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1036                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1037                                 brgphy_fixup_disable_early_dac(sc);
1038
1039                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1040                         brgphy_ethernet_wirespeed(sc);
1041                 } else {
1042                         brgphy_fixup_ber_bug(sc);
1043                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1044                         brgphy_ethernet_wirespeed(sc);
1045                 }
1046
1047         }
1048 }
1049