sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int mii_oui;
  72         int mii_model;
  73         int mii_rev;
  74         int serdes_flags;       /* Keeps track of the serdes type used */
  75 #define BRGPHY_5706S            0x0001
  76 #define BRGPHY_5708S            0x0002
  77 #define BRGPHY_NOANWAIT         0x0004
  78 #define BRGPHY_5709S            0x0008
  79         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  80 };
  81
  82 static device_method_t brgphy_methods[] = {
  83         /* device interface */
  84         DEVMETHOD(device_probe,         brgphy_probe),
  85         DEVMETHOD(device_attach,        brgphy_attach),
  86         DEVMETHOD(device_detach,        mii_phy_detach),
  87         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  88         { 0, 0 }
  89 };
  90
  91 static devclass_t brgphy_devclass;
  92
  93 static driver_t brgphy_driver = {
  94         "brgphy",
  95         brgphy_methods,
  96         sizeof(struct brgphy_softc)
  97 };
  98
  99 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
 100
 101 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 102 static void     brgphy_setmedia(struct mii_softc *, int, int);
 103 static void     brgphy_status(struct mii_softc *);
 104 static void     brgphy_mii_phy_auto(struct mii_softc *);
 105 static void     brgphy_reset(struct mii_softc *);
 106 static void     brgphy_enable_loopback(struct mii_softc *);
 107 static void     bcm5401_load_dspcode(struct mii_softc *);
 108 static void     bcm5411_load_dspcode(struct mii_softc *);
 109 static void     bcm54k2_load_dspcode(struct mii_softc *);
 110 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 111 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 113 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 114 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 115 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 116 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 117 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 118
 119 static const struct mii_phydesc brgphys[] = {
 120         MII_PHY_DESC(xxBROADCOM, BCM5400),
 121         MII_PHY_DESC(xxBROADCOM, BCM5401),
 122         MII_PHY_DESC(xxBROADCOM, BCM5411),
 123         MII_PHY_DESC(xxBROADCOM, BCM54K2),
 124         MII_PHY_DESC(xxBROADCOM, BCM5701),
 125         MII_PHY_DESC(xxBROADCOM, BCM5703),
 126         MII_PHY_DESC(xxBROADCOM, BCM5704),
 127         MII_PHY_DESC(xxBROADCOM, BCM5705),
 128         MII_PHY_DESC(xxBROADCOM, BCM5706),
 129         MII_PHY_DESC(xxBROADCOM, BCM5714),
 130         MII_PHY_DESC(xxBROADCOM, BCM5750),
 131         MII_PHY_DESC(xxBROADCOM, BCM5752),
 132         MII_PHY_DESC(xxBROADCOM, BCM5754),
 133         MII_PHY_DESC(xxBROADCOM, BCM5780),
 134         MII_PHY_DESC(xxBROADCOM, BCM5708C),
 135         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
 136         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
 137         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
 138         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
 139         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
 140         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
 141         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
 142         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
 143         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
 144         MII_PHY_DESC(BROADCOM2, BCM5906),
 145         MII_PHY_END
 146 };
 147
 148 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
 149 #define HS21_BCM_CHIPID 0x57081021
 150
 151 static int
 152 detect_hs21(struct bce_softc *bce_sc)
 153 {
 154         char *sysenv;
 155
 156         if (bce_sc->bce_chipid != HS21_BCM_CHIPID)
 157                 return (0);
 158         sysenv = getenv("smbios.system.product");
 159         if (sysenv == NULL)
 160                 return (0);
 161         if (strncmp(sysenv, HS21_PRODUCT_ID, strlen(HS21_PRODUCT_ID)) != 0)
 162                 return (0);
 163         return (1);
 164 }
 165
 166 /* Search for our PHY in the list of known PHYs */
 167 static int
 168 brgphy_probe(device_t dev)
 169 {
 170         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 171 }
 172
 173 /* Attach the PHY to the MII bus */
 174 static int
 175 brgphy_attach(device_t dev)
 176 {
 177         struct brgphy_softc *bsc;
 178         struct bge_softc *bge_sc = NULL;
 179         struct bce_softc *bce_sc = NULL;
 180         struct mii_softc *sc;
 181         struct mii_attach_args *ma;
 182         struct mii_data *mii;
 183         struct ifnet *ifp;
 184         int fast_ether;
 185
 186         bsc = device_get_softc(dev);
 187         sc = &bsc->mii_sc;
 188         ma = device_get_ivars(dev);
 189         sc->mii_dev = device_get_parent(dev);
 190         mii = device_get_softc(sc->mii_dev);
 191         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 192
 193         /* Initialize mii_softc structure */
 194         sc->mii_inst = mii->mii_instance;
 195         sc->mii_phy = ma->mii_phyno;
 196         sc->mii_service = brgphy_service;
 197         sc->mii_pdata = mii;
 198         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 199         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
 200         mii->mii_instance++;
 201
 202         /* Initialize brgphy_softc structure */
 203         bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
 204         bsc->mii_model = MII_MODEL(ma->mii_id2);
 205         bsc->mii_rev = MII_REV(ma->mii_id2);
 206         bsc->serdes_flags = 0;
 207
 208         fast_ether = 0;
 209
 210         if (bootverbose)
 211                 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
 212                     bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
 213
 214         /* Handle any special cases based on the PHY ID */
 215         switch (bsc->mii_oui) {
 216         case MII_OUI_BROADCOM:
 217         case MII_OUI_BROADCOM2:
 218                 break;
 219         case MII_OUI_xxBROADCOM:
 220                 switch (bsc->mii_model) {
 221                 case MII_MODEL_xxBROADCOM_BCM5706:
 222                 case MII_MODEL_xxBROADCOM_BCM5714:
 223                         /*
 224                          * The 5464 PHY used in the 5706 supports both copper
 225                          * and fiber interfaces over GMII.  Need to check the
 226                          * shadow registers to see which mode is actually
 227                          * in effect, and therefore whether we have 5706C or
 228                          * 5706S.
 229                          */
 230                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 231                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 232                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 233                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 234                                 bsc->serdes_flags |= BRGPHY_5706S;
 235                                 sc->mii_flags |= MIIF_HAVEFIBER;
 236                         }
 237                         break;
 238                 } break;
 239         case MII_OUI_xxBROADCOM_ALT1:
 240                 switch (bsc->mii_model) {
 241                 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
 242                         bsc->serdes_flags |= BRGPHY_5708S;
 243                         sc->mii_flags |= MIIF_HAVEFIBER;
 244                         break;
 245                 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
 246                         bsc->serdes_flags |= BRGPHY_5709S;
 247                         sc->mii_flags |= MIIF_HAVEFIBER;
 248                         break;
 249                 }
 250                 break;
 251         default:
 252                 device_printf(dev, "Unrecognized OUI for PHY!\n");
 253         }
 254
 255         ifp = sc->mii_pdata->mii_ifp;
 256
 257         /* Find the MAC driver associated with this PHY. */
 258         if (strcmp(ifp->if_dname, "bge") == 0)  {
 259                 bge_sc = ifp->if_softc;
 260         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 261                 bce_sc = ifp->if_softc;
 262         }
 263
 264         /* Todo: Need to add additional controllers such as 5906 & 5787F */
 265         /* The 590x chips are 10/100 only. */
 266         if (bge_sc &&
 267             pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
 268             (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
 269             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
 270             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
 271             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
 272                 fast_ether = 1;
 273                 sc->mii_anegticks = MII_ANEGTICKS;
 274         }
 275
 276         brgphy_reset(sc);
 277
 278         /* Read the PHY's capabilities. */
 279         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 280         if (sc->mii_capabilities & BMSR_EXTSTAT)
 281                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 282         device_printf(dev, " ");
 283
 284 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 285
 286         /* Create an instance of Ethernet media. */
 287         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO);
 288
 289         /* Add the supported media types */
 290         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 291                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
 292                         BRGPHY_S10);
 293                 printf("10baseT, ");
 294                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
 295                         BRGPHY_S10 | BRGPHY_BMCR_FDX);
 296                 printf("10baseT-FDX, ");
 297                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
 298                         BRGPHY_S100);
 299                 printf("100baseTX, ");
 300                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
 301                         BRGPHY_S100 | BRGPHY_BMCR_FDX);
 302                 printf("100baseTX-FDX, ");
 303                 if (fast_ether == 0) {
 304                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
 305                                 BRGPHY_S1000);
 306                         printf("1000baseT, ");
 307                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
 308                                 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 309                         printf("1000baseT-FDX, ");
 310                 }
 311         } else {
 312                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 313                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 314                 printf("1000baseSX-FDX, ");
 315                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 316                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 317                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 318                         printf("2500baseSX-FDX, ");
 319                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 320                     (detect_hs21(bce_sc) != 0)) {
 321                         /*
 322                          * There appears to be certain silicon revision
 323                          * in IBM HS21 blades that is having issues with
 324                          * this driver wating for the auto-negotiation to
 325                          * complete. This happens with a specific chip id
 326                          * only and when the 1000baseSX-FDX is the only
 327                          * mode. Workaround this issue since it's unlikely
 328                          * to be ever addressed.
 329                          */
 330                         printf("auto-neg workaround, ");
 331                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 332                 }
 333         }
 334
 335         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 336         printf("auto\n");
 337
 338 #undef ADD
 339         MIIBUS_MEDIAINIT(sc->mii_dev);
 340         return (0);
 341 }
 342
 343 static int
 344 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 345 {
 346         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 347         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 348         int error = 0;
 349         int val;
 350
 351         switch (cmd) {
 352         case MII_POLLSTAT:
 353                 /* If we're not polling our PHY instance, just return. */
 354                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 355                         goto brgphy_service_exit;
 356                 break;
 357         case MII_MEDIACHG:
 358                 /*
 359                  * If the media indicates a different PHY instance,
 360                  * isolate ourselves.
 361                  */
 362                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 363                         PHY_WRITE(sc, MII_BMCR,
 364                             PHY_READ(sc, MII_BMCR) | BMCR_ISO);
 365                         goto brgphy_service_exit;
 366                 }
 367
 368                 /* If the interface is not up, don't do anything. */
 369                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 370                         break;
 371
 372                 /* Todo: Why is this here?  Is it really needed? */
 373                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 374
 375                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 376                 case IFM_AUTO:
 377                         brgphy_mii_phy_auto(sc);
 378                         break;
 379                 case IFM_2500_SX:
 380                 case IFM_1000_SX:
 381                 case IFM_1000_T:
 382                 case IFM_100_TX:
 383                 case IFM_10_T:
 384                         brgphy_setmedia(sc, ife->ifm_media,
 385                             mii->mii_ifp->if_flags & IFF_LINK0);
 386                         break;
 387                 default:
 388                         error = EINVAL;
 389                         goto brgphy_service_exit;
 390                 }
 391                 break;
 392         case MII_TICK:
 393                 /* Bail if we're not currently selected. */
 394                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 395                         goto brgphy_service_exit;
 396
 397                 /* Bail if the interface isn't up. */
 398                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 399                         goto brgphy_service_exit;
 400
 401
 402                 /* Bail if autoneg isn't in process. */
 403                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 404                         sc->mii_ticks = 0;
 405                         break;
 406                 }
 407
 408                 /*
 409                  * Check to see if we have link.  If we do, we don't
 410                  * need to restart the autonegotiation process.
 411                  */
 412                 val     = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 413                 if (val & BMSR_LINK) {
 414                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 415                         break;
 416                 }
 417
 418                 /* Announce link loss right after it happens. */
 419                 if (sc->mii_ticks++ == 0)
 420                         break;
 421
 422                 /* Only retry autonegotiation every mii_anegticks seconds. */
 423                 if (sc->mii_ticks <= sc->mii_anegticks)
 424                         break;
 425
 426
 427                 /* Retry autonegotiation */
 428                 sc->mii_ticks = 0;
 429                 brgphy_mii_phy_auto(sc);
 430                 break;
 431         }
 432
 433         /* Update the media status. */
 434         brgphy_status(sc);
 435
 436         /*
 437          * Callback if something changed. Note that we need to poke
 438          * the DSP on the Broadcom PHYs if the media changes.
 439          */
 440         if (sc->mii_media_active != mii->mii_media_active ||
 441             sc->mii_media_status != mii->mii_media_status ||
 442             cmd == MII_MEDIACHG) {
 443                 switch (bsc->mii_oui) {
 444                 case MII_OUI_BROADCOM:
 445                         break;
 446                 case MII_OUI_xxBROADCOM:
 447                         switch (bsc->mii_model) {
 448                         case MII_MODEL_xxBROADCOM_BCM5400:
 449                                 bcm5401_load_dspcode(sc);
 450                                 break;
 451                         case MII_MODEL_xxBROADCOM_BCM5401:
 452                                 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 453                                         bcm5401_load_dspcode(sc);
 454                                 break;
 455                         case MII_MODEL_xxBROADCOM_BCM5411:
 456                                 bcm5411_load_dspcode(sc);
 457                                 break;
 458                         case MII_MODEL_xxBROADCOM_BCM54K2:
 459                                 bcm54k2_load_dspcode(sc);
 460                                 break;
 461                         }
 462                         break;
 463                 case MII_OUI_xxBROADCOM_ALT1:
 464                         break;
 465                 }
 466         }
 467         mii_phy_update(sc, cmd);
 468 brgphy_service_exit:
 469         return (error);
 470 }
 471
 472
 473 /****************************************************************************/
 474 /* Sets the PHY link speed.                                                 */
 475 /*                                                                          */
 476 /* Returns:                                                                 */
 477 /*   None                                                                   */
 478 /****************************************************************************/
 479 static void
 480 brgphy_setmedia(struct mii_softc *sc, int media, int master)
 481 {
 482         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 483         int bmcr = 0, gig;
 484
 485         /* Calculate the value for the BMCR register. */
 486         switch (IFM_SUBTYPE(media)) {
 487         case IFM_2500_SX:
 488                 break;
 489         case IFM_1000_SX:
 490         case IFM_1000_T:
 491                 bmcr = BRGPHY_S1000;
 492                 break;
 493         case IFM_100_TX:
 494                 bmcr = BRGPHY_S100;
 495                 break;
 496         case IFM_10_T:
 497         default:
 498                 bmcr = BRGPHY_S10;
 499                 break;
 500         }
 501
 502         /* Calculate duplex settings for 1000BasetT/1000BaseX. */
 503         if ((media & IFM_GMASK) == IFM_FDX) {
 504                 bmcr |= BRGPHY_BMCR_FDX;
 505                 gig = BRGPHY_1000CTL_AFD;
 506         } else {
 507                 gig = BRGPHY_1000CTL_AHD;
 508         }
 509
 510         /* Force loopback to disconnect PHY for Ethernet medium. */
 511         brgphy_enable_loopback(sc);
 512
 513         /* Disable 1000BaseT advertisements. */
 514         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 515         /* Disable 10/100 advertisements. */
 516         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 517         /* Write forced link speed. */
 518         PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 519
 520         /* If 10/100 only then configuration is complete. */
 521         if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
 522                 goto brgphy_setmedia_exit;
 523
 524         /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */
 525         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 526         /* Restart auto-negotiation for 1000BaseT/1000BaseX. */
 527         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 528             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 529
 530         /* If not 5701 PHY then configuration is complete. */
 531         if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 532                 goto brgphy_setmedia_exit;
 533
 534         /*
 535          * When setting the link manually, one side must be the master and
 536          * the other the slave. However ifmedia doesn't give us a good way
 537          * to specify this, so we fake it by using one of the LINK flags.
 538          * If LINK0 is set, we program the PHY to be a master, otherwise
 539          * it's a slave.
 540          */
 541         if (master) {
 542                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 543                     gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
 544         } else {
 545                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 546                     gig | BRGPHY_1000CTL_MSE);
 547         }
 548
 549 brgphy_setmedia_exit:
 550         return;
 551 }
 552
 553 /****************************************************************************/
 554 /* Set the media status based on the PHY settings.                          */
 555 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled)                   */
 556 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled)                   */
 557 /*                                                                          */
 558 /* Returns:                                                                 */
 559 /*   None                                                                   */
 560 /****************************************************************************/
 561 static void
 562 brgphy_status(struct mii_softc *sc)
 563 {
 564         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 565         struct mii_data *mii = sc->mii_pdata;
 566         int aux, bmcr, bmsr, anar, anlpar, xstat, val;
 567
 568
 569         mii->mii_media_status = IFM_AVALID;
 570         mii->mii_media_active = IFM_ETHER;
 571
 572         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 573         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 574         anar = PHY_READ(sc, BRGPHY_MII_ANAR);
 575         anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
 576
 577         /* Loopback is enabled. */
 578         if (bmcr & BRGPHY_BMCR_LOOP) {
 579
 580                 mii->mii_media_active |= IFM_LOOP;
 581         }
 582
 583         /* Autoneg is still in progress. */
 584         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 585             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 586             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 587                 /* Erg, still trying, I guess... */
 588                 mii->mii_media_active |= IFM_NONE;
 589                 goto brgphy_status_exit;
 590         }
 591
 592         /* Autoneg is enabled and complete, link should be up. */
 593         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 594                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 595
 596                 /* If copper link is up, get the negotiated speed/duplex. */
 597                 if (aux & BRGPHY_AUXSTS_LINK) {
 598                         mii->mii_media_status |= IFM_ACTIVE;
 599                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 600                         case BRGPHY_RES_1000FD:
 601                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 602                         case BRGPHY_RES_1000HD:
 603                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 604                         case BRGPHY_RES_100FD:
 605                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 606                         case BRGPHY_RES_100T4:
 607                                 mii->mii_media_active |= IFM_100_T4; break;
 608                         case BRGPHY_RES_100HD:
 609                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 610                         case BRGPHY_RES_10FD:
 611                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 612                         case BRGPHY_RES_10HD:
 613                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 614                         default:
 615                                 mii->mii_media_active |= IFM_NONE; break;
 616                         }
 617                 }
 618         } else {
 619                 /* If serdes link is up, get the negotiated speed/duplex. */
 620                 if (bmsr & BRGPHY_BMSR_LINK) {
 621                         mii->mii_media_status |= IFM_ACTIVE;
 622                 }
 623
 624                 /* Check the link speed/duplex based on the PHY type. */
 625                 if (bsc->serdes_flags & BRGPHY_5706S) {
 626                         mii->mii_media_active |= IFM_1000_SX;
 627
 628                         /* If autoneg enabled, read negotiated duplex settings */
 629                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 630                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 631                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 632                                         mii->mii_media_active |= IFM_FDX;
 633                                 else
 634                                         mii->mii_media_active |= IFM_HDX;
 635                         }
 636
 637                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 638                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 639                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 640
 641                         /* Check for MRBE auto-negotiated speed results. */
 642                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 643                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 644                                 mii->mii_media_active |= IFM_10_FL; break;
 645                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 646                                 mii->mii_media_active |= IFM_100_FX; break;
 647                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 648                                 mii->mii_media_active |= IFM_1000_SX; break;
 649                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 650                                 mii->mii_media_active |= IFM_2500_SX; break;
 651                         }
 652
 653                         /* Check for MRBE auto-negotiated duplex results. */
 654                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 655                                 mii->mii_media_active |= IFM_FDX;
 656                         else
 657                                 mii->mii_media_active |= IFM_HDX;
 658
 659                 } else if (bsc->serdes_flags & BRGPHY_5709S) {
 660
 661                         /* Select GP Status Block of the AN MMD, get autoneg results. */
 662                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 663                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 664
 665                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 666                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 667
 668                         /* Check for MRBE auto-negotiated speed results. */
 669                         switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 670                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 671                                         mii->mii_media_active |= IFM_10_FL; break;
 672                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 673                                         mii->mii_media_active |= IFM_100_FX; break;
 674                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 675                                         mii->mii_media_active |= IFM_1000_SX; break;
 676                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 677                                         mii->mii_media_active |= IFM_2500_SX; break;
 678                         }
 679
 680                         /* Check for MRBE auto-negotiated duplex results. */
 681                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 682                                 mii->mii_media_active |= IFM_FDX;
 683                         else
 684                                 mii->mii_media_active |= IFM_HDX;
 685                 }
 686
 687         }
 688
 689         /* Todo: Change bge to use these settings. */
 690
 691         /* Fetch flow control settings from the copper PHY. */
 692         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 693                 /* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */
 694                 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
 695                         mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
 696                 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
 697                     (anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 698                         mii->mii_media_active |= IFM_FLAG1;
 699                 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
 700                     !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 701                         mii->mii_media_active |= IFM_FLAG0;
 702                 }
 703         }
 704
 705         /* Todo: Add support for fiber settings too. */
 706
 707
 708 brgphy_status_exit:
 709         return;
 710 }
 711
 712 static void
 713 brgphy_mii_phy_auto(struct mii_softc *sc)
 714 {
 715         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 716         int ktcr = 0;
 717
 718         brgphy_reset(sc);
 719
 720         /* Enable flow control in the advertisement register. */
 721         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 722                 /* Pause capability advertisement (pause capable & asymmetric) */
 723                 PHY_WRITE(sc, BRGPHY_MII_ANAR,
 724                 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
 725                 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
 726         } else {
 727                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 728                         BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
 729         }
 730
 731         /* Enable speed in the 1000baseT control register */
 732         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 733         if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 734                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 735         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 736         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 737
 738         /* Start autonegotiation */
 739         PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 740         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 741
 742 }
 743
 744
 745 /* Enable loopback to force the link down. */
 746 static void
 747 brgphy_enable_loopback(struct mii_softc *sc)
 748 {
 749         int i;
 750
 751         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 752         for (i = 0; i < 15000; i++) {
 753                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 754                         break;
 755                 DELAY(10);
 756         }
 757 }
 758
 759 /* Turn off tap power management on 5401. */
 760 static void
 761 bcm5401_load_dspcode(struct mii_softc *sc)
 762 {
 763         static const struct {
 764                 int             reg;
 765                 uint16_t        val;
 766         } dspcode[] = {
 767                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 768                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 769                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 770                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 771                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 772                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 773                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 774                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 775                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 776                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 777                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 778                 { 0,                            0 },
 779         };
 780         int i;
 781
 782         for (i = 0; dspcode[i].reg != 0; i++)
 783                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 784         DELAY(40);
 785 }
 786
 787 static void
 788 bcm5411_load_dspcode(struct mii_softc *sc)
 789 {
 790         static const struct {
 791                 int             reg;
 792                 uint16_t        val;
 793         } dspcode[] = {
 794                 { 0x1c,                         0x8c23 },
 795                 { 0x1c,                         0x8ca3 },
 796                 { 0x1c,                         0x8c23 },
 797                 { 0,                            0 },
 798         };
 799         int i;
 800
 801         for (i = 0; dspcode[i].reg != 0; i++)
 802                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 803 }
 804
 805 void
 806 bcm54k2_load_dspcode(struct mii_softc *sc)
 807 {
 808         static const struct {
 809                 int             reg;
 810                 uint16_t        val;
 811         } dspcode[] = {
 812                 { 4,                            0x01e1 },
 813                 { 9,                            0x0300 },
 814                 { 0,                            0 },
 815         };
 816         int i;
 817
 818         for (i = 0; dspcode[i].reg != 0; i++)
 819                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 820
 821 }
 822
 823 static void
 824 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 825 {
 826         static const struct {
 827                 int             reg;
 828                 uint16_t        val;
 829         } dspcode[] = {
 830                 { 0x1c,                         0x8d68 },
 831                 { 0x1c,                         0x8d68 },
 832                 { 0,                            0 },
 833         };
 834         int i;
 835
 836         for (i = 0; dspcode[i].reg != 0; i++)
 837                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 838 }
 839
 840 static void
 841 brgphy_fixup_adc_bug(struct mii_softc *sc)
 842 {
 843         static const struct {
 844                 int             reg;
 845                 uint16_t        val;
 846         } dspcode[] = {
 847                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 848                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 849                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 850                 { 0,                            0 },
 851         };
 852         int i;
 853
 854         for (i = 0; dspcode[i].reg != 0; i++)
 855                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 856 }
 857
 858 static void
 859 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 860 {
 861         static const struct {
 862                 int             reg;
 863                 uint16_t        val;
 864         } dspcode[] = {
 865                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 866                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 867                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 868                 { BRGPHY_MII_TEST1,                     0x0014 },
 869                 { BRGPHY_MII_AUXCTL,            0x0400 },
 870                 { 0,                            0 },
 871         };
 872         int i;
 873
 874         for (i = 0; dspcode[i].reg != 0; i++)
 875                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 876 }
 877
 878 static void
 879 brgphy_fixup_ber_bug(struct mii_softc *sc)
 880 {
 881         static const struct {
 882                 int             reg;
 883                 uint16_t        val;
 884         } dspcode[] = {
 885                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 886                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 887                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 888                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 889                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 890                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 891                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 892                 { BRGPHY_MII_AUXCTL,            0x0400 },
 893                 { 0,                            0 },
 894         };
 895         int i;
 896
 897         for (i = 0; dspcode[i].reg != 0; i++)
 898                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 899 }
 900
 901 static void
 902 brgphy_fixup_crc_bug(struct mii_softc *sc)
 903 {
 904         static const struct {
 905                 int             reg;
 906                 uint16_t        val;
 907         } dspcode[] = {
 908                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 909                 { 0x1c,                         0x8c68 },
 910                 { 0x1c,                         0x8d68 },
 911                 { 0x1c,                         0x8c68 },
 912                 { 0,                            0 },
 913         };
 914         int i;
 915
 916         for (i = 0; dspcode[i].reg != 0; i++)
 917                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 918 }
 919
 920 static void
 921 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 922 {
 923         static const struct {
 924                 int             reg;
 925                 uint16_t        val;
 926         } dspcode[] = {
 927                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 928                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 929                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 930                 { BRGPHY_MII_AUXCTL,            0x0400 },
 931                 { 0,                            0 },
 932         };
 933         int i;
 934
 935         for (i = 0; dspcode[i].reg != 0; i++)
 936                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 937 }
 938
 939
 940 static void
 941 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 942 {
 943         uint32_t val;
 944
 945         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 946         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 947         val &= ~(1 << 8);
 948         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 949
 950 }
 951
 952
 953 static void
 954 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 955 {
 956         uint32_t        val;
 957
 958         /* Enable Ethernet@WireSpeed. */
 959         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 960         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 961         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 962 }
 963
 964
 965 static void
 966 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 967 {
 968         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 969         uint32_t        val;
 970
 971         /* Set or clear jumbo frame settings in the PHY. */
 972         if (mtu > ETHER_MAX_LEN) {
 973                 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 974                         /* BCM5401 PHY cannot read-modify-write. */
 975                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 976                 } else {
 977                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 978                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 979                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 980                             val | BRGPHY_AUXCTL_LONG_PKT);
 981                 }
 982
 983                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 984                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 985                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 986         } else {
 987                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 988                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 989                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 990                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 991
 992                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 993                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 994                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 995         }
 996 }
 997
 998 static void
 999 brgphy_reset(struct mii_softc *sc)
1000 {
1001         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
1002         struct bge_softc *bge_sc = NULL;
1003         struct bce_softc *bce_sc = NULL;
1004         struct ifnet *ifp;
1005     int val;
1006
1007         /* Perform a standard PHY reset. */
1008         mii_phy_reset(sc);
1009
1010         /* Handle any PHY specific procedures following the reset. */
1011         switch (bsc->mii_oui) {
1012         case MII_OUI_BROADCOM:
1013                 break;
1014         case MII_OUI_xxBROADCOM:
1015                 switch (bsc->mii_model) {
1016                 case MII_MODEL_xxBROADCOM_BCM5400:
1017                         bcm5401_load_dspcode(sc);
1018                         break;
1019                 case MII_MODEL_xxBROADCOM_BCM5401:
1020                         if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
1021                                 bcm5401_load_dspcode(sc);
1022                         break;
1023                 case MII_MODEL_xxBROADCOM_BCM5411:
1024                         bcm5411_load_dspcode(sc);
1025                         break;
1026                 case MII_MODEL_xxBROADCOM_BCM54K2:
1027                         bcm54k2_load_dspcode(sc);
1028                         break;
1029                 }
1030                 break;
1031         case MII_OUI_xxBROADCOM_ALT1:
1032                 break;
1033         }
1034
1035         ifp = sc->mii_pdata->mii_ifp;
1036
1037         /* Find the driver associated with this PHY. */
1038         if (strcmp(ifp->if_dname, "bge") == 0)  {
1039                 bge_sc = ifp->if_softc;
1040         } else if (strcmp(ifp->if_dname, "bce") == 0) {
1041                 bce_sc = ifp->if_softc;
1042         }
1043
1044         /* Handle any bge (NetXtreme/NetLink) workarounds. */
1045         if (bge_sc) {
1046                 /* Fix up various bugs */
1047                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
1048                         brgphy_fixup_5704_a0_bug(sc);
1049                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
1050                         brgphy_fixup_adc_bug(sc);
1051                 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
1052                         brgphy_fixup_adjust_trim(sc);
1053                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
1054                         brgphy_fixup_ber_bug(sc);
1055                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
1056                         brgphy_fixup_crc_bug(sc);
1057                 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
1058                         brgphy_fixup_jitter_bug(sc);
1059
1060                 brgphy_jumbo_settings(sc, ifp->if_mtu);
1061
1062                 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
1063                         brgphy_ethernet_wirespeed(sc);
1064
1065                 /* Enable Link LED on Dell boxes */
1066                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
1067                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
1068                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
1069                             ~BRGPHY_PHY_EXTCTL_3_LED);
1070                 }
1071
1072                 /* Adjust output voltage (From Linux driver) */
1073                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
1074                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
1075
1076         /* Handle any bce (NetXtreme II) workarounds. */
1077         } else if (bce_sc) {
1078
1079                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
1080                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1081
1082                         /* Store autoneg capabilities/results in digital block (Page 0) */
1083                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
1084                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
1085                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
1086                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1087
1088                         /* Enable fiber mode and autodetection */
1089                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1090                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1091                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1092                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1093
1094                         /* Enable parallel detection */
1095                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1096                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1097                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1098
1099                         /* Advertise 2.5G support through next page during autoneg */
1100                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1101                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1102                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1103                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1104
1105                         /* Increase TX signal amplitude */
1106                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1107                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1108                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1109                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1110                                         BRGPHY_5708S_TX_MISC_PG5);
1111                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1112                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1113                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1114                                         BRGPHY_5708S_DIG_PG0);
1115                         }
1116
1117                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1118                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1119                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1120                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1121                                                 BRGPHY_5708S_TX_MISC_PG5);
1122                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1123                                                 bce_sc->bce_port_hw_cfg &
1124                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1125                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1126                                                 BRGPHY_5708S_DIG_PG0);
1127                         }
1128                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1129                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1130
1131                         /* Select the SerDes Digital block of the AN MMD. */
1132                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1133                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1134                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1135                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1136                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1137
1138                         /* Select the Over 1G block of the AN MMD. */
1139                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1140
1141                         /* Enable autoneg "Next Page" to advertise 2.5G support. */
1142                         val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1143                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1144                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1145                         else
1146                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1147                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1148
1149                         /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1150                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1151
1152                         /* Enable MRBE speed autoneg. */
1153                         val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1154                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1155                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1156                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1157
1158                         /* Select the Clause 73 User B0 block of the AN MMD. */
1159                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1160
1161                         /* Enable MRBE speed autoneg. */
1162                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1163                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1164                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1165                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1166
1167                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1168                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1169
1170         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1171                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1172                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1173                                 brgphy_fixup_disable_early_dac(sc);
1174
1175                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1176                         brgphy_ethernet_wirespeed(sc);
1177                 } else {
1178                         brgphy_fixup_ber_bug(sc);
1179                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1180                         brgphy_ethernet_wirespeed(sc);
1181                 }
1182
1183         }
1184 }
1185