2 * Principal Author: Parag Patel
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Additional Copyright (c) 2001 by Traakan Software under same licence.
29 * Secondary Author: Matthew Jacob
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
42 * Nathan Binkert <nate@openbsd.org>
43 * Jung-uk Kim <jkim@niksun.com>
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/socket.h>
55 #include <net/if_media.h>
57 #include <dev/mii/mii.h>
58 #include <dev/mii/miivar.h>
61 #include <dev/mii/e1000phyreg.h>
63 #include "miibus_if.h"
65 static int e1000phy_probe(device_t);
66 static int e1000phy_attach(device_t);
68 static device_method_t e1000phy_methods[] = {
69 /* device interface */
70 DEVMETHOD(device_probe, e1000phy_probe),
71 DEVMETHOD(device_attach, e1000phy_attach),
72 DEVMETHOD(device_detach, mii_phy_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
77 static devclass_t e1000phy_devclass;
78 static driver_t e1000phy_driver = {
81 sizeof(struct mii_softc)
84 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
86 static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
87 static void e1000phy_status(struct mii_softc *);
88 static void e1000phy_reset(struct mii_softc *);
89 static int e1000phy_mii_phy_auto(struct mii_softc *, int);
91 static const struct mii_phydesc e1000phys[] = {
92 MII_PHY_DESC(MARVELL, E1000),
93 MII_PHY_DESC(MARVELL, E1011),
94 MII_PHY_DESC(MARVELL, E1000_3),
95 MII_PHY_DESC(MARVELL, E1000_5),
96 MII_PHY_DESC(MARVELL, E1111),
97 MII_PHY_DESC(xxMARVELL, E1000),
98 MII_PHY_DESC(xxMARVELL, E1011),
99 MII_PHY_DESC(xxMARVELL, E1000_3),
100 MII_PHY_DESC(xxMARVELL, E1000S),
101 MII_PHY_DESC(xxMARVELL, E1000_5),
102 MII_PHY_DESC(xxMARVELL, E1101),
103 MII_PHY_DESC(xxMARVELL, E3082),
104 MII_PHY_DESC(xxMARVELL, E1112),
105 MII_PHY_DESC(xxMARVELL, E1149),
106 MII_PHY_DESC(xxMARVELL, E1111),
107 MII_PHY_DESC(xxMARVELL, E1116),
108 MII_PHY_DESC(xxMARVELL, E1116R),
109 MII_PHY_DESC(xxMARVELL, E1118),
110 MII_PHY_DESC(xxMARVELL, E1149R),
111 MII_PHY_DESC(xxMARVELL, E3016),
112 MII_PHY_DESC(xxMARVELL, PHYG65G),
116 static const struct mii_phy_funcs e1000phy_funcs = {
123 e1000phy_probe(device_t dev)
126 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
130 e1000phy_attach(device_t dev)
132 struct mii_softc *sc;
135 sc = device_get_softc(dev);
137 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0);
139 ifp = sc->mii_pdata->mii_ifp;
140 if (strcmp(ifp->if_dname, "msk") == 0 &&
141 (sc->mii_flags & MIIF_MACPRIV0) != 0)
142 sc->mii_flags |= MIIF_PHYPRIV0;
144 switch (sc->mii_mpd_model) {
145 case MII_MODEL_xxMARVELL_E1011:
146 case MII_MODEL_xxMARVELL_E1112:
147 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
148 sc->mii_flags |= MIIF_HAVEFIBER;
150 case MII_MODEL_xxMARVELL_E1149:
151 case MII_MODEL_xxMARVELL_E1149R:
153 * Some 88E1149 PHY's page select is initialized to
154 * point to other bank instead of copper/fiber bank
155 * which in turn resulted in wrong registers were
156 * accessed during PHY operation. It is believed that
157 * page 0 should be used for copper PHY so reinitialize
158 * E1000_EADR to select default copper PHY. If parent
159 * device know the type of PHY(either copper or fiber),
160 * that information should be used to select default
163 PHY_WRITE(sc, E1000_EADR, 0);
169 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
170 if (sc->mii_capabilities & BMSR_EXTSTAT) {
171 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
172 if ((sc->mii_extcapabilities &
173 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
174 sc->mii_flags |= MIIF_HAVE_GTCR;
176 device_printf(dev, " ");
177 mii_phy_add_media(sc);
180 MIIBUS_MEDIAINIT(sc->mii_dev);
185 e1000phy_reset(struct mii_softc *sc)
189 reg = PHY_READ(sc, E1000_SCR);
190 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
191 reg &= ~E1000_SCR_AUTO_X_MODE;
192 PHY_WRITE(sc, E1000_SCR, reg);
193 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) {
194 /* Select 1000BASE-X only mode. */
195 page = PHY_READ(sc, E1000_EADR);
196 PHY_WRITE(sc, E1000_EADR, 2);
197 reg = PHY_READ(sc, E1000_SCR);
198 reg &= ~E1000_SCR_MODE_MASK;
199 reg |= E1000_SCR_MODE_1000BX;
200 PHY_WRITE(sc, E1000_SCR, reg);
201 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
202 /* Set SIGDET polarity low for SFP module. */
203 PHY_WRITE(sc, E1000_EADR, 1);
204 reg = PHY_READ(sc, E1000_SCR);
205 reg |= E1000_SCR_FIB_SIGDET_POLARITY;
206 PHY_WRITE(sc, E1000_SCR, reg);
208 PHY_WRITE(sc, E1000_EADR, page);
211 switch (sc->mii_mpd_model) {
212 case MII_MODEL_xxMARVELL_E1111:
213 case MII_MODEL_xxMARVELL_E1112:
214 case MII_MODEL_xxMARVELL_E1116:
215 case MII_MODEL_xxMARVELL_E1118:
216 case MII_MODEL_xxMARVELL_E1149:
217 case MII_MODEL_xxMARVELL_E1149R:
218 case MII_MODEL_xxMARVELL_PHYG65G:
219 /* Disable energy detect mode. */
220 reg &= ~E1000_SCR_EN_DETECT_MASK;
221 reg |= E1000_SCR_AUTO_X_MODE;
222 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116)
223 reg &= ~E1000_SCR_POWER_DOWN;
224 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
226 case MII_MODEL_xxMARVELL_E3082:
227 reg |= (E1000_SCR_AUTO_X_MODE >> 1);
228 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
230 case MII_MODEL_xxMARVELL_E3016:
231 reg |= E1000_SCR_AUTO_MDIX;
232 reg &= ~(E1000_SCR_EN_DETECT |
233 E1000_SCR_SCRAMBLER_DISABLE);
234 reg |= E1000_SCR_LPNP;
235 /* XXX Enable class A driver for Yukon FE+ A0. */
236 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
239 reg &= ~E1000_SCR_AUTO_X_MODE;
240 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
243 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) {
244 /* Auto correction for reversed cable polarity. */
245 reg &= ~E1000_SCR_POLARITY_REVERSAL;
247 PHY_WRITE(sc, E1000_SCR, reg);
249 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
250 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 ||
251 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) {
252 PHY_WRITE(sc, E1000_EADR, 2);
253 reg = PHY_READ(sc, E1000_SCR);
254 reg |= E1000_SCR_RGMII_POWER_UP;
255 PHY_WRITE(sc, E1000_SCR, reg);
256 PHY_WRITE(sc, E1000_EADR, 0);
260 switch (sc->mii_mpd_model) {
261 case MII_MODEL_xxMARVELL_E3082:
262 case MII_MODEL_xxMARVELL_E1112:
263 case MII_MODEL_xxMARVELL_E1118:
265 case MII_MODEL_xxMARVELL_E1116:
266 page = PHY_READ(sc, E1000_EADR);
267 /* Select page 3, LED control register. */
268 PHY_WRITE(sc, E1000_EADR, 3);
269 PHY_WRITE(sc, E1000_SCR,
270 E1000_SCR_LED_LOS(1) | /* Link/Act */
271 E1000_SCR_LED_INIT(8) | /* 10Mbps */
272 E1000_SCR_LED_STAT1(7) | /* 100Mbps */
273 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
274 /* Set blink rate. */
275 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
276 E1000_BLINK_RATE(E1000_BLINK_84MS));
277 PHY_WRITE(sc, E1000_EADR, page);
279 case MII_MODEL_xxMARVELL_E3016:
280 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
281 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
282 /* Integrated register calibration workaround. */
283 PHY_WRITE(sc, 0x1D, 17);
284 PHY_WRITE(sc, 0x1E, 0x3F60);
287 /* Force TX_CLK to 25MHz clock. */
288 reg = PHY_READ(sc, E1000_ESCR);
289 reg |= E1000_ESCR_TX_CLK_25;
290 PHY_WRITE(sc, E1000_ESCR, reg);
294 /* Reset the PHY so all changes take effect. */
295 reg = PHY_READ(sc, E1000_CR);
296 reg |= E1000_CR_RESET;
297 PHY_WRITE(sc, E1000_CR, reg);
301 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
303 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
313 * If the interface is not up, don't do anything.
315 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
318 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
319 e1000phy_mii_phy_auto(sc, ife->ifm_media);
324 switch (IFM_SUBTYPE(ife->ifm_media)) {
326 if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0)
328 speed = E1000_CR_SPEED_1000;
331 if ((sc->mii_extcapabilities &
332 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
334 speed = E1000_CR_SPEED_1000;
337 speed = E1000_CR_SPEED_100;
340 speed = E1000_CR_SPEED_10;
343 reg = PHY_READ(sc, E1000_CR);
344 PHY_WRITE(sc, E1000_CR,
345 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
351 if ((ife->ifm_media & IFM_FDX) != 0) {
352 speed |= E1000_CR_FULL_DUPLEX;
353 gig = E1000_1GCR_1000T_FD;
355 gig = E1000_1GCR_1000T;
357 reg = PHY_READ(sc, E1000_CR);
358 reg &= ~E1000_CR_AUTO_NEG_ENABLE;
359 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
361 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
362 gig |= E1000_1GCR_MS_ENABLE;
363 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
364 gig |= E1000_1GCR_MS_VALUE;
365 } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0)
367 PHY_WRITE(sc, E1000_1GCR, gig);
368 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
369 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
374 * Is the interface even up?
376 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
380 * Only used for autonegotiation.
382 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
389 * Read the status register twice; BMSR_LINK is latch-low.
391 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
392 if (reg & BMSR_LINK) {
397 /* Announce link loss right after it happens. */
398 if (sc->mii_ticks++ == 0)
400 if (sc->mii_ticks <= sc->mii_anegticks)
405 e1000phy_mii_phy_auto(sc, ife->ifm_media);
409 /* Update the media status. */
412 /* Callback if something changed. */
413 mii_phy_update(sc, cmd);
418 e1000phy_status(struct mii_softc *sc)
420 struct mii_data *mii = sc->mii_pdata;
423 mii->mii_media_status = IFM_AVALID;
424 mii->mii_media_active = IFM_ETHER;
426 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
427 bmcr = PHY_READ(sc, E1000_CR);
428 ssr = PHY_READ(sc, E1000_SSR);
430 if (bmsr & E1000_SR_LINK_STATUS)
431 mii->mii_media_status |= IFM_ACTIVE;
433 if (bmcr & E1000_CR_LOOPBACK)
434 mii->mii_media_active |= IFM_LOOP;
436 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
437 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
438 /* Erg, still trying, I guess... */
439 mii->mii_media_active |= IFM_NONE;
443 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
444 switch (ssr & E1000_SSR_SPEED) {
445 case E1000_SSR_1000MBS:
446 mii->mii_media_active |= IFM_1000_T;
448 case E1000_SSR_100MBS:
449 mii->mii_media_active |= IFM_100_TX;
451 case E1000_SSR_10MBS:
452 mii->mii_media_active |= IFM_10_T;
455 mii->mii_media_active |= IFM_NONE;
460 * Some fiber PHY(88E1112) does not seem to set resolved
461 * speed so always assume we've got IFM_1000_SX.
463 mii->mii_media_active |= IFM_1000_SX;
466 if (ssr & E1000_SSR_DUPLEX) {
467 mii->mii_media_active |= IFM_FDX;
468 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
469 mii->mii_media_active |= mii_phy_flowstatus(sc);
471 mii->mii_media_active |= IFM_HDX;
473 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
474 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) &
475 E1000_1GSR_MS_CONFIG_RES) != 0)
476 mii->mii_media_active |= IFM_ETH_MASTER;
481 e1000phy_mii_phy_auto(struct mii_softc *sc, int media)
485 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
486 reg = PHY_READ(sc, E1000_AR);
487 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);
488 reg |= E1000_AR_10T | E1000_AR_10T_FD |
489 E1000_AR_100TX | E1000_AR_100TX_FD;
490 if ((media & IFM_FLOW) != 0 ||
491 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
492 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;
493 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
495 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X);
496 if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
498 if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0)
499 reg |= E1000_1GCR_1000T_FD;
500 if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0)
501 reg |= E1000_1GCR_1000T;
502 PHY_WRITE(sc, E1000_1GCR, reg);
504 PHY_WRITE(sc, E1000_CR,
505 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
507 return (EJUSTRETURN);