3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
48 #include <net/if_arp.h>
49 #include <net/if_media.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
55 #include <dev/mii/rgephyreg.h>
57 #include "miibus_if.h"
59 #include <machine/bus.h>
60 #include <pci/if_rlreg.h>
62 static int rgephy_probe(device_t);
63 static int rgephy_attach(device_t);
65 static device_method_t rgephy_methods[] = {
66 /* device interface */
67 DEVMETHOD(device_probe, rgephy_probe),
68 DEVMETHOD(device_attach, rgephy_attach),
69 DEVMETHOD(device_detach, mii_phy_detach),
70 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 static devclass_t rgephy_devclass;
76 static driver_t rgephy_driver = {
79 sizeof(struct mii_softc)
82 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
84 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
85 static void rgephy_status(struct mii_softc *);
86 static int rgephy_mii_phy_auto(struct mii_softc *, int);
87 static void rgephy_reset(struct mii_softc *);
88 static void rgephy_loop(struct mii_softc *);
89 static void rgephy_load_dspcode(struct mii_softc *);
91 static const struct mii_phydesc rgephys[] = {
92 MII_PHY_DESC(REALTEK, RTL8169S),
96 static const struct mii_phy_funcs rgephy_funcs = {
103 rgephy_probe(device_t dev)
106 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
110 rgephy_attach(device_t dev)
112 struct mii_softc *sc;
113 struct mii_attach_args *ma;
116 sc = device_get_softc(dev);
117 ma = device_get_ivars(dev);
119 if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0)
120 flags |= MIIF_PHYPRIV0;
121 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0);
123 /* RTL8169S do not report auto-sense; add manually. */
124 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
126 if (sc->mii_capabilities & BMSR_EXTSTAT)
127 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
128 device_printf(dev, " ");
129 mii_phy_add_media(sc);
132 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with
133 * manual configuration, which is used to work around issues with
134 * certain setups by default, should not be triggered as it may in
135 * turn cause harm in some edge cases.
137 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0;
141 MIIBUS_MEDIAINIT(sc->mii_dev);
146 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
148 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
149 int reg, speed, gig, anar;
157 * If the interface is not up, don't do anything.
159 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
162 PHY_RESET(sc); /* XXX hardware bug work-around */
164 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
165 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
166 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
167 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
169 switch (IFM_SUBTYPE(ife->ifm_media)) {
173 * If we're already in auto mode, just return.
175 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
178 (void)rgephy_mii_phy_auto(sc, ife->ifm_media);
181 speed = RGEPHY_S1000;
185 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
189 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
191 if ((ife->ifm_media & IFM_FLOW) != 0 &&
192 (mii->mii_media.ifm_media & IFM_FLAG0) != 0)
195 if ((ife->ifm_media & IFM_FDX) != 0) {
196 speed |= RGEPHY_BMCR_FDX;
197 gig = RGEPHY_1000CTL_AFD;
198 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
199 if ((ife->ifm_media & IFM_FLOW) != 0 ||
200 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
202 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
204 gig = RGEPHY_1000CTL_AHD;
206 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
208 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
209 gig |= RGEPHY_1000CTL_MSE;
210 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
211 gig |= RGEPHY_1000CTL_MSC;
214 anar &= ~RGEPHY_ANAR_ASP;
216 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0)
218 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG;
220 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
221 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
222 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
225 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
234 * Is the interface even up?
236 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
240 * Only used for autonegotiation.
242 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
248 * Check to see if we have link. If we do, we don't
249 * need to restart the autonegotiation process.
251 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
252 sc->mii_mpd_rev >= 2) {
254 reg = PHY_READ(sc, RGEPHY_MII_SSR);
255 if (reg & RGEPHY_SSR_LINK) {
260 reg = PHY_READ(sc, RL_GMEDIASTAT);
261 if (reg & RL_GMEDIASTAT_LINK) {
267 /* Announce link loss right after it happens. */
268 if (sc->mii_ticks++ == 0)
271 /* Only retry autonegotiation every mii_anegticks seconds. */
272 if (sc->mii_ticks <= sc->mii_anegticks)
276 rgephy_mii_phy_auto(sc, ife->ifm_media);
280 /* Update the media status. */
284 * Callback if something changed. Note that we need to poke
285 * the DSP on the RealTek PHYs if the media changes.
288 if (sc->mii_media_active != mii->mii_media_active ||
289 sc->mii_media_status != mii->mii_media_status ||
290 cmd == MII_MEDIACHG) {
291 rgephy_load_dspcode(sc);
293 mii_phy_update(sc, cmd);
298 rgephy_status(struct mii_softc *sc)
300 struct mii_data *mii = sc->mii_pdata;
304 mii->mii_media_status = IFM_AVALID;
305 mii->mii_media_active = IFM_ETHER;
307 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) {
308 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
309 if (ssr & RGEPHY_SSR_LINK)
310 mii->mii_media_status |= IFM_ACTIVE;
312 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
313 if (bmsr & RL_GMEDIASTAT_LINK)
314 mii->mii_media_status |= IFM_ACTIVE;
317 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
319 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
320 if (bmcr & RGEPHY_BMCR_ISO) {
321 mii->mii_media_active |= IFM_NONE;
322 mii->mii_media_status = 0;
326 if (bmcr & RGEPHY_BMCR_LOOP)
327 mii->mii_media_active |= IFM_LOOP;
329 if (bmcr & RGEPHY_BMCR_AUTOEN) {
330 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
331 /* Erg, still trying, I guess... */
332 mii->mii_media_active |= IFM_NONE;
337 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) {
338 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
339 switch (ssr & RGEPHY_SSR_SPD_MASK) {
340 case RGEPHY_SSR_S1000:
341 mii->mii_media_active |= IFM_1000_T;
343 case RGEPHY_SSR_S100:
344 mii->mii_media_active |= IFM_100_TX;
347 mii->mii_media_active |= IFM_10_T;
350 mii->mii_media_active |= IFM_NONE;
353 if (ssr & RGEPHY_SSR_FDX)
354 mii->mii_media_active |= IFM_FDX;
356 mii->mii_media_active |= IFM_HDX;
358 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
359 if (bmsr & RL_GMEDIASTAT_1000MBPS)
360 mii->mii_media_active |= IFM_1000_T;
361 else if (bmsr & RL_GMEDIASTAT_100MBPS)
362 mii->mii_media_active |= IFM_100_TX;
363 else if (bmsr & RL_GMEDIASTAT_10MBPS)
364 mii->mii_media_active |= IFM_10_T;
366 mii->mii_media_active |= IFM_NONE;
367 if (bmsr & RL_GMEDIASTAT_FDX)
368 mii->mii_media_active |= IFM_FDX;
370 mii->mii_media_active |= IFM_HDX;
373 if ((mii->mii_media_active & IFM_FDX) != 0)
374 mii->mii_media_active |= mii_phy_flowstatus(sc);
376 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
377 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
378 mii->mii_media_active |= IFM_ETH_MASTER;
382 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
389 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
390 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
391 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
392 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
394 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
395 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
397 PHY_WRITE(sc, RGEPHY_MII_BMCR,
398 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
401 return (EJUSTRETURN);
405 rgephy_loop(struct mii_softc *sc)
409 if (sc->mii_mpd_rev < 2) {
410 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
414 for (i = 0; i < 15000; i++) {
415 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
417 device_printf(sc->mii_dev, "looped %d\n", i);
425 #define PHY_SETBIT(x, y, z) \
426 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
427 #define PHY_CLRBIT(x, y, z) \
428 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
431 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
432 * existing revisions of the 8169S/8110S chips need to be tuned in
433 * order to reliably negotiate a 1000Mbps link. This is only needed
434 * for rev 0 and rev 1 of the PHY. Later versions work without
438 rgephy_load_dspcode(struct mii_softc *sc)
442 if (sc->mii_mpd_rev >= 2)
445 PHY_WRITE(sc, 31, 0x0001);
446 PHY_WRITE(sc, 21, 0x1000);
447 PHY_WRITE(sc, 24, 0x65C7);
448 PHY_CLRBIT(sc, 4, 0x0800);
449 val = PHY_READ(sc, 4) & 0xFFF;
450 PHY_WRITE(sc, 4, val);
451 PHY_WRITE(sc, 3, 0x00A1);
452 PHY_WRITE(sc, 2, 0x0008);
453 PHY_WRITE(sc, 1, 0x1020);
454 PHY_WRITE(sc, 0, 0x1000);
455 PHY_SETBIT(sc, 4, 0x0800);
456 PHY_CLRBIT(sc, 4, 0x0800);
457 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
458 PHY_WRITE(sc, 4, val);
459 PHY_WRITE(sc, 3, 0xFF41);
460 PHY_WRITE(sc, 2, 0xDE60);
461 PHY_WRITE(sc, 1, 0x0140);
462 PHY_WRITE(sc, 0, 0x0077);
463 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
464 PHY_WRITE(sc, 4, val);
465 PHY_WRITE(sc, 3, 0xDF01);
466 PHY_WRITE(sc, 2, 0xDF20);
467 PHY_WRITE(sc, 1, 0xFF95);
468 PHY_WRITE(sc, 0, 0xFA00);
469 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
470 PHY_WRITE(sc, 4, val);
471 PHY_WRITE(sc, 3, 0xFF41);
472 PHY_WRITE(sc, 2, 0xDE20);
473 PHY_WRITE(sc, 1, 0x0140);
474 PHY_WRITE(sc, 0, 0x00BB);
475 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
476 PHY_WRITE(sc, 4, val);
477 PHY_WRITE(sc, 3, 0xDF01);
478 PHY_WRITE(sc, 2, 0xDF20);
479 PHY_WRITE(sc, 1, 0xFF95);
480 PHY_WRITE(sc, 0, 0xBF00);
481 PHY_SETBIT(sc, 4, 0x0800);
482 PHY_CLRBIT(sc, 4, 0x0800);
483 PHY_WRITE(sc, 31, 0x0000);
489 rgephy_reset(struct mii_softc *sc)
493 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) {
495 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
496 if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
497 ssr &= ~RGEPHY_SSR_ALDPS;
498 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
502 if (sc->mii_mpd_rev >= 2) {
503 pcr = PHY_READ(sc, RGEPHY_MII_PCR);
504 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) {
505 pcr &= ~RGEPHY_PCR_MDI_MASK;
506 pcr |= RGEPHY_PCR_MDIX_AUTO;
507 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
513 rgephy_load_dspcode(sc);