2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/mii_layer/truephy.c,v 1.3 2008/02/10 07:29:27 sephe Exp $
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/errno.h>
43 #include <sys/module.h>
47 #include <net/if_media.h>
48 #include <net/if_arp.h>
49 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
56 #include <dev/mii/truephyreg.h>
58 #include "miibus_if.h"
60 #define TRUEPHY_FRAMELEN(mtu) \
61 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + (mtu) + ETHER_CRC_LEN)
63 static int truephy_service(struct mii_softc *, struct mii_data *, int);
64 static int truephy_attach(device_t);
65 static int truephy_probe(device_t);
66 static void truephy_reset(struct mii_softc *);
67 static void truephy_status(struct mii_softc *);
69 static device_method_t truephy_methods[] = {
70 /* device interface */
71 DEVMETHOD(device_probe, truephy_probe),
72 DEVMETHOD(device_attach, truephy_attach),
73 DEVMETHOD(device_detach, mii_phy_detach),
74 DEVMETHOD(device_shutdown, bus_generic_shutdown),
78 static const struct mii_phydesc truephys[] = {
79 MII_PHY_DESC(AGERE, ET1011),
80 MII_PHY_DESC(AGERE, ET1011C),
84 static devclass_t truephy_devclass;
86 static driver_t truephy_driver = {
89 sizeof(struct mii_softc)
92 DRIVER_MODULE(truephy, miibus, truephy_driver, truephy_devclass, 0, 0);
94 static const struct mii_phy_funcs truephy_funcs = {
100 static const struct truephy_dsp {
103 } truephy_dspcode[] = {
104 { 0x880b, 0x0926 }, /* AfeIfCreg4B1000Msbs */
105 { 0x880c, 0x0926 }, /* AfeIfCreg4B100Msbs */
106 { 0x880d, 0x0926 }, /* AfeIfCreg4B10Msbs */
108 { 0x880e, 0xb4d3 }, /* AfeIfCreg4B1000Lsbs */
109 { 0x880f, 0xb4d3 }, /* AfeIfCreg4B100Lsbs */
110 { 0x8810, 0xb4d3 }, /* AfeIfCreg4B10Lsbs */
112 { 0x8805, 0xb03e }, /* AfeIfCreg3B1000Msbs */
113 { 0x8806, 0xb03e }, /* AfeIfCreg3B100Msbs */
114 { 0x8807, 0xff00 }, /* AfeIfCreg3B10Msbs */
116 { 0x8808, 0xe090 }, /* AfeIfCreg3B1000Lsbs */
117 { 0x8809, 0xe110 }, /* AfeIfCreg3B100Lsbs */
118 { 0x880a, 0x0000 }, /* AfeIfCreg3B10Lsbs */
120 { 0x300d, 1 }, /* DisableNorm */
122 { 0x280c, 0x0180 }, /* LinkHoldEnd */
124 { 0x1c21, 0x0002 }, /* AlphaM */
126 { 0x3821, 6 }, /* FfeLkgTx0 */
127 { 0x381d, 1 }, /* FfeLkg1g4 */
128 { 0x381e, 1 }, /* FfeLkg1g5 */
129 { 0x381f, 1 }, /* FfeLkg1g6 */
130 { 0x3820, 1 }, /* FfeLkg1g7 */
132 { 0x8402, 0x01f0 }, /* Btinact */
133 { 0x800e, 20 }, /* LftrainTime */
134 { 0x800f, 24 }, /* DvguardTime */
135 { 0x8010, 46 } /* IdlguardTime */
139 truephy_probe(device_t dev)
142 return (mii_phy_dev_probe(dev, truephys, BUS_PROBE_DEFAULT));
146 truephy_attach(device_t dev)
148 struct mii_softc *sc;
150 sc = device_get_softc(dev);
152 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
157 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
158 if (sc->mii_capabilities & BMSR_EXTSTAT) {
159 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
160 /* No 1000baseT half-duplex support */
161 sc->mii_extcapabilities &= ~EXTSR_1000THDX;
164 device_printf(dev, " ");
165 mii_phy_add_media(sc);
168 MIIBUS_MEDIAINIT(sc->mii_dev);
173 truephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
175 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
184 * If the interface is not up, don't do anything.
186 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
189 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
190 bmcr = PHY_READ(sc, MII_BMCR) & ~BMCR_AUTOEN;
191 PHY_WRITE(sc, MII_BMCR, bmcr);
192 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_PDOWN);
195 mii_phy_setmedia(sc);
197 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
198 bmcr = PHY_READ(sc, MII_BMCR) & ~BMCR_PDOWN;
199 PHY_WRITE(sc, MII_BMCR, bmcr);
201 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
202 PHY_WRITE(sc, MII_BMCR,
203 bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
209 if (mii_phy_tick(sc) == EJUSTRETURN)
214 /* Update the media status. */
217 /* Callback if something changed. */
218 mii_phy_update(sc, cmd);
223 truephy_reset(struct mii_softc *sc)
227 if (sc->mii_mpd_model == MII_MODEL_AGERE_ET1011) {
232 for (i = 0; i < 2; ++i) {
233 PHY_READ(sc, MII_PHYIDR1);
234 PHY_READ(sc, MII_PHYIDR2);
236 PHY_READ(sc, TRUEPHY_CTRL);
237 PHY_WRITE(sc, TRUEPHY_CTRL,
238 TRUEPHY_CTRL_DIAG | TRUEPHY_CTRL_RSV1);
240 PHY_WRITE(sc, TRUEPHY_INDEX, TRUEPHY_INDEX_MAGIC);
241 PHY_READ(sc, TRUEPHY_DATA);
243 PHY_WRITE(sc, TRUEPHY_CTRL, TRUEPHY_CTRL_RSV1);
246 PHY_READ(sc, MII_BMCR);
247 PHY_READ(sc, TRUEPHY_CTRL);
248 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN | BMCR_S1000);
249 PHY_WRITE(sc, TRUEPHY_CTRL,
250 TRUEPHY_CTRL_DIAG | TRUEPHY_CTRL_RSV1 | TRUEPHY_CTRL_RSV0);
252 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
254 for (i = 0; i < N(truephy_dspcode); ++i) {
255 const struct truephy_dsp *dsp = &truephy_dspcode[i];
257 PHY_WRITE(sc, TRUEPHY_INDEX, dsp->index);
258 PHY_WRITE(sc, TRUEPHY_DATA, dsp->data);
260 PHY_WRITE(sc, TRUEPHY_INDEX, dsp->index);
261 PHY_READ(sc, TRUEPHY_DATA);
266 PHY_READ(sc, MII_BMCR);
267 PHY_READ(sc, TRUEPHY_CTRL);
268 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_S1000);
269 PHY_WRITE(sc, TRUEPHY_CTRL, TRUEPHY_CTRL_RSV1);
273 if (TRUEPHY_FRAMELEN(sc->mii_pdata->mii_ifp->if_mtu) > 2048) {
276 conf = PHY_READ(sc, TRUEPHY_CONF);
277 conf &= ~TRUEPHY_CONF_TXFIFO_MASK;
278 conf |= TRUEPHY_CONF_TXFIFO_24;
279 PHY_WRITE(sc, TRUEPHY_CONF, conf);
284 truephy_status(struct mii_softc *sc)
286 struct mii_data *mii = sc->mii_pdata;
289 mii->mii_media_status = IFM_AVALID;
290 mii->mii_media_active = IFM_ETHER;
292 sr = PHY_READ(sc, TRUEPHY_SR);
293 bmcr = PHY_READ(sc, MII_BMCR);
295 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
296 if (bmsr & BMSR_LINK)
297 mii->mii_media_status |= IFM_ACTIVE;
299 if (bmcr & BMCR_AUTOEN) {
300 if ((bmsr & BMSR_ACOMP) == 0) {
301 mii->mii_media_active |= IFM_NONE;
306 switch (sr & TRUEPHY_SR_SPD_MASK) {
307 case TRUEPHY_SR_SPD_1000T:
308 mii->mii_media_active |= IFM_1000_T;
310 case TRUEPHY_SR_SPD_100TX:
311 mii->mii_media_active |= IFM_100_TX;
313 case TRUEPHY_SR_SPD_10T:
314 mii->mii_media_active |= IFM_10_T;
317 /* XXX will this ever happen? */
318 printf("invalid media SR %#x\n", sr);
319 mii->mii_media_active |= IFM_NONE;
323 if (sr & TRUEPHY_SR_FDX)
324 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
326 mii->mii_media_active |= IFM_HDX;