2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <dev/mlx5/driver.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32 #include "mlx5_core.h"
35 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
36 MLX5_EQE_OWNER_INIT_VAL = 0x1,
40 MLX5_NUM_SPARE_EQE = 0x80,
41 MLX5_NUM_ASYNC_EQE = 0x100,
42 MLX5_NUM_CMD_EQE = 32,
46 MLX5_EQ_DOORBEL_OFFSET = 0x40,
49 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
50 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
51 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
52 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
53 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
54 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
55 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
56 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
57 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
58 (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE) | \
59 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
60 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
61 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
74 /*Function prototype*/
75 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
76 struct mlx5_eqe *eqe);
78 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
80 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)];
81 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)];
83 memset(in, 0, sizeof(in));
85 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
86 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
88 memset(out, 0, sizeof(out));
89 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
93 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
95 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
98 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
100 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
102 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
105 static const char *eqe_type_str(u8 type)
108 case MLX5_EVENT_TYPE_COMP:
109 return "MLX5_EVENT_TYPE_COMP";
110 case MLX5_EVENT_TYPE_PATH_MIG:
111 return "MLX5_EVENT_TYPE_PATH_MIG";
112 case MLX5_EVENT_TYPE_COMM_EST:
113 return "MLX5_EVENT_TYPE_COMM_EST";
114 case MLX5_EVENT_TYPE_SQ_DRAINED:
115 return "MLX5_EVENT_TYPE_SQ_DRAINED";
116 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
117 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
118 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
119 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
120 case MLX5_EVENT_TYPE_CQ_ERROR:
121 return "MLX5_EVENT_TYPE_CQ_ERROR";
122 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
123 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
124 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
125 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
126 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
127 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
128 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
129 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
130 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
131 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
132 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
133 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
134 case MLX5_EVENT_TYPE_PORT_CHANGE:
135 return "MLX5_EVENT_TYPE_PORT_CHANGE";
136 case MLX5_EVENT_TYPE_GPIO_EVENT:
137 return "MLX5_EVENT_TYPE_GPIO_EVENT";
138 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
139 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
140 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
141 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
142 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
143 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
144 case MLX5_EVENT_TYPE_STALL_EVENT:
145 return "MLX5_EVENT_TYPE_STALL_EVENT";
146 case MLX5_EVENT_TYPE_CMD:
147 return "MLX5_EVENT_TYPE_CMD";
148 case MLX5_EVENT_TYPE_PAGE_REQUEST:
149 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
150 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
151 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
153 return "Unrecognized event";
157 static enum mlx5_dev_event port_subtype_event(u8 subtype)
160 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
161 return MLX5_DEV_EVENT_PORT_DOWN;
162 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
163 return MLX5_DEV_EVENT_PORT_UP;
164 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
165 return MLX5_DEV_EVENT_PORT_INITIALIZED;
166 case MLX5_PORT_CHANGE_SUBTYPE_LID:
167 return MLX5_DEV_EVENT_LID_CHANGE;
168 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
169 return MLX5_DEV_EVENT_PKEY_CHANGE;
170 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
171 return MLX5_DEV_EVENT_GUID_CHANGE;
172 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
173 return MLX5_DEV_EVENT_CLIENT_REREG;
178 static void eq_update_ci(struct mlx5_eq *eq, int arm)
180 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
181 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
182 __raw_writel((__force u32) cpu_to_be32(val), addr);
183 /* We still want ordering, just not swabbing, so add a barrier */
187 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
189 struct mlx5_eqe *eqe;
196 while ((eqe = next_eqe_sw(eq))) {
198 * Make sure we read EQ entry contents after we've
199 * checked the ownership bit.
203 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
204 eq->eqn, eqe_type_str(eqe->type));
206 case MLX5_EVENT_TYPE_COMP:
207 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
208 mlx5_cq_completion(dev, cqn);
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 case MLX5_EVENT_TYPE_COMM_EST:
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
215 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
216 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
217 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
219 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
220 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
221 eqe_type_str(eqe->type), eqe->type, rsn);
222 mlx5_rsc_event(dev, rsn, eqe->type);
225 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
226 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
227 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
228 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
229 eqe_type_str(eqe->type), eqe->type, rsn);
230 mlx5_srq_event(dev, rsn, eqe->type);
233 case MLX5_EVENT_TYPE_CMD:
234 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
237 case MLX5_EVENT_TYPE_PORT_CHANGE:
238 port = (eqe->data.port.port >> 4) & 0xf;
239 switch (eqe->sub_type) {
240 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
241 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
242 case MLX5_PORT_CHANGE_SUBTYPE_LID:
243 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
244 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
245 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
246 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
248 dev->event(dev, port_subtype_event(eqe->sub_type),
249 (unsigned long)port);
252 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
253 port, eqe->sub_type);
256 case MLX5_EVENT_TYPE_CQ_ERROR:
257 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
258 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
259 cqn, eqe->data.cq_err.syndrome);
260 mlx5_cq_event(dev, cqn, eqe->type);
263 case MLX5_EVENT_TYPE_PAGE_REQUEST:
265 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
266 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
268 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
270 mlx5_core_req_pages_handler(dev, func_id, npages);
274 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
275 mlx5_port_module_event(dev, eqe);
278 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
280 struct mlx5_eqe_vport_change *vc_eqe =
281 &eqe->data.vport_change;
282 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
286 MLX5_DEV_EVENT_VPORT_CHANGE,
287 (unsigned long)vport_num);
292 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
301 /* The HCA will think the queue has overflowed if we
302 * don't tell it we've been processing events. We
303 * create our EQs with MLX5_NUM_SPARE_EQE extra
304 * entries, so we must update our consumer index at
307 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
318 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
320 struct mlx5_eq *eq = eq_ptr;
321 struct mlx5_core_dev *dev = eq->dev;
323 mlx5_eq_int(dev, eq);
325 /* MSI-X vectors always belong to us */
329 static void init_eq_buf(struct mlx5_eq *eq)
331 struct mlx5_eqe *eqe;
334 for (i = 0; i < eq->nent; i++) {
335 eqe = get_eqe(eq, i);
336 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
340 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
341 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
343 struct mlx5_priv *priv = &dev->priv;
344 struct mlx5_create_eq_mbox_in *in;
345 struct mlx5_create_eq_mbox_out out;
349 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
350 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
357 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
358 in = mlx5_vzalloc(inlen);
363 memset(&out, 0, sizeof(out));
365 mlx5_fill_page_array(&eq->buf, in->pas);
367 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
368 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
369 in->ctx.intr = vecidx;
370 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
371 in->events_mask = cpu_to_be64(mask);
373 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
377 if (out.hdr.status) {
378 err = mlx5_cmd_status_to_err(&out.hdr);
382 eq->eqn = out.eq_number;
385 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
386 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
387 name, pci_name(dev->pdev));
388 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
389 priv->irq_info[vecidx].name, eq);
394 /* EQs are created in ARMED state
403 mlx5_cmd_destroy_eq(dev, eq->eqn);
409 mlx5_buf_free(dev, &eq->buf);
412 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
414 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
418 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
419 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
421 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
423 mlx5_buf_free(dev, &eq->buf);
427 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
429 int mlx5_eq_init(struct mlx5_core_dev *dev)
433 spin_lock_init(&dev->priv.eq_table.lock);
441 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
445 int mlx5_start_eqs(struct mlx5_core_dev *dev)
447 struct mlx5_eq_table *table = &dev->priv.eq_table;
448 u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
451 if (MLX5_CAP_GEN(dev, port_module_event))
452 async_event_mask |= (1ull <<
453 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
455 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
456 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
457 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
459 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
463 mlx5_cmd_use_events(dev);
465 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
466 MLX5_NUM_ASYNC_EQE, async_event_mask,
467 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
469 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
473 err = mlx5_create_map_eq(dev, &table->pages_eq,
475 /* TODO: sriov max_vf + */ 1,
476 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
477 &dev->priv.uuari.uars[0]);
479 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
486 mlx5_destroy_unmap_eq(dev, &table->async_eq);
489 mlx5_cmd_use_polling(dev);
490 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
494 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
496 struct mlx5_eq_table *table = &dev->priv.eq_table;
499 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
503 mlx5_destroy_unmap_eq(dev, &table->async_eq);
504 mlx5_cmd_use_polling(dev);
506 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
508 mlx5_cmd_use_events(dev);
513 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
514 struct mlx5_query_eq_mbox_out *out, int outlen)
516 struct mlx5_query_eq_mbox_in in;
519 memset(&in, 0, sizeof(in));
520 memset(out, 0, outlen);
521 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
523 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
528 err = mlx5_cmd_status_to_err(&out->hdr);
533 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
535 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
537 switch (error_type) {
538 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
539 return "Power Budget Exceeded";
540 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
541 return "Long Range for non MLNX cable/module";
542 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
543 return "Bus stuck(I2C or data shorted)";
544 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
545 return "No EEPROM/retry timeout";
546 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
547 return "Enforce part number list";
548 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER:
549 return "Unknown identifier";
550 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
551 return "High Temperature";
554 return "Unknown error type";
558 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
559 struct mlx5_eqe *eqe)
561 unsigned int module_num;
562 unsigned int module_status;
563 unsigned int error_type;
564 struct mlx5_eqe_port_module_event *module_event_eqe;
565 struct pci_dev *pdev = dev->pdev;
567 module_event_eqe = &eqe->data.port_module_event;
569 module_num = (unsigned int)module_event_eqe->module;
570 module_status = (unsigned int)module_event_eqe->module_status &
571 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
572 error_type = (unsigned int)module_event_eqe->error_type &
573 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
575 switch (module_status) {
576 case MLX5_MODULE_STATUS_PLUGGED:
577 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged", module_num);
580 case MLX5_MODULE_STATUS_UNPLUGGED:
581 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged", module_num);
584 case MLX5_MODULE_STATUS_ERROR:
585 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s", module_num, mlx5_port_module_event_error_type_to_string(error_type));
589 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status", module_num);