2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
53 #if (__FreeBSD_version >= 1100000)
58 #include <net/rss_config.h>
59 #include <netinet/in_rss.h>
62 #include <machine/bus.h>
68 #include <dev/mlx5/driver.h>
69 #include <dev/mlx5/qp.h>
70 #include <dev/mlx5/cq.h>
71 #include <dev/mlx5/vport.h>
73 #include <dev/mlx5/mlx5_core/wq.h>
74 #include <dev/mlx5/mlx5_core/transobj.h>
75 #include <dev/mlx5/mlx5_core/mlx5_core.h>
77 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
78 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
79 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe
81 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
82 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
83 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe
85 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */
86 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES
87 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
88 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
89 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
90 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
91 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
92 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
93 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
94 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
95 #define MLX5E_HW2SW_MTU(hwmtu) \
96 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
97 #define MLX5E_SW2HW_MTU(swmtu) \
98 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
99 #define MLX5E_SW2MB_MTU(swmtu) \
100 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
101 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
102 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
105 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
106 #define MLX5E_RX_BUDGET_MAX 256
107 #define MLX5E_SQ_BF_BUDGET 16
108 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
110 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
111 #define MLX5E_MAX_TX_HEADER 128 /* bytes */
112 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
113 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
114 #define MLX5E_MAX_TX_MBUF_FRAGS \
115 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
116 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */
117 #define MLX5E_MAX_TX_INLINE \
118 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
119 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
121 MALLOC_DECLARE(M_MLX5EN);
123 struct mlx5_core_dev;
126 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
128 #define MLX5E_STATS_COUNT(a,b,c,d) a
129 #define MLX5E_STATS_VAR(a,b,c,d) b;
130 #define MLX5E_STATS_DESC(a,b,c,d) c, d,
132 #define MLX5E_VPORT_STATS(m) \
134 m(+1, u64 rx_packets, "rx_packets", "Received packets") \
135 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \
136 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \
137 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \
138 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
139 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \
140 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
141 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
142 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
143 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
144 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
145 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
146 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
147 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
148 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
149 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
150 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
151 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
152 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
153 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
154 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
156 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \
157 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
158 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
159 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
160 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
161 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
162 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
163 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
164 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
165 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
166 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
167 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors")
169 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
171 struct mlx5e_vport_stats {
172 struct sysctl_ctx_list ctx;
174 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
175 u32 rx_out_of_buffer_prev;
178 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
179 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \
180 m(+1, u64 frames_rx, "frames_rx", "Frames received") \
181 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \
182 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \
183 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \
184 m(+1, u64 octets_received, "octets_received", "Bytes received") \
185 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
186 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
187 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \
188 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \
189 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
190 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
191 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \
192 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \
193 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
194 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \
195 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
196 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
197 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
199 #define MLX5E_PPORT_RFC2819_STATS(m) \
200 m(+1, u64 drop_events, "drop_events", "Dropped events") \
201 m(+1, u64 octets, "octets", "Octets") \
202 m(+1, u64 pkts, "pkts", "Packets") \
203 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
204 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \
205 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
206 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \
207 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \
208 m(+1, u64 fragments, "fragments", "Fragments") \
209 m(+1, u64 jabbers, "jabbers", "Jabbers") \
210 m(+1, u64 collisions, "collisions", "Collisions")
212 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
213 m(+1, u64 p64octets, "p64octets", "Bytes") \
214 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \
215 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \
216 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \
217 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \
218 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \
219 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \
220 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \
221 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \
222 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
224 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
225 m(+1, u64 in_octets, "in_octets", "In octets") \
226 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
227 m(+1, u64 in_discards, "in_discards", "In discards") \
228 m(+1, u64 in_errors, "in_errors", "In errors") \
229 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
230 m(+1, u64 out_octets, "out_octets", "Out octets") \
231 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
232 m(+1, u64 out_discards, "out_discards", "Out discards") \
233 m(+1, u64 out_errors, "out_errors", "Out errors") \
234 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
235 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
236 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
237 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
239 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
240 m(+1, u64 time_since_last_clear, "time_since_last_clear", \
241 "Time since the last counters clear event (msec)") \
242 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \
243 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \
244 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \
245 "Indicates the number of PRBS errors on lane 0") \
246 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \
247 "Indicates the number of PRBS errors on lane 1") \
248 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \
249 "Indicates the number of PRBS errors on lane 2") \
250 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \
251 "Indicates the number of PRBS errors on lane 3") \
252 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
253 "FEC correctable block counter lane 0") \
254 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
255 "FEC correctable block counter lane 1") \
256 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
257 "FEC correctable block counter lane 2") \
258 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
259 "FEC correctable block counter lane 3") \
260 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \
261 "FEC correcable block counter") \
262 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
263 "FEC uncorrecable block counter") \
264 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \
265 "The number of RS-FEC blocks received that had no errors") \
266 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \
267 "The number of corrected RS-FEC blocks received that had" \
268 "exactly 1 error symbol") \
269 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \
270 "Port FEC corrected symbol counter") \
271 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
272 "FEC corrected symbol counter lane 0") \
273 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
274 "FEC corrected symbol counter lane 1") \
275 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
276 "FEC corrected symbol counter lane 2") \
277 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
278 "FEC corrected symbol counter lane 3") \
281 * Make sure to update mlx5e_update_pport_counters()
282 * when adding a new MLX5E_PPORT_STATS block
284 #define MLX5E_PPORT_STATS(m) \
285 MLX5E_PPORT_IEEE802_3_STATS(m) \
286 MLX5E_PPORT_RFC2819_STATS(m)
288 #define MLX5E_PORT_STATS_DEBUG(m) \
289 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
290 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
291 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
293 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
294 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
295 #define MLX5E_PPORT_RFC2819_STATS_NUM \
296 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
297 #define MLX5E_PPORT_STATS_NUM \
298 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
300 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
301 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
302 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
303 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
304 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
305 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
306 #define MLX5E_PORT_STATS_DEBUG_NUM \
307 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
309 struct mlx5e_pport_stats {
310 struct sysctl_ctx_list ctx;
312 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
315 struct mlx5e_port_stats_debug {
316 struct sysctl_ctx_list ctx;
318 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
321 #define MLX5E_RQ_STATS(m) \
322 m(+1, u64 packets, "packets", "Received packets") \
323 m(+1, u64 csum_none, "csum_none", "Received packets") \
324 m(+1, u64 lro_packets, "lro_packets", "Received packets") \
325 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \
326 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
327 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
328 m(+1, u64 wqe_err, "wqe_err", "Received packets")
330 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
332 struct mlx5e_rq_stats {
333 struct sysctl_ctx_list ctx;
335 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
338 #define MLX5E_SQ_STATS(m) \
339 m(+1, u64 packets, "packets", "Transmitted packets") \
340 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \
341 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \
342 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \
343 m(+1, u64 defragged, "defragged", "Transmitted packets") \
344 m(+1, u64 dropped, "dropped", "Transmitted packets") \
345 m(+1, u64 nop, "nop", "Transmitted packets")
347 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
349 struct mlx5e_sq_stats {
350 struct sysctl_ctx_list ctx;
352 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
356 struct mlx5e_vport_stats vport;
357 struct mlx5e_pport_stats pport;
358 struct mlx5e_port_stats_debug port_stats_debug;
361 struct mlx5e_params {
365 u8 default_vlan_prio;
367 u8 rx_cq_moderation_mode;
368 u8 tx_cq_moderation_mode;
369 u16 rx_cq_moderation_usec;
370 u16 rx_cq_moderation_pkts;
371 u16 tx_cq_moderation_usec;
372 u16 tx_cq_moderation_pkts;
377 u16 rx_hash_log_tbl_sz;
378 u32 tx_pauseframe_control;
379 u32 rx_pauseframe_control;
382 #define MLX5E_PARAMS(m) \
383 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
384 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
385 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \
386 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
387 m(+1, u64 channels, "channels", "Default number of channels") \
388 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
389 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
390 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
391 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
392 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
393 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
394 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
395 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
396 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
397 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
398 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
399 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled")
401 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
403 struct mlx5e_params_ethtool {
405 MLX5E_PARAMS(MLX5E_STATS_VAR)
408 /* EEPROM Standards for plug in modules */
409 #ifndef MLX5E_ETH_MODULE_SFF_8472
410 #define MLX5E_ETH_MODULE_SFF_8472 0x1
411 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128
414 #ifndef MLX5E_ETH_MODULE_SFF_8636
415 #define MLX5E_ETH_MODULE_SFF_8636 0x2
416 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256
419 #ifndef MLX5E_ETH_MODULE_SFF_8436
420 #define MLX5E_ETH_MODULE_SFF_8436 0x3
421 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256
424 /* EEPROM I2C Addresses */
425 #define MLX5E_I2C_ADDR_LOW 0x50
426 #define MLX5E_I2C_ADDR_HIGH 0x51
428 #define MLX5E_EEPROM_LOW_PAGE 0x0
429 #define MLX5E_EEPROM_HIGH_PAGE 0x3
431 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128
432 #define MLX5E_EEPROM_PAGE_LENGTH 256
434 #define MLX5E_EEPROM_INFO_BYTES 0x3
437 /* data path - accessed per cqe */
440 /* data path - accessed per HW polling */
441 struct mlx5_core_cq mcq;
442 struct mlx5e_channel *channel;
445 struct mlx5_wq_ctrl wq_ctrl;
446 } __aligned(MLX5E_CACHELINE_SIZE);
448 struct mlx5e_rq_mbuf {
449 bus_dmamap_t dma_map;
456 struct mlx5_wq_ll wq;
458 bus_dma_tag_t dma_tag;
460 struct mlx5e_rq_mbuf *mbuf;
463 struct mlx5e_rq_stats stats;
465 #ifdef HAVE_TURBO_LRO
466 struct tlro_ctrl lro;
470 volatile int enabled;
474 struct mlx5_wq_ctrl wq_ctrl;
476 struct mlx5e_channel *channel;
477 } __aligned(MLX5E_CACHELINE_SIZE);
479 struct mlx5e_sq_mbuf {
480 bus_dmamap_t dma_map;
494 bus_dma_tag_t dma_tag;
495 struct mtx comp_lock;
497 /* dirtied @completion */
501 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
503 u16 cev_counter; /* completion event counter */
504 u16 cev_factor; /* completion event factor */
505 u32 cev_next_state; /* next completion event state */
506 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
507 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
508 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
509 struct callout cev_callout;
514 struct mlx5e_sq_stats stats;
518 struct taskqueue *sq_tq;
520 /* pointers to per packet info: write@xmit, read@completion */
521 struct mlx5e_sq_mbuf *mbuf;
525 struct mlx5_wq_cyc wq;
526 void __iomem *uar_map;
527 void __iomem *uar_bf_map;
534 struct mlx5_wq_ctrl wq_ctrl;
536 struct mlx5e_channel *channel;
538 unsigned int queue_state;
539 } __aligned(MLX5E_CACHELINE_SIZE);
542 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
544 return ((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n ||
548 struct mlx5e_channel {
551 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
558 struct mlx5e_priv *priv;
561 } __aligned(MLX5E_CACHELINE_SIZE);
563 enum mlx5e_traffic_types {
568 MLX5E_TT_IPV4_IPSEC_AH,
569 MLX5E_TT_IPV6_IPSEC_AH,
570 MLX5E_TT_IPV4_IPSEC_ESP,
571 MLX5E_TT_IPV6_IPSEC_ESP,
579 MLX5E_RQT_SPREADING = 0,
580 MLX5E_RQT_DEFAULT_RQ = 1,
584 struct mlx5e_eth_addr_info {
585 u8 addr [ETH_ALEN + 2];
587 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */
590 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
592 struct mlx5e_eth_addr_hash_node;
594 struct mlx5e_eth_addr_hash_head {
595 struct mlx5e_eth_addr_hash_node *lh_first;
598 struct mlx5e_eth_addr_db {
599 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
600 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
601 struct mlx5e_eth_addr_info broadcast;
602 struct mlx5e_eth_addr_info allmulti;
603 struct mlx5e_eth_addr_info promisc;
604 bool broadcast_enabled;
605 bool allmulti_enabled;
606 bool promisc_enabled;
610 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
614 struct mlx5e_vlan_db {
615 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
616 u32 active_vlans_ft_ix[VLAN_N_VID];
617 u32 untagged_rule_ft_ix;
618 u32 any_vlan_rule_ft_ix;
619 bool filter_disabled;
622 struct mlx5e_flow_table {
628 /* priv data path fields - start */
629 int order_base_2_num_channels;
630 int queue_mapping_channel_mask;
632 int default_vlan_prio;
633 /* priv data path fields - end */
637 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
638 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
639 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
640 struct sx state_lock; /* Protects Interface state */
641 struct mlx5_uar cq_uar;
644 struct mlx5_core_mr mr;
646 struct mlx5e_channel *volatile *channel;
647 u32 tisn[MLX5E_MAX_TX_NUM_TC];
649 u32 tirn[MLX5E_NUM_TT];
651 struct mlx5e_flow_table ft;
652 struct mlx5e_eth_addr_db eth_addr;
653 struct mlx5e_vlan_db vlan;
655 struct mlx5e_params params;
656 struct mlx5e_params_ethtool params_ethtool;
657 struct mtx async_events_mtx; /* sync hw events */
658 struct work_struct update_stats_work;
659 struct work_struct update_carrier_work;
660 struct work_struct set_rx_mode_work;
662 struct mlx5_core_dev *mdev;
664 struct sysctl_ctx_list sysctl_ctx;
665 struct sysctl_oid *sysctl_ifnet;
666 struct sysctl_oid *sysctl_hw;
668 struct mlx5e_stats stats;
671 eventhandler_tag vlan_detach;
672 eventhandler_tag vlan_attach;
673 struct ifmedia media;
674 int media_status_last;
675 int media_active_last;
677 struct callout watchdog;
680 #define MLX5E_NET_IP_ALIGN 2
682 struct mlx5e_tx_wqe {
683 struct mlx5_wqe_ctrl_seg ctrl;
684 struct mlx5_wqe_eth_seg eth;
687 struct mlx5e_rx_wqe {
688 struct mlx5_wqe_srq_next_seg next;
689 struct mlx5_wqe_data_seg data;
692 struct mlx5e_eeprom {
704 enum mlx5e_link_mode {
705 MLX5E_1000BASE_CX_SGMII = 0,
706 MLX5E_1000BASE_KX = 1,
707 MLX5E_10GBASE_CX4 = 2,
708 MLX5E_10GBASE_KX4 = 3,
709 MLX5E_10GBASE_KR = 4,
710 MLX5E_20GBASE_KR2 = 5,
711 MLX5E_40GBASE_CR4 = 6,
712 MLX5E_40GBASE_KR4 = 7,
713 MLX5E_56GBASE_R4 = 8,
714 MLX5E_10GBASE_CR = 12,
715 MLX5E_10GBASE_SR = 13,
716 MLX5E_10GBASE_LR = 14,
717 MLX5E_40GBASE_SR4 = 15,
718 MLX5E_40GBASE_LR4 = 16,
719 MLX5E_100GBASE_CR4 = 20,
720 MLX5E_100GBASE_SR4 = 21,
721 MLX5E_100GBASE_KR4 = 22,
722 MLX5E_100GBASE_LR4 = 23,
723 MLX5E_100BASE_TX = 24,
724 MLX5E_100BASE_T = 25,
725 MLX5E_10GBASE_T = 26,
726 MLX5E_25GBASE_CR = 27,
727 MLX5E_25GBASE_KR = 28,
728 MLX5E_25GBASE_SR = 29,
729 MLX5E_50GBASE_CR2 = 30,
730 MLX5E_50GBASE_KR2 = 31,
731 MLX5E_LINK_MODES_NUMBER,
734 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
735 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
737 int mlx5e_xmit(struct ifnet *, struct mbuf *);
739 int mlx5e_open_locked(struct ifnet *);
740 int mlx5e_close_locked(struct ifnet *);
742 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
743 void mlx5e_rx_cq_comp(struct mlx5_core_cq *);
744 void mlx5e_tx_cq_comp(struct mlx5_core_cq *);
745 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
746 void mlx5e_tx_que(void *context, int pending);
748 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
749 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
750 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
751 void mlx5e_set_rx_mode_work(struct work_struct *work);
753 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
754 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
755 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
756 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
757 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
758 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
761 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
763 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
765 /* ensure wqe is visible to device before updating doorbell record */
768 *sq->wq.db = cpu_to_be32(sq->pc);
771 * Ensure the doorbell record is visible to device before ringing
777 __iowrite64_copy(sq->uar_bf_map + ofst, wqe, bf_sz);
779 /* flush the write-combining mapped buffer */
783 mlx5_write64(wqe, sq->uar_map + ofst, NULL);
786 sq->bf_offset ^= sq->bf_buf_size;
790 mlx5e_cq_arm(struct mlx5e_cq *cq)
792 struct mlx5_core_cq *mcq;
795 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
798 extern const struct ethtool_ops mlx5e_ethtool_ops;
799 void mlx5e_create_ethtool(struct mlx5e_priv *);
800 void mlx5e_create_stats(struct sysctl_ctx_list *,
801 struct sysctl_oid_list *, const char *,
802 const char **, unsigned, u64 *);
803 void mlx5e_send_nop(struct mlx5e_sq *, u32);
804 void mlx5e_sq_cev_timeout(void *);
805 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
807 #endif /* _MLX5_EN_H_ */