sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 static void
 310 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 311 {
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         struct mlx5e_pport_stats *s = &priv->stats.pport;
 314         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 315         u32 *in;
 316         u32 *out;
 317         u64 *ptr;
 318         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 319         unsigned x;
 320         unsigned y;
 321
 322         in = mlx5_vzalloc(sz);
 323         out = mlx5_vzalloc(sz);
 324         if (in == NULL || out == NULL)
 325                 goto free_out;
 326
 327         ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 328
 329         MLX5_SET(ppcnt_reg, in, local_port, 1);
 330
 331         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 332         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 333         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 334                 s->arg[y] = be64toh(ptr[x]);
 335
 336         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 337         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 338         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 339                 s->arg[y] = be64toh(ptr[x]);
 340         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 341             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 342                 s_debug->arg[y] = be64toh(ptr[x]);
 343
 344         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 345         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 346         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 347                 s_debug->arg[y] = be64toh(ptr[x]);
 348
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 352                 s_debug->arg[y] = be64toh(ptr[x]);
 353 free_out:
 354         kvfree(in);
 355         kvfree(out);
 356 }
 357
 358 static void
 359 mlx5e_update_stats_work(struct work_struct *work)
 360 {
 361         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 362             update_stats_work);
 363         struct mlx5_core_dev *mdev = priv->mdev;
 364         struct mlx5e_vport_stats *s = &priv->stats.vport;
 365         struct mlx5e_rq_stats *rq_stats;
 366         struct mlx5e_sq_stats *sq_stats;
 367         struct buf_ring *sq_br;
 368 #if (__FreeBSD_version < 1100000)
 369         struct ifnet *ifp = priv->ifp;
 370 #endif
 371
 372         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 373         u32 *out;
 374         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 375         u64 tso_packets = 0;
 376         u64 tso_bytes = 0;
 377         u64 tx_queue_dropped = 0;
 378         u64 tx_defragged = 0;
 379         u64 tx_offload_none = 0;
 380         u64 lro_packets = 0;
 381         u64 lro_bytes = 0;
 382         u64 sw_lro_queued = 0;
 383         u64 sw_lro_flushed = 0;
 384         u64 rx_csum_none = 0;
 385         u64 rx_wqe_err = 0;
 386         u32 rx_out_of_buffer = 0;
 387         int i;
 388         int j;
 389
 390         PRIV_LOCK(priv);
 391         out = mlx5_vzalloc(outlen);
 392         if (out == NULL)
 393                 goto free_out;
 394         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 395                 goto free_out;
 396
 397         /* Collect firts the SW counters and then HW for consistency */
 398         for (i = 0; i < priv->params.num_channels; i++) {
 399                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 400
 401                 rq_stats = &priv->channel[i]->rq.stats;
 402
 403                 /* collect stats from LRO */
 404                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 405                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 406                 sw_lro_queued += rq_stats->sw_lro_queued;
 407                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 408                 lro_packets += rq_stats->lro_packets;
 409                 lro_bytes += rq_stats->lro_bytes;
 410                 rx_csum_none += rq_stats->csum_none;
 411                 rx_wqe_err += rq_stats->wqe_err;
 412
 413                 for (j = 0; j < priv->num_tc; j++) {
 414                         sq_stats = &priv->channel[i]->sq[j].stats;
 415                         sq_br = priv->channel[i]->sq[j].br;
 416
 417                         tso_packets += sq_stats->tso_packets;
 418                         tso_bytes += sq_stats->tso_bytes;
 419                         tx_queue_dropped += sq_stats->dropped;
 420                         tx_queue_dropped += sq_br->br_drops;
 421                         tx_defragged += sq_stats->defragged;
 422                         tx_offload_none += sq_stats->csum_offload_none;
 423                 }
 424         }
 425
 426         /* update counters */
 427         s->tso_packets = tso_packets;
 428         s->tso_bytes = tso_bytes;
 429         s->tx_queue_dropped = tx_queue_dropped;
 430         s->tx_defragged = tx_defragged;
 431         s->lro_packets = lro_packets;
 432         s->lro_bytes = lro_bytes;
 433         s->sw_lro_queued = sw_lro_queued;
 434         s->sw_lro_flushed = sw_lro_flushed;
 435         s->rx_csum_none = rx_csum_none;
 436         s->rx_wqe_err = rx_wqe_err;
 437
 438         /* HW counters */
 439         memset(in, 0, sizeof(in));
 440
 441         MLX5_SET(query_vport_counter_in, in, opcode,
 442             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 443         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 444         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 445
 446         memset(out, 0, outlen);
 447
 448         /* get number of out-of-buffer drops first */
 449         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 450             &rx_out_of_buffer))
 451                 goto free_out;
 452
 453         /* accumulate difference into a 64-bit counter */
 454         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 455         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 456
 457         /* get port statistics */
 458         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 459                 goto free_out;
 460
 461 #define MLX5_GET_CTR(out, x) \
 462         MLX5_GET64(query_vport_counter_out, out, x)
 463
 464         s->rx_error_packets =
 465             MLX5_GET_CTR(out, received_errors.packets);
 466         s->rx_error_bytes =
 467             MLX5_GET_CTR(out, received_errors.octets);
 468         s->tx_error_packets =
 469             MLX5_GET_CTR(out, transmit_errors.packets);
 470         s->tx_error_bytes =
 471             MLX5_GET_CTR(out, transmit_errors.octets);
 472
 473         s->rx_unicast_packets =
 474             MLX5_GET_CTR(out, received_eth_unicast.packets);
 475         s->rx_unicast_bytes =
 476             MLX5_GET_CTR(out, received_eth_unicast.octets);
 477         s->tx_unicast_packets =
 478             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 479         s->tx_unicast_bytes =
 480             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 481
 482         s->rx_multicast_packets =
 483             MLX5_GET_CTR(out, received_eth_multicast.packets);
 484         s->rx_multicast_bytes =
 485             MLX5_GET_CTR(out, received_eth_multicast.octets);
 486         s->tx_multicast_packets =
 487             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 488         s->tx_multicast_bytes =
 489             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 490
 491         s->rx_broadcast_packets =
 492             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 493         s->rx_broadcast_bytes =
 494             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 495         s->tx_broadcast_packets =
 496             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 497         s->tx_broadcast_bytes =
 498             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 499
 500         s->rx_packets =
 501             s->rx_unicast_packets +
 502             s->rx_multicast_packets +
 503             s->rx_broadcast_packets -
 504             s->rx_out_of_buffer;
 505         s->rx_bytes =
 506             s->rx_unicast_bytes +
 507             s->rx_multicast_bytes +
 508             s->rx_broadcast_bytes;
 509         s->tx_packets =
 510             s->tx_unicast_packets +
 511             s->tx_multicast_packets +
 512             s->tx_broadcast_packets;
 513         s->tx_bytes =
 514             s->tx_unicast_bytes +
 515             s->tx_multicast_bytes +
 516             s->tx_broadcast_bytes;
 517
 518         /* Update calculated offload counters */
 519         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 520         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 521
 522         /* Update per port counters */
 523         mlx5e_update_pport_counters(priv);
 524
 525 #if (__FreeBSD_version < 1100000)
 526         /* no get_counters interface in fbsd 10 */
 527         ifp->if_ipackets = s->rx_packets;
 528         ifp->if_ierrors = s->rx_error_packets;
 529         ifp->if_iqdrops = s->rx_out_of_buffer;
 530         ifp->if_opackets = s->tx_packets;
 531         ifp->if_oerrors = s->tx_error_packets;
 532         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 533         ifp->if_ibytes = s->rx_bytes;
 534         ifp->if_obytes = s->tx_bytes;
 535 #endif
 536
 537 free_out:
 538         kvfree(out);
 539         PRIV_UNLOCK(priv);
 540 }
 541
 542 static void
 543 mlx5e_update_stats(void *arg)
 544 {
 545         struct mlx5e_priv *priv = arg;
 546
 547         schedule_work(&priv->update_stats_work);
 548
 549         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 550 }
 551
 552 static void
 553 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 554     enum mlx5_dev_event event)
 555 {
 556         switch (event) {
 557         case MLX5_DEV_EVENT_PORT_UP:
 558         case MLX5_DEV_EVENT_PORT_DOWN:
 559                 schedule_work(&priv->update_carrier_work);
 560                 break;
 561
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 static void
 568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 569     enum mlx5_dev_event event, unsigned long param)
 570 {
 571         struct mlx5e_priv *priv = vpriv;
 572
 573         mtx_lock(&priv->async_events_mtx);
 574         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 575                 mlx5e_async_event_sub(priv, event);
 576         mtx_unlock(&priv->async_events_mtx);
 577 }
 578
 579 static void
 580 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 581 {
 582         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 583 }
 584
 585 static void
 586 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 587 {
 588         mtx_lock(&priv->async_events_mtx);
 589         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 590         mtx_unlock(&priv->async_events_mtx);
 591 }
 592
 593 static const char *mlx5e_rq_stats_desc[] = {
 594         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 595 };
 596
 597 static int
 598 mlx5e_create_rq(struct mlx5e_channel *c,
 599     struct mlx5e_rq_param *param,
 600     struct mlx5e_rq *rq)
 601 {
 602         struct mlx5e_priv *priv = c->priv;
 603         struct mlx5_core_dev *mdev = priv->mdev;
 604         char buffer[16];
 605         void *rqc = param->rqc;
 606         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 607         int wq_sz;
 608         int err;
 609         int i;
 610
 611         /* Create DMA descriptor TAG */
 612         if ((err = -bus_dma_tag_create(
 613             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 614             1,                          /* any alignment */
 615             0,                          /* no boundary */
 616             BUS_SPACE_MAXADDR,          /* lowaddr */
 617             BUS_SPACE_MAXADDR,          /* highaddr */
 618             NULL, NULL,                 /* filter, filterarg */
 619             MJUM16BYTES,                /* maxsize */
 620             1,                          /* nsegments */
 621             MJUM16BYTES,                /* maxsegsize */
 622             0,                          /* flags */
 623             NULL, NULL,                 /* lockfunc, lockfuncarg */
 624             &rq->dma_tag)))
 625                 goto done;
 626
 627         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 628             &rq->wq_ctrl);
 629         if (err)
 630                 goto err_free_dma_tag;
 631
 632         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 633
 634         if (priv->params.hw_lro_en) {
 635                 rq->wqe_sz = priv->params.lro_wqe_sz;
 636         } else {
 637                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 638         }
 639         if (rq->wqe_sz > MJUM16BYTES) {
 640                 err = -ENOMEM;
 641                 goto err_rq_wq_destroy;
 642         } else if (rq->wqe_sz > MJUM9BYTES) {
 643                 rq->wqe_sz = MJUM16BYTES;
 644         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 645                 rq->wqe_sz = MJUM9BYTES;
 646         } else if (rq->wqe_sz > MCLBYTES) {
 647                 rq->wqe_sz = MJUMPAGESIZE;
 648         } else {
 649                 rq->wqe_sz = MCLBYTES;
 650         }
 651
 652         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 653         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 654         if (rq->mbuf == NULL) {
 655                 err = -ENOMEM;
 656                 goto err_rq_wq_destroy;
 657         }
 658         for (i = 0; i != wq_sz; i++) {
 659                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 660                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 661
 662                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 663                 if (err != 0) {
 664                         while (i--)
 665                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 666                         goto err_rq_mbuf_free;
 667                 }
 668                 wqe->data.lkey = c->mkey_be;
 669                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 670         }
 671
 672         rq->ifp = c->ifp;
 673         rq->channel = c;
 674         rq->ix = c->ix;
 675
 676         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 677         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 678             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 679             rq->stats.arg);
 680
 681 #ifdef HAVE_TURBO_LRO
 682         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 683                 rq->lro.mbuf = NULL;
 684 #else
 685         if (tcp_lro_init(&rq->lro))
 686                 rq->lro.lro_cnt = 0;
 687         else
 688                 rq->lro.ifp = c->ifp;
 689 #endif
 690         return (0);
 691
 692 err_rq_mbuf_free:
 693         free(rq->mbuf, M_MLX5EN);
 694 err_rq_wq_destroy:
 695         mlx5_wq_destroy(&rq->wq_ctrl);
 696 err_free_dma_tag:
 697         bus_dma_tag_destroy(rq->dma_tag);
 698 done:
 699         return (err);
 700 }
 701
 702 static void
 703 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 704 {
 705         int wq_sz;
 706         int i;
 707
 708         /* destroy all sysctl nodes */
 709         sysctl_ctx_free(&rq->stats.ctx);
 710
 711         /* free leftover LRO packets, if any */
 712 #ifdef HAVE_TURBO_LRO
 713         tcp_tlro_free(&rq->lro);
 714 #else
 715         tcp_lro_free(&rq->lro);
 716 #endif
 717         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 718         for (i = 0; i != wq_sz; i++) {
 719                 if (rq->mbuf[i].mbuf != NULL) {
 720                         bus_dmamap_unload(rq->dma_tag,
 721                             rq->mbuf[i].dma_map);
 722                         m_freem(rq->mbuf[i].mbuf);
 723                 }
 724                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 725         }
 726         free(rq->mbuf, M_MLX5EN);
 727         mlx5_wq_destroy(&rq->wq_ctrl);
 728 }
 729
 730 static int
 731 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 732 {
 733         struct mlx5e_channel *c = rq->channel;
 734         struct mlx5e_priv *priv = c->priv;
 735         struct mlx5_core_dev *mdev = priv->mdev;
 736
 737         void *in;
 738         void *rqc;
 739         void *wq;
 740         int inlen;
 741         int err;
 742
 743         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 744             sizeof(u64) * rq->wq_ctrl.buf.npages;
 745         in = mlx5_vzalloc(inlen);
 746         if (in == NULL)
 747                 return (-ENOMEM);
 748
 749         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 750         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 751
 752         memcpy(rqc, param->rqc, sizeof(param->rqc));
 753
 754         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 755         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 756         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 757         if (priv->counter_set_id >= 0)
 758                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 759         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 760             PAGE_SHIFT);
 761         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 762
 763         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 764             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 765
 766         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 767
 768         kvfree(in);
 769
 770         return (err);
 771 }
 772
 773 static int
 774 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 775 {
 776         struct mlx5e_channel *c = rq->channel;
 777         struct mlx5e_priv *priv = c->priv;
 778         struct mlx5_core_dev *mdev = priv->mdev;
 779
 780         void *in;
 781         void *rqc;
 782         int inlen;
 783         int err;
 784
 785         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 786         in = mlx5_vzalloc(inlen);
 787         if (in == NULL)
 788                 return (-ENOMEM);
 789
 790         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 791
 792         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 793         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 794         MLX5_SET(rqc, rqc, state, next_state);
 795
 796         err = mlx5_core_modify_rq(mdev, in, inlen);
 797
 798         kvfree(in);
 799
 800         return (err);
 801 }
 802
 803 static void
 804 mlx5e_disable_rq(struct mlx5e_rq *rq)
 805 {
 806         struct mlx5e_channel *c = rq->channel;
 807         struct mlx5e_priv *priv = c->priv;
 808         struct mlx5_core_dev *mdev = priv->mdev;
 809
 810         mlx5_core_destroy_rq(mdev, rq->rqn);
 811 }
 812
 813 static int
 814 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 815 {
 816         struct mlx5e_channel *c = rq->channel;
 817         struct mlx5e_priv *priv = c->priv;
 818         struct mlx5_wq_ll *wq = &rq->wq;
 819         int i;
 820
 821         for (i = 0; i < 1000; i++) {
 822                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 823                         return (0);
 824
 825                 msleep(4);
 826         }
 827         return (-ETIMEDOUT);
 828 }
 829
 830 static int
 831 mlx5e_open_rq(struct mlx5e_channel *c,
 832     struct mlx5e_rq_param *param,
 833     struct mlx5e_rq *rq)
 834 {
 835         int err;
 836
 837         err = mlx5e_create_rq(c, param, rq);
 838         if (err)
 839                 return (err);
 840
 841         err = mlx5e_enable_rq(rq, param);
 842         if (err)
 843                 goto err_destroy_rq;
 844
 845         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 846         if (err)
 847                 goto err_disable_rq;
 848
 849         c->rq.enabled = 1;
 850
 851         return (0);
 852
 853 err_disable_rq:
 854         mlx5e_disable_rq(rq);
 855 err_destroy_rq:
 856         mlx5e_destroy_rq(rq);
 857
 858         return (err);
 859 }
 860
 861 static void
 862 mlx5e_close_rq(struct mlx5e_rq *rq)
 863 {
 864         mtx_lock(&rq->mtx);
 865         rq->enabled = 0;
 866         callout_stop(&rq->watchdog);
 867         mtx_unlock(&rq->mtx);
 868
 869         callout_drain(&rq->watchdog);
 870
 871         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 872 }
 873
 874 static void
 875 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 876 {
 877         /* wait till RQ is empty */
 878         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 879                 msleep(4);
 880                 rq->cq.mcq.comp(&rq->cq.mcq);
 881         }
 882
 883         mlx5e_disable_rq(rq);
 884         mlx5e_destroy_rq(rq);
 885 }
 886
 887 void
 888 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 889 {
 890         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 891         int x;
 892
 893         for (x = 0; x != wq_sz; x++)
 894                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 895         free(sq->mbuf, M_MLX5EN);
 896 }
 897
 898 int
 899 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 900 {
 901         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 902         int err;
 903         int x;
 904
 905         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 906         if (sq->mbuf == NULL)
 907                 return (-ENOMEM);
 908
 909         /* Create DMA descriptor MAPs */
 910         for (x = 0; x != wq_sz; x++) {
 911                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 912                 if (err != 0) {
 913                         while (x--)
 914                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 915                         free(sq->mbuf, M_MLX5EN);
 916                         return (err);
 917                 }
 918         }
 919         return (0);
 920 }
 921
 922 static const char *mlx5e_sq_stats_desc[] = {
 923         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 924 };
 925
 926 static int
 927 mlx5e_create_sq(struct mlx5e_channel *c,
 928     int tc,
 929     struct mlx5e_sq_param *param,
 930     struct mlx5e_sq *sq)
 931 {
 932         struct mlx5e_priv *priv = c->priv;
 933         struct mlx5_core_dev *mdev = priv->mdev;
 934         char buffer[16];
 935
 936         void *sqc = param->sqc;
 937         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 938 #ifdef RSS
 939         cpuset_t cpu_mask;
 940         int cpu_id;
 941 #endif
 942         int err;
 943
 944         /* Create DMA descriptor TAG */
 945         if ((err = -bus_dma_tag_create(
 946             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 947             1,                          /* any alignment */
 948             0,                          /* no boundary */
 949             BUS_SPACE_MAXADDR,          /* lowaddr */
 950             BUS_SPACE_MAXADDR,          /* highaddr */
 951             NULL, NULL,                 /* filter, filterarg */
 952             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 953             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 954             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 955             0,                          /* flags */
 956             NULL, NULL,                 /* lockfunc, lockfuncarg */
 957             &sq->dma_tag)))
 958                 goto done;
 959
 960         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 961         if (err)
 962                 goto err_free_dma_tag;
 963
 964         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 965             &sq->wq_ctrl);
 966         if (err)
 967                 goto err_unmap_free_uar;
 968
 969         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 970         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 971
 972         err = mlx5e_alloc_sq_db(sq);
 973         if (err)
 974                 goto err_sq_wq_destroy;
 975
 976         sq->mkey_be = c->mkey_be;
 977         sq->ifp = priv->ifp;
 978         sq->priv = priv;
 979         sq->tc = tc;
 980
 981         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
 982             M_WAITOK, &sq->lock);
 983         if (sq->br == NULL) {
 984                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
 985                     __func__);
 986                 err = -ENOMEM;
 987                 goto err_free_sq_db;
 988         }
 989
 990         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
 991             taskqueue_thread_enqueue, &sq->sq_tq);
 992         if (sq->sq_tq == NULL) {
 993                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
 994                     __func__);
 995                 err = -ENOMEM;
 996                 goto err_free_drbr;
 997         }
 998
 999         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1000 #ifdef RSS
1001         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1002         CPU_SETOF(cpu_id, &cpu_mask);
1003         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1004             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1005 #else
1006         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1007             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1008 #endif
1009         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1010         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1011             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1012             sq->stats.arg);
1013
1014         return (0);
1015
1016 err_free_drbr:
1017         buf_ring_free(sq->br, M_MLX5EN);
1018 err_free_sq_db:
1019         mlx5e_free_sq_db(sq);
1020 err_sq_wq_destroy:
1021         mlx5_wq_destroy(&sq->wq_ctrl);
1022
1023 err_unmap_free_uar:
1024         mlx5_unmap_free_uar(mdev, &sq->uar);
1025
1026 err_free_dma_tag:
1027         bus_dma_tag_destroy(sq->dma_tag);
1028 done:
1029         return (err);
1030 }
1031
1032 static void
1033 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1034 {
1035         /* destroy all sysctl nodes */
1036         sysctl_ctx_free(&sq->stats.ctx);
1037
1038         mlx5e_free_sq_db(sq);
1039         mlx5_wq_destroy(&sq->wq_ctrl);
1040         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1041         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1042         taskqueue_free(sq->sq_tq);
1043         buf_ring_free(sq->br, M_MLX5EN);
1044 }
1045
1046 int
1047 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1048     int tis_num)
1049 {
1050         void *in;
1051         void *sqc;
1052         void *wq;
1053         int inlen;
1054         int err;
1055
1056         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1057             sizeof(u64) * sq->wq_ctrl.buf.npages;
1058         in = mlx5_vzalloc(inlen);
1059         if (in == NULL)
1060                 return (-ENOMEM);
1061
1062         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1063         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1064
1065         memcpy(sqc, param->sqc, sizeof(param->sqc));
1066
1067         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1068         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1069         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1070         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1071         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1072
1073         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1074         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1075         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1076             PAGE_SHIFT);
1077         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1078
1079         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1080             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1081
1082         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1083
1084         kvfree(in);
1085
1086         return (err);
1087 }
1088
1089 int
1090 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1091 {
1092         void *in;
1093         void *sqc;
1094         int inlen;
1095         int err;
1096
1097         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1098         in = mlx5_vzalloc(inlen);
1099         if (in == NULL)
1100                 return (-ENOMEM);
1101
1102         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1103
1104         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1105         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1106         MLX5_SET(sqc, sqc, state, next_state);
1107
1108         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1109
1110         kvfree(in);
1111
1112         return (err);
1113 }
1114
1115 void
1116 mlx5e_disable_sq(struct mlx5e_sq *sq)
1117 {
1118
1119         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1120 }
1121
1122 static int
1123 mlx5e_open_sq(struct mlx5e_channel *c,
1124     int tc,
1125     struct mlx5e_sq_param *param,
1126     struct mlx5e_sq *sq)
1127 {
1128         int err;
1129
1130         err = mlx5e_create_sq(c, tc, param, sq);
1131         if (err)
1132                 return (err);
1133
1134         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1135         if (err)
1136                 goto err_destroy_sq;
1137
1138         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1139         if (err)
1140                 goto err_disable_sq;
1141
1142         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1143
1144         return (0);
1145
1146 err_disable_sq:
1147         mlx5e_disable_sq(sq);
1148 err_destroy_sq:
1149         mlx5e_destroy_sq(sq);
1150
1151         return (err);
1152 }
1153
1154 static void
1155 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1156 {
1157         /* fill up remainder with NOPs */
1158         while (sq->cev_counter != 0) {
1159                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1160                         if (can_sleep != 0) {
1161                                 mtx_unlock(&sq->lock);
1162                                 msleep(4);
1163                                 mtx_lock(&sq->lock);
1164                         } else {
1165                                 goto done;
1166                         }
1167                 }
1168                 /* send a single NOP */
1169                 mlx5e_send_nop(sq, 1);
1170                 wmb();
1171         }
1172 done:
1173         /* Check if we need to write the doorbell */
1174         if (likely(sq->doorbell.d64 != 0)) {
1175                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1176                 sq->doorbell.d64 = 0;
1177         }
1178         return;
1179 }
1180
1181 void
1182 mlx5e_sq_cev_timeout(void *arg)
1183 {
1184         struct mlx5e_sq *sq = arg;
1185
1186         mtx_assert(&sq->lock, MA_OWNED);
1187
1188         /* check next state */
1189         switch (sq->cev_next_state) {
1190         case MLX5E_CEV_STATE_SEND_NOPS:
1191                 /* fill TX ring with NOPs, if any */
1192                 mlx5e_sq_send_nops_locked(sq, 0);
1193
1194                 /* check if completed */
1195                 if (sq->cev_counter == 0) {
1196                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1197                         return;
1198                 }
1199                 break;
1200         default:
1201                 /* send NOPs on next timeout */
1202                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1203                 break;
1204         }
1205
1206         /* restart timer */
1207         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1208 }
1209
1210 void
1211 mlx5e_drain_sq(struct mlx5e_sq *sq)
1212 {
1213
1214         mtx_lock(&sq->lock);
1215         /* teardown event factor timer, if any */
1216         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1217         callout_stop(&sq->cev_callout);
1218
1219         /* send dummy NOPs in order to flush the transmit ring */
1220         mlx5e_sq_send_nops_locked(sq, 1);
1221         mtx_unlock(&sq->lock);
1222
1223         /* make sure it is safe to free the callout */
1224         callout_drain(&sq->cev_callout);
1225
1226         /* error out remaining requests */
1227         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1228
1229         /* wait till SQ is empty */
1230         mtx_lock(&sq->lock);
1231         while (sq->cc != sq->pc) {
1232                 mtx_unlock(&sq->lock);
1233                 msleep(4);
1234                 sq->cq.mcq.comp(&sq->cq.mcq);
1235                 mtx_lock(&sq->lock);
1236         }
1237         mtx_unlock(&sq->lock);
1238 }
1239
1240 static void
1241 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1242 {
1243
1244         mlx5e_drain_sq(sq);
1245         mlx5e_disable_sq(sq);
1246         mlx5e_destroy_sq(sq);
1247 }
1248
1249 static int
1250 mlx5e_create_cq(struct mlx5e_priv *priv,
1251     struct mlx5e_cq_param *param,
1252     struct mlx5e_cq *cq,
1253     mlx5e_cq_comp_t *comp,
1254     int eq_ix)
1255 {
1256         struct mlx5_core_dev *mdev = priv->mdev;
1257         struct mlx5_core_cq *mcq = &cq->mcq;
1258         int eqn_not_used;
1259         int irqn;
1260         int err;
1261         u32 i;
1262
1263         param->wq.buf_numa_node = 0;
1264         param->wq.db_numa_node = 0;
1265
1266         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1267             &cq->wq_ctrl);
1268         if (err)
1269                 return (err);
1270
1271         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1272
1273         mcq->cqe_sz = 64;
1274         mcq->set_ci_db = cq->wq_ctrl.db.db;
1275         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1276         *mcq->set_ci_db = 0;
1277         *mcq->arm_db = 0;
1278         mcq->vector = eq_ix;
1279         mcq->comp = comp;
1280         mcq->event = mlx5e_cq_error_event;
1281         mcq->irqn = irqn;
1282         mcq->uar = &priv->cq_uar;
1283
1284         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1285                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1286
1287                 cqe->op_own = 0xf1;
1288         }
1289
1290         cq->priv = priv;
1291
1292         return (0);
1293 }
1294
1295 static void
1296 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1297 {
1298         mlx5_wq_destroy(&cq->wq_ctrl);
1299 }
1300
1301 static int
1302 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1303 {
1304         struct mlx5_core_cq *mcq = &cq->mcq;
1305         void *in;
1306         void *cqc;
1307         int inlen;
1308         int irqn_not_used;
1309         int eqn;
1310         int err;
1311
1312         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1313             sizeof(u64) * cq->wq_ctrl.buf.npages;
1314         in = mlx5_vzalloc(inlen);
1315         if (in == NULL)
1316                 return (-ENOMEM);
1317
1318         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1319
1320         memcpy(cqc, param->cqc, sizeof(param->cqc));
1321
1322         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1323             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1324
1325         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1326
1327         MLX5_SET(cqc, cqc, c_eqn, eqn);
1328         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1329         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1330             PAGE_SHIFT);
1331         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1332
1333         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1334
1335         kvfree(in);
1336
1337         if (err)
1338                 return (err);
1339
1340         mlx5e_cq_arm(cq);
1341
1342         return (0);
1343 }
1344
1345 static void
1346 mlx5e_disable_cq(struct mlx5e_cq *cq)
1347 {
1348
1349         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1350 }
1351
1352 int
1353 mlx5e_open_cq(struct mlx5e_priv *priv,
1354     struct mlx5e_cq_param *param,
1355     struct mlx5e_cq *cq,
1356     mlx5e_cq_comp_t *comp,
1357     int eq_ix)
1358 {
1359         int err;
1360
1361         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1362         if (err)
1363                 return (err);
1364
1365         err = mlx5e_enable_cq(cq, param, eq_ix);
1366         if (err)
1367                 goto err_destroy_cq;
1368
1369         return (0);
1370
1371 err_destroy_cq:
1372         mlx5e_destroy_cq(cq);
1373
1374         return (err);
1375 }
1376
1377 void
1378 mlx5e_close_cq(struct mlx5e_cq *cq)
1379 {
1380         mlx5e_disable_cq(cq);
1381         mlx5e_destroy_cq(cq);
1382 }
1383
1384 static int
1385 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1386     struct mlx5e_channel_param *cparam)
1387 {
1388         int err;
1389         int tc;
1390
1391         for (tc = 0; tc < c->num_tc; tc++) {
1392                 /* open completion queue */
1393                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1394                     &mlx5e_tx_cq_comp, c->ix);
1395                 if (err)
1396                         goto err_close_tx_cqs;
1397         }
1398         return (0);
1399
1400 err_close_tx_cqs:
1401         for (tc--; tc >= 0; tc--)
1402                 mlx5e_close_cq(&c->sq[tc].cq);
1403
1404         return (err);
1405 }
1406
1407 static void
1408 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1409 {
1410         int tc;
1411
1412         for (tc = 0; tc < c->num_tc; tc++)
1413                 mlx5e_close_cq(&c->sq[tc].cq);
1414 }
1415
1416 static int
1417 mlx5e_open_sqs(struct mlx5e_channel *c,
1418     struct mlx5e_channel_param *cparam)
1419 {
1420         int err;
1421         int tc;
1422
1423         for (tc = 0; tc < c->num_tc; tc++) {
1424                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1425                 if (err)
1426                         goto err_close_sqs;
1427         }
1428
1429         return (0);
1430
1431 err_close_sqs:
1432         for (tc--; tc >= 0; tc--)
1433                 mlx5e_close_sq_wait(&c->sq[tc]);
1434
1435         return (err);
1436 }
1437
1438 static void
1439 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1440 {
1441         int tc;
1442
1443         for (tc = 0; tc < c->num_tc; tc++)
1444                 mlx5e_close_sq_wait(&c->sq[tc]);
1445 }
1446
1447 static void
1448 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1449 {
1450         int tc;
1451
1452         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1453
1454         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1455
1456         for (tc = 0; tc < c->num_tc; tc++) {
1457                 struct mlx5e_sq *sq = c->sq + tc;
1458
1459                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1460                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1461                     MTX_DEF);
1462
1463                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1464
1465                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1466
1467                 /* ensure the TX completion event factor is not zero */
1468                 if (sq->cev_factor == 0)
1469                         sq->cev_factor = 1;
1470         }
1471 }
1472
1473 static void
1474 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1475 {
1476         int tc;
1477
1478         mtx_destroy(&c->rq.mtx);
1479
1480         for (tc = 0; tc < c->num_tc; tc++) {
1481                 mtx_destroy(&c->sq[tc].lock);
1482                 mtx_destroy(&c->sq[tc].comp_lock);
1483         }
1484 }
1485
1486 static int
1487 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1488     struct mlx5e_channel_param *cparam,
1489     struct mlx5e_channel *volatile *cp)
1490 {
1491         struct mlx5e_channel *c;
1492         int err;
1493
1494         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1495         if (c == NULL)
1496                 return (-ENOMEM);
1497
1498         c->priv = priv;
1499         c->ix = ix;
1500         c->cpu = 0;
1501         c->ifp = priv->ifp;
1502         c->mkey_be = cpu_to_be32(priv->mr.key);
1503         c->num_tc = priv->num_tc;
1504
1505         /* init mutexes */
1506         mlx5e_chan_mtx_init(c);
1507
1508         /* open transmit completion queue */
1509         err = mlx5e_open_tx_cqs(c, cparam);
1510         if (err)
1511                 goto err_free;
1512
1513         /* open receive completion queue */
1514         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1515             &mlx5e_rx_cq_comp, c->ix);
1516         if (err)
1517                 goto err_close_tx_cqs;
1518
1519         err = mlx5e_open_sqs(c, cparam);
1520         if (err)
1521                 goto err_close_rx_cq;
1522
1523         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1524         if (err)
1525                 goto err_close_sqs;
1526
1527         /* store channel pointer */
1528         *cp = c;
1529
1530         /* poll receive queue initially */
1531         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1532
1533         return (0);
1534
1535 err_close_sqs:
1536         mlx5e_close_sqs_wait(c);
1537
1538 err_close_rx_cq:
1539         mlx5e_close_cq(&c->rq.cq);
1540
1541 err_close_tx_cqs:
1542         mlx5e_close_tx_cqs(c);
1543
1544 err_free:
1545         /* destroy mutexes */
1546         mlx5e_chan_mtx_destroy(c);
1547         free(c, M_MLX5EN);
1548         return (err);
1549 }
1550
1551 static void
1552 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1553 {
1554         struct mlx5e_channel *c = *pp;
1555
1556         /* check if channel is already closed */
1557         if (c == NULL)
1558                 return;
1559         mlx5e_close_rq(&c->rq);
1560 }
1561
1562 static void
1563 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1564 {
1565         struct mlx5e_channel *c = *pp;
1566
1567         /* check if channel is already closed */
1568         if (c == NULL)
1569                 return;
1570         /* ensure channel pointer is no longer used */
1571         *pp = NULL;
1572
1573         mlx5e_close_rq_wait(&c->rq);
1574         mlx5e_close_sqs_wait(c);
1575         mlx5e_close_cq(&c->rq.cq);
1576         mlx5e_close_tx_cqs(c);
1577         /* destroy mutexes */
1578         mlx5e_chan_mtx_destroy(c);
1579         free(c, M_MLX5EN);
1580 }
1581
1582 static void
1583 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1584     struct mlx5e_rq_param *param)
1585 {
1586         void *rqc = param->rqc;
1587         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1588
1589         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1590         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1591         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1592         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1593         MLX5_SET(wq, wq, pd, priv->pdn);
1594
1595         param->wq.buf_numa_node = 0;
1596         param->wq.db_numa_node = 0;
1597         param->wq.linear = 1;
1598 }
1599
1600 static void
1601 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1602     struct mlx5e_sq_param *param)
1603 {
1604         void *sqc = param->sqc;
1605         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1606
1607         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1608         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1609         MLX5_SET(wq, wq, pd, priv->pdn);
1610
1611         param->wq.buf_numa_node = 0;
1612         param->wq.db_numa_node = 0;
1613         param->wq.linear = 1;
1614 }
1615
1616 static void
1617 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1618     struct mlx5e_cq_param *param)
1619 {
1620         void *cqc = param->cqc;
1621
1622         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1623 }
1624
1625 static void
1626 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1627     struct mlx5e_cq_param *param)
1628 {
1629         void *cqc = param->cqc;
1630
1631
1632         /*
1633          * TODO The sysctl to control on/off is a bool value for now, which means
1634          * we only support CSUM, once HASH is implemnted we'll need to address that.
1635          */
1636         if (priv->params.cqe_zipping_en) {
1637                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1638                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1639         }
1640
1641         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1642         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1643         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1644
1645         switch (priv->params.rx_cq_moderation_mode) {
1646         case 0:
1647                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1648                 break;
1649         default:
1650                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1651                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1652                 else
1653                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1654                 break;
1655         }
1656
1657         mlx5e_build_common_cq_param(priv, param);
1658 }
1659
1660 static void
1661 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1662     struct mlx5e_cq_param *param)
1663 {
1664         void *cqc = param->cqc;
1665
1666         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1667         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1668         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1669
1670         switch (priv->params.tx_cq_moderation_mode) {
1671         case 0:
1672                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1673                 break;
1674         default:
1675                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1676                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1677                 else
1678                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1679                 break;
1680         }
1681
1682         mlx5e_build_common_cq_param(priv, param);
1683 }
1684
1685 static void
1686 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1687     struct mlx5e_channel_param *cparam)
1688 {
1689         memset(cparam, 0, sizeof(*cparam));
1690
1691         mlx5e_build_rq_param(priv, &cparam->rq);
1692         mlx5e_build_sq_param(priv, &cparam->sq);
1693         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1694         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1695 }
1696
1697 static int
1698 mlx5e_open_channels(struct mlx5e_priv *priv)
1699 {
1700         struct mlx5e_channel_param cparam;
1701         void *ptr;
1702         int err;
1703         int i;
1704         int j;
1705
1706         priv->channel = malloc(priv->params.num_channels *
1707             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1708         if (priv->channel == NULL)
1709                 return (-ENOMEM);
1710
1711         mlx5e_build_channel_param(priv, &cparam);
1712         for (i = 0; i < priv->params.num_channels; i++) {
1713                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1714                 if (err)
1715                         goto err_close_channels;
1716         }
1717
1718         for (j = 0; j < priv->params.num_channels; j++) {
1719                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1720                 if (err)
1721                         goto err_close_channels;
1722         }
1723
1724         return (0);
1725
1726 err_close_channels:
1727         for (i--; i >= 0; i--) {
1728                 mlx5e_close_channel(&priv->channel[i]);
1729                 mlx5e_close_channel_wait(&priv->channel[i]);
1730         }
1731
1732         /* remove "volatile" attribute from "channel" pointer */
1733         ptr = __DECONST(void *, priv->channel);
1734         priv->channel = NULL;
1735
1736         free(ptr, M_MLX5EN);
1737
1738         return (err);
1739 }
1740
1741 static void
1742 mlx5e_close_channels(struct mlx5e_priv *priv)
1743 {
1744         void *ptr;
1745         int i;
1746
1747         if (priv->channel == NULL)
1748                 return;
1749
1750         for (i = 0; i < priv->params.num_channels; i++)
1751                 mlx5e_close_channel(&priv->channel[i]);
1752         for (i = 0; i < priv->params.num_channels; i++)
1753                 mlx5e_close_channel_wait(&priv->channel[i]);
1754
1755         /* remove "volatile" attribute from "channel" pointer */
1756         ptr = __DECONST(void *, priv->channel);
1757         priv->channel = NULL;
1758
1759         free(ptr, M_MLX5EN);
1760 }
1761
1762 static int
1763 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1764 {
1765         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1766             priv->params.tx_cq_moderation_usec,
1767             priv->params.tx_cq_moderation_pkts));
1768 }
1769
1770 static int
1771 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1772 {
1773         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1774             priv->params.rx_cq_moderation_usec,
1775             priv->params.rx_cq_moderation_pkts));
1776 }
1777
1778 static int
1779 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1780 {
1781         int err;
1782         int i;
1783
1784         if (c == NULL)
1785                 return (EINVAL);
1786
1787         err = mlx5e_refresh_rq_params(priv, &c->rq);
1788         if (err)
1789                 goto done;
1790
1791         for (i = 0; i != c->num_tc; i++) {
1792                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1793                 if (err)
1794                         goto done;
1795         }
1796 done:
1797         return (err);
1798 }
1799
1800 int
1801 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1802 {
1803         int i;
1804
1805         if (priv->channel == NULL)
1806                 return (EINVAL);
1807
1808         for (i = 0; i < priv->params.num_channels; i++) {
1809                 int err;
1810
1811                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1812                 if (err)
1813                         return (err);
1814         }
1815         return (0);
1816 }
1817
1818 static int
1819 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1820 {
1821         struct mlx5_core_dev *mdev = priv->mdev;
1822         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1823         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1824
1825         memset(in, 0, sizeof(in));
1826
1827         MLX5_SET(tisc, tisc, prio, tc);
1828         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1829
1830         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1831 }
1832
1833 static void
1834 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1835 {
1836         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1837 }
1838
1839 static int
1840 mlx5e_open_tises(struct mlx5e_priv *priv)
1841 {
1842         int num_tc = priv->num_tc;
1843         int err;
1844         int tc;
1845
1846         for (tc = 0; tc < num_tc; tc++) {
1847                 err = mlx5e_open_tis(priv, tc);
1848                 if (err)
1849                         goto err_close_tises;
1850         }
1851
1852         return (0);
1853
1854 err_close_tises:
1855         for (tc--; tc >= 0; tc--)
1856                 mlx5e_close_tis(priv, tc);
1857
1858         return (err);
1859 }
1860
1861 static void
1862 mlx5e_close_tises(struct mlx5e_priv *priv)
1863 {
1864         int num_tc = priv->num_tc;
1865         int tc;
1866
1867         for (tc = 0; tc < num_tc; tc++)
1868                 mlx5e_close_tis(priv, tc);
1869 }
1870
1871 static int
1872 mlx5e_open_rqt(struct mlx5e_priv *priv)
1873 {
1874         struct mlx5_core_dev *mdev = priv->mdev;
1875         u32 *in;
1876         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1877         void *rqtc;
1878         int inlen;
1879         int err;
1880         int sz;
1881         int i;
1882
1883         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1884
1885         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1886         in = mlx5_vzalloc(inlen);
1887         if (in == NULL)
1888                 return (-ENOMEM);
1889         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1890
1891         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1892         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1893
1894         for (i = 0; i < sz; i++) {
1895                 int ix;
1896 #ifdef RSS
1897                 ix = rss_get_indirection_to_bucket(i);
1898 #else
1899                 ix = i;
1900 #endif
1901                 /* ensure we don't overflow */
1902                 ix %= priv->params.num_channels;
1903                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1904         }
1905
1906         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1907
1908         memset(out, 0, sizeof(out));
1909         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1910         if (!err)
1911                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1912
1913         kvfree(in);
1914
1915         return (err);
1916 }
1917
1918 static void
1919 mlx5e_close_rqt(struct mlx5e_priv *priv)
1920 {
1921         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1922         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1923
1924         memset(in, 0, sizeof(in));
1925
1926         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1927         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1928
1929         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1930             sizeof(out));
1931 }
1932
1933 static void
1934 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1935 {
1936         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1937         __be32 *hkey;
1938
1939         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1940
1941 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1942
1943 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1944                           MLX5_HASH_FIELD_SEL_DST_IP)
1945
1946 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1947                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1948                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1949                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1950
1951 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1952                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1953                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1954
1955         if (priv->params.hw_lro_en) {
1956                 MLX5_SET(tirc, tirc, lro_enable_mask,
1957                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1958                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1959                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1960                     (priv->params.lro_wqe_sz -
1961                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1962                 /* TODO: add the option to choose timer value dynamically */
1963                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1964                     MLX5_CAP_ETH(priv->mdev,
1965                     lro_timer_supported_periods[2]));
1966         }
1967
1968         /* setup parameters for hashing TIR type, if any */
1969         switch (tt) {
1970         case MLX5E_TT_ANY:
1971                 MLX5_SET(tirc, tirc, disp_type,
1972                     MLX5_TIRC_DISP_TYPE_DIRECT);
1973                 MLX5_SET(tirc, tirc, inline_rqn,
1974                     priv->channel[0]->rq.rqn);
1975                 break;
1976         default:
1977                 MLX5_SET(tirc, tirc, disp_type,
1978                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1979                 MLX5_SET(tirc, tirc, indirect_table,
1980                     priv->rqtn);
1981                 MLX5_SET(tirc, tirc, rx_hash_fn,
1982                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1983                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1984 #ifdef RSS
1985                 /*
1986                  * The FreeBSD RSS implementation does currently not
1987                  * support symmetric Toeplitz hashes:
1988                  */
1989                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1990                 rss_getkey((uint8_t *)hkey);
1991 #else
1992                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1993                 hkey[0] = cpu_to_be32(0xD181C62C);
1994                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1995                 hkey[2] = cpu_to_be32(0x1983A2FC);
1996                 hkey[3] = cpu_to_be32(0x943E1ADB);
1997                 hkey[4] = cpu_to_be32(0xD9389E6B);
1998                 hkey[5] = cpu_to_be32(0xD1039C2C);
1999                 hkey[6] = cpu_to_be32(0xA74499AD);
2000                 hkey[7] = cpu_to_be32(0x593D56D9);
2001                 hkey[8] = cpu_to_be32(0xF3253C06);
2002                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2003 #endif
2004                 break;
2005         }
2006
2007         switch (tt) {
2008         case MLX5E_TT_IPV4_TCP:
2009                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2010                     MLX5_L3_PROT_TYPE_IPV4);
2011                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2012                     MLX5_L4_PROT_TYPE_TCP);
2013 #ifdef RSS
2014                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2015                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2016                             MLX5_HASH_IP);
2017                 } else
2018 #endif
2019                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2020                     MLX5_HASH_ALL);
2021                 break;
2022
2023         case MLX5E_TT_IPV6_TCP:
2024                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2025                     MLX5_L3_PROT_TYPE_IPV6);
2026                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2027                     MLX5_L4_PROT_TYPE_TCP);
2028 #ifdef RSS
2029                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2030                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2031                             MLX5_HASH_IP);
2032                 } else
2033 #endif
2034                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2035                     MLX5_HASH_ALL);
2036                 break;
2037
2038         case MLX5E_TT_IPV4_UDP:
2039                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2040                     MLX5_L3_PROT_TYPE_IPV4);
2041                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2042                     MLX5_L4_PROT_TYPE_UDP);
2043 #ifdef RSS
2044                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2045                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2046                             MLX5_HASH_IP);
2047                 } else
2048 #endif
2049                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2050                     MLX5_HASH_ALL);
2051                 break;
2052
2053         case MLX5E_TT_IPV6_UDP:
2054                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2055                     MLX5_L3_PROT_TYPE_IPV6);
2056                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2057                     MLX5_L4_PROT_TYPE_UDP);
2058 #ifdef RSS
2059                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2060                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2061                             MLX5_HASH_IP);
2062                 } else
2063 #endif
2064                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2065                     MLX5_HASH_ALL);
2066                 break;
2067
2068         case MLX5E_TT_IPV4_IPSEC_AH:
2069                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2070                     MLX5_L3_PROT_TYPE_IPV4);
2071                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2072                     MLX5_HASH_IP_IPSEC_SPI);
2073                 break;
2074
2075         case MLX5E_TT_IPV6_IPSEC_AH:
2076                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2077                     MLX5_L3_PROT_TYPE_IPV6);
2078                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2079                     MLX5_HASH_IP_IPSEC_SPI);
2080                 break;
2081
2082         case MLX5E_TT_IPV4_IPSEC_ESP:
2083                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2084                     MLX5_L3_PROT_TYPE_IPV4);
2085                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2086                     MLX5_HASH_IP_IPSEC_SPI);
2087                 break;
2088
2089         case MLX5E_TT_IPV6_IPSEC_ESP:
2090                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2091                     MLX5_L3_PROT_TYPE_IPV6);
2092                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2093                     MLX5_HASH_IP_IPSEC_SPI);
2094                 break;
2095
2096         case MLX5E_TT_IPV4:
2097                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2098                     MLX5_L3_PROT_TYPE_IPV4);
2099                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2100                     MLX5_HASH_IP);
2101                 break;
2102
2103         case MLX5E_TT_IPV6:
2104                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2105                     MLX5_L3_PROT_TYPE_IPV6);
2106                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2107                     MLX5_HASH_IP);
2108                 break;
2109
2110         default:
2111                 break;
2112         }
2113 }
2114
2115 static int
2116 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2117 {
2118         struct mlx5_core_dev *mdev = priv->mdev;
2119         u32 *in;
2120         void *tirc;
2121         int inlen;
2122         int err;
2123
2124         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2125         in = mlx5_vzalloc(inlen);
2126         if (in == NULL)
2127                 return (-ENOMEM);
2128         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2129
2130         mlx5e_build_tir_ctx(priv, tirc, tt);
2131
2132         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2133
2134         kvfree(in);
2135
2136         return (err);
2137 }
2138
2139 static void
2140 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2141 {
2142         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2143 }
2144
2145 static int
2146 mlx5e_open_tirs(struct mlx5e_priv *priv)
2147 {
2148         int err;
2149         int i;
2150
2151         for (i = 0; i < MLX5E_NUM_TT; i++) {
2152                 err = mlx5e_open_tir(priv, i);
2153                 if (err)
2154                         goto err_close_tirs;
2155         }
2156
2157         return (0);
2158
2159 err_close_tirs:
2160         for (i--; i >= 0; i--)
2161                 mlx5e_close_tir(priv, i);
2162
2163         return (err);
2164 }
2165
2166 static void
2167 mlx5e_close_tirs(struct mlx5e_priv *priv)
2168 {
2169         int i;
2170
2171         for (i = 0; i < MLX5E_NUM_TT; i++)
2172                 mlx5e_close_tir(priv, i);
2173 }
2174
2175 /*
2176  * SW MTU does not include headers,
2177  * HW MTU includes all headers and checksums.
2178  */
2179 static int
2180 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2181 {
2182         struct mlx5e_priv *priv = ifp->if_softc;
2183         struct mlx5_core_dev *mdev = priv->mdev;
2184         int hw_mtu;
2185         int err;
2186
2187         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2188         if (err) {
2189                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2190                     __func__, sw_mtu, err);
2191                 return (err);
2192         }
2193         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2194         if (err) {
2195                 if_printf(ifp, "Query port MTU, after setting new "
2196                     "MTU value, failed\n");
2197         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2198                 err = -E2BIG,
2199                 if_printf(ifp, "Port MTU %d is smaller than "
2200                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2201         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2202                 err = -EINVAL;
2203                 if_printf(ifp, "Port MTU %d is bigger than "
2204                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2205         }
2206         ifp->if_mtu = sw_mtu;
2207         return (err);
2208 }
2209
2210 int
2211 mlx5e_open_locked(struct ifnet *ifp)
2212 {
2213         struct mlx5e_priv *priv = ifp->if_softc;
2214         int err;
2215         u16 set_id;
2216
2217         /* check if already opened */
2218         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2219                 return (0);
2220
2221 #ifdef RSS
2222         if (rss_getnumbuckets() > priv->params.num_channels) {
2223                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2224                     "channels(%u) available\n", rss_getnumbuckets(),
2225                     priv->params.num_channels);
2226         }
2227 #endif
2228         err = mlx5e_open_tises(priv);
2229         if (err) {
2230                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2231                     __func__, err);
2232                 return (err);
2233         }
2234         err = mlx5_vport_alloc_q_counter(priv->mdev,
2235             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2236         if (err) {
2237                 if_printf(priv->ifp,
2238                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2239                     __func__, err);
2240                 goto err_close_tises;
2241         }
2242         /* store counter set ID */
2243         priv->counter_set_id = set_id;
2244
2245         err = mlx5e_open_channels(priv);
2246         if (err) {
2247                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2248                     __func__, err);
2249                 goto err_dalloc_q_counter;
2250         }
2251         err = mlx5e_open_rqt(priv);
2252         if (err) {
2253                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2254                     __func__, err);
2255                 goto err_close_channels;
2256         }
2257         err = mlx5e_open_tirs(priv);
2258         if (err) {
2259                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2260                     __func__, err);
2261                 goto err_close_rqls;
2262         }
2263         err = mlx5e_open_flow_table(priv);
2264         if (err) {
2265                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2266                     __func__, err);
2267                 goto err_close_tirs;
2268         }
2269         err = mlx5e_add_all_vlan_rules(priv);
2270         if (err) {
2271                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2272                     __func__, err);
2273                 goto err_close_flow_table;
2274         }
2275         set_bit(MLX5E_STATE_OPENED, &priv->state);
2276
2277         mlx5e_update_carrier(priv);
2278         mlx5e_set_rx_mode_core(priv);
2279
2280         return (0);
2281
2282 err_close_flow_table:
2283         mlx5e_close_flow_table(priv);
2284
2285 err_close_tirs:
2286         mlx5e_close_tirs(priv);
2287
2288 err_close_rqls:
2289         mlx5e_close_rqt(priv);
2290
2291 err_close_channels:
2292         mlx5e_close_channels(priv);
2293
2294 err_dalloc_q_counter:
2295         mlx5_vport_dealloc_q_counter(priv->mdev,
2296             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2297
2298 err_close_tises:
2299         mlx5e_close_tises(priv);
2300
2301         return (err);
2302 }
2303
2304 static void
2305 mlx5e_open(void *arg)
2306 {
2307         struct mlx5e_priv *priv = arg;
2308
2309         PRIV_LOCK(priv);
2310         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2311                 if_printf(priv->ifp,
2312                     "%s: Setting port status to up failed\n",
2313                     __func__);
2314
2315         mlx5e_open_locked(priv->ifp);
2316         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2317         PRIV_UNLOCK(priv);
2318 }
2319
2320 int
2321 mlx5e_close_locked(struct ifnet *ifp)
2322 {
2323         struct mlx5e_priv *priv = ifp->if_softc;
2324
2325         /* check if already closed */
2326         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2327                 return (0);
2328
2329         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2330
2331         mlx5e_set_rx_mode_core(priv);
2332         mlx5e_del_all_vlan_rules(priv);
2333         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2334         mlx5e_close_flow_table(priv);
2335         mlx5e_close_tirs(priv);
2336         mlx5e_close_rqt(priv);
2337         mlx5e_close_channels(priv);
2338         mlx5_vport_dealloc_q_counter(priv->mdev,
2339             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2340         mlx5e_close_tises(priv);
2341
2342         return (0);
2343 }
2344
2345 #if (__FreeBSD_version >= 1100000)
2346 static uint64_t
2347 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2348 {
2349         struct mlx5e_priv *priv = ifp->if_softc;
2350         u64 retval;
2351
2352         /* PRIV_LOCK(priv); XXX not allowed */
2353         switch (cnt) {
2354         case IFCOUNTER_IPACKETS:
2355                 retval = priv->stats.vport.rx_packets;
2356                 break;
2357         case IFCOUNTER_IERRORS:
2358                 retval = priv->stats.vport.rx_error_packets;
2359                 break;
2360         case IFCOUNTER_IQDROPS:
2361                 retval = priv->stats.vport.rx_out_of_buffer;
2362                 break;
2363         case IFCOUNTER_OPACKETS:
2364                 retval = priv->stats.vport.tx_packets;
2365                 break;
2366         case IFCOUNTER_OERRORS:
2367                 retval = priv->stats.vport.tx_error_packets;
2368                 break;
2369         case IFCOUNTER_IBYTES:
2370                 retval = priv->stats.vport.rx_bytes;
2371                 break;
2372         case IFCOUNTER_OBYTES:
2373                 retval = priv->stats.vport.tx_bytes;
2374                 break;
2375         case IFCOUNTER_IMCASTS:
2376                 retval = priv->stats.vport.rx_multicast_packets;
2377                 break;
2378         case IFCOUNTER_OMCASTS:
2379                 retval = priv->stats.vport.tx_multicast_packets;
2380                 break;
2381         case IFCOUNTER_OQDROPS:
2382                 retval = priv->stats.vport.tx_queue_dropped;
2383                 break;
2384         default:
2385                 retval = if_get_counter_default(ifp, cnt);
2386                 break;
2387         }
2388         /* PRIV_UNLOCK(priv); XXX not allowed */
2389         return (retval);
2390 }
2391 #endif
2392
2393 static void
2394 mlx5e_set_rx_mode(struct ifnet *ifp)
2395 {
2396         struct mlx5e_priv *priv = ifp->if_softc;
2397
2398         schedule_work(&priv->set_rx_mode_work);
2399 }
2400
2401 static int
2402 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2403 {
2404         struct mlx5e_priv *priv;
2405         struct ifreq *ifr;
2406         struct ifi2creq i2c;
2407         int error = 0;
2408         int mask = 0;
2409         int size_read = 0;
2410         int module_num;
2411         int max_mtu;
2412         uint8_t read_addr;
2413
2414         priv = ifp->if_softc;
2415
2416         /* check if detaching */
2417         if (priv == NULL || priv->gone != 0)
2418                 return (ENXIO);
2419
2420         switch (command) {
2421         case SIOCSIFMTU:
2422                 ifr = (struct ifreq *)data;
2423
2424                 PRIV_LOCK(priv);
2425                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2426
2427                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2428                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2429                         int was_opened;
2430
2431                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2432                         if (was_opened)
2433                                 mlx5e_close_locked(ifp);
2434
2435                         /* set new MTU */
2436                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2437
2438                         if (was_opened)
2439                                 mlx5e_open_locked(ifp);
2440                 } else {
2441                         error = EINVAL;
2442                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2443                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2444                 }
2445                 PRIV_UNLOCK(priv);
2446                 break;
2447         case SIOCSIFFLAGS:
2448                 if ((ifp->if_flags & IFF_UP) &&
2449                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2450                         mlx5e_set_rx_mode(ifp);
2451                         break;
2452                 }
2453                 PRIV_LOCK(priv);
2454                 if (ifp->if_flags & IFF_UP) {
2455                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2456                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2457                                         mlx5e_open_locked(ifp);
2458                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2459                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2460                         }
2461                 } else {
2462                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2463                                 mlx5_set_port_status(priv->mdev,
2464                                     MLX5_PORT_DOWN);
2465                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2466                                         mlx5e_close_locked(ifp);
2467                                 mlx5e_update_carrier(priv);
2468                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2469                         }
2470                 }
2471                 PRIV_UNLOCK(priv);
2472                 break;
2473         case SIOCADDMULTI:
2474         case SIOCDELMULTI:
2475                 mlx5e_set_rx_mode(ifp);
2476                 break;
2477         case SIOCSIFMEDIA:
2478         case SIOCGIFMEDIA:
2479         case SIOCGIFXMEDIA:
2480                 ifr = (struct ifreq *)data;
2481                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2482                 break;
2483         case SIOCSIFCAP:
2484                 ifr = (struct ifreq *)data;
2485                 PRIV_LOCK(priv);
2486                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2487
2488                 if (mask & IFCAP_TXCSUM) {
2489                         ifp->if_capenable ^= IFCAP_TXCSUM;
2490                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2491
2492                         if (IFCAP_TSO4 & ifp->if_capenable &&
2493                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2494                                 ifp->if_capenable &= ~IFCAP_TSO4;
2495                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2496                                 if_printf(ifp,
2497                                     "tso4 disabled due to -txcsum.\n");
2498                         }
2499                 }
2500                 if (mask & IFCAP_TXCSUM_IPV6) {
2501                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2502                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2503
2504                         if (IFCAP_TSO6 & ifp->if_capenable &&
2505                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2506                                 ifp->if_capenable &= ~IFCAP_TSO6;
2507                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2508                                 if_printf(ifp,
2509                                     "tso6 disabled due to -txcsum6.\n");
2510                         }
2511                 }
2512                 if (mask & IFCAP_RXCSUM)
2513                         ifp->if_capenable ^= IFCAP_RXCSUM;
2514                 if (mask & IFCAP_RXCSUM_IPV6)
2515                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2516                 if (mask & IFCAP_TSO4) {
2517                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2518                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2519                                 if_printf(ifp, "enable txcsum first.\n");
2520                                 error = EAGAIN;
2521                                 goto out;
2522                         }
2523                         ifp->if_capenable ^= IFCAP_TSO4;
2524                         ifp->if_hwassist ^= CSUM_IP_TSO;
2525                 }
2526                 if (mask & IFCAP_TSO6) {
2527                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2528                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2529                                 if_printf(ifp, "enable txcsum6 first.\n");
2530                                 error = EAGAIN;
2531                                 goto out;
2532                         }
2533                         ifp->if_capenable ^= IFCAP_TSO6;
2534                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2535                 }
2536                 if (mask & IFCAP_VLAN_HWFILTER) {
2537                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2538                                 mlx5e_disable_vlan_filter(priv);
2539                         else
2540                                 mlx5e_enable_vlan_filter(priv);
2541
2542                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2543                 }
2544                 if (mask & IFCAP_VLAN_HWTAGGING)
2545                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2546                 if (mask & IFCAP_WOL_MAGIC)
2547                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2548
2549                 VLAN_CAPABILITIES(ifp);
2550                 /* turn off LRO means also turn of HW LRO - if it's on */
2551                 if (mask & IFCAP_LRO) {
2552                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2553                         bool need_restart = false;
2554
2555                         ifp->if_capenable ^= IFCAP_LRO;
2556                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2557                                 if (priv->params.hw_lro_en) {
2558                                         priv->params.hw_lro_en = false;
2559                                         need_restart = true;
2560                                         /* Not sure this is the correct way */
2561                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2562                                 }
2563                         }
2564                         if (was_opened && need_restart) {
2565                                 mlx5e_close_locked(ifp);
2566                                 mlx5e_open_locked(ifp);
2567                         }
2568                 }
2569 out:
2570                 PRIV_UNLOCK(priv);
2571                 break;
2572
2573         case SIOCGI2C:
2574                 ifr = (struct ifreq *)data;
2575
2576                 /*
2577                  * Copy from the user-space address ifr_data to the
2578                  * kernel-space address i2c
2579                  */
2580                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2581                 if (error)
2582                         break;
2583
2584                 if (i2c.len > sizeof(i2c.data)) {
2585                         error = EINVAL;
2586                         break;
2587                 }
2588
2589                 PRIV_LOCK(priv);
2590                 /* Get module_num which is required for the query_eeprom */
2591                 error = mlx5_query_module_num(priv->mdev, &module_num);
2592                 if (error) {
2593                         if_printf(ifp, "Query module num failed, eeprom "
2594                             "reading is not supported\n");
2595                         error = EINVAL;
2596                         goto err_i2c;
2597                 }
2598                 /* Check if module is present before doing an access */
2599                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2600                     MLX5_MODULE_STATUS_PLUGGED) {
2601                         error = EINVAL;
2602                         goto err_i2c;
2603                 }
2604                 /*
2605                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2606                  * The internal conversion is as follows:
2607                  */
2608                 if (i2c.dev_addr == 0xA0)
2609                         read_addr = MLX5E_I2C_ADDR_LOW;
2610                 else if (i2c.dev_addr == 0xA2)
2611                         read_addr = MLX5E_I2C_ADDR_HIGH;
2612                 else {
2613                         if_printf(ifp, "Query eeprom failed, "
2614                             "Invalid Address: %X\n", i2c.dev_addr);
2615                         error = EINVAL;
2616                         goto err_i2c;
2617                 }
2618                 error = mlx5_query_eeprom(priv->mdev,
2619                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2620                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2621                     (uint32_t *)i2c.data, &size_read);
2622                 if (error) {
2623                         if_printf(ifp, "Query eeprom failed, eeprom "
2624                             "reading is not supported\n");
2625                         error = EINVAL;
2626                         goto err_i2c;
2627                 }
2628
2629                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2630                         error = mlx5_query_eeprom(priv->mdev,
2631                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2632                             (uint32_t)(i2c.offset + size_read),
2633                             (uint32_t)(i2c.len - size_read), module_num,
2634                             (uint32_t *)(i2c.data + size_read), &size_read);
2635                 }
2636                 if (error) {
2637                         if_printf(ifp, "Query eeprom failed, eeprom "
2638                             "reading is not supported\n");
2639                         error = EINVAL;
2640                         goto err_i2c;
2641                 }
2642
2643                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2644 err_i2c:
2645                 PRIV_UNLOCK(priv);
2646                 break;
2647
2648         default:
2649                 error = ether_ioctl(ifp, command, data);
2650                 break;
2651         }
2652         return (error);
2653 }
2654
2655 static int
2656 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2657 {
2658         /*
2659          * TODO: uncoment once FW really sets all these bits if
2660          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2661          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2662          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2663          * -ENOTSUPP;
2664          */
2665
2666         /* TODO: add more must-to-have features */
2667
2668         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2669                 return (-ENODEV);
2670
2671         return (0);
2672 }
2673
2674 static void
2675 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2676     struct mlx5e_priv *priv,
2677     int num_comp_vectors)
2678 {
2679         /*
2680          * TODO: Consider link speed for setting "log_sq_size",
2681          * "log_rq_size" and "cq_moderation_xxx":
2682          */
2683         priv->params.log_sq_size =
2684             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2685         priv->params.log_rq_size =
2686             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2687         priv->params.rx_cq_moderation_usec =
2688             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2689             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2690             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2691         priv->params.rx_cq_moderation_mode =
2692             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2693         priv->params.rx_cq_moderation_pkts =
2694             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2695         priv->params.tx_cq_moderation_usec =
2696             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2697         priv->params.tx_cq_moderation_pkts =
2698             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2699         priv->params.min_rx_wqes =
2700             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2701         priv->params.rx_hash_log_tbl_sz =
2702             (order_base_2(num_comp_vectors) >
2703             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2704             order_base_2(num_comp_vectors) :
2705             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2706         priv->params.num_tc = 1;
2707         priv->params.default_vlan_prio = 0;
2708         priv->counter_set_id = -1;
2709
2710         /*
2711          * hw lro is currently defaulted to off. when it won't anymore we
2712          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2713          */
2714         priv->params.hw_lro_en = false;
2715         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2716
2717         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2718
2719         priv->mdev = mdev;
2720         priv->params.num_channels = num_comp_vectors;
2721         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2722         priv->queue_mapping_channel_mask =
2723             roundup_pow_of_two(num_comp_vectors) - 1;
2724         priv->num_tc = priv->params.num_tc;
2725         priv->default_vlan_prio = priv->params.default_vlan_prio;
2726
2727         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2728         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2729         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2730 }
2731
2732 static int
2733 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2734     struct mlx5_core_mr *mr)
2735 {
2736         struct ifnet *ifp = priv->ifp;
2737         struct mlx5_core_dev *mdev = priv->mdev;
2738         struct mlx5_create_mkey_mbox_in *in;
2739         int err;
2740
2741         in = mlx5_vzalloc(sizeof(*in));
2742         if (in == NULL) {
2743                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2744                 return (-ENOMEM);
2745         }
2746         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2747             MLX5_PERM_LOCAL_READ |
2748             MLX5_ACCESS_MODE_PA;
2749         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2750         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2751
2752         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2753             NULL);
2754         if (err)
2755                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2756                     __func__, err);
2757
2758         kvfree(in);
2759
2760         return (err);
2761 }
2762
2763 static const char *mlx5e_vport_stats_desc[] = {
2764         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2765 };
2766
2767 static const char *mlx5e_pport_stats_desc[] = {
2768         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2769 };
2770
2771 static void
2772 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2773 {
2774         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2775         sx_init(&priv->state_lock, "mlx5state");
2776         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2777         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2778 }
2779
2780 static void
2781 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2782 {
2783         mtx_destroy(&priv->async_events_mtx);
2784         sx_destroy(&priv->state_lock);
2785 }
2786
2787 static int
2788 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2789 {
2790         /*
2791          * %d.%d%.d the string format.
2792          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2793          * We need at most 5 chars to store that.
2794          * It also has: two "." and NULL at the end, which means we need 18
2795          * (5*3 + 3) chars at most.
2796          */
2797         char fw[18];
2798         struct mlx5e_priv *priv = arg1;
2799         int error;
2800
2801         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2802             fw_rev_sub(priv->mdev));
2803         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2804         return (error);
2805 }
2806
2807 static void
2808 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2809 {
2810         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2811             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2812             sysctl_firmware, "A", "HCA firmware version");
2813
2814         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2815             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2816             "Board ID");
2817 }
2818
2819 static void
2820 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2821 {
2822 #if (__FreeBSD_version < 1100000)
2823         char path[64];
2824
2825 #endif
2826         /* Only receiving pauseframes is enabled by default */
2827         priv->params.tx_pauseframe_control = 0;
2828         priv->params.rx_pauseframe_control = 1;
2829
2830 #if (__FreeBSD_version < 1100000)
2831         /* compute path for sysctl */
2832         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2833             device_get_unit(priv->mdev->pdev->dev.bsddev));
2834
2835         /* try to fetch tunable, if any */
2836         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2837
2838         /* compute path for sysctl */
2839         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2840             device_get_unit(priv->mdev->pdev->dev.bsddev));
2841
2842         /* try to fetch tunable, if any */
2843         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2844 #endif
2845
2846         /* register pausframe SYSCTLs */
2847         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2848             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2849             &priv->params.tx_pauseframe_control, 0,
2850             "Set to enable TX pause frames. Clear to disable.");
2851
2852         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2853             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2854             &priv->params.rx_pauseframe_control, 0,
2855             "Set to enable RX pause frames. Clear to disable.");
2856
2857         /* range check */
2858         priv->params.tx_pauseframe_control =
2859             priv->params.tx_pauseframe_control ? 1 : 0;
2860         priv->params.rx_pauseframe_control =
2861             priv->params.rx_pauseframe_control ? 1 : 0;
2862
2863         /* update firmware */
2864         mlx5_set_port_pause(priv->mdev, 1,
2865             priv->params.rx_pauseframe_control,
2866             priv->params.tx_pauseframe_control);
2867 }
2868
2869 static void *
2870 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2871 {
2872         static volatile int mlx5_en_unit;
2873         struct ifnet *ifp;
2874         struct mlx5e_priv *priv;
2875         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2876         struct sysctl_oid_list *child;
2877         int ncv = mdev->priv.eq_table.num_comp_vectors;
2878         char unit[16];
2879         int err;
2880         int i;
2881         u32 eth_proto_cap;
2882
2883         if (mlx5e_check_required_hca_cap(mdev)) {
2884                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2885                 return (NULL);
2886         }
2887         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2888         if (priv == NULL) {
2889                 mlx5_core_err(mdev, "malloc() failed\n");
2890                 return (NULL);
2891         }
2892         mlx5e_priv_mtx_init(priv);
2893
2894         ifp = priv->ifp = if_alloc(IFT_ETHER);
2895         if (ifp == NULL) {
2896                 mlx5_core_err(mdev, "if_alloc() failed\n");
2897                 goto err_free_priv;
2898         }
2899         ifp->if_softc = priv;
2900         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2901         ifp->if_mtu = ETHERMTU;
2902         ifp->if_init = mlx5e_open;
2903         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2904         ifp->if_ioctl = mlx5e_ioctl;
2905         ifp->if_transmit = mlx5e_xmit;
2906         ifp->if_qflush = if_qflush;
2907 #if (__FreeBSD_version >= 1100000)
2908         ifp->if_get_counter = mlx5e_get_counter;
2909 #endif
2910         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2911         /*
2912          * Set driver features
2913          */
2914         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2915         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2916         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2917         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2918         ifp->if_capabilities |= IFCAP_LRO;
2919         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2920         ifp->if_capabilities |= IFCAP_HWSTATS;
2921
2922         /* set TSO limits so that we don't have to drop TX packets */
2923         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2924         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2925         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2926
2927         ifp->if_capenable = ifp->if_capabilities;
2928         ifp->if_hwassist = 0;
2929         if (ifp->if_capenable & IFCAP_TSO)
2930                 ifp->if_hwassist |= CSUM_TSO;
2931         if (ifp->if_capenable & IFCAP_TXCSUM)
2932                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2933         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2934                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2935
2936         /* ifnet sysctl tree */
2937         sysctl_ctx_init(&priv->sysctl_ctx);
2938         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2939             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2940         if (priv->sysctl_ifnet == NULL) {
2941                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2942                 goto err_free_sysctl;
2943         }
2944         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2945         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2946             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2947         if (priv->sysctl_ifnet == NULL) {
2948                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2949                 goto err_free_sysctl;
2950         }
2951
2952         /* HW sysctl tree */
2953         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2954         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2955             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2956         if (priv->sysctl_hw == NULL) {
2957                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2958                 goto err_free_sysctl;
2959         }
2960         mlx5e_build_ifp_priv(mdev, priv, ncv);
2961         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2962         if (err) {
2963                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2964                     __func__, err);
2965                 goto err_free_sysctl;
2966         }
2967         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2968         if (err) {
2969                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2970                     __func__, err);
2971                 goto err_unmap_free_uar;
2972         }
2973         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2974         if (err) {
2975                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2976                     __func__, err);
2977                 goto err_dealloc_pd;
2978         }
2979         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2980         if (err) {
2981                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2982                     __func__, err);
2983                 goto err_dealloc_transport_domain;
2984         }
2985         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2986
2987         /* check if we should generate a random MAC address */
2988         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2989             is_zero_ether_addr(dev_addr)) {
2990                 random_ether_addr(dev_addr);
2991                 if_printf(ifp, "Assigned random MAC address\n");
2992         }
2993
2994         /* set default MTU */
2995         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2996
2997         /* Set desc */
2998         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2999
3000         /* Set default media status */
3001         priv->media_status_last = IFM_AVALID;
3002         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3003             IFM_ETH_RXPAUSE | IFM_FDX;
3004
3005         /* setup default pauseframes configuration */
3006         mlx5e_setup_pauseframes(priv);
3007
3008         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3009         if (err) {
3010                 eth_proto_cap = 0;
3011                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3012                     __func__, err);
3013         }
3014
3015         /* Setup supported medias */
3016         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3017             mlx5e_media_change, mlx5e_media_status);
3018
3019         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3020                 if (mlx5e_mode_table[i].baudrate == 0)
3021                         continue;
3022                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3023                         ifmedia_add(&priv->media,
3024                             mlx5e_mode_table[i].subtype |
3025                             IFM_ETHER, 0, NULL);
3026                         ifmedia_add(&priv->media,
3027                             mlx5e_mode_table[i].subtype |
3028                             IFM_ETHER | IFM_FDX |
3029                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3030                 }
3031         }
3032
3033         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3034         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3035             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3036
3037         /* Set autoselect by default */
3038         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3039             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3040         ether_ifattach(ifp, dev_addr);
3041
3042         /* Register for VLAN events */
3043         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3044             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3045         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3046             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3047
3048         /* Link is down by default */
3049         if_link_state_change(ifp, LINK_STATE_DOWN);
3050
3051         mlx5e_enable_async_events(priv);
3052
3053         mlx5e_add_hw_stats(priv);
3054
3055         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3056             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3057             priv->stats.vport.arg);
3058
3059         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3060             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3061             priv->stats.pport.arg);
3062
3063         mlx5e_create_ethtool(priv);
3064
3065         mtx_lock(&priv->async_events_mtx);
3066         mlx5e_update_stats(priv);
3067         mtx_unlock(&priv->async_events_mtx);
3068
3069         return (priv);
3070
3071 err_dealloc_transport_domain:
3072         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3073
3074 err_dealloc_pd:
3075         mlx5_core_dealloc_pd(mdev, priv->pdn);
3076
3077 err_unmap_free_uar:
3078         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3079
3080 err_free_sysctl:
3081         sysctl_ctx_free(&priv->sysctl_ctx);
3082
3083         if_free(ifp);
3084
3085 err_free_priv:
3086         mlx5e_priv_mtx_destroy(priv);
3087         free(priv, M_MLX5EN);
3088         return (NULL);
3089 }
3090
3091 static void
3092 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3093 {
3094         struct mlx5e_priv *priv = vpriv;
3095         struct ifnet *ifp = priv->ifp;
3096
3097         /* don't allow more IOCTLs */
3098         priv->gone = 1;
3099
3100         /*
3101          * Clear the device description to avoid use after free,
3102          * because the bsddev is not destroyed when this module is
3103          * unloaded:
3104          */
3105         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3106
3107         /* XXX wait a bit to allow IOCTL handlers to complete */
3108         pause("W", hz);
3109
3110         /* stop watchdog timer */
3111         callout_drain(&priv->watchdog);
3112
3113         if (priv->vlan_attach != NULL)
3114                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3115         if (priv->vlan_detach != NULL)
3116                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3117
3118         /* make sure device gets closed */
3119         PRIV_LOCK(priv);
3120         mlx5e_close_locked(ifp);
3121         PRIV_UNLOCK(priv);
3122
3123         /* unregister device */
3124         ifmedia_removeall(&priv->media);
3125         ether_ifdetach(ifp);
3126         if_free(ifp);
3127
3128         /* destroy all remaining sysctl nodes */
3129         if (priv->sysctl_debug)
3130                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3131         sysctl_ctx_free(&priv->stats.vport.ctx);
3132         sysctl_ctx_free(&priv->stats.pport.ctx);
3133         sysctl_ctx_free(&priv->sysctl_ctx);
3134
3135         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3136         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3137         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3138         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3139         mlx5e_disable_async_events(priv);
3140         flush_scheduled_work();
3141         mlx5e_priv_mtx_destroy(priv);
3142         free(priv, M_MLX5EN);
3143 }
3144
3145 static void *
3146 mlx5e_get_ifp(void *vpriv)
3147 {
3148         struct mlx5e_priv *priv = vpriv;
3149
3150         return (priv->ifp);
3151 }
3152
3153 static struct mlx5_interface mlx5e_interface = {
3154         .add = mlx5e_create_ifp,
3155         .remove = mlx5e_destroy_ifp,
3156         .event = mlx5e_async_event,
3157         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3158         .get_dev = mlx5e_get_ifp,
3159 };
3160
3161 void
3162 mlx5e_init(void)
3163 {
3164         mlx5_register_interface(&mlx5e_interface);
3165 }
3166
3167 void
3168 mlx5e_cleanup(void)
3169 {
3170         mlx5_unregister_interface(&mlx5e_interface);
3171 }
3172
3173 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3174 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3175
3176 #if (__FreeBSD_version >= 1100000)
3177 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3178 #endif
3179 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3180 MODULE_VERSION(mlx5en, 1);