sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 static void
 310 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 311 {
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         struct mlx5e_pport_stats *s = &priv->stats.pport;
 314         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 315         u32 *in;
 316         u32 *out;
 317         u64 *ptr;
 318         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 319         unsigned x;
 320         unsigned y;
 321
 322         in = mlx5_vzalloc(sz);
 323         out = mlx5_vzalloc(sz);
 324         if (in == NULL || out == NULL)
 325                 goto free_out;
 326
 327         ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 328
 329         MLX5_SET(ppcnt_reg, in, local_port, 1);
 330
 331         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 332         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 333         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 334                 s->arg[y] = be64toh(ptr[x]);
 335
 336         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 337         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 338         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 339                 s->arg[y] = be64toh(ptr[x]);
 340         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 341             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 342                 s_debug->arg[y] = be64toh(ptr[x]);
 343
 344         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 345         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 346         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 347                 s_debug->arg[y] = be64toh(ptr[x]);
 348
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 352                 s_debug->arg[y] = be64toh(ptr[x]);
 353 free_out:
 354         kvfree(in);
 355         kvfree(out);
 356 }
 357
 358 static void
 359 mlx5e_update_stats_work(struct work_struct *work)
 360 {
 361         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 362             update_stats_work);
 363         struct mlx5_core_dev *mdev = priv->mdev;
 364         struct mlx5e_vport_stats *s = &priv->stats.vport;
 365         struct mlx5e_rq_stats *rq_stats;
 366         struct mlx5e_sq_stats *sq_stats;
 367         struct buf_ring *sq_br;
 368 #if (__FreeBSD_version < 1100000)
 369         struct ifnet *ifp = priv->ifp;
 370 #endif
 371
 372         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 373         u32 *out;
 374         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 375         u64 tso_packets = 0;
 376         u64 tso_bytes = 0;
 377         u64 tx_queue_dropped = 0;
 378         u64 tx_defragged = 0;
 379         u64 tx_offload_none = 0;
 380         u64 lro_packets = 0;
 381         u64 lro_bytes = 0;
 382         u64 sw_lro_queued = 0;
 383         u64 sw_lro_flushed = 0;
 384         u64 rx_csum_none = 0;
 385         u64 rx_wqe_err = 0;
 386         u32 rx_out_of_buffer = 0;
 387         int i;
 388         int j;
 389
 390         PRIV_LOCK(priv);
 391         out = mlx5_vzalloc(outlen);
 392         if (out == NULL)
 393                 goto free_out;
 394         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 395                 goto free_out;
 396
 397         /* Collect firts the SW counters and then HW for consistency */
 398         for (i = 0; i < priv->params.num_channels; i++) {
 399                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 400
 401                 rq_stats = &priv->channel[i]->rq.stats;
 402
 403                 /* collect stats from LRO */
 404                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 405                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 406                 sw_lro_queued += rq_stats->sw_lro_queued;
 407                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 408                 lro_packets += rq_stats->lro_packets;
 409                 lro_bytes += rq_stats->lro_bytes;
 410                 rx_csum_none += rq_stats->csum_none;
 411                 rx_wqe_err += rq_stats->wqe_err;
 412
 413                 for (j = 0; j < priv->num_tc; j++) {
 414                         sq_stats = &priv->channel[i]->sq[j].stats;
 415                         sq_br = priv->channel[i]->sq[j].br;
 416
 417                         tso_packets += sq_stats->tso_packets;
 418                         tso_bytes += sq_stats->tso_bytes;
 419                         tx_queue_dropped += sq_stats->dropped;
 420                         tx_queue_dropped += sq_br->br_drops;
 421                         tx_defragged += sq_stats->defragged;
 422                         tx_offload_none += sq_stats->csum_offload_none;
 423                 }
 424         }
 425
 426         /* update counters */
 427         s->tso_packets = tso_packets;
 428         s->tso_bytes = tso_bytes;
 429         s->tx_queue_dropped = tx_queue_dropped;
 430         s->tx_defragged = tx_defragged;
 431         s->lro_packets = lro_packets;
 432         s->lro_bytes = lro_bytes;
 433         s->sw_lro_queued = sw_lro_queued;
 434         s->sw_lro_flushed = sw_lro_flushed;
 435         s->rx_csum_none = rx_csum_none;
 436         s->rx_wqe_err = rx_wqe_err;
 437
 438         /* HW counters */
 439         memset(in, 0, sizeof(in));
 440
 441         MLX5_SET(query_vport_counter_in, in, opcode,
 442             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 443         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 444         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 445
 446         memset(out, 0, outlen);
 447
 448         /* get number of out-of-buffer drops first */
 449         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 450             &rx_out_of_buffer))
 451                 goto free_out;
 452
 453         /* accumulate difference into a 64-bit counter */
 454         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 455         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 456
 457         /* get port statistics */
 458         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 459                 goto free_out;
 460
 461 #define MLX5_GET_CTR(out, x) \
 462         MLX5_GET64(query_vport_counter_out, out, x)
 463
 464         s->rx_error_packets =
 465             MLX5_GET_CTR(out, received_errors.packets);
 466         s->rx_error_bytes =
 467             MLX5_GET_CTR(out, received_errors.octets);
 468         s->tx_error_packets =
 469             MLX5_GET_CTR(out, transmit_errors.packets);
 470         s->tx_error_bytes =
 471             MLX5_GET_CTR(out, transmit_errors.octets);
 472
 473         s->rx_unicast_packets =
 474             MLX5_GET_CTR(out, received_eth_unicast.packets);
 475         s->rx_unicast_bytes =
 476             MLX5_GET_CTR(out, received_eth_unicast.octets);
 477         s->tx_unicast_packets =
 478             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 479         s->tx_unicast_bytes =
 480             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 481
 482         s->rx_multicast_packets =
 483             MLX5_GET_CTR(out, received_eth_multicast.packets);
 484         s->rx_multicast_bytes =
 485             MLX5_GET_CTR(out, received_eth_multicast.octets);
 486         s->tx_multicast_packets =
 487             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 488         s->tx_multicast_bytes =
 489             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 490
 491         s->rx_broadcast_packets =
 492             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 493         s->rx_broadcast_bytes =
 494             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 495         s->tx_broadcast_packets =
 496             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 497         s->tx_broadcast_bytes =
 498             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 499
 500         s->rx_packets =
 501             s->rx_unicast_packets +
 502             s->rx_multicast_packets +
 503             s->rx_broadcast_packets -
 504             s->rx_out_of_buffer;
 505         s->rx_bytes =
 506             s->rx_unicast_bytes +
 507             s->rx_multicast_bytes +
 508             s->rx_broadcast_bytes;
 509         s->tx_packets =
 510             s->tx_unicast_packets +
 511             s->tx_multicast_packets +
 512             s->tx_broadcast_packets;
 513         s->tx_bytes =
 514             s->tx_unicast_bytes +
 515             s->tx_multicast_bytes +
 516             s->tx_broadcast_bytes;
 517
 518         /* Update calculated offload counters */
 519         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 520         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 521
 522         /* Update per port counters */
 523         mlx5e_update_pport_counters(priv);
 524
 525 #if (__FreeBSD_version < 1100000)
 526         /* no get_counters interface in fbsd 10 */
 527         ifp->if_ipackets = s->rx_packets;
 528         ifp->if_ierrors = s->rx_error_packets;
 529         ifp->if_iqdrops = s->rx_out_of_buffer;
 530         ifp->if_opackets = s->tx_packets;
 531         ifp->if_oerrors = s->tx_error_packets;
 532         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 533         ifp->if_ibytes = s->rx_bytes;
 534         ifp->if_obytes = s->tx_bytes;
 535 #endif
 536
 537 free_out:
 538         kvfree(out);
 539         PRIV_UNLOCK(priv);
 540 }
 541
 542 static void
 543 mlx5e_update_stats(void *arg)
 544 {
 545         struct mlx5e_priv *priv = arg;
 546
 547         schedule_work(&priv->update_stats_work);
 548
 549         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 550 }
 551
 552 static void
 553 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 554     enum mlx5_dev_event event)
 555 {
 556         switch (event) {
 557         case MLX5_DEV_EVENT_PORT_UP:
 558         case MLX5_DEV_EVENT_PORT_DOWN:
 559                 schedule_work(&priv->update_carrier_work);
 560                 break;
 561
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 static void
 568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 569     enum mlx5_dev_event event, unsigned long param)
 570 {
 571         struct mlx5e_priv *priv = vpriv;
 572
 573         mtx_lock(&priv->async_events_mtx);
 574         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 575                 mlx5e_async_event_sub(priv, event);
 576         mtx_unlock(&priv->async_events_mtx);
 577 }
 578
 579 static void
 580 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 581 {
 582         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 583 }
 584
 585 static void
 586 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 587 {
 588         mtx_lock(&priv->async_events_mtx);
 589         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 590         mtx_unlock(&priv->async_events_mtx);
 591 }
 592
 593 static const char *mlx5e_rq_stats_desc[] = {
 594         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 595 };
 596
 597 static int
 598 mlx5e_create_rq(struct mlx5e_channel *c,
 599     struct mlx5e_rq_param *param,
 600     struct mlx5e_rq *rq)
 601 {
 602         struct mlx5e_priv *priv = c->priv;
 603         struct mlx5_core_dev *mdev = priv->mdev;
 604         char buffer[16];
 605         void *rqc = param->rqc;
 606         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 607         int wq_sz;
 608         int err;
 609         int i;
 610
 611         /* Create DMA descriptor TAG */
 612         if ((err = -bus_dma_tag_create(
 613             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 614             1,                          /* any alignment */
 615             0,                          /* no boundary */
 616             BUS_SPACE_MAXADDR,          /* lowaddr */
 617             BUS_SPACE_MAXADDR,          /* highaddr */
 618             NULL, NULL,                 /* filter, filterarg */
 619             MJUM16BYTES,                /* maxsize */
 620             1,                          /* nsegments */
 621             MJUM16BYTES,                /* maxsegsize */
 622             0,                          /* flags */
 623             NULL, NULL,                 /* lockfunc, lockfuncarg */
 624             &rq->dma_tag)))
 625                 goto done;
 626
 627         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 628             &rq->wq_ctrl);
 629         if (err)
 630                 goto err_free_dma_tag;
 631
 632         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 633
 634         if (priv->params.hw_lro_en) {
 635                 rq->wqe_sz = priv->params.lro_wqe_sz;
 636         } else {
 637                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 638         }
 639         if (rq->wqe_sz > MJUM16BYTES) {
 640                 err = -ENOMEM;
 641                 goto err_rq_wq_destroy;
 642         } else if (rq->wqe_sz > MJUM9BYTES) {
 643                 rq->wqe_sz = MJUM16BYTES;
 644         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 645                 rq->wqe_sz = MJUM9BYTES;
 646         } else if (rq->wqe_sz > MCLBYTES) {
 647                 rq->wqe_sz = MJUMPAGESIZE;
 648         } else {
 649                 rq->wqe_sz = MCLBYTES;
 650         }
 651
 652         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 653         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 654         if (rq->mbuf == NULL) {
 655                 err = -ENOMEM;
 656                 goto err_rq_wq_destroy;
 657         }
 658         for (i = 0; i != wq_sz; i++) {
 659                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 660                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 661
 662                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 663                 if (err != 0) {
 664                         while (i--)
 665                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 666                         goto err_rq_mbuf_free;
 667                 }
 668                 wqe->data.lkey = c->mkey_be;
 669                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 670         }
 671
 672         rq->ifp = c->ifp;
 673         rq->channel = c;
 674         rq->ix = c->ix;
 675
 676         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 677         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 678             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 679             rq->stats.arg);
 680
 681 #ifdef HAVE_TURBO_LRO
 682         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 683                 rq->lro.mbuf = NULL;
 684 #else
 685         if (tcp_lro_init(&rq->lro))
 686                 rq->lro.lro_cnt = 0;
 687         else
 688                 rq->lro.ifp = c->ifp;
 689 #endif
 690         return (0);
 691
 692 err_rq_mbuf_free:
 693         free(rq->mbuf, M_MLX5EN);
 694 err_rq_wq_destroy:
 695         mlx5_wq_destroy(&rq->wq_ctrl);
 696 err_free_dma_tag:
 697         bus_dma_tag_destroy(rq->dma_tag);
 698 done:
 699         return (err);
 700 }
 701
 702 static void
 703 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 704 {
 705         int wq_sz;
 706         int i;
 707
 708         /* destroy all sysctl nodes */
 709         sysctl_ctx_free(&rq->stats.ctx);
 710
 711         /* free leftover LRO packets, if any */
 712 #ifdef HAVE_TURBO_LRO
 713         tcp_tlro_free(&rq->lro);
 714 #else
 715         tcp_lro_free(&rq->lro);
 716 #endif
 717         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 718         for (i = 0; i != wq_sz; i++) {
 719                 if (rq->mbuf[i].mbuf != NULL) {
 720                         bus_dmamap_unload(rq->dma_tag,
 721                             rq->mbuf[i].dma_map);
 722                         m_freem(rq->mbuf[i].mbuf);
 723                 }
 724                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 725         }
 726         free(rq->mbuf, M_MLX5EN);
 727         mlx5_wq_destroy(&rq->wq_ctrl);
 728 }
 729
 730 static int
 731 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 732 {
 733         struct mlx5e_channel *c = rq->channel;
 734         struct mlx5e_priv *priv = c->priv;
 735         struct mlx5_core_dev *mdev = priv->mdev;
 736
 737         void *in;
 738         void *rqc;
 739         void *wq;
 740         int inlen;
 741         int err;
 742
 743         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 744             sizeof(u64) * rq->wq_ctrl.buf.npages;
 745         in = mlx5_vzalloc(inlen);
 746         if (in == NULL)
 747                 return (-ENOMEM);
 748
 749         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 750         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 751
 752         memcpy(rqc, param->rqc, sizeof(param->rqc));
 753
 754         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 755         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 756         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 757         if (priv->counter_set_id >= 0)
 758                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 759         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 760             PAGE_SHIFT);
 761         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 762
 763         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 764             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 765
 766         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 767
 768         kvfree(in);
 769
 770         return (err);
 771 }
 772
 773 static int
 774 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 775 {
 776         struct mlx5e_channel *c = rq->channel;
 777         struct mlx5e_priv *priv = c->priv;
 778         struct mlx5_core_dev *mdev = priv->mdev;
 779
 780         void *in;
 781         void *rqc;
 782         int inlen;
 783         int err;
 784
 785         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 786         in = mlx5_vzalloc(inlen);
 787         if (in == NULL)
 788                 return (-ENOMEM);
 789
 790         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 791
 792         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 793         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 794         MLX5_SET(rqc, rqc, state, next_state);
 795
 796         err = mlx5_core_modify_rq(mdev, in, inlen);
 797
 798         kvfree(in);
 799
 800         return (err);
 801 }
 802
 803 static void
 804 mlx5e_disable_rq(struct mlx5e_rq *rq)
 805 {
 806         struct mlx5e_channel *c = rq->channel;
 807         struct mlx5e_priv *priv = c->priv;
 808         struct mlx5_core_dev *mdev = priv->mdev;
 809
 810         mlx5_core_destroy_rq(mdev, rq->rqn);
 811 }
 812
 813 static int
 814 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 815 {
 816         struct mlx5e_channel *c = rq->channel;
 817         struct mlx5e_priv *priv = c->priv;
 818         struct mlx5_wq_ll *wq = &rq->wq;
 819         int i;
 820
 821         for (i = 0; i < 1000; i++) {
 822                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 823                         return (0);
 824
 825                 msleep(4);
 826         }
 827         return (-ETIMEDOUT);
 828 }
 829
 830 static int
 831 mlx5e_open_rq(struct mlx5e_channel *c,
 832     struct mlx5e_rq_param *param,
 833     struct mlx5e_rq *rq)
 834 {
 835         int err;
 836
 837         err = mlx5e_create_rq(c, param, rq);
 838         if (err)
 839                 return (err);
 840
 841         err = mlx5e_enable_rq(rq, param);
 842         if (err)
 843                 goto err_destroy_rq;
 844
 845         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 846         if (err)
 847                 goto err_disable_rq;
 848
 849         c->rq.enabled = 1;
 850
 851         return (0);
 852
 853 err_disable_rq:
 854         mlx5e_disable_rq(rq);
 855 err_destroy_rq:
 856         mlx5e_destroy_rq(rq);
 857
 858         return (err);
 859 }
 860
 861 static void
 862 mlx5e_close_rq(struct mlx5e_rq *rq)
 863 {
 864         rq->enabled = 0;
 865         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 866 }
 867
 868 static void
 869 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 870 {
 871         /* wait till RQ is empty */
 872         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 873                 msleep(4);
 874                 rq->cq.mcq.comp(&rq->cq.mcq);
 875         }
 876
 877         mlx5e_disable_rq(rq);
 878         mlx5e_destroy_rq(rq);
 879 }
 880
 881 void
 882 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 883 {
 884         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 885         int x;
 886
 887         for (x = 0; x != wq_sz; x++)
 888                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 889         free(sq->mbuf, M_MLX5EN);
 890 }
 891
 892 int
 893 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 894 {
 895         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 896         int err;
 897         int x;
 898
 899         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 900         if (sq->mbuf == NULL)
 901                 return (-ENOMEM);
 902
 903         /* Create DMA descriptor MAPs */
 904         for (x = 0; x != wq_sz; x++) {
 905                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 906                 if (err != 0) {
 907                         while (x--)
 908                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 909                         free(sq->mbuf, M_MLX5EN);
 910                         return (err);
 911                 }
 912         }
 913         return (0);
 914 }
 915
 916 static const char *mlx5e_sq_stats_desc[] = {
 917         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 918 };
 919
 920 static int
 921 mlx5e_create_sq(struct mlx5e_channel *c,
 922     int tc,
 923     struct mlx5e_sq_param *param,
 924     struct mlx5e_sq *sq)
 925 {
 926         struct mlx5e_priv *priv = c->priv;
 927         struct mlx5_core_dev *mdev = priv->mdev;
 928         char buffer[16];
 929
 930         void *sqc = param->sqc;
 931         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 932 #ifdef RSS
 933         cpuset_t cpu_mask;
 934         int cpu_id;
 935 #endif
 936         int err;
 937
 938         /* Create DMA descriptor TAG */
 939         if ((err = -bus_dma_tag_create(
 940             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 941             1,                          /* any alignment */
 942             0,                          /* no boundary */
 943             BUS_SPACE_MAXADDR,          /* lowaddr */
 944             BUS_SPACE_MAXADDR,          /* highaddr */
 945             NULL, NULL,                 /* filter, filterarg */
 946             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 947             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 948             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 949             0,                          /* flags */
 950             NULL, NULL,                 /* lockfunc, lockfuncarg */
 951             &sq->dma_tag)))
 952                 goto done;
 953
 954         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 955         if (err)
 956                 goto err_free_dma_tag;
 957
 958         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 959             &sq->wq_ctrl);
 960         if (err)
 961                 goto err_unmap_free_uar;
 962
 963         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 964         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 965
 966         err = mlx5e_alloc_sq_db(sq);
 967         if (err)
 968                 goto err_sq_wq_destroy;
 969
 970         sq->mkey_be = c->mkey_be;
 971         sq->ifp = priv->ifp;
 972         sq->priv = priv;
 973         sq->tc = tc;
 974
 975         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
 976             M_WAITOK, &sq->lock);
 977         if (sq->br == NULL) {
 978                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
 979                     __func__);
 980                 err = -ENOMEM;
 981                 goto err_free_sq_db;
 982         }
 983
 984         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
 985             taskqueue_thread_enqueue, &sq->sq_tq);
 986         if (sq->sq_tq == NULL) {
 987                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
 988                     __func__);
 989                 err = -ENOMEM;
 990                 goto err_free_drbr;
 991         }
 992
 993         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
 994 #ifdef RSS
 995         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
 996         CPU_SETOF(cpu_id, &cpu_mask);
 997         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
 998             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
 999 #else
1000         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1001             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1002 #endif
1003         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1004         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1005             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1006             sq->stats.arg);
1007
1008         return (0);
1009
1010 err_free_drbr:
1011         buf_ring_free(sq->br, M_MLX5EN);
1012 err_free_sq_db:
1013         mlx5e_free_sq_db(sq);
1014 err_sq_wq_destroy:
1015         mlx5_wq_destroy(&sq->wq_ctrl);
1016
1017 err_unmap_free_uar:
1018         mlx5_unmap_free_uar(mdev, &sq->uar);
1019
1020 err_free_dma_tag:
1021         bus_dma_tag_destroy(sq->dma_tag);
1022 done:
1023         return (err);
1024 }
1025
1026 static void
1027 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1028 {
1029         /* destroy all sysctl nodes */
1030         sysctl_ctx_free(&sq->stats.ctx);
1031
1032         mlx5e_free_sq_db(sq);
1033         mlx5_wq_destroy(&sq->wq_ctrl);
1034         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1035         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1036         taskqueue_free(sq->sq_tq);
1037         buf_ring_free(sq->br, M_MLX5EN);
1038 }
1039
1040 int
1041 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1042     int tis_num)
1043 {
1044         void *in;
1045         void *sqc;
1046         void *wq;
1047         int inlen;
1048         int err;
1049
1050         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1051             sizeof(u64) * sq->wq_ctrl.buf.npages;
1052         in = mlx5_vzalloc(inlen);
1053         if (in == NULL)
1054                 return (-ENOMEM);
1055
1056         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1057         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1058
1059         memcpy(sqc, param->sqc, sizeof(param->sqc));
1060
1061         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1062         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1063         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1064         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1065         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1066
1067         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1068         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1069         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1070             PAGE_SHIFT);
1071         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1072
1073         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1074             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1075
1076         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1077
1078         kvfree(in);
1079
1080         return (err);
1081 }
1082
1083 int
1084 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1085 {
1086         void *in;
1087         void *sqc;
1088         int inlen;
1089         int err;
1090
1091         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1092         in = mlx5_vzalloc(inlen);
1093         if (in == NULL)
1094                 return (-ENOMEM);
1095
1096         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1097
1098         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1099         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1100         MLX5_SET(sqc, sqc, state, next_state);
1101
1102         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1103
1104         kvfree(in);
1105
1106         return (err);
1107 }
1108
1109 void
1110 mlx5e_disable_sq(struct mlx5e_sq *sq)
1111 {
1112
1113         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1114 }
1115
1116 static int
1117 mlx5e_open_sq(struct mlx5e_channel *c,
1118     int tc,
1119     struct mlx5e_sq_param *param,
1120     struct mlx5e_sq *sq)
1121 {
1122         int err;
1123
1124         err = mlx5e_create_sq(c, tc, param, sq);
1125         if (err)
1126                 return (err);
1127
1128         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1129         if (err)
1130                 goto err_destroy_sq;
1131
1132         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1133         if (err)
1134                 goto err_disable_sq;
1135
1136         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1137
1138         return (0);
1139
1140 err_disable_sq:
1141         mlx5e_disable_sq(sq);
1142 err_destroy_sq:
1143         mlx5e_destroy_sq(sq);
1144
1145         return (err);
1146 }
1147
1148 static void
1149 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1150 {
1151         /* fill up remainder with NOPs */
1152         while (sq->cev_counter != 0) {
1153                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1154                         if (can_sleep != 0) {
1155                                 mtx_unlock(&sq->lock);
1156                                 msleep(4);
1157                                 mtx_lock(&sq->lock);
1158                         } else {
1159                                 goto done;
1160                         }
1161                 }
1162                 /* send a single NOP */
1163                 mlx5e_send_nop(sq, 1);
1164                 wmb();
1165         }
1166 done:
1167         /* Check if we need to write the doorbell */
1168         if (likely(sq->doorbell.d64 != 0)) {
1169                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1170                 sq->doorbell.d64 = 0;
1171         }
1172         return;
1173 }
1174
1175 void
1176 mlx5e_sq_cev_timeout(void *arg)
1177 {
1178         struct mlx5e_sq *sq = arg;
1179
1180         mtx_assert(&sq->lock, MA_OWNED);
1181
1182         /* check next state */
1183         switch (sq->cev_next_state) {
1184         case MLX5E_CEV_STATE_SEND_NOPS:
1185                 /* fill TX ring with NOPs, if any */
1186                 mlx5e_sq_send_nops_locked(sq, 0);
1187
1188                 /* check if completed */
1189                 if (sq->cev_counter == 0) {
1190                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1191                         return;
1192                 }
1193                 break;
1194         default:
1195                 /* send NOPs on next timeout */
1196                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1197                 break;
1198         }
1199
1200         /* restart timer */
1201         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1202 }
1203
1204 void
1205 mlx5e_drain_sq(struct mlx5e_sq *sq)
1206 {
1207
1208         mtx_lock(&sq->lock);
1209         /* teardown event factor timer, if any */
1210         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1211         callout_stop(&sq->cev_callout);
1212
1213         /* send dummy NOPs in order to flush the transmit ring */
1214         mlx5e_sq_send_nops_locked(sq, 1);
1215         mtx_unlock(&sq->lock);
1216
1217         /* make sure it is safe to free the callout */
1218         callout_drain(&sq->cev_callout);
1219
1220         /* error out remaining requests */
1221         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1222
1223         /* wait till SQ is empty */
1224         mtx_lock(&sq->lock);
1225         while (sq->cc != sq->pc) {
1226                 mtx_unlock(&sq->lock);
1227                 msleep(4);
1228                 sq->cq.mcq.comp(&sq->cq.mcq);
1229                 mtx_lock(&sq->lock);
1230         }
1231         mtx_unlock(&sq->lock);
1232 }
1233
1234 static void
1235 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1236 {
1237
1238         mlx5e_drain_sq(sq);
1239         mlx5e_disable_sq(sq);
1240         mlx5e_destroy_sq(sq);
1241 }
1242
1243 static int
1244 mlx5e_create_cq(struct mlx5e_priv *priv,
1245     struct mlx5e_cq_param *param,
1246     struct mlx5e_cq *cq,
1247     mlx5e_cq_comp_t *comp,
1248     int eq_ix)
1249 {
1250         struct mlx5_core_dev *mdev = priv->mdev;
1251         struct mlx5_core_cq *mcq = &cq->mcq;
1252         int eqn_not_used;
1253         int irqn;
1254         int err;
1255         u32 i;
1256
1257         param->wq.buf_numa_node = 0;
1258         param->wq.db_numa_node = 0;
1259
1260         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1261             &cq->wq_ctrl);
1262         if (err)
1263                 return (err);
1264
1265         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1266
1267         mcq->cqe_sz = 64;
1268         mcq->set_ci_db = cq->wq_ctrl.db.db;
1269         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1270         *mcq->set_ci_db = 0;
1271         *mcq->arm_db = 0;
1272         mcq->vector = eq_ix;
1273         mcq->comp = comp;
1274         mcq->event = mlx5e_cq_error_event;
1275         mcq->irqn = irqn;
1276         mcq->uar = &priv->cq_uar;
1277
1278         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1279                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1280
1281                 cqe->op_own = 0xf1;
1282         }
1283
1284         cq->priv = priv;
1285
1286         return (0);
1287 }
1288
1289 static void
1290 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1291 {
1292         mlx5_wq_destroy(&cq->wq_ctrl);
1293 }
1294
1295 static int
1296 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1297 {
1298         struct mlx5_core_cq *mcq = &cq->mcq;
1299         void *in;
1300         void *cqc;
1301         int inlen;
1302         int irqn_not_used;
1303         int eqn;
1304         int err;
1305
1306         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1307             sizeof(u64) * cq->wq_ctrl.buf.npages;
1308         in = mlx5_vzalloc(inlen);
1309         if (in == NULL)
1310                 return (-ENOMEM);
1311
1312         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1313
1314         memcpy(cqc, param->cqc, sizeof(param->cqc));
1315
1316         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1317             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1318
1319         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1320
1321         MLX5_SET(cqc, cqc, c_eqn, eqn);
1322         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1323         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1324             PAGE_SHIFT);
1325         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1326
1327         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1328
1329         kvfree(in);
1330
1331         if (err)
1332                 return (err);
1333
1334         mlx5e_cq_arm(cq);
1335
1336         return (0);
1337 }
1338
1339 static void
1340 mlx5e_disable_cq(struct mlx5e_cq *cq)
1341 {
1342
1343         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1344 }
1345
1346 int
1347 mlx5e_open_cq(struct mlx5e_priv *priv,
1348     struct mlx5e_cq_param *param,
1349     struct mlx5e_cq *cq,
1350     mlx5e_cq_comp_t *comp,
1351     int eq_ix)
1352 {
1353         int err;
1354
1355         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1356         if (err)
1357                 return (err);
1358
1359         err = mlx5e_enable_cq(cq, param, eq_ix);
1360         if (err)
1361                 goto err_destroy_cq;
1362
1363         return (0);
1364
1365 err_destroy_cq:
1366         mlx5e_destroy_cq(cq);
1367
1368         return (err);
1369 }
1370
1371 void
1372 mlx5e_close_cq(struct mlx5e_cq *cq)
1373 {
1374         mlx5e_disable_cq(cq);
1375         mlx5e_destroy_cq(cq);
1376 }
1377
1378 static int
1379 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1380     struct mlx5e_channel_param *cparam)
1381 {
1382         int err;
1383         int tc;
1384
1385         for (tc = 0; tc < c->num_tc; tc++) {
1386                 /* open completion queue */
1387                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1388                     &mlx5e_tx_cq_comp, c->ix);
1389                 if (err)
1390                         goto err_close_tx_cqs;
1391         }
1392         return (0);
1393
1394 err_close_tx_cqs:
1395         for (tc--; tc >= 0; tc--)
1396                 mlx5e_close_cq(&c->sq[tc].cq);
1397
1398         return (err);
1399 }
1400
1401 static void
1402 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1403 {
1404         int tc;
1405
1406         for (tc = 0; tc < c->num_tc; tc++)
1407                 mlx5e_close_cq(&c->sq[tc].cq);
1408 }
1409
1410 static int
1411 mlx5e_open_sqs(struct mlx5e_channel *c,
1412     struct mlx5e_channel_param *cparam)
1413 {
1414         int err;
1415         int tc;
1416
1417         for (tc = 0; tc < c->num_tc; tc++) {
1418                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1419                 if (err)
1420                         goto err_close_sqs;
1421         }
1422
1423         return (0);
1424
1425 err_close_sqs:
1426         for (tc--; tc >= 0; tc--)
1427                 mlx5e_close_sq_wait(&c->sq[tc]);
1428
1429         return (err);
1430 }
1431
1432 static void
1433 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1434 {
1435         int tc;
1436
1437         for (tc = 0; tc < c->num_tc; tc++)
1438                 mlx5e_close_sq_wait(&c->sq[tc]);
1439 }
1440
1441 static void
1442 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1443 {
1444         int tc;
1445
1446         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1447
1448         for (tc = 0; tc < c->num_tc; tc++) {
1449                 struct mlx5e_sq *sq = c->sq + tc;
1450
1451                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1452                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1453                     MTX_DEF);
1454
1455                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1456
1457                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1458
1459                 /* ensure the TX completion event factor is not zero */
1460                 if (sq->cev_factor == 0)
1461                         sq->cev_factor = 1;
1462         }
1463 }
1464
1465 static void
1466 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1467 {
1468         int tc;
1469
1470         mtx_destroy(&c->rq.mtx);
1471
1472         for (tc = 0; tc < c->num_tc; tc++) {
1473                 mtx_destroy(&c->sq[tc].lock);
1474                 mtx_destroy(&c->sq[tc].comp_lock);
1475         }
1476 }
1477
1478 static int
1479 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1480     struct mlx5e_channel_param *cparam,
1481     struct mlx5e_channel *volatile *cp)
1482 {
1483         struct mlx5e_channel *c;
1484         int err;
1485
1486         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1487         if (c == NULL)
1488                 return (-ENOMEM);
1489
1490         c->priv = priv;
1491         c->ix = ix;
1492         c->cpu = 0;
1493         c->ifp = priv->ifp;
1494         c->mkey_be = cpu_to_be32(priv->mr.key);
1495         c->num_tc = priv->num_tc;
1496
1497         /* init mutexes */
1498         mlx5e_chan_mtx_init(c);
1499
1500         /* open transmit completion queue */
1501         err = mlx5e_open_tx_cqs(c, cparam);
1502         if (err)
1503                 goto err_free;
1504
1505         /* open receive completion queue */
1506         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1507             &mlx5e_rx_cq_comp, c->ix);
1508         if (err)
1509                 goto err_close_tx_cqs;
1510
1511         err = mlx5e_open_sqs(c, cparam);
1512         if (err)
1513                 goto err_close_rx_cq;
1514
1515         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1516         if (err)
1517                 goto err_close_sqs;
1518
1519         /* store channel pointer */
1520         *cp = c;
1521
1522         /* poll receive queue initially */
1523         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1524
1525         return (0);
1526
1527 err_close_sqs:
1528         mlx5e_close_sqs_wait(c);
1529
1530 err_close_rx_cq:
1531         mlx5e_close_cq(&c->rq.cq);
1532
1533 err_close_tx_cqs:
1534         mlx5e_close_tx_cqs(c);
1535
1536 err_free:
1537         /* destroy mutexes */
1538         mlx5e_chan_mtx_destroy(c);
1539         free(c, M_MLX5EN);
1540         return (err);
1541 }
1542
1543 static void
1544 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1545 {
1546         struct mlx5e_channel *c = *pp;
1547
1548         /* check if channel is already closed */
1549         if (c == NULL)
1550                 return;
1551         mlx5e_close_rq(&c->rq);
1552 }
1553
1554 static void
1555 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1556 {
1557         struct mlx5e_channel *c = *pp;
1558
1559         /* check if channel is already closed */
1560         if (c == NULL)
1561                 return;
1562         /* ensure channel pointer is no longer used */
1563         *pp = NULL;
1564
1565         mlx5e_close_rq_wait(&c->rq);
1566         mlx5e_close_sqs_wait(c);
1567         mlx5e_close_cq(&c->rq.cq);
1568         mlx5e_close_tx_cqs(c);
1569         /* destroy mutexes */
1570         mlx5e_chan_mtx_destroy(c);
1571         free(c, M_MLX5EN);
1572 }
1573
1574 static void
1575 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1576     struct mlx5e_rq_param *param)
1577 {
1578         void *rqc = param->rqc;
1579         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1580
1581         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1582         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1583         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1584         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1585         MLX5_SET(wq, wq, pd, priv->pdn);
1586
1587         param->wq.buf_numa_node = 0;
1588         param->wq.db_numa_node = 0;
1589         param->wq.linear = 1;
1590 }
1591
1592 static void
1593 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1594     struct mlx5e_sq_param *param)
1595 {
1596         void *sqc = param->sqc;
1597         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1598
1599         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1600         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1601         MLX5_SET(wq, wq, pd, priv->pdn);
1602
1603         param->wq.buf_numa_node = 0;
1604         param->wq.db_numa_node = 0;
1605         param->wq.linear = 1;
1606 }
1607
1608 static void
1609 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1610     struct mlx5e_cq_param *param)
1611 {
1612         void *cqc = param->cqc;
1613
1614         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1615 }
1616
1617 static void
1618 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1619     struct mlx5e_cq_param *param)
1620 {
1621         void *cqc = param->cqc;
1622
1623
1624         /*
1625          * TODO The sysctl to control on/off is a bool value for now, which means
1626          * we only support CSUM, once HASH is implemnted we'll need to address that.
1627          */
1628         if (priv->params.cqe_zipping_en) {
1629                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1630                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1631         }
1632
1633         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1634         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1635         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1636
1637         switch (priv->params.rx_cq_moderation_mode) {
1638         case 0:
1639                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1640                 break;
1641         default:
1642                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1643                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1644                 else
1645                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1646                 break;
1647         }
1648
1649         mlx5e_build_common_cq_param(priv, param);
1650 }
1651
1652 static void
1653 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1654     struct mlx5e_cq_param *param)
1655 {
1656         void *cqc = param->cqc;
1657
1658         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1659         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1660         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1661
1662         switch (priv->params.tx_cq_moderation_mode) {
1663         case 0:
1664                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1665                 break;
1666         default:
1667                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1668                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1669                 else
1670                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1671                 break;
1672         }
1673
1674         mlx5e_build_common_cq_param(priv, param);
1675 }
1676
1677 static void
1678 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1679     struct mlx5e_channel_param *cparam)
1680 {
1681         memset(cparam, 0, sizeof(*cparam));
1682
1683         mlx5e_build_rq_param(priv, &cparam->rq);
1684         mlx5e_build_sq_param(priv, &cparam->sq);
1685         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1686         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1687 }
1688
1689 static int
1690 mlx5e_open_channels(struct mlx5e_priv *priv)
1691 {
1692         struct mlx5e_channel_param cparam;
1693         void *ptr;
1694         int err;
1695         int i;
1696         int j;
1697
1698         priv->channel = malloc(priv->params.num_channels *
1699             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1700         if (priv->channel == NULL)
1701                 return (-ENOMEM);
1702
1703         mlx5e_build_channel_param(priv, &cparam);
1704         for (i = 0; i < priv->params.num_channels; i++) {
1705                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1706                 if (err)
1707                         goto err_close_channels;
1708         }
1709
1710         for (j = 0; j < priv->params.num_channels; j++) {
1711                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1712                 if (err)
1713                         goto err_close_channels;
1714         }
1715
1716         return (0);
1717
1718 err_close_channels:
1719         for (i--; i >= 0; i--) {
1720                 mlx5e_close_channel(&priv->channel[i]);
1721                 mlx5e_close_channel_wait(&priv->channel[i]);
1722         }
1723
1724         /* remove "volatile" attribute from "channel" pointer */
1725         ptr = __DECONST(void *, priv->channel);
1726         priv->channel = NULL;
1727
1728         free(ptr, M_MLX5EN);
1729
1730         return (err);
1731 }
1732
1733 static void
1734 mlx5e_close_channels(struct mlx5e_priv *priv)
1735 {
1736         void *ptr;
1737         int i;
1738
1739         if (priv->channel == NULL)
1740                 return;
1741
1742         for (i = 0; i < priv->params.num_channels; i++)
1743                 mlx5e_close_channel(&priv->channel[i]);
1744         for (i = 0; i < priv->params.num_channels; i++)
1745                 mlx5e_close_channel_wait(&priv->channel[i]);
1746
1747         /* remove "volatile" attribute from "channel" pointer */
1748         ptr = __DECONST(void *, priv->channel);
1749         priv->channel = NULL;
1750
1751         free(ptr, M_MLX5EN);
1752 }
1753
1754 static int
1755 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1756 {
1757         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1758             priv->params.tx_cq_moderation_usec,
1759             priv->params.tx_cq_moderation_pkts));
1760 }
1761
1762 static int
1763 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1764 {
1765         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1766             priv->params.rx_cq_moderation_usec,
1767             priv->params.rx_cq_moderation_pkts));
1768 }
1769
1770 static int
1771 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1772 {
1773         int err;
1774         int i;
1775
1776         if (c == NULL)
1777                 return (EINVAL);
1778
1779         err = mlx5e_refresh_rq_params(priv, &c->rq);
1780         if (err)
1781                 goto done;
1782
1783         for (i = 0; i != c->num_tc; i++) {
1784                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1785                 if (err)
1786                         goto done;
1787         }
1788 done:
1789         return (err);
1790 }
1791
1792 int
1793 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1794 {
1795         int i;
1796
1797         if (priv->channel == NULL)
1798                 return (EINVAL);
1799
1800         for (i = 0; i < priv->params.num_channels; i++) {
1801                 int err;
1802
1803                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1804                 if (err)
1805                         return (err);
1806         }
1807         return (0);
1808 }
1809
1810 static int
1811 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1812 {
1813         struct mlx5_core_dev *mdev = priv->mdev;
1814         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1815         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1816
1817         memset(in, 0, sizeof(in));
1818
1819         MLX5_SET(tisc, tisc, prio, tc);
1820         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1821
1822         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1823 }
1824
1825 static void
1826 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1827 {
1828         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1829 }
1830
1831 static int
1832 mlx5e_open_tises(struct mlx5e_priv *priv)
1833 {
1834         int num_tc = priv->num_tc;
1835         int err;
1836         int tc;
1837
1838         for (tc = 0; tc < num_tc; tc++) {
1839                 err = mlx5e_open_tis(priv, tc);
1840                 if (err)
1841                         goto err_close_tises;
1842         }
1843
1844         return (0);
1845
1846 err_close_tises:
1847         for (tc--; tc >= 0; tc--)
1848                 mlx5e_close_tis(priv, tc);
1849
1850         return (err);
1851 }
1852
1853 static void
1854 mlx5e_close_tises(struct mlx5e_priv *priv)
1855 {
1856         int num_tc = priv->num_tc;
1857         int tc;
1858
1859         for (tc = 0; tc < num_tc; tc++)
1860                 mlx5e_close_tis(priv, tc);
1861 }
1862
1863 static int
1864 mlx5e_open_rqt(struct mlx5e_priv *priv)
1865 {
1866         struct mlx5_core_dev *mdev = priv->mdev;
1867         u32 *in;
1868         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1869         void *rqtc;
1870         int inlen;
1871         int err;
1872         int sz;
1873         int i;
1874
1875         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1876
1877         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1878         in = mlx5_vzalloc(inlen);
1879         if (in == NULL)
1880                 return (-ENOMEM);
1881         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1882
1883         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1884         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1885
1886         for (i = 0; i < sz; i++) {
1887                 int ix;
1888 #ifdef RSS
1889                 ix = rss_get_indirection_to_bucket(i);
1890 #else
1891                 ix = i;
1892 #endif
1893                 /* ensure we don't overflow */
1894                 ix %= priv->params.num_channels;
1895                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1896         }
1897
1898         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1899
1900         memset(out, 0, sizeof(out));
1901         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1902         if (!err)
1903                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1904
1905         kvfree(in);
1906
1907         return (err);
1908 }
1909
1910 static void
1911 mlx5e_close_rqt(struct mlx5e_priv *priv)
1912 {
1913         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1914         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1915
1916         memset(in, 0, sizeof(in));
1917
1918         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1919         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1920
1921         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1922             sizeof(out));
1923 }
1924
1925 static void
1926 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1927 {
1928         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1929         __be32 *hkey;
1930
1931         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1932
1933 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1934
1935 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1936                           MLX5_HASH_FIELD_SEL_DST_IP)
1937
1938 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1939                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1940                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1941                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1942
1943 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1944                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1945                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1946
1947         if (priv->params.hw_lro_en) {
1948                 MLX5_SET(tirc, tirc, lro_enable_mask,
1949                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1950                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1951                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1952                     (priv->params.lro_wqe_sz -
1953                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1954                 /* TODO: add the option to choose timer value dynamically */
1955                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1956                     MLX5_CAP_ETH(priv->mdev,
1957                     lro_timer_supported_periods[2]));
1958         }
1959
1960         /* setup parameters for hashing TIR type, if any */
1961         switch (tt) {
1962         case MLX5E_TT_ANY:
1963                 MLX5_SET(tirc, tirc, disp_type,
1964                     MLX5_TIRC_DISP_TYPE_DIRECT);
1965                 MLX5_SET(tirc, tirc, inline_rqn,
1966                     priv->channel[0]->rq.rqn);
1967                 break;
1968         default:
1969                 MLX5_SET(tirc, tirc, disp_type,
1970                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1971                 MLX5_SET(tirc, tirc, indirect_table,
1972                     priv->rqtn);
1973                 MLX5_SET(tirc, tirc, rx_hash_fn,
1974                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1975                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1976 #ifdef RSS
1977                 /*
1978                  * The FreeBSD RSS implementation does currently not
1979                  * support symmetric Toeplitz hashes:
1980                  */
1981                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1982                 rss_getkey((uint8_t *)hkey);
1983 #else
1984                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1985                 hkey[0] = cpu_to_be32(0xD181C62C);
1986                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1987                 hkey[2] = cpu_to_be32(0x1983A2FC);
1988                 hkey[3] = cpu_to_be32(0x943E1ADB);
1989                 hkey[4] = cpu_to_be32(0xD9389E6B);
1990                 hkey[5] = cpu_to_be32(0xD1039C2C);
1991                 hkey[6] = cpu_to_be32(0xA74499AD);
1992                 hkey[7] = cpu_to_be32(0x593D56D9);
1993                 hkey[8] = cpu_to_be32(0xF3253C06);
1994                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
1995 #endif
1996                 break;
1997         }
1998
1999         switch (tt) {
2000         case MLX5E_TT_IPV4_TCP:
2001                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2002                     MLX5_L3_PROT_TYPE_IPV4);
2003                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2004                     MLX5_L4_PROT_TYPE_TCP);
2005 #ifdef RSS
2006                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2007                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2008                             MLX5_HASH_IP);
2009                 } else
2010 #endif
2011                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2012                     MLX5_HASH_ALL);
2013                 break;
2014
2015         case MLX5E_TT_IPV6_TCP:
2016                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2017                     MLX5_L3_PROT_TYPE_IPV6);
2018                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2019                     MLX5_L4_PROT_TYPE_TCP);
2020 #ifdef RSS
2021                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2022                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2023                             MLX5_HASH_IP);
2024                 } else
2025 #endif
2026                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2027                     MLX5_HASH_ALL);
2028                 break;
2029
2030         case MLX5E_TT_IPV4_UDP:
2031                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2032                     MLX5_L3_PROT_TYPE_IPV4);
2033                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2034                     MLX5_L4_PROT_TYPE_UDP);
2035 #ifdef RSS
2036                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2037                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2038                             MLX5_HASH_IP);
2039                 } else
2040 #endif
2041                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2042                     MLX5_HASH_ALL);
2043                 break;
2044
2045         case MLX5E_TT_IPV6_UDP:
2046                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2047                     MLX5_L3_PROT_TYPE_IPV6);
2048                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2049                     MLX5_L4_PROT_TYPE_UDP);
2050 #ifdef RSS
2051                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2052                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2053                             MLX5_HASH_IP);
2054                 } else
2055 #endif
2056                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2057                     MLX5_HASH_ALL);
2058                 break;
2059
2060         case MLX5E_TT_IPV4_IPSEC_AH:
2061                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2062                     MLX5_L3_PROT_TYPE_IPV4);
2063                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2064                     MLX5_HASH_IP_IPSEC_SPI);
2065                 break;
2066
2067         case MLX5E_TT_IPV6_IPSEC_AH:
2068                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2069                     MLX5_L3_PROT_TYPE_IPV6);
2070                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2071                     MLX5_HASH_IP_IPSEC_SPI);
2072                 break;
2073
2074         case MLX5E_TT_IPV4_IPSEC_ESP:
2075                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2076                     MLX5_L3_PROT_TYPE_IPV4);
2077                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2078                     MLX5_HASH_IP_IPSEC_SPI);
2079                 break;
2080
2081         case MLX5E_TT_IPV6_IPSEC_ESP:
2082                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2083                     MLX5_L3_PROT_TYPE_IPV6);
2084                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2085                     MLX5_HASH_IP_IPSEC_SPI);
2086                 break;
2087
2088         case MLX5E_TT_IPV4:
2089                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2090                     MLX5_L3_PROT_TYPE_IPV4);
2091                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2092                     MLX5_HASH_IP);
2093                 break;
2094
2095         case MLX5E_TT_IPV6:
2096                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2097                     MLX5_L3_PROT_TYPE_IPV6);
2098                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2099                     MLX5_HASH_IP);
2100                 break;
2101
2102         default:
2103                 break;
2104         }
2105 }
2106
2107 static int
2108 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2109 {
2110         struct mlx5_core_dev *mdev = priv->mdev;
2111         u32 *in;
2112         void *tirc;
2113         int inlen;
2114         int err;
2115
2116         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2117         in = mlx5_vzalloc(inlen);
2118         if (in == NULL)
2119                 return (-ENOMEM);
2120         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2121
2122         mlx5e_build_tir_ctx(priv, tirc, tt);
2123
2124         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2125
2126         kvfree(in);
2127
2128         return (err);
2129 }
2130
2131 static void
2132 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2133 {
2134         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2135 }
2136
2137 static int
2138 mlx5e_open_tirs(struct mlx5e_priv *priv)
2139 {
2140         int err;
2141         int i;
2142
2143         for (i = 0; i < MLX5E_NUM_TT; i++) {
2144                 err = mlx5e_open_tir(priv, i);
2145                 if (err)
2146                         goto err_close_tirs;
2147         }
2148
2149         return (0);
2150
2151 err_close_tirs:
2152         for (i--; i >= 0; i--)
2153                 mlx5e_close_tir(priv, i);
2154
2155         return (err);
2156 }
2157
2158 static void
2159 mlx5e_close_tirs(struct mlx5e_priv *priv)
2160 {
2161         int i;
2162
2163         for (i = 0; i < MLX5E_NUM_TT; i++)
2164                 mlx5e_close_tir(priv, i);
2165 }
2166
2167 /*
2168  * SW MTU does not include headers,
2169  * HW MTU includes all headers and checksums.
2170  */
2171 static int
2172 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2173 {
2174         struct mlx5e_priv *priv = ifp->if_softc;
2175         struct mlx5_core_dev *mdev = priv->mdev;
2176         int hw_mtu;
2177         int err;
2178
2179         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2180         if (err) {
2181                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2182                     __func__, sw_mtu, err);
2183                 return (err);
2184         }
2185         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2186         if (err) {
2187                 if_printf(ifp, "Query port MTU, after setting new "
2188                     "MTU value, failed\n");
2189         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2190                 err = -E2BIG,
2191                 if_printf(ifp, "Port MTU %d is smaller than "
2192                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2193         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2194                 err = -EINVAL;
2195                 if_printf(ifp, "Port MTU %d is bigger than "
2196                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2197         }
2198         ifp->if_mtu = sw_mtu;
2199         return (err);
2200 }
2201
2202 int
2203 mlx5e_open_locked(struct ifnet *ifp)
2204 {
2205         struct mlx5e_priv *priv = ifp->if_softc;
2206         int err;
2207         u16 set_id;
2208
2209         /* check if already opened */
2210         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2211                 return (0);
2212
2213 #ifdef RSS
2214         if (rss_getnumbuckets() > priv->params.num_channels) {
2215                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2216                     "channels(%u) available\n", rss_getnumbuckets(),
2217                     priv->params.num_channels);
2218         }
2219 #endif
2220         err = mlx5e_open_tises(priv);
2221         if (err) {
2222                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2223                     __func__, err);
2224                 return (err);
2225         }
2226         err = mlx5_vport_alloc_q_counter(priv->mdev,
2227             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2228         if (err) {
2229                 if_printf(priv->ifp,
2230                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2231                     __func__, err);
2232                 goto err_close_tises;
2233         }
2234         /* store counter set ID */
2235         priv->counter_set_id = set_id;
2236
2237         err = mlx5e_open_channels(priv);
2238         if (err) {
2239                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2240                     __func__, err);
2241                 goto err_dalloc_q_counter;
2242         }
2243         err = mlx5e_open_rqt(priv);
2244         if (err) {
2245                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2246                     __func__, err);
2247                 goto err_close_channels;
2248         }
2249         err = mlx5e_open_tirs(priv);
2250         if (err) {
2251                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2252                     __func__, err);
2253                 goto err_close_rqls;
2254         }
2255         err = mlx5e_open_flow_table(priv);
2256         if (err) {
2257                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2258                     __func__, err);
2259                 goto err_close_tirs;
2260         }
2261         err = mlx5e_add_all_vlan_rules(priv);
2262         if (err) {
2263                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2264                     __func__, err);
2265                 goto err_close_flow_table;
2266         }
2267         set_bit(MLX5E_STATE_OPENED, &priv->state);
2268
2269         mlx5e_update_carrier(priv);
2270         mlx5e_set_rx_mode_core(priv);
2271
2272         return (0);
2273
2274 err_close_flow_table:
2275         mlx5e_close_flow_table(priv);
2276
2277 err_close_tirs:
2278         mlx5e_close_tirs(priv);
2279
2280 err_close_rqls:
2281         mlx5e_close_rqt(priv);
2282
2283 err_close_channels:
2284         mlx5e_close_channels(priv);
2285
2286 err_dalloc_q_counter:
2287         mlx5_vport_dealloc_q_counter(priv->mdev,
2288             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2289
2290 err_close_tises:
2291         mlx5e_close_tises(priv);
2292
2293         return (err);
2294 }
2295
2296 static void
2297 mlx5e_open(void *arg)
2298 {
2299         struct mlx5e_priv *priv = arg;
2300
2301         PRIV_LOCK(priv);
2302         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2303                 if_printf(priv->ifp,
2304                     "%s: Setting port status to up failed\n",
2305                     __func__);
2306
2307         mlx5e_open_locked(priv->ifp);
2308         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2309         PRIV_UNLOCK(priv);
2310 }
2311
2312 int
2313 mlx5e_close_locked(struct ifnet *ifp)
2314 {
2315         struct mlx5e_priv *priv = ifp->if_softc;
2316
2317         /* check if already closed */
2318         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2319                 return (0);
2320
2321         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2322
2323         mlx5e_set_rx_mode_core(priv);
2324         mlx5e_del_all_vlan_rules(priv);
2325         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2326         mlx5e_close_flow_table(priv);
2327         mlx5e_close_tirs(priv);
2328         mlx5e_close_rqt(priv);
2329         mlx5e_close_channels(priv);
2330         mlx5_vport_dealloc_q_counter(priv->mdev,
2331             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2332         mlx5e_close_tises(priv);
2333
2334         return (0);
2335 }
2336
2337 #if (__FreeBSD_version >= 1100000)
2338 static uint64_t
2339 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2340 {
2341         struct mlx5e_priv *priv = ifp->if_softc;
2342         u64 retval;
2343
2344         /* PRIV_LOCK(priv); XXX not allowed */
2345         switch (cnt) {
2346         case IFCOUNTER_IPACKETS:
2347                 retval = priv->stats.vport.rx_packets;
2348                 break;
2349         case IFCOUNTER_IERRORS:
2350                 retval = priv->stats.vport.rx_error_packets;
2351                 break;
2352         case IFCOUNTER_IQDROPS:
2353                 retval = priv->stats.vport.rx_out_of_buffer;
2354                 break;
2355         case IFCOUNTER_OPACKETS:
2356                 retval = priv->stats.vport.tx_packets;
2357                 break;
2358         case IFCOUNTER_OERRORS:
2359                 retval = priv->stats.vport.tx_error_packets;
2360                 break;
2361         case IFCOUNTER_IBYTES:
2362                 retval = priv->stats.vport.rx_bytes;
2363                 break;
2364         case IFCOUNTER_OBYTES:
2365                 retval = priv->stats.vport.tx_bytes;
2366                 break;
2367         case IFCOUNTER_IMCASTS:
2368                 retval = priv->stats.vport.rx_multicast_packets;
2369                 break;
2370         case IFCOUNTER_OMCASTS:
2371                 retval = priv->stats.vport.tx_multicast_packets;
2372                 break;
2373         case IFCOUNTER_OQDROPS:
2374                 retval = priv->stats.vport.tx_queue_dropped;
2375                 break;
2376         default:
2377                 retval = if_get_counter_default(ifp, cnt);
2378                 break;
2379         }
2380         /* PRIV_UNLOCK(priv); XXX not allowed */
2381         return (retval);
2382 }
2383 #endif
2384
2385 static void
2386 mlx5e_set_rx_mode(struct ifnet *ifp)
2387 {
2388         struct mlx5e_priv *priv = ifp->if_softc;
2389
2390         schedule_work(&priv->set_rx_mode_work);
2391 }
2392
2393 static int
2394 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2395 {
2396         struct mlx5e_priv *priv;
2397         struct ifreq *ifr;
2398         struct ifi2creq i2c;
2399         int error = 0;
2400         int mask = 0;
2401         int size_read = 0;
2402         int module_num;
2403         int max_mtu;
2404         uint8_t read_addr;
2405
2406         priv = ifp->if_softc;
2407
2408         /* check if detaching */
2409         if (priv == NULL || priv->gone != 0)
2410                 return (ENXIO);
2411
2412         switch (command) {
2413         case SIOCSIFMTU:
2414                 ifr = (struct ifreq *)data;
2415
2416                 PRIV_LOCK(priv);
2417                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2418
2419                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2420                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2421                         int was_opened;
2422
2423                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2424                         if (was_opened)
2425                                 mlx5e_close_locked(ifp);
2426
2427                         /* set new MTU */
2428                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2429
2430                         if (was_opened)
2431                                 mlx5e_open_locked(ifp);
2432                 } else {
2433                         error = EINVAL;
2434                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2435                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2436                 }
2437                 PRIV_UNLOCK(priv);
2438                 break;
2439         case SIOCSIFFLAGS:
2440                 if ((ifp->if_flags & IFF_UP) &&
2441                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2442                         mlx5e_set_rx_mode(ifp);
2443                         break;
2444                 }
2445                 PRIV_LOCK(priv);
2446                 if (ifp->if_flags & IFF_UP) {
2447                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2448                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2449                                         mlx5e_open_locked(ifp);
2450                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2451                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2452                         }
2453                 } else {
2454                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2455                                 mlx5_set_port_status(priv->mdev,
2456                                     MLX5_PORT_DOWN);
2457                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2458                                         mlx5e_close_locked(ifp);
2459                                 mlx5e_update_carrier(priv);
2460                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2461                         }
2462                 }
2463                 PRIV_UNLOCK(priv);
2464                 break;
2465         case SIOCADDMULTI:
2466         case SIOCDELMULTI:
2467                 mlx5e_set_rx_mode(ifp);
2468                 break;
2469         case SIOCSIFMEDIA:
2470         case SIOCGIFMEDIA:
2471         case SIOCGIFXMEDIA:
2472                 ifr = (struct ifreq *)data;
2473                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2474                 break;
2475         case SIOCSIFCAP:
2476                 ifr = (struct ifreq *)data;
2477                 PRIV_LOCK(priv);
2478                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2479
2480                 if (mask & IFCAP_TXCSUM) {
2481                         ifp->if_capenable ^= IFCAP_TXCSUM;
2482                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2483
2484                         if (IFCAP_TSO4 & ifp->if_capenable &&
2485                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2486                                 ifp->if_capenable &= ~IFCAP_TSO4;
2487                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2488                                 if_printf(ifp,
2489                                     "tso4 disabled due to -txcsum.\n");
2490                         }
2491                 }
2492                 if (mask & IFCAP_TXCSUM_IPV6) {
2493                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2494                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2495
2496                         if (IFCAP_TSO6 & ifp->if_capenable &&
2497                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2498                                 ifp->if_capenable &= ~IFCAP_TSO6;
2499                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2500                                 if_printf(ifp,
2501                                     "tso6 disabled due to -txcsum6.\n");
2502                         }
2503                 }
2504                 if (mask & IFCAP_RXCSUM)
2505                         ifp->if_capenable ^= IFCAP_RXCSUM;
2506                 if (mask & IFCAP_RXCSUM_IPV6)
2507                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2508                 if (mask & IFCAP_TSO4) {
2509                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2510                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2511                                 if_printf(ifp, "enable txcsum first.\n");
2512                                 error = EAGAIN;
2513                                 goto out;
2514                         }
2515                         ifp->if_capenable ^= IFCAP_TSO4;
2516                         ifp->if_hwassist ^= CSUM_IP_TSO;
2517                 }
2518                 if (mask & IFCAP_TSO6) {
2519                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2520                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2521                                 if_printf(ifp, "enable txcsum6 first.\n");
2522                                 error = EAGAIN;
2523                                 goto out;
2524                         }
2525                         ifp->if_capenable ^= IFCAP_TSO6;
2526                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2527                 }
2528                 if (mask & IFCAP_VLAN_HWFILTER) {
2529                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2530                                 mlx5e_disable_vlan_filter(priv);
2531                         else
2532                                 mlx5e_enable_vlan_filter(priv);
2533
2534                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2535                 }
2536                 if (mask & IFCAP_VLAN_HWTAGGING)
2537                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2538                 if (mask & IFCAP_WOL_MAGIC)
2539                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2540
2541                 VLAN_CAPABILITIES(ifp);
2542                 /* turn off LRO means also turn of HW LRO - if it's on */
2543                 if (mask & IFCAP_LRO) {
2544                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2545                         bool need_restart = false;
2546
2547                         ifp->if_capenable ^= IFCAP_LRO;
2548                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2549                                 if (priv->params.hw_lro_en) {
2550                                         priv->params.hw_lro_en = false;
2551                                         need_restart = true;
2552                                         /* Not sure this is the correct way */
2553                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2554                                 }
2555                         }
2556                         if (was_opened && need_restart) {
2557                                 mlx5e_close_locked(ifp);
2558                                 mlx5e_open_locked(ifp);
2559                         }
2560                 }
2561 out:
2562                 PRIV_UNLOCK(priv);
2563                 break;
2564
2565         case SIOCGI2C:
2566                 ifr = (struct ifreq *)data;
2567
2568                 /*
2569                  * Copy from the user-space address ifr_data to the
2570                  * kernel-space address i2c
2571                  */
2572                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2573                 if (error)
2574                         break;
2575
2576                 if (i2c.len > sizeof(i2c.data)) {
2577                         error = EINVAL;
2578                         break;
2579                 }
2580
2581                 PRIV_LOCK(priv);
2582                 /* Get module_num which is required for the query_eeprom */
2583                 error = mlx5_query_module_num(priv->mdev, &module_num);
2584                 if (error) {
2585                         if_printf(ifp, "Query module num failed, eeprom "
2586                             "reading is not supported\n");
2587                         error = EINVAL;
2588                         goto err_i2c;
2589                 }
2590                 /* Check if module is present before doing an access */
2591                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2592                     MLX5_MODULE_STATUS_PLUGGED) {
2593                         error = EINVAL;
2594                         goto err_i2c;
2595                 }
2596                 /*
2597                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2598                  * The internal conversion is as follows:
2599                  */
2600                 if (i2c.dev_addr == 0xA0)
2601                         read_addr = MLX5E_I2C_ADDR_LOW;
2602                 else if (i2c.dev_addr == 0xA2)
2603                         read_addr = MLX5E_I2C_ADDR_HIGH;
2604                 else {
2605                         if_printf(ifp, "Query eeprom failed, "
2606                             "Invalid Address: %X\n", i2c.dev_addr);
2607                         error = EINVAL;
2608                         goto err_i2c;
2609                 }
2610                 error = mlx5_query_eeprom(priv->mdev,
2611                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2612                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2613                     (uint32_t *)i2c.data, &size_read);
2614                 if (error) {
2615                         if_printf(ifp, "Query eeprom failed, eeprom "
2616                             "reading is not supported\n");
2617                         error = EINVAL;
2618                         goto err_i2c;
2619                 }
2620
2621                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2622                         error = mlx5_query_eeprom(priv->mdev,
2623                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2624                             (uint32_t)(i2c.offset + size_read),
2625                             (uint32_t)(i2c.len - size_read), module_num,
2626                             (uint32_t *)(i2c.data + size_read), &size_read);
2627                 }
2628                 if (error) {
2629                         if_printf(ifp, "Query eeprom failed, eeprom "
2630                             "reading is not supported\n");
2631                         error = EINVAL;
2632                         goto err_i2c;
2633                 }
2634
2635                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2636 err_i2c:
2637                 PRIV_UNLOCK(priv);
2638                 break;
2639
2640         default:
2641                 error = ether_ioctl(ifp, command, data);
2642                 break;
2643         }
2644         return (error);
2645 }
2646
2647 static int
2648 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2649 {
2650         /*
2651          * TODO: uncoment once FW really sets all these bits if
2652          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2653          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2654          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2655          * -ENOTSUPP;
2656          */
2657
2658         /* TODO: add more must-to-have features */
2659
2660         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2661                 return (-ENODEV);
2662
2663         return (0);
2664 }
2665
2666 static void
2667 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2668     struct mlx5e_priv *priv,
2669     int num_comp_vectors)
2670 {
2671         /*
2672          * TODO: Consider link speed for setting "log_sq_size",
2673          * "log_rq_size" and "cq_moderation_xxx":
2674          */
2675         priv->params.log_sq_size =
2676             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2677         priv->params.log_rq_size =
2678             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2679         priv->params.rx_cq_moderation_usec =
2680             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2681             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2682             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2683         priv->params.rx_cq_moderation_mode =
2684             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2685         priv->params.rx_cq_moderation_pkts =
2686             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2687         priv->params.tx_cq_moderation_usec =
2688             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2689         priv->params.tx_cq_moderation_pkts =
2690             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2691         priv->params.min_rx_wqes =
2692             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2693         priv->params.rx_hash_log_tbl_sz =
2694             (order_base_2(num_comp_vectors) >
2695             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2696             order_base_2(num_comp_vectors) :
2697             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2698         priv->params.num_tc = 1;
2699         priv->params.default_vlan_prio = 0;
2700         priv->counter_set_id = -1;
2701
2702         /*
2703          * hw lro is currently defaulted to off. when it won't anymore we
2704          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2705          */
2706         priv->params.hw_lro_en = false;
2707         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2708
2709         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2710
2711         priv->mdev = mdev;
2712         priv->params.num_channels = num_comp_vectors;
2713         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2714         priv->queue_mapping_channel_mask =
2715             roundup_pow_of_two(num_comp_vectors) - 1;
2716         priv->num_tc = priv->params.num_tc;
2717         priv->default_vlan_prio = priv->params.default_vlan_prio;
2718
2719         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2720         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2721         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2722 }
2723
2724 static int
2725 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2726     struct mlx5_core_mr *mr)
2727 {
2728         struct ifnet *ifp = priv->ifp;
2729         struct mlx5_core_dev *mdev = priv->mdev;
2730         struct mlx5_create_mkey_mbox_in *in;
2731         int err;
2732
2733         in = mlx5_vzalloc(sizeof(*in));
2734         if (in == NULL) {
2735                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2736                 return (-ENOMEM);
2737         }
2738         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2739             MLX5_PERM_LOCAL_READ |
2740             MLX5_ACCESS_MODE_PA;
2741         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2742         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2743
2744         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2745             NULL);
2746         if (err)
2747                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2748                     __func__, err);
2749
2750         kvfree(in);
2751
2752         return (err);
2753 }
2754
2755 static const char *mlx5e_vport_stats_desc[] = {
2756         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2757 };
2758
2759 static const char *mlx5e_pport_stats_desc[] = {
2760         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2761 };
2762
2763 static void
2764 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2765 {
2766         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2767         sx_init(&priv->state_lock, "mlx5state");
2768         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2769         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2770 }
2771
2772 static void
2773 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2774 {
2775         mtx_destroy(&priv->async_events_mtx);
2776         sx_destroy(&priv->state_lock);
2777 }
2778
2779 static int
2780 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2781 {
2782         /*
2783          * %d.%d%.d the string format.
2784          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2785          * We need at most 5 chars to store that.
2786          * It also has: two "." and NULL at the end, which means we need 18
2787          * (5*3 + 3) chars at most.
2788          */
2789         char fw[18];
2790         struct mlx5e_priv *priv = arg1;
2791         int error;
2792
2793         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2794             fw_rev_sub(priv->mdev));
2795         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2796         return (error);
2797 }
2798
2799 static void
2800 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2801 {
2802         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2803             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2804             sysctl_firmware, "A", "HCA firmware version");
2805
2806         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2807             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2808             "Board ID");
2809 }
2810
2811 static void
2812 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2813 {
2814 #if (__FreeBSD_version < 1100000)
2815         char path[64];
2816
2817 #endif
2818         /* Only receiving pauseframes is enabled by default */
2819         priv->params.tx_pauseframe_control = 0;
2820         priv->params.rx_pauseframe_control = 1;
2821
2822 #if (__FreeBSD_version < 1100000)
2823         /* compute path for sysctl */
2824         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2825             device_get_unit(priv->mdev->pdev->dev.bsddev));
2826
2827         /* try to fetch tunable, if any */
2828         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2829
2830         /* compute path for sysctl */
2831         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2832             device_get_unit(priv->mdev->pdev->dev.bsddev));
2833
2834         /* try to fetch tunable, if any */
2835         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2836 #endif
2837
2838         /* register pausframe SYSCTLs */
2839         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2840             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2841             &priv->params.tx_pauseframe_control, 0,
2842             "Set to enable TX pause frames. Clear to disable.");
2843
2844         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2845             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2846             &priv->params.rx_pauseframe_control, 0,
2847             "Set to enable RX pause frames. Clear to disable.");
2848
2849         /* range check */
2850         priv->params.tx_pauseframe_control =
2851             priv->params.tx_pauseframe_control ? 1 : 0;
2852         priv->params.rx_pauseframe_control =
2853             priv->params.rx_pauseframe_control ? 1 : 0;
2854
2855         /* update firmware */
2856         mlx5_set_port_pause(priv->mdev, 1,
2857             priv->params.rx_pauseframe_control,
2858             priv->params.tx_pauseframe_control);
2859 }
2860
2861 static void *
2862 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2863 {
2864         static volatile int mlx5_en_unit;
2865         struct ifnet *ifp;
2866         struct mlx5e_priv *priv;
2867         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2868         struct sysctl_oid_list *child;
2869         int ncv = mdev->priv.eq_table.num_comp_vectors;
2870         char unit[16];
2871         int err;
2872         int i;
2873         u32 eth_proto_cap;
2874
2875         if (mlx5e_check_required_hca_cap(mdev)) {
2876                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2877                 return (NULL);
2878         }
2879         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2880         if (priv == NULL) {
2881                 mlx5_core_err(mdev, "malloc() failed\n");
2882                 return (NULL);
2883         }
2884         mlx5e_priv_mtx_init(priv);
2885
2886         ifp = priv->ifp = if_alloc(IFT_ETHER);
2887         if (ifp == NULL) {
2888                 mlx5_core_err(mdev, "if_alloc() failed\n");
2889                 goto err_free_priv;
2890         }
2891         ifp->if_softc = priv;
2892         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2893         ifp->if_mtu = ETHERMTU;
2894         ifp->if_init = mlx5e_open;
2895         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2896         ifp->if_ioctl = mlx5e_ioctl;
2897         ifp->if_transmit = mlx5e_xmit;
2898         ifp->if_qflush = if_qflush;
2899 #if (__FreeBSD_version >= 1100000)
2900         ifp->if_get_counter = mlx5e_get_counter;
2901 #endif
2902         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2903         /*
2904          * Set driver features
2905          */
2906         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2907         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2908         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2909         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2910         ifp->if_capabilities |= IFCAP_LRO;
2911         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2912
2913         /* set TSO limits so that we don't have to drop TX packets */
2914         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2915         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2916         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2917
2918         ifp->if_capenable = ifp->if_capabilities;
2919         ifp->if_hwassist = 0;
2920         if (ifp->if_capenable & IFCAP_TSO)
2921                 ifp->if_hwassist |= CSUM_TSO;
2922         if (ifp->if_capenable & IFCAP_TXCSUM)
2923                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2924         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2925                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2926
2927         /* ifnet sysctl tree */
2928         sysctl_ctx_init(&priv->sysctl_ctx);
2929         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2930             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2931         if (priv->sysctl_ifnet == NULL) {
2932                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2933                 goto err_free_sysctl;
2934         }
2935         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2936         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2937             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2938         if (priv->sysctl_ifnet == NULL) {
2939                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2940                 goto err_free_sysctl;
2941         }
2942
2943         /* HW sysctl tree */
2944         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2945         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2946             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2947         if (priv->sysctl_hw == NULL) {
2948                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2949                 goto err_free_sysctl;
2950         }
2951         mlx5e_build_ifp_priv(mdev, priv, ncv);
2952         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2953         if (err) {
2954                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2955                     __func__, err);
2956                 goto err_free_sysctl;
2957         }
2958         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2959         if (err) {
2960                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2961                     __func__, err);
2962                 goto err_unmap_free_uar;
2963         }
2964         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2965         if (err) {
2966                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2967                     __func__, err);
2968                 goto err_dealloc_pd;
2969         }
2970         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2971         if (err) {
2972                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2973                     __func__, err);
2974                 goto err_dealloc_transport_domain;
2975         }
2976         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2977
2978         /* check if we should generate a random MAC address */
2979         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2980             is_zero_ether_addr(dev_addr)) {
2981                 random_ether_addr(dev_addr);
2982                 if_printf(ifp, "Assigned random MAC address\n");
2983         }
2984
2985         /* set default MTU */
2986         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2987
2988         /* Set desc */
2989         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2990
2991         /* Set default media status */
2992         priv->media_status_last = IFM_AVALID;
2993         priv->media_active_last = IFM_ETHER | IFM_AUTO |
2994             IFM_ETH_RXPAUSE | IFM_FDX;
2995
2996         /* setup default pauseframes configuration */
2997         mlx5e_setup_pauseframes(priv);
2998
2999         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3000         if (err) {
3001                 eth_proto_cap = 0;
3002                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3003                     __func__, err);
3004         }
3005
3006         /* Setup supported medias */
3007         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3008             mlx5e_media_change, mlx5e_media_status);
3009
3010         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3011                 if (mlx5e_mode_table[i].baudrate == 0)
3012                         continue;
3013                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3014                         ifmedia_add(&priv->media,
3015                             mlx5e_mode_table[i].subtype |
3016                             IFM_ETHER, 0, NULL);
3017                         ifmedia_add(&priv->media,
3018                             mlx5e_mode_table[i].subtype |
3019                             IFM_ETHER | IFM_FDX |
3020                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3021                 }
3022         }
3023
3024         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3025         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3026             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3027
3028         /* Set autoselect by default */
3029         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3030             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3031         ether_ifattach(ifp, dev_addr);
3032
3033         /* Register for VLAN events */
3034         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3035             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3036         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3037             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3038
3039         /* Link is down by default */
3040         if_link_state_change(ifp, LINK_STATE_DOWN);
3041
3042         mlx5e_enable_async_events(priv);
3043
3044         mlx5e_add_hw_stats(priv);
3045
3046         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3047             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3048             priv->stats.vport.arg);
3049
3050         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3051             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3052             priv->stats.pport.arg);
3053
3054         mlx5e_create_ethtool(priv);
3055
3056         mtx_lock(&priv->async_events_mtx);
3057         mlx5e_update_stats(priv);
3058         mtx_unlock(&priv->async_events_mtx);
3059
3060         return (priv);
3061
3062 err_dealloc_transport_domain:
3063         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3064
3065 err_dealloc_pd:
3066         mlx5_core_dealloc_pd(mdev, priv->pdn);
3067
3068 err_unmap_free_uar:
3069         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3070
3071 err_free_sysctl:
3072         sysctl_ctx_free(&priv->sysctl_ctx);
3073
3074         if_free(ifp);
3075
3076 err_free_priv:
3077         mlx5e_priv_mtx_destroy(priv);
3078         free(priv, M_MLX5EN);
3079         return (NULL);
3080 }
3081
3082 static void
3083 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3084 {
3085         struct mlx5e_priv *priv = vpriv;
3086         struct ifnet *ifp = priv->ifp;
3087
3088         /* don't allow more IOCTLs */
3089         priv->gone = 1;
3090
3091         /*
3092          * Clear the device description to avoid use after free,
3093          * because the bsddev is not destroyed when this module is
3094          * unloaded:
3095          */
3096         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3097
3098         /* XXX wait a bit to allow IOCTL handlers to complete */
3099         pause("W", hz);
3100
3101         /* stop watchdog timer */
3102         callout_drain(&priv->watchdog);
3103
3104         if (priv->vlan_attach != NULL)
3105                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3106         if (priv->vlan_detach != NULL)
3107                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3108
3109         /* make sure device gets closed */
3110         PRIV_LOCK(priv);
3111         mlx5e_close_locked(ifp);
3112         PRIV_UNLOCK(priv);
3113
3114         /* unregister device */
3115         ifmedia_removeall(&priv->media);
3116         ether_ifdetach(ifp);
3117         if_free(ifp);
3118
3119         /* destroy all remaining sysctl nodes */
3120         if (priv->sysctl_debug)
3121                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3122         sysctl_ctx_free(&priv->stats.vport.ctx);
3123         sysctl_ctx_free(&priv->stats.pport.ctx);
3124         sysctl_ctx_free(&priv->sysctl_ctx);
3125
3126         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3127         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3128         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3129         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3130         mlx5e_disable_async_events(priv);
3131         flush_scheduled_work();
3132         mlx5e_priv_mtx_destroy(priv);
3133         free(priv, M_MLX5EN);
3134 }
3135
3136 static void *
3137 mlx5e_get_ifp(void *vpriv)
3138 {
3139         struct mlx5e_priv *priv = vpriv;
3140
3141         return (priv->ifp);
3142 }
3143
3144 static struct mlx5_interface mlx5e_interface = {
3145         .add = mlx5e_create_ifp,
3146         .remove = mlx5e_destroy_ifp,
3147         .event = mlx5e_async_event,
3148         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3149         .get_dev = mlx5e_get_ifp,
3150 };
3151
3152 void
3153 mlx5e_init(void)
3154 {
3155         mlx5_register_interface(&mlx5e_interface);
3156 }
3157
3158 void
3159 mlx5e_cleanup(void)
3160 {
3161         mlx5_unregister_interface(&mlx5e_interface);
3162 }
3163
3164 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3165 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3166
3167 #if (__FreeBSD_version >= 1100000)
3168 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3169 #endif
3170 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3171 MODULE_VERSION(mlx5en, 1);