sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 static void
 310 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 311 {
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         struct mlx5e_pport_stats *s = &priv->stats.pport;
 314         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 315         u32 *in;
 316         u32 *out;
 317         const u64 *ptr;
 318         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 319         unsigned x;
 320         unsigned y;
 321
 322         in = mlx5_vzalloc(sz);
 323         out = mlx5_vzalloc(sz);
 324         if (in == NULL || out == NULL)
 325                 goto free_out;
 326
 327         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 328
 329         MLX5_SET(ppcnt_reg, in, local_port, 1);
 330
 331         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 332         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 333         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 334                 s->arg[y] = be64toh(ptr[x]);
 335
 336         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 337         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 338         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 339                 s->arg[y] = be64toh(ptr[x]);
 340         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 341             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 342                 s_debug->arg[y] = be64toh(ptr[x]);
 343
 344         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 345         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 346         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 347                 s_debug->arg[y] = be64toh(ptr[x]);
 348
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 352                 s_debug->arg[y] = be64toh(ptr[x]);
 353 free_out:
 354         kvfree(in);
 355         kvfree(out);
 356 }
 357
 358 static void
 359 mlx5e_update_stats_work(struct work_struct *work)
 360 {
 361         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 362             update_stats_work);
 363         struct mlx5_core_dev *mdev = priv->mdev;
 364         struct mlx5e_vport_stats *s = &priv->stats.vport;
 365         struct mlx5e_rq_stats *rq_stats;
 366         struct mlx5e_sq_stats *sq_stats;
 367         struct buf_ring *sq_br;
 368 #if (__FreeBSD_version < 1100000)
 369         struct ifnet *ifp = priv->ifp;
 370 #endif
 371
 372         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 373         u32 *out;
 374         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 375         u64 tso_packets = 0;
 376         u64 tso_bytes = 0;
 377         u64 tx_queue_dropped = 0;
 378         u64 tx_defragged = 0;
 379         u64 tx_offload_none = 0;
 380         u64 lro_packets = 0;
 381         u64 lro_bytes = 0;
 382         u64 sw_lro_queued = 0;
 383         u64 sw_lro_flushed = 0;
 384         u64 rx_csum_none = 0;
 385         u64 rx_wqe_err = 0;
 386         u32 rx_out_of_buffer = 0;
 387         int i;
 388         int j;
 389
 390         PRIV_LOCK(priv);
 391         out = mlx5_vzalloc(outlen);
 392         if (out == NULL)
 393                 goto free_out;
 394         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 395                 goto free_out;
 396
 397         /* Collect firts the SW counters and then HW for consistency */
 398         for (i = 0; i < priv->params.num_channels; i++) {
 399                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 400
 401                 rq_stats = &priv->channel[i]->rq.stats;
 402
 403                 /* collect stats from LRO */
 404                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 405                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 406                 sw_lro_queued += rq_stats->sw_lro_queued;
 407                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 408                 lro_packets += rq_stats->lro_packets;
 409                 lro_bytes += rq_stats->lro_bytes;
 410                 rx_csum_none += rq_stats->csum_none;
 411                 rx_wqe_err += rq_stats->wqe_err;
 412
 413                 for (j = 0; j < priv->num_tc; j++) {
 414                         sq_stats = &priv->channel[i]->sq[j].stats;
 415                         sq_br = priv->channel[i]->sq[j].br;
 416
 417                         tso_packets += sq_stats->tso_packets;
 418                         tso_bytes += sq_stats->tso_bytes;
 419                         tx_queue_dropped += sq_stats->dropped;
 420                         tx_queue_dropped += sq_br->br_drops;
 421                         tx_defragged += sq_stats->defragged;
 422                         tx_offload_none += sq_stats->csum_offload_none;
 423                 }
 424         }
 425
 426         /* update counters */
 427         s->tso_packets = tso_packets;
 428         s->tso_bytes = tso_bytes;
 429         s->tx_queue_dropped = tx_queue_dropped;
 430         s->tx_defragged = tx_defragged;
 431         s->lro_packets = lro_packets;
 432         s->lro_bytes = lro_bytes;
 433         s->sw_lro_queued = sw_lro_queued;
 434         s->sw_lro_flushed = sw_lro_flushed;
 435         s->rx_csum_none = rx_csum_none;
 436         s->rx_wqe_err = rx_wqe_err;
 437
 438         /* HW counters */
 439         memset(in, 0, sizeof(in));
 440
 441         MLX5_SET(query_vport_counter_in, in, opcode,
 442             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 443         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 444         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 445
 446         memset(out, 0, outlen);
 447
 448         /* get number of out-of-buffer drops first */
 449         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 450             &rx_out_of_buffer))
 451                 goto free_out;
 452
 453         /* accumulate difference into a 64-bit counter */
 454         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 455         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 456
 457         /* get port statistics */
 458         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 459                 goto free_out;
 460
 461 #define MLX5_GET_CTR(out, x) \
 462         MLX5_GET64(query_vport_counter_out, out, x)
 463
 464         s->rx_error_packets =
 465             MLX5_GET_CTR(out, received_errors.packets);
 466         s->rx_error_bytes =
 467             MLX5_GET_CTR(out, received_errors.octets);
 468         s->tx_error_packets =
 469             MLX5_GET_CTR(out, transmit_errors.packets);
 470         s->tx_error_bytes =
 471             MLX5_GET_CTR(out, transmit_errors.octets);
 472
 473         s->rx_unicast_packets =
 474             MLX5_GET_CTR(out, received_eth_unicast.packets);
 475         s->rx_unicast_bytes =
 476             MLX5_GET_CTR(out, received_eth_unicast.octets);
 477         s->tx_unicast_packets =
 478             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 479         s->tx_unicast_bytes =
 480             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 481
 482         s->rx_multicast_packets =
 483             MLX5_GET_CTR(out, received_eth_multicast.packets);
 484         s->rx_multicast_bytes =
 485             MLX5_GET_CTR(out, received_eth_multicast.octets);
 486         s->tx_multicast_packets =
 487             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 488         s->tx_multicast_bytes =
 489             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 490
 491         s->rx_broadcast_packets =
 492             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 493         s->rx_broadcast_bytes =
 494             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 495         s->tx_broadcast_packets =
 496             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 497         s->tx_broadcast_bytes =
 498             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 499
 500         s->rx_packets =
 501             s->rx_unicast_packets +
 502             s->rx_multicast_packets +
 503             s->rx_broadcast_packets -
 504             s->rx_out_of_buffer;
 505         s->rx_bytes =
 506             s->rx_unicast_bytes +
 507             s->rx_multicast_bytes +
 508             s->rx_broadcast_bytes;
 509         s->tx_packets =
 510             s->tx_unicast_packets +
 511             s->tx_multicast_packets +
 512             s->tx_broadcast_packets;
 513         s->tx_bytes =
 514             s->tx_unicast_bytes +
 515             s->tx_multicast_bytes +
 516             s->tx_broadcast_bytes;
 517
 518         /* Update calculated offload counters */
 519         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 520         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 521
 522         /* Update per port counters */
 523         mlx5e_update_pport_counters(priv);
 524
 525 #if (__FreeBSD_version < 1100000)
 526         /* no get_counters interface in fbsd 10 */
 527         ifp->if_ipackets = s->rx_packets;
 528         ifp->if_ierrors = s->rx_error_packets;
 529         ifp->if_iqdrops = s->rx_out_of_buffer;
 530         ifp->if_opackets = s->tx_packets;
 531         ifp->if_oerrors = s->tx_error_packets;
 532         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 533         ifp->if_ibytes = s->rx_bytes;
 534         ifp->if_obytes = s->tx_bytes;
 535 #endif
 536
 537 free_out:
 538         kvfree(out);
 539         PRIV_UNLOCK(priv);
 540 }
 541
 542 static void
 543 mlx5e_update_stats(void *arg)
 544 {
 545         struct mlx5e_priv *priv = arg;
 546
 547         schedule_work(&priv->update_stats_work);
 548
 549         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 550 }
 551
 552 static void
 553 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 554     enum mlx5_dev_event event)
 555 {
 556         switch (event) {
 557         case MLX5_DEV_EVENT_PORT_UP:
 558         case MLX5_DEV_EVENT_PORT_DOWN:
 559                 schedule_work(&priv->update_carrier_work);
 560                 break;
 561
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 static void
 568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 569     enum mlx5_dev_event event, unsigned long param)
 570 {
 571         struct mlx5e_priv *priv = vpriv;
 572
 573         mtx_lock(&priv->async_events_mtx);
 574         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 575                 mlx5e_async_event_sub(priv, event);
 576         mtx_unlock(&priv->async_events_mtx);
 577 }
 578
 579 static void
 580 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 581 {
 582         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 583 }
 584
 585 static void
 586 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 587 {
 588         mtx_lock(&priv->async_events_mtx);
 589         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 590         mtx_unlock(&priv->async_events_mtx);
 591 }
 592
 593 static const char *mlx5e_rq_stats_desc[] = {
 594         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 595 };
 596
 597 static int
 598 mlx5e_create_rq(struct mlx5e_channel *c,
 599     struct mlx5e_rq_param *param,
 600     struct mlx5e_rq *rq)
 601 {
 602         struct mlx5e_priv *priv = c->priv;
 603         struct mlx5_core_dev *mdev = priv->mdev;
 604         char buffer[16];
 605         void *rqc = param->rqc;
 606         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 607         int wq_sz;
 608         int err;
 609         int i;
 610
 611         /* Create DMA descriptor TAG */
 612         if ((err = -bus_dma_tag_create(
 613             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 614             1,                          /* any alignment */
 615             0,                          /* no boundary */
 616             BUS_SPACE_MAXADDR,          /* lowaddr */
 617             BUS_SPACE_MAXADDR,          /* highaddr */
 618             NULL, NULL,                 /* filter, filterarg */
 619             MJUM16BYTES,                /* maxsize */
 620             1,                          /* nsegments */
 621             MJUM16BYTES,                /* maxsegsize */
 622             0,                          /* flags */
 623             NULL, NULL,                 /* lockfunc, lockfuncarg */
 624             &rq->dma_tag)))
 625                 goto done;
 626
 627         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 628             &rq->wq_ctrl);
 629         if (err)
 630                 goto err_free_dma_tag;
 631
 632         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 633
 634         if (priv->params.hw_lro_en) {
 635                 rq->wqe_sz = priv->params.lro_wqe_sz;
 636         } else {
 637                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 638         }
 639         if (rq->wqe_sz > MJUM16BYTES) {
 640                 err = -ENOMEM;
 641                 goto err_rq_wq_destroy;
 642         } else if (rq->wqe_sz > MJUM9BYTES) {
 643                 rq->wqe_sz = MJUM16BYTES;
 644         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 645                 rq->wqe_sz = MJUM9BYTES;
 646         } else if (rq->wqe_sz > MCLBYTES) {
 647                 rq->wqe_sz = MJUMPAGESIZE;
 648         } else {
 649                 rq->wqe_sz = MCLBYTES;
 650         }
 651
 652         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 653         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 654         for (i = 0; i != wq_sz; i++) {
 655                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 656                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 657
 658                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 659                 if (err != 0) {
 660                         while (i--)
 661                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 662                         goto err_rq_mbuf_free;
 663                 }
 664                 wqe->data.lkey = c->mkey_be;
 665                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 666         }
 667
 668         rq->ifp = c->ifp;
 669         rq->channel = c;
 670         rq->ix = c->ix;
 671
 672         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 673         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 674             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 675             rq->stats.arg);
 676
 677 #ifdef HAVE_TURBO_LRO
 678         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 679                 rq->lro.mbuf = NULL;
 680 #else
 681         if (tcp_lro_init(&rq->lro))
 682                 rq->lro.lro_cnt = 0;
 683         else
 684                 rq->lro.ifp = c->ifp;
 685 #endif
 686         return (0);
 687
 688 err_rq_mbuf_free:
 689         free(rq->mbuf, M_MLX5EN);
 690 err_rq_wq_destroy:
 691         mlx5_wq_destroy(&rq->wq_ctrl);
 692 err_free_dma_tag:
 693         bus_dma_tag_destroy(rq->dma_tag);
 694 done:
 695         return (err);
 696 }
 697
 698 static void
 699 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 700 {
 701         int wq_sz;
 702         int i;
 703
 704         /* destroy all sysctl nodes */
 705         sysctl_ctx_free(&rq->stats.ctx);
 706
 707         /* free leftover LRO packets, if any */
 708 #ifdef HAVE_TURBO_LRO
 709         tcp_tlro_free(&rq->lro);
 710 #else
 711         tcp_lro_free(&rq->lro);
 712 #endif
 713         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 714         for (i = 0; i != wq_sz; i++) {
 715                 if (rq->mbuf[i].mbuf != NULL) {
 716                         bus_dmamap_unload(rq->dma_tag,
 717                             rq->mbuf[i].dma_map);
 718                         m_freem(rq->mbuf[i].mbuf);
 719                 }
 720                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 721         }
 722         free(rq->mbuf, M_MLX5EN);
 723         mlx5_wq_destroy(&rq->wq_ctrl);
 724 }
 725
 726 static int
 727 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 728 {
 729         struct mlx5e_channel *c = rq->channel;
 730         struct mlx5e_priv *priv = c->priv;
 731         struct mlx5_core_dev *mdev = priv->mdev;
 732
 733         void *in;
 734         void *rqc;
 735         void *wq;
 736         int inlen;
 737         int err;
 738
 739         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 740             sizeof(u64) * rq->wq_ctrl.buf.npages;
 741         in = mlx5_vzalloc(inlen);
 742         if (in == NULL)
 743                 return (-ENOMEM);
 744
 745         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 746         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 747
 748         memcpy(rqc, param->rqc, sizeof(param->rqc));
 749
 750         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 751         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 752         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 753         if (priv->counter_set_id >= 0)
 754                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 755         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 756             PAGE_SHIFT);
 757         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 758
 759         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 760             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 761
 762         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 763
 764         kvfree(in);
 765
 766         return (err);
 767 }
 768
 769 static int
 770 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 771 {
 772         struct mlx5e_channel *c = rq->channel;
 773         struct mlx5e_priv *priv = c->priv;
 774         struct mlx5_core_dev *mdev = priv->mdev;
 775
 776         void *in;
 777         void *rqc;
 778         int inlen;
 779         int err;
 780
 781         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 782         in = mlx5_vzalloc(inlen);
 783         if (in == NULL)
 784                 return (-ENOMEM);
 785
 786         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 787
 788         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 789         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 790         MLX5_SET(rqc, rqc, state, next_state);
 791
 792         err = mlx5_core_modify_rq(mdev, in, inlen);
 793
 794         kvfree(in);
 795
 796         return (err);
 797 }
 798
 799 static void
 800 mlx5e_disable_rq(struct mlx5e_rq *rq)
 801 {
 802         struct mlx5e_channel *c = rq->channel;
 803         struct mlx5e_priv *priv = c->priv;
 804         struct mlx5_core_dev *mdev = priv->mdev;
 805
 806         mlx5_core_destroy_rq(mdev, rq->rqn);
 807 }
 808
 809 static int
 810 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 811 {
 812         struct mlx5e_channel *c = rq->channel;
 813         struct mlx5e_priv *priv = c->priv;
 814         struct mlx5_wq_ll *wq = &rq->wq;
 815         int i;
 816
 817         for (i = 0; i < 1000; i++) {
 818                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 819                         return (0);
 820
 821                 msleep(4);
 822         }
 823         return (-ETIMEDOUT);
 824 }
 825
 826 static int
 827 mlx5e_open_rq(struct mlx5e_channel *c,
 828     struct mlx5e_rq_param *param,
 829     struct mlx5e_rq *rq)
 830 {
 831         int err;
 832
 833         err = mlx5e_create_rq(c, param, rq);
 834         if (err)
 835                 return (err);
 836
 837         err = mlx5e_enable_rq(rq, param);
 838         if (err)
 839                 goto err_destroy_rq;
 840
 841         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 842         if (err)
 843                 goto err_disable_rq;
 844
 845         c->rq.enabled = 1;
 846
 847         return (0);
 848
 849 err_disable_rq:
 850         mlx5e_disable_rq(rq);
 851 err_destroy_rq:
 852         mlx5e_destroy_rq(rq);
 853
 854         return (err);
 855 }
 856
 857 static void
 858 mlx5e_close_rq(struct mlx5e_rq *rq)
 859 {
 860         mtx_lock(&rq->mtx);
 861         rq->enabled = 0;
 862         callout_stop(&rq->watchdog);
 863         mtx_unlock(&rq->mtx);
 864
 865         callout_drain(&rq->watchdog);
 866
 867         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 868 }
 869
 870 static void
 871 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 872 {
 873         /* wait till RQ is empty */
 874         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 875                 msleep(4);
 876                 rq->cq.mcq.comp(&rq->cq.mcq);
 877         }
 878
 879         mlx5e_disable_rq(rq);
 880         mlx5e_destroy_rq(rq);
 881 }
 882
 883 void
 884 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 885 {
 886         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 887         int x;
 888
 889         for (x = 0; x != wq_sz; x++)
 890                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 891         free(sq->mbuf, M_MLX5EN);
 892 }
 893
 894 int
 895 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 896 {
 897         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 898         int err;
 899         int x;
 900
 901         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 902
 903         /* Create DMA descriptor MAPs */
 904         for (x = 0; x != wq_sz; x++) {
 905                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 906                 if (err != 0) {
 907                         while (x--)
 908                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 909                         free(sq->mbuf, M_MLX5EN);
 910                         return (err);
 911                 }
 912         }
 913         return (0);
 914 }
 915
 916 static const char *mlx5e_sq_stats_desc[] = {
 917         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 918 };
 919
 920 static int
 921 mlx5e_create_sq(struct mlx5e_channel *c,
 922     int tc,
 923     struct mlx5e_sq_param *param,
 924     struct mlx5e_sq *sq)
 925 {
 926         struct mlx5e_priv *priv = c->priv;
 927         struct mlx5_core_dev *mdev = priv->mdev;
 928         char buffer[16];
 929
 930         void *sqc = param->sqc;
 931         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 932 #ifdef RSS
 933         cpuset_t cpu_mask;
 934         int cpu_id;
 935 #endif
 936         int err;
 937
 938         /* Create DMA descriptor TAG */
 939         if ((err = -bus_dma_tag_create(
 940             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 941             1,                          /* any alignment */
 942             0,                          /* no boundary */
 943             BUS_SPACE_MAXADDR,          /* lowaddr */
 944             BUS_SPACE_MAXADDR,          /* highaddr */
 945             NULL, NULL,                 /* filter, filterarg */
 946             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 947             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 948             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 949             0,                          /* flags */
 950             NULL, NULL,                 /* lockfunc, lockfuncarg */
 951             &sq->dma_tag)))
 952                 goto done;
 953
 954         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 955         if (err)
 956                 goto err_free_dma_tag;
 957
 958         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 959             &sq->wq_ctrl);
 960         if (err)
 961                 goto err_unmap_free_uar;
 962
 963         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 964         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 965
 966         err = mlx5e_alloc_sq_db(sq);
 967         if (err)
 968                 goto err_sq_wq_destroy;
 969
 970         sq->mkey_be = c->mkey_be;
 971         sq->ifp = priv->ifp;
 972         sq->priv = priv;
 973         sq->tc = tc;
 974
 975         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
 976             M_WAITOK, &sq->lock);
 977         if (sq->br == NULL) {
 978                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
 979                     __func__);
 980                 err = -ENOMEM;
 981                 goto err_free_sq_db;
 982         }
 983
 984         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
 985             taskqueue_thread_enqueue, &sq->sq_tq);
 986         if (sq->sq_tq == NULL) {
 987                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
 988                     __func__);
 989                 err = -ENOMEM;
 990                 goto err_free_drbr;
 991         }
 992
 993         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
 994 #ifdef RSS
 995         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
 996         CPU_SETOF(cpu_id, &cpu_mask);
 997         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
 998             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
 999 #else
1000         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1001             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1002 #endif
1003         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1004         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1005             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1006             sq->stats.arg);
1007
1008         return (0);
1009
1010 err_free_drbr:
1011         buf_ring_free(sq->br, M_MLX5EN);
1012 err_free_sq_db:
1013         mlx5e_free_sq_db(sq);
1014 err_sq_wq_destroy:
1015         mlx5_wq_destroy(&sq->wq_ctrl);
1016
1017 err_unmap_free_uar:
1018         mlx5_unmap_free_uar(mdev, &sq->uar);
1019
1020 err_free_dma_tag:
1021         bus_dma_tag_destroy(sq->dma_tag);
1022 done:
1023         return (err);
1024 }
1025
1026 static void
1027 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1028 {
1029         /* destroy all sysctl nodes */
1030         sysctl_ctx_free(&sq->stats.ctx);
1031
1032         mlx5e_free_sq_db(sq);
1033         mlx5_wq_destroy(&sq->wq_ctrl);
1034         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1035         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1036         taskqueue_free(sq->sq_tq);
1037         buf_ring_free(sq->br, M_MLX5EN);
1038 }
1039
1040 int
1041 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1042     int tis_num)
1043 {
1044         void *in;
1045         void *sqc;
1046         void *wq;
1047         int inlen;
1048         int err;
1049
1050         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1051             sizeof(u64) * sq->wq_ctrl.buf.npages;
1052         in = mlx5_vzalloc(inlen);
1053         if (in == NULL)
1054                 return (-ENOMEM);
1055
1056         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1057         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1058
1059         memcpy(sqc, param->sqc, sizeof(param->sqc));
1060
1061         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1062         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1063         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1064         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1065         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1066
1067         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1068         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1069         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1070             PAGE_SHIFT);
1071         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1072
1073         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1074             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1075
1076         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1077
1078         kvfree(in);
1079
1080         return (err);
1081 }
1082
1083 int
1084 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1085 {
1086         void *in;
1087         void *sqc;
1088         int inlen;
1089         int err;
1090
1091         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1092         in = mlx5_vzalloc(inlen);
1093         if (in == NULL)
1094                 return (-ENOMEM);
1095
1096         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1097
1098         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1099         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1100         MLX5_SET(sqc, sqc, state, next_state);
1101
1102         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1103
1104         kvfree(in);
1105
1106         return (err);
1107 }
1108
1109 void
1110 mlx5e_disable_sq(struct mlx5e_sq *sq)
1111 {
1112
1113         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1114 }
1115
1116 static int
1117 mlx5e_open_sq(struct mlx5e_channel *c,
1118     int tc,
1119     struct mlx5e_sq_param *param,
1120     struct mlx5e_sq *sq)
1121 {
1122         int err;
1123
1124         err = mlx5e_create_sq(c, tc, param, sq);
1125         if (err)
1126                 return (err);
1127
1128         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1129         if (err)
1130                 goto err_destroy_sq;
1131
1132         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1133         if (err)
1134                 goto err_disable_sq;
1135
1136         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1137
1138         return (0);
1139
1140 err_disable_sq:
1141         mlx5e_disable_sq(sq);
1142 err_destroy_sq:
1143         mlx5e_destroy_sq(sq);
1144
1145         return (err);
1146 }
1147
1148 static void
1149 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1150 {
1151         /* fill up remainder with NOPs */
1152         while (sq->cev_counter != 0) {
1153                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1154                         if (can_sleep != 0) {
1155                                 mtx_unlock(&sq->lock);
1156                                 msleep(4);
1157                                 mtx_lock(&sq->lock);
1158                         } else {
1159                                 goto done;
1160                         }
1161                 }
1162                 /* send a single NOP */
1163                 mlx5e_send_nop(sq, 1);
1164                 wmb();
1165         }
1166 done:
1167         /* Check if we need to write the doorbell */
1168         if (likely(sq->doorbell.d64 != 0)) {
1169                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1170                 sq->doorbell.d64 = 0;
1171         }
1172         return;
1173 }
1174
1175 void
1176 mlx5e_sq_cev_timeout(void *arg)
1177 {
1178         struct mlx5e_sq *sq = arg;
1179
1180         mtx_assert(&sq->lock, MA_OWNED);
1181
1182         /* check next state */
1183         switch (sq->cev_next_state) {
1184         case MLX5E_CEV_STATE_SEND_NOPS:
1185                 /* fill TX ring with NOPs, if any */
1186                 mlx5e_sq_send_nops_locked(sq, 0);
1187
1188                 /* check if completed */
1189                 if (sq->cev_counter == 0) {
1190                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1191                         return;
1192                 }
1193                 break;
1194         default:
1195                 /* send NOPs on next timeout */
1196                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1197                 break;
1198         }
1199
1200         /* restart timer */
1201         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1202 }
1203
1204 void
1205 mlx5e_drain_sq(struct mlx5e_sq *sq)
1206 {
1207
1208         mtx_lock(&sq->lock);
1209         /* teardown event factor timer, if any */
1210         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1211         callout_stop(&sq->cev_callout);
1212
1213         /* send dummy NOPs in order to flush the transmit ring */
1214         mlx5e_sq_send_nops_locked(sq, 1);
1215         mtx_unlock(&sq->lock);
1216
1217         /* make sure it is safe to free the callout */
1218         callout_drain(&sq->cev_callout);
1219
1220         /* error out remaining requests */
1221         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1222
1223         /* wait till SQ is empty */
1224         mtx_lock(&sq->lock);
1225         while (sq->cc != sq->pc) {
1226                 mtx_unlock(&sq->lock);
1227                 msleep(4);
1228                 sq->cq.mcq.comp(&sq->cq.mcq);
1229                 mtx_lock(&sq->lock);
1230         }
1231         mtx_unlock(&sq->lock);
1232 }
1233
1234 static void
1235 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1236 {
1237
1238         mlx5e_drain_sq(sq);
1239         mlx5e_disable_sq(sq);
1240         mlx5e_destroy_sq(sq);
1241 }
1242
1243 static int
1244 mlx5e_create_cq(struct mlx5e_priv *priv,
1245     struct mlx5e_cq_param *param,
1246     struct mlx5e_cq *cq,
1247     mlx5e_cq_comp_t *comp,
1248     int eq_ix)
1249 {
1250         struct mlx5_core_dev *mdev = priv->mdev;
1251         struct mlx5_core_cq *mcq = &cq->mcq;
1252         int eqn_not_used;
1253         int irqn;
1254         int err;
1255         u32 i;
1256
1257         param->wq.buf_numa_node = 0;
1258         param->wq.db_numa_node = 0;
1259
1260         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1261             &cq->wq_ctrl);
1262         if (err)
1263                 return (err);
1264
1265         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1266
1267         mcq->cqe_sz = 64;
1268         mcq->set_ci_db = cq->wq_ctrl.db.db;
1269         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1270         *mcq->set_ci_db = 0;
1271         *mcq->arm_db = 0;
1272         mcq->vector = eq_ix;
1273         mcq->comp = comp;
1274         mcq->event = mlx5e_cq_error_event;
1275         mcq->irqn = irqn;
1276         mcq->uar = &priv->cq_uar;
1277
1278         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1279                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1280
1281                 cqe->op_own = 0xf1;
1282         }
1283
1284         cq->priv = priv;
1285
1286         return (0);
1287 }
1288
1289 static void
1290 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1291 {
1292         mlx5_wq_destroy(&cq->wq_ctrl);
1293 }
1294
1295 static int
1296 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1297 {
1298         struct mlx5_core_cq *mcq = &cq->mcq;
1299         void *in;
1300         void *cqc;
1301         int inlen;
1302         int irqn_not_used;
1303         int eqn;
1304         int err;
1305
1306         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1307             sizeof(u64) * cq->wq_ctrl.buf.npages;
1308         in = mlx5_vzalloc(inlen);
1309         if (in == NULL)
1310                 return (-ENOMEM);
1311
1312         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1313
1314         memcpy(cqc, param->cqc, sizeof(param->cqc));
1315
1316         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1317             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1318
1319         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1320
1321         MLX5_SET(cqc, cqc, c_eqn, eqn);
1322         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1323         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1324             PAGE_SHIFT);
1325         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1326
1327         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1328
1329         kvfree(in);
1330
1331         if (err)
1332                 return (err);
1333
1334         mlx5e_cq_arm(cq);
1335
1336         return (0);
1337 }
1338
1339 static void
1340 mlx5e_disable_cq(struct mlx5e_cq *cq)
1341 {
1342
1343         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1344 }
1345
1346 int
1347 mlx5e_open_cq(struct mlx5e_priv *priv,
1348     struct mlx5e_cq_param *param,
1349     struct mlx5e_cq *cq,
1350     mlx5e_cq_comp_t *comp,
1351     int eq_ix)
1352 {
1353         int err;
1354
1355         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1356         if (err)
1357                 return (err);
1358
1359         err = mlx5e_enable_cq(cq, param, eq_ix);
1360         if (err)
1361                 goto err_destroy_cq;
1362
1363         return (0);
1364
1365 err_destroy_cq:
1366         mlx5e_destroy_cq(cq);
1367
1368         return (err);
1369 }
1370
1371 void
1372 mlx5e_close_cq(struct mlx5e_cq *cq)
1373 {
1374         mlx5e_disable_cq(cq);
1375         mlx5e_destroy_cq(cq);
1376 }
1377
1378 static int
1379 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1380     struct mlx5e_channel_param *cparam)
1381 {
1382         int err;
1383         int tc;
1384
1385         for (tc = 0; tc < c->num_tc; tc++) {
1386                 /* open completion queue */
1387                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1388                     &mlx5e_tx_cq_comp, c->ix);
1389                 if (err)
1390                         goto err_close_tx_cqs;
1391         }
1392         return (0);
1393
1394 err_close_tx_cqs:
1395         for (tc--; tc >= 0; tc--)
1396                 mlx5e_close_cq(&c->sq[tc].cq);
1397
1398         return (err);
1399 }
1400
1401 static void
1402 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1403 {
1404         int tc;
1405
1406         for (tc = 0; tc < c->num_tc; tc++)
1407                 mlx5e_close_cq(&c->sq[tc].cq);
1408 }
1409
1410 static int
1411 mlx5e_open_sqs(struct mlx5e_channel *c,
1412     struct mlx5e_channel_param *cparam)
1413 {
1414         int err;
1415         int tc;
1416
1417         for (tc = 0; tc < c->num_tc; tc++) {
1418                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1419                 if (err)
1420                         goto err_close_sqs;
1421         }
1422
1423         return (0);
1424
1425 err_close_sqs:
1426         for (tc--; tc >= 0; tc--)
1427                 mlx5e_close_sq_wait(&c->sq[tc]);
1428
1429         return (err);
1430 }
1431
1432 static void
1433 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1434 {
1435         int tc;
1436
1437         for (tc = 0; tc < c->num_tc; tc++)
1438                 mlx5e_close_sq_wait(&c->sq[tc]);
1439 }
1440
1441 static void
1442 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1443 {
1444         int tc;
1445
1446         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1447
1448         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1449
1450         for (tc = 0; tc < c->num_tc; tc++) {
1451                 struct mlx5e_sq *sq = c->sq + tc;
1452
1453                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1454                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1455                     MTX_DEF);
1456
1457                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1458
1459                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1460
1461                 /* ensure the TX completion event factor is not zero */
1462                 if (sq->cev_factor == 0)
1463                         sq->cev_factor = 1;
1464         }
1465 }
1466
1467 static void
1468 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1469 {
1470         int tc;
1471
1472         mtx_destroy(&c->rq.mtx);
1473
1474         for (tc = 0; tc < c->num_tc; tc++) {
1475                 mtx_destroy(&c->sq[tc].lock);
1476                 mtx_destroy(&c->sq[tc].comp_lock);
1477         }
1478 }
1479
1480 static int
1481 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1482     struct mlx5e_channel_param *cparam,
1483     struct mlx5e_channel *volatile *cp)
1484 {
1485         struct mlx5e_channel *c;
1486         int err;
1487
1488         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1489         c->priv = priv;
1490         c->ix = ix;
1491         c->cpu = 0;
1492         c->ifp = priv->ifp;
1493         c->mkey_be = cpu_to_be32(priv->mr.key);
1494         c->num_tc = priv->num_tc;
1495
1496         /* init mutexes */
1497         mlx5e_chan_mtx_init(c);
1498
1499         /* open transmit completion queue */
1500         err = mlx5e_open_tx_cqs(c, cparam);
1501         if (err)
1502                 goto err_free;
1503
1504         /* open receive completion queue */
1505         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1506             &mlx5e_rx_cq_comp, c->ix);
1507         if (err)
1508                 goto err_close_tx_cqs;
1509
1510         err = mlx5e_open_sqs(c, cparam);
1511         if (err)
1512                 goto err_close_rx_cq;
1513
1514         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1515         if (err)
1516                 goto err_close_sqs;
1517
1518         /* store channel pointer */
1519         *cp = c;
1520
1521         /* poll receive queue initially */
1522         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1523
1524         return (0);
1525
1526 err_close_sqs:
1527         mlx5e_close_sqs_wait(c);
1528
1529 err_close_rx_cq:
1530         mlx5e_close_cq(&c->rq.cq);
1531
1532 err_close_tx_cqs:
1533         mlx5e_close_tx_cqs(c);
1534
1535 err_free:
1536         /* destroy mutexes */
1537         mlx5e_chan_mtx_destroy(c);
1538         free(c, M_MLX5EN);
1539         return (err);
1540 }
1541
1542 static void
1543 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1544 {
1545         struct mlx5e_channel *c = *pp;
1546
1547         /* check if channel is already closed */
1548         if (c == NULL)
1549                 return;
1550         mlx5e_close_rq(&c->rq);
1551 }
1552
1553 static void
1554 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1555 {
1556         struct mlx5e_channel *c = *pp;
1557
1558         /* check if channel is already closed */
1559         if (c == NULL)
1560                 return;
1561         /* ensure channel pointer is no longer used */
1562         *pp = NULL;
1563
1564         mlx5e_close_rq_wait(&c->rq);
1565         mlx5e_close_sqs_wait(c);
1566         mlx5e_close_cq(&c->rq.cq);
1567         mlx5e_close_tx_cqs(c);
1568         /* destroy mutexes */
1569         mlx5e_chan_mtx_destroy(c);
1570         free(c, M_MLX5EN);
1571 }
1572
1573 static void
1574 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1575     struct mlx5e_rq_param *param)
1576 {
1577         void *rqc = param->rqc;
1578         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1579
1580         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1581         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1582         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1583         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1584         MLX5_SET(wq, wq, pd, priv->pdn);
1585
1586         param->wq.buf_numa_node = 0;
1587         param->wq.db_numa_node = 0;
1588         param->wq.linear = 1;
1589 }
1590
1591 static void
1592 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1593     struct mlx5e_sq_param *param)
1594 {
1595         void *sqc = param->sqc;
1596         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1597
1598         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1599         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1600         MLX5_SET(wq, wq, pd, priv->pdn);
1601
1602         param->wq.buf_numa_node = 0;
1603         param->wq.db_numa_node = 0;
1604         param->wq.linear = 1;
1605 }
1606
1607 static void
1608 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1609     struct mlx5e_cq_param *param)
1610 {
1611         void *cqc = param->cqc;
1612
1613         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1614 }
1615
1616 static void
1617 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1618     struct mlx5e_cq_param *param)
1619 {
1620         void *cqc = param->cqc;
1621
1622
1623         /*
1624          * TODO The sysctl to control on/off is a bool value for now, which means
1625          * we only support CSUM, once HASH is implemnted we'll need to address that.
1626          */
1627         if (priv->params.cqe_zipping_en) {
1628                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1629                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1630         }
1631
1632         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1633         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1634         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1635
1636         switch (priv->params.rx_cq_moderation_mode) {
1637         case 0:
1638                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1639                 break;
1640         default:
1641                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1642                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1643                 else
1644                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1645                 break;
1646         }
1647
1648         mlx5e_build_common_cq_param(priv, param);
1649 }
1650
1651 static void
1652 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1653     struct mlx5e_cq_param *param)
1654 {
1655         void *cqc = param->cqc;
1656
1657         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1658         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1659         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1660
1661         switch (priv->params.tx_cq_moderation_mode) {
1662         case 0:
1663                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1664                 break;
1665         default:
1666                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1667                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1668                 else
1669                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1670                 break;
1671         }
1672
1673         mlx5e_build_common_cq_param(priv, param);
1674 }
1675
1676 static void
1677 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1678     struct mlx5e_channel_param *cparam)
1679 {
1680         memset(cparam, 0, sizeof(*cparam));
1681
1682         mlx5e_build_rq_param(priv, &cparam->rq);
1683         mlx5e_build_sq_param(priv, &cparam->sq);
1684         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1685         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1686 }
1687
1688 static int
1689 mlx5e_open_channels(struct mlx5e_priv *priv)
1690 {
1691         struct mlx5e_channel_param cparam;
1692         void *ptr;
1693         int err;
1694         int i;
1695         int j;
1696
1697         priv->channel = malloc(priv->params.num_channels *
1698             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1699
1700         mlx5e_build_channel_param(priv, &cparam);
1701         for (i = 0; i < priv->params.num_channels; i++) {
1702                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1703                 if (err)
1704                         goto err_close_channels;
1705         }
1706
1707         for (j = 0; j < priv->params.num_channels; j++) {
1708                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1709                 if (err)
1710                         goto err_close_channels;
1711         }
1712
1713         return (0);
1714
1715 err_close_channels:
1716         for (i--; i >= 0; i--) {
1717                 mlx5e_close_channel(&priv->channel[i]);
1718                 mlx5e_close_channel_wait(&priv->channel[i]);
1719         }
1720
1721         /* remove "volatile" attribute from "channel" pointer */
1722         ptr = __DECONST(void *, priv->channel);
1723         priv->channel = NULL;
1724
1725         free(ptr, M_MLX5EN);
1726
1727         return (err);
1728 }
1729
1730 static void
1731 mlx5e_close_channels(struct mlx5e_priv *priv)
1732 {
1733         void *ptr;
1734         int i;
1735
1736         if (priv->channel == NULL)
1737                 return;
1738
1739         for (i = 0; i < priv->params.num_channels; i++)
1740                 mlx5e_close_channel(&priv->channel[i]);
1741         for (i = 0; i < priv->params.num_channels; i++)
1742                 mlx5e_close_channel_wait(&priv->channel[i]);
1743
1744         /* remove "volatile" attribute from "channel" pointer */
1745         ptr = __DECONST(void *, priv->channel);
1746         priv->channel = NULL;
1747
1748         free(ptr, M_MLX5EN);
1749 }
1750
1751 static int
1752 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1753 {
1754         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1755             priv->params.tx_cq_moderation_usec,
1756             priv->params.tx_cq_moderation_pkts));
1757 }
1758
1759 static int
1760 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1761 {
1762         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1763             priv->params.rx_cq_moderation_usec,
1764             priv->params.rx_cq_moderation_pkts));
1765 }
1766
1767 static int
1768 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1769 {
1770         int err;
1771         int i;
1772
1773         if (c == NULL)
1774                 return (EINVAL);
1775
1776         err = mlx5e_refresh_rq_params(priv, &c->rq);
1777         if (err)
1778                 goto done;
1779
1780         for (i = 0; i != c->num_tc; i++) {
1781                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1782                 if (err)
1783                         goto done;
1784         }
1785 done:
1786         return (err);
1787 }
1788
1789 int
1790 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1791 {
1792         int i;
1793
1794         if (priv->channel == NULL)
1795                 return (EINVAL);
1796
1797         for (i = 0; i < priv->params.num_channels; i++) {
1798                 int err;
1799
1800                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1801                 if (err)
1802                         return (err);
1803         }
1804         return (0);
1805 }
1806
1807 static int
1808 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1809 {
1810         struct mlx5_core_dev *mdev = priv->mdev;
1811         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1812         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1813
1814         memset(in, 0, sizeof(in));
1815
1816         MLX5_SET(tisc, tisc, prio, tc);
1817         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1818
1819         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1820 }
1821
1822 static void
1823 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1824 {
1825         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1826 }
1827
1828 static int
1829 mlx5e_open_tises(struct mlx5e_priv *priv)
1830 {
1831         int num_tc = priv->num_tc;
1832         int err;
1833         int tc;
1834
1835         for (tc = 0; tc < num_tc; tc++) {
1836                 err = mlx5e_open_tis(priv, tc);
1837                 if (err)
1838                         goto err_close_tises;
1839         }
1840
1841         return (0);
1842
1843 err_close_tises:
1844         for (tc--; tc >= 0; tc--)
1845                 mlx5e_close_tis(priv, tc);
1846
1847         return (err);
1848 }
1849
1850 static void
1851 mlx5e_close_tises(struct mlx5e_priv *priv)
1852 {
1853         int num_tc = priv->num_tc;
1854         int tc;
1855
1856         for (tc = 0; tc < num_tc; tc++)
1857                 mlx5e_close_tis(priv, tc);
1858 }
1859
1860 static int
1861 mlx5e_open_rqt(struct mlx5e_priv *priv)
1862 {
1863         struct mlx5_core_dev *mdev = priv->mdev;
1864         u32 *in;
1865         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1866         void *rqtc;
1867         int inlen;
1868         int err;
1869         int sz;
1870         int i;
1871
1872         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1873
1874         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1875         in = mlx5_vzalloc(inlen);
1876         if (in == NULL)
1877                 return (-ENOMEM);
1878         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1879
1880         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1881         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1882
1883         for (i = 0; i < sz; i++) {
1884                 int ix;
1885 #ifdef RSS
1886                 ix = rss_get_indirection_to_bucket(i);
1887 #else
1888                 ix = i;
1889 #endif
1890                 /* ensure we don't overflow */
1891                 ix %= priv->params.num_channels;
1892                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1893         }
1894
1895         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1896
1897         memset(out, 0, sizeof(out));
1898         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1899         if (!err)
1900                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1901
1902         kvfree(in);
1903
1904         return (err);
1905 }
1906
1907 static void
1908 mlx5e_close_rqt(struct mlx5e_priv *priv)
1909 {
1910         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1911         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1912
1913         memset(in, 0, sizeof(in));
1914
1915         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1916         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1917
1918         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1919             sizeof(out));
1920 }
1921
1922 static void
1923 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1924 {
1925         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1926         __be32 *hkey;
1927
1928         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1929
1930 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1931
1932 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1933                           MLX5_HASH_FIELD_SEL_DST_IP)
1934
1935 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1936                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1937                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1938                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1939
1940 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1941                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1942                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1943
1944         if (priv->params.hw_lro_en) {
1945                 MLX5_SET(tirc, tirc, lro_enable_mask,
1946                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1947                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1948                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1949                     (priv->params.lro_wqe_sz -
1950                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1951                 /* TODO: add the option to choose timer value dynamically */
1952                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1953                     MLX5_CAP_ETH(priv->mdev,
1954                     lro_timer_supported_periods[2]));
1955         }
1956
1957         /* setup parameters for hashing TIR type, if any */
1958         switch (tt) {
1959         case MLX5E_TT_ANY:
1960                 MLX5_SET(tirc, tirc, disp_type,
1961                     MLX5_TIRC_DISP_TYPE_DIRECT);
1962                 MLX5_SET(tirc, tirc, inline_rqn,
1963                     priv->channel[0]->rq.rqn);
1964                 break;
1965         default:
1966                 MLX5_SET(tirc, tirc, disp_type,
1967                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1968                 MLX5_SET(tirc, tirc, indirect_table,
1969                     priv->rqtn);
1970                 MLX5_SET(tirc, tirc, rx_hash_fn,
1971                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1972                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1973 #ifdef RSS
1974                 /*
1975                  * The FreeBSD RSS implementation does currently not
1976                  * support symmetric Toeplitz hashes:
1977                  */
1978                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1979                 rss_getkey((uint8_t *)hkey);
1980 #else
1981                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1982                 hkey[0] = cpu_to_be32(0xD181C62C);
1983                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1984                 hkey[2] = cpu_to_be32(0x1983A2FC);
1985                 hkey[3] = cpu_to_be32(0x943E1ADB);
1986                 hkey[4] = cpu_to_be32(0xD9389E6B);
1987                 hkey[5] = cpu_to_be32(0xD1039C2C);
1988                 hkey[6] = cpu_to_be32(0xA74499AD);
1989                 hkey[7] = cpu_to_be32(0x593D56D9);
1990                 hkey[8] = cpu_to_be32(0xF3253C06);
1991                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
1992 #endif
1993                 break;
1994         }
1995
1996         switch (tt) {
1997         case MLX5E_TT_IPV4_TCP:
1998                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1999                     MLX5_L3_PROT_TYPE_IPV4);
2000                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2001                     MLX5_L4_PROT_TYPE_TCP);
2002 #ifdef RSS
2003                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2004                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2005                             MLX5_HASH_IP);
2006                 } else
2007 #endif
2008                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2009                     MLX5_HASH_ALL);
2010                 break;
2011
2012         case MLX5E_TT_IPV6_TCP:
2013                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2014                     MLX5_L3_PROT_TYPE_IPV6);
2015                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2016                     MLX5_L4_PROT_TYPE_TCP);
2017 #ifdef RSS
2018                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2019                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2020                             MLX5_HASH_IP);
2021                 } else
2022 #endif
2023                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2024                     MLX5_HASH_ALL);
2025                 break;
2026
2027         case MLX5E_TT_IPV4_UDP:
2028                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2029                     MLX5_L3_PROT_TYPE_IPV4);
2030                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2031                     MLX5_L4_PROT_TYPE_UDP);
2032 #ifdef RSS
2033                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2034                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2035                             MLX5_HASH_IP);
2036                 } else
2037 #endif
2038                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2039                     MLX5_HASH_ALL);
2040                 break;
2041
2042         case MLX5E_TT_IPV6_UDP:
2043                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2044                     MLX5_L3_PROT_TYPE_IPV6);
2045                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2046                     MLX5_L4_PROT_TYPE_UDP);
2047 #ifdef RSS
2048                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2049                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2050                             MLX5_HASH_IP);
2051                 } else
2052 #endif
2053                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2054                     MLX5_HASH_ALL);
2055                 break;
2056
2057         case MLX5E_TT_IPV4_IPSEC_AH:
2058                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2059                     MLX5_L3_PROT_TYPE_IPV4);
2060                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2061                     MLX5_HASH_IP_IPSEC_SPI);
2062                 break;
2063
2064         case MLX5E_TT_IPV6_IPSEC_AH:
2065                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2066                     MLX5_L3_PROT_TYPE_IPV6);
2067                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2068                     MLX5_HASH_IP_IPSEC_SPI);
2069                 break;
2070
2071         case MLX5E_TT_IPV4_IPSEC_ESP:
2072                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2073                     MLX5_L3_PROT_TYPE_IPV4);
2074                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2075                     MLX5_HASH_IP_IPSEC_SPI);
2076                 break;
2077
2078         case MLX5E_TT_IPV6_IPSEC_ESP:
2079                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2080                     MLX5_L3_PROT_TYPE_IPV6);
2081                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2082                     MLX5_HASH_IP_IPSEC_SPI);
2083                 break;
2084
2085         case MLX5E_TT_IPV4:
2086                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2087                     MLX5_L3_PROT_TYPE_IPV4);
2088                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2089                     MLX5_HASH_IP);
2090                 break;
2091
2092         case MLX5E_TT_IPV6:
2093                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2094                     MLX5_L3_PROT_TYPE_IPV6);
2095                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2096                     MLX5_HASH_IP);
2097                 break;
2098
2099         default:
2100                 break;
2101         }
2102 }
2103
2104 static int
2105 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2106 {
2107         struct mlx5_core_dev *mdev = priv->mdev;
2108         u32 *in;
2109         void *tirc;
2110         int inlen;
2111         int err;
2112
2113         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2114         in = mlx5_vzalloc(inlen);
2115         if (in == NULL)
2116                 return (-ENOMEM);
2117         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2118
2119         mlx5e_build_tir_ctx(priv, tirc, tt);
2120
2121         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2122
2123         kvfree(in);
2124
2125         return (err);
2126 }
2127
2128 static void
2129 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2130 {
2131         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2132 }
2133
2134 static int
2135 mlx5e_open_tirs(struct mlx5e_priv *priv)
2136 {
2137         int err;
2138         int i;
2139
2140         for (i = 0; i < MLX5E_NUM_TT; i++) {
2141                 err = mlx5e_open_tir(priv, i);
2142                 if (err)
2143                         goto err_close_tirs;
2144         }
2145
2146         return (0);
2147
2148 err_close_tirs:
2149         for (i--; i >= 0; i--)
2150                 mlx5e_close_tir(priv, i);
2151
2152         return (err);
2153 }
2154
2155 static void
2156 mlx5e_close_tirs(struct mlx5e_priv *priv)
2157 {
2158         int i;
2159
2160         for (i = 0; i < MLX5E_NUM_TT; i++)
2161                 mlx5e_close_tir(priv, i);
2162 }
2163
2164 /*
2165  * SW MTU does not include headers,
2166  * HW MTU includes all headers and checksums.
2167  */
2168 static int
2169 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2170 {
2171         struct mlx5e_priv *priv = ifp->if_softc;
2172         struct mlx5_core_dev *mdev = priv->mdev;
2173         int hw_mtu;
2174         int err;
2175
2176         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2177         if (err) {
2178                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2179                     __func__, sw_mtu, err);
2180                 return (err);
2181         }
2182         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2183         if (err) {
2184                 if_printf(ifp, "Query port MTU, after setting new "
2185                     "MTU value, failed\n");
2186         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2187                 err = -E2BIG,
2188                 if_printf(ifp, "Port MTU %d is smaller than "
2189                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2190         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2191                 err = -EINVAL;
2192                 if_printf(ifp, "Port MTU %d is bigger than "
2193                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2194         }
2195         ifp->if_mtu = sw_mtu;
2196         return (err);
2197 }
2198
2199 int
2200 mlx5e_open_locked(struct ifnet *ifp)
2201 {
2202         struct mlx5e_priv *priv = ifp->if_softc;
2203         int err;
2204         u16 set_id;
2205
2206         /* check if already opened */
2207         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2208                 return (0);
2209
2210 #ifdef RSS
2211         if (rss_getnumbuckets() > priv->params.num_channels) {
2212                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2213                     "channels(%u) available\n", rss_getnumbuckets(),
2214                     priv->params.num_channels);
2215         }
2216 #endif
2217         err = mlx5e_open_tises(priv);
2218         if (err) {
2219                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2220                     __func__, err);
2221                 return (err);
2222         }
2223         err = mlx5_vport_alloc_q_counter(priv->mdev,
2224             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2225         if (err) {
2226                 if_printf(priv->ifp,
2227                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2228                     __func__, err);
2229                 goto err_close_tises;
2230         }
2231         /* store counter set ID */
2232         priv->counter_set_id = set_id;
2233
2234         err = mlx5e_open_channels(priv);
2235         if (err) {
2236                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2237                     __func__, err);
2238                 goto err_dalloc_q_counter;
2239         }
2240         err = mlx5e_open_rqt(priv);
2241         if (err) {
2242                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2243                     __func__, err);
2244                 goto err_close_channels;
2245         }
2246         err = mlx5e_open_tirs(priv);
2247         if (err) {
2248                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2249                     __func__, err);
2250                 goto err_close_rqls;
2251         }
2252         err = mlx5e_open_flow_table(priv);
2253         if (err) {
2254                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2255                     __func__, err);
2256                 goto err_close_tirs;
2257         }
2258         err = mlx5e_add_all_vlan_rules(priv);
2259         if (err) {
2260                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2261                     __func__, err);
2262                 goto err_close_flow_table;
2263         }
2264         set_bit(MLX5E_STATE_OPENED, &priv->state);
2265
2266         mlx5e_update_carrier(priv);
2267         mlx5e_set_rx_mode_core(priv);
2268
2269         return (0);
2270
2271 err_close_flow_table:
2272         mlx5e_close_flow_table(priv);
2273
2274 err_close_tirs:
2275         mlx5e_close_tirs(priv);
2276
2277 err_close_rqls:
2278         mlx5e_close_rqt(priv);
2279
2280 err_close_channels:
2281         mlx5e_close_channels(priv);
2282
2283 err_dalloc_q_counter:
2284         mlx5_vport_dealloc_q_counter(priv->mdev,
2285             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2286
2287 err_close_tises:
2288         mlx5e_close_tises(priv);
2289
2290         return (err);
2291 }
2292
2293 static void
2294 mlx5e_open(void *arg)
2295 {
2296         struct mlx5e_priv *priv = arg;
2297
2298         PRIV_LOCK(priv);
2299         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2300                 if_printf(priv->ifp,
2301                     "%s: Setting port status to up failed\n",
2302                     __func__);
2303
2304         mlx5e_open_locked(priv->ifp);
2305         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2306         PRIV_UNLOCK(priv);
2307 }
2308
2309 int
2310 mlx5e_close_locked(struct ifnet *ifp)
2311 {
2312         struct mlx5e_priv *priv = ifp->if_softc;
2313
2314         /* check if already closed */
2315         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2316                 return (0);
2317
2318         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2319
2320         mlx5e_set_rx_mode_core(priv);
2321         mlx5e_del_all_vlan_rules(priv);
2322         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2323         mlx5e_close_flow_table(priv);
2324         mlx5e_close_tirs(priv);
2325         mlx5e_close_rqt(priv);
2326         mlx5e_close_channels(priv);
2327         mlx5_vport_dealloc_q_counter(priv->mdev,
2328             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2329         mlx5e_close_tises(priv);
2330
2331         return (0);
2332 }
2333
2334 #if (__FreeBSD_version >= 1100000)
2335 static uint64_t
2336 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2337 {
2338         struct mlx5e_priv *priv = ifp->if_softc;
2339         u64 retval;
2340
2341         /* PRIV_LOCK(priv); XXX not allowed */
2342         switch (cnt) {
2343         case IFCOUNTER_IPACKETS:
2344                 retval = priv->stats.vport.rx_packets;
2345                 break;
2346         case IFCOUNTER_IERRORS:
2347                 retval = priv->stats.vport.rx_error_packets;
2348                 break;
2349         case IFCOUNTER_IQDROPS:
2350                 retval = priv->stats.vport.rx_out_of_buffer;
2351                 break;
2352         case IFCOUNTER_OPACKETS:
2353                 retval = priv->stats.vport.tx_packets;
2354                 break;
2355         case IFCOUNTER_OERRORS:
2356                 retval = priv->stats.vport.tx_error_packets;
2357                 break;
2358         case IFCOUNTER_IBYTES:
2359                 retval = priv->stats.vport.rx_bytes;
2360                 break;
2361         case IFCOUNTER_OBYTES:
2362                 retval = priv->stats.vport.tx_bytes;
2363                 break;
2364         case IFCOUNTER_IMCASTS:
2365                 retval = priv->stats.vport.rx_multicast_packets;
2366                 break;
2367         case IFCOUNTER_OMCASTS:
2368                 retval = priv->stats.vport.tx_multicast_packets;
2369                 break;
2370         case IFCOUNTER_OQDROPS:
2371                 retval = priv->stats.vport.tx_queue_dropped;
2372                 break;
2373         default:
2374                 retval = if_get_counter_default(ifp, cnt);
2375                 break;
2376         }
2377         /* PRIV_UNLOCK(priv); XXX not allowed */
2378         return (retval);
2379 }
2380 #endif
2381
2382 static void
2383 mlx5e_set_rx_mode(struct ifnet *ifp)
2384 {
2385         struct mlx5e_priv *priv = ifp->if_softc;
2386
2387         schedule_work(&priv->set_rx_mode_work);
2388 }
2389
2390 static int
2391 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2392 {
2393         struct mlx5e_priv *priv;
2394         struct ifreq *ifr;
2395         struct ifi2creq i2c;
2396         int error = 0;
2397         int mask = 0;
2398         int size_read = 0;
2399         int module_num;
2400         int max_mtu;
2401         uint8_t read_addr;
2402
2403         priv = ifp->if_softc;
2404
2405         /* check if detaching */
2406         if (priv == NULL || priv->gone != 0)
2407                 return (ENXIO);
2408
2409         switch (command) {
2410         case SIOCSIFMTU:
2411                 ifr = (struct ifreq *)data;
2412
2413                 PRIV_LOCK(priv);
2414                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2415
2416                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2417                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2418                         int was_opened;
2419
2420                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2421                         if (was_opened)
2422                                 mlx5e_close_locked(ifp);
2423
2424                         /* set new MTU */
2425                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2426
2427                         if (was_opened)
2428                                 mlx5e_open_locked(ifp);
2429                 } else {
2430                         error = EINVAL;
2431                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2432                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2433                 }
2434                 PRIV_UNLOCK(priv);
2435                 break;
2436         case SIOCSIFFLAGS:
2437                 if ((ifp->if_flags & IFF_UP) &&
2438                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2439                         mlx5e_set_rx_mode(ifp);
2440                         break;
2441                 }
2442                 PRIV_LOCK(priv);
2443                 if (ifp->if_flags & IFF_UP) {
2444                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2445                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2446                                         mlx5e_open_locked(ifp);
2447                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2448                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2449                         }
2450                 } else {
2451                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2452                                 mlx5_set_port_status(priv->mdev,
2453                                     MLX5_PORT_DOWN);
2454                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2455                                         mlx5e_close_locked(ifp);
2456                                 mlx5e_update_carrier(priv);
2457                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2458                         }
2459                 }
2460                 PRIV_UNLOCK(priv);
2461                 break;
2462         case SIOCADDMULTI:
2463         case SIOCDELMULTI:
2464                 mlx5e_set_rx_mode(ifp);
2465                 break;
2466         case SIOCSIFMEDIA:
2467         case SIOCGIFMEDIA:
2468         case SIOCGIFXMEDIA:
2469                 ifr = (struct ifreq *)data;
2470                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2471                 break;
2472         case SIOCSIFCAP:
2473                 ifr = (struct ifreq *)data;
2474                 PRIV_LOCK(priv);
2475                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2476
2477                 if (mask & IFCAP_TXCSUM) {
2478                         ifp->if_capenable ^= IFCAP_TXCSUM;
2479                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2480
2481                         if (IFCAP_TSO4 & ifp->if_capenable &&
2482                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2483                                 ifp->if_capenable &= ~IFCAP_TSO4;
2484                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2485                                 if_printf(ifp,
2486                                     "tso4 disabled due to -txcsum.\n");
2487                         }
2488                 }
2489                 if (mask & IFCAP_TXCSUM_IPV6) {
2490                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2491                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2492
2493                         if (IFCAP_TSO6 & ifp->if_capenable &&
2494                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2495                                 ifp->if_capenable &= ~IFCAP_TSO6;
2496                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2497                                 if_printf(ifp,
2498                                     "tso6 disabled due to -txcsum6.\n");
2499                         }
2500                 }
2501                 if (mask & IFCAP_RXCSUM)
2502                         ifp->if_capenable ^= IFCAP_RXCSUM;
2503                 if (mask & IFCAP_RXCSUM_IPV6)
2504                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2505                 if (mask & IFCAP_TSO4) {
2506                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2507                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2508                                 if_printf(ifp, "enable txcsum first.\n");
2509                                 error = EAGAIN;
2510                                 goto out;
2511                         }
2512                         ifp->if_capenable ^= IFCAP_TSO4;
2513                         ifp->if_hwassist ^= CSUM_IP_TSO;
2514                 }
2515                 if (mask & IFCAP_TSO6) {
2516                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2517                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2518                                 if_printf(ifp, "enable txcsum6 first.\n");
2519                                 error = EAGAIN;
2520                                 goto out;
2521                         }
2522                         ifp->if_capenable ^= IFCAP_TSO6;
2523                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2524                 }
2525                 if (mask & IFCAP_VLAN_HWFILTER) {
2526                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2527                                 mlx5e_disable_vlan_filter(priv);
2528                         else
2529                                 mlx5e_enable_vlan_filter(priv);
2530
2531                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2532                 }
2533                 if (mask & IFCAP_VLAN_HWTAGGING)
2534                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2535                 if (mask & IFCAP_WOL_MAGIC)
2536                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2537
2538                 VLAN_CAPABILITIES(ifp);
2539                 /* turn off LRO means also turn of HW LRO - if it's on */
2540                 if (mask & IFCAP_LRO) {
2541                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2542                         bool need_restart = false;
2543
2544                         ifp->if_capenable ^= IFCAP_LRO;
2545                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2546                                 if (priv->params.hw_lro_en) {
2547                                         priv->params.hw_lro_en = false;
2548                                         need_restart = true;
2549                                         /* Not sure this is the correct way */
2550                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2551                                 }
2552                         }
2553                         if (was_opened && need_restart) {
2554                                 mlx5e_close_locked(ifp);
2555                                 mlx5e_open_locked(ifp);
2556                         }
2557                 }
2558 out:
2559                 PRIV_UNLOCK(priv);
2560                 break;
2561
2562         case SIOCGI2C:
2563                 ifr = (struct ifreq *)data;
2564
2565                 /*
2566                  * Copy from the user-space address ifr_data to the
2567                  * kernel-space address i2c
2568                  */
2569                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2570                 if (error)
2571                         break;
2572
2573                 if (i2c.len > sizeof(i2c.data)) {
2574                         error = EINVAL;
2575                         break;
2576                 }
2577
2578                 PRIV_LOCK(priv);
2579                 /* Get module_num which is required for the query_eeprom */
2580                 error = mlx5_query_module_num(priv->mdev, &module_num);
2581                 if (error) {
2582                         if_printf(ifp, "Query module num failed, eeprom "
2583                             "reading is not supported\n");
2584                         error = EINVAL;
2585                         goto err_i2c;
2586                 }
2587                 /* Check if module is present before doing an access */
2588                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2589                     MLX5_MODULE_STATUS_PLUGGED) {
2590                         error = EINVAL;
2591                         goto err_i2c;
2592                 }
2593                 /*
2594                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2595                  * The internal conversion is as follows:
2596                  */
2597                 if (i2c.dev_addr == 0xA0)
2598                         read_addr = MLX5E_I2C_ADDR_LOW;
2599                 else if (i2c.dev_addr == 0xA2)
2600                         read_addr = MLX5E_I2C_ADDR_HIGH;
2601                 else {
2602                         if_printf(ifp, "Query eeprom failed, "
2603                             "Invalid Address: %X\n", i2c.dev_addr);
2604                         error = EINVAL;
2605                         goto err_i2c;
2606                 }
2607                 error = mlx5_query_eeprom(priv->mdev,
2608                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2609                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2610                     (uint32_t *)i2c.data, &size_read);
2611                 if (error) {
2612                         if_printf(ifp, "Query eeprom failed, eeprom "
2613                             "reading is not supported\n");
2614                         error = EINVAL;
2615                         goto err_i2c;
2616                 }
2617
2618                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2619                         error = mlx5_query_eeprom(priv->mdev,
2620                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2621                             (uint32_t)(i2c.offset + size_read),
2622                             (uint32_t)(i2c.len - size_read), module_num,
2623                             (uint32_t *)(i2c.data + size_read), &size_read);
2624                 }
2625                 if (error) {
2626                         if_printf(ifp, "Query eeprom failed, eeprom "
2627                             "reading is not supported\n");
2628                         error = EINVAL;
2629                         goto err_i2c;
2630                 }
2631
2632                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2633 err_i2c:
2634                 PRIV_UNLOCK(priv);
2635                 break;
2636
2637         default:
2638                 error = ether_ioctl(ifp, command, data);
2639                 break;
2640         }
2641         return (error);
2642 }
2643
2644 static int
2645 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2646 {
2647         /*
2648          * TODO: uncoment once FW really sets all these bits if
2649          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2650          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2651          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2652          * -ENOTSUPP;
2653          */
2654
2655         /* TODO: add more must-to-have features */
2656
2657         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2658                 return (-ENODEV);
2659
2660         return (0);
2661 }
2662
2663 static void
2664 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2665     struct mlx5e_priv *priv,
2666     int num_comp_vectors)
2667 {
2668         /*
2669          * TODO: Consider link speed for setting "log_sq_size",
2670          * "log_rq_size" and "cq_moderation_xxx":
2671          */
2672         priv->params.log_sq_size =
2673             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2674         priv->params.log_rq_size =
2675             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2676         priv->params.rx_cq_moderation_usec =
2677             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2678             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2679             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2680         priv->params.rx_cq_moderation_mode =
2681             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2682         priv->params.rx_cq_moderation_pkts =
2683             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2684         priv->params.tx_cq_moderation_usec =
2685             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2686         priv->params.tx_cq_moderation_pkts =
2687             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2688         priv->params.min_rx_wqes =
2689             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2690         priv->params.rx_hash_log_tbl_sz =
2691             (order_base_2(num_comp_vectors) >
2692             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2693             order_base_2(num_comp_vectors) :
2694             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2695         priv->params.num_tc = 1;
2696         priv->params.default_vlan_prio = 0;
2697         priv->counter_set_id = -1;
2698
2699         /*
2700          * hw lro is currently defaulted to off. when it won't anymore we
2701          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2702          */
2703         priv->params.hw_lro_en = false;
2704         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2705
2706         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2707
2708         priv->mdev = mdev;
2709         priv->params.num_channels = num_comp_vectors;
2710         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2711         priv->queue_mapping_channel_mask =
2712             roundup_pow_of_two(num_comp_vectors) - 1;
2713         priv->num_tc = priv->params.num_tc;
2714         priv->default_vlan_prio = priv->params.default_vlan_prio;
2715
2716         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2717         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2718         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2719 }
2720
2721 static int
2722 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2723     struct mlx5_core_mr *mr)
2724 {
2725         struct ifnet *ifp = priv->ifp;
2726         struct mlx5_core_dev *mdev = priv->mdev;
2727         struct mlx5_create_mkey_mbox_in *in;
2728         int err;
2729
2730         in = mlx5_vzalloc(sizeof(*in));
2731         if (in == NULL) {
2732                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2733                 return (-ENOMEM);
2734         }
2735         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2736             MLX5_PERM_LOCAL_READ |
2737             MLX5_ACCESS_MODE_PA;
2738         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2739         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2740
2741         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2742             NULL);
2743         if (err)
2744                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2745                     __func__, err);
2746
2747         kvfree(in);
2748
2749         return (err);
2750 }
2751
2752 static const char *mlx5e_vport_stats_desc[] = {
2753         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2754 };
2755
2756 static const char *mlx5e_pport_stats_desc[] = {
2757         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2758 };
2759
2760 static void
2761 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2762 {
2763         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2764         sx_init(&priv->state_lock, "mlx5state");
2765         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2766         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2767 }
2768
2769 static void
2770 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2771 {
2772         mtx_destroy(&priv->async_events_mtx);
2773         sx_destroy(&priv->state_lock);
2774 }
2775
2776 static int
2777 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2778 {
2779         /*
2780          * %d.%d%.d the string format.
2781          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2782          * We need at most 5 chars to store that.
2783          * It also has: two "." and NULL at the end, which means we need 18
2784          * (5*3 + 3) chars at most.
2785          */
2786         char fw[18];
2787         struct mlx5e_priv *priv = arg1;
2788         int error;
2789
2790         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2791             fw_rev_sub(priv->mdev));
2792         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2793         return (error);
2794 }
2795
2796 static void
2797 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2798 {
2799         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2800             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2801             sysctl_firmware, "A", "HCA firmware version");
2802
2803         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2804             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2805             "Board ID");
2806 }
2807
2808 static void
2809 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2810 {
2811 #if (__FreeBSD_version < 1100000)
2812         char path[64];
2813
2814 #endif
2815         /* Only receiving pauseframes is enabled by default */
2816         priv->params.tx_pauseframe_control = 0;
2817         priv->params.rx_pauseframe_control = 1;
2818
2819 #if (__FreeBSD_version < 1100000)
2820         /* compute path for sysctl */
2821         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2822             device_get_unit(priv->mdev->pdev->dev.bsddev));
2823
2824         /* try to fetch tunable, if any */
2825         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2826
2827         /* compute path for sysctl */
2828         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2829             device_get_unit(priv->mdev->pdev->dev.bsddev));
2830
2831         /* try to fetch tunable, if any */
2832         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2833 #endif
2834
2835         /* register pausframe SYSCTLs */
2836         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2837             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2838             &priv->params.tx_pauseframe_control, 0,
2839             "Set to enable TX pause frames. Clear to disable.");
2840
2841         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2842             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2843             &priv->params.rx_pauseframe_control, 0,
2844             "Set to enable RX pause frames. Clear to disable.");
2845
2846         /* range check */
2847         priv->params.tx_pauseframe_control =
2848             priv->params.tx_pauseframe_control ? 1 : 0;
2849         priv->params.rx_pauseframe_control =
2850             priv->params.rx_pauseframe_control ? 1 : 0;
2851
2852         /* update firmware */
2853         mlx5_set_port_pause(priv->mdev, 1,
2854             priv->params.rx_pauseframe_control,
2855             priv->params.tx_pauseframe_control);
2856 }
2857
2858 static void *
2859 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2860 {
2861         static volatile int mlx5_en_unit;
2862         struct ifnet *ifp;
2863         struct mlx5e_priv *priv;
2864         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2865         struct sysctl_oid_list *child;
2866         int ncv = mdev->priv.eq_table.num_comp_vectors;
2867         char unit[16];
2868         int err;
2869         int i;
2870         u32 eth_proto_cap;
2871
2872         if (mlx5e_check_required_hca_cap(mdev)) {
2873                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2874                 return (NULL);
2875         }
2876         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2877         mlx5e_priv_mtx_init(priv);
2878
2879         ifp = priv->ifp = if_alloc(IFT_ETHER);
2880         if (ifp == NULL) {
2881                 mlx5_core_err(mdev, "if_alloc() failed\n");
2882                 goto err_free_priv;
2883         }
2884         ifp->if_softc = priv;
2885         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2886         ifp->if_mtu = ETHERMTU;
2887         ifp->if_init = mlx5e_open;
2888         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2889         ifp->if_ioctl = mlx5e_ioctl;
2890         ifp->if_transmit = mlx5e_xmit;
2891         ifp->if_qflush = if_qflush;
2892 #if (__FreeBSD_version >= 1100000)
2893         ifp->if_get_counter = mlx5e_get_counter;
2894 #endif
2895         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2896         /*
2897          * Set driver features
2898          */
2899         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2900         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2901         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2902         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2903         ifp->if_capabilities |= IFCAP_LRO;
2904         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2905         ifp->if_capabilities |= IFCAP_HWSTATS;
2906
2907         /* set TSO limits so that we don't have to drop TX packets */
2908         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2909         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2910         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2911
2912         ifp->if_capenable = ifp->if_capabilities;
2913         ifp->if_hwassist = 0;
2914         if (ifp->if_capenable & IFCAP_TSO)
2915                 ifp->if_hwassist |= CSUM_TSO;
2916         if (ifp->if_capenable & IFCAP_TXCSUM)
2917                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2918         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2919                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2920
2921         /* ifnet sysctl tree */
2922         sysctl_ctx_init(&priv->sysctl_ctx);
2923         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2924             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2925         if (priv->sysctl_ifnet == NULL) {
2926                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2927                 goto err_free_sysctl;
2928         }
2929         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2930         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2931             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2932         if (priv->sysctl_ifnet == NULL) {
2933                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2934                 goto err_free_sysctl;
2935         }
2936
2937         /* HW sysctl tree */
2938         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2939         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2940             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2941         if (priv->sysctl_hw == NULL) {
2942                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2943                 goto err_free_sysctl;
2944         }
2945         mlx5e_build_ifp_priv(mdev, priv, ncv);
2946         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2947         if (err) {
2948                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2949                     __func__, err);
2950                 goto err_free_sysctl;
2951         }
2952         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2953         if (err) {
2954                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2955                     __func__, err);
2956                 goto err_unmap_free_uar;
2957         }
2958         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2959         if (err) {
2960                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2961                     __func__, err);
2962                 goto err_dealloc_pd;
2963         }
2964         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2965         if (err) {
2966                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2967                     __func__, err);
2968                 goto err_dealloc_transport_domain;
2969         }
2970         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2971
2972         /* check if we should generate a random MAC address */
2973         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2974             is_zero_ether_addr(dev_addr)) {
2975                 random_ether_addr(dev_addr);
2976                 if_printf(ifp, "Assigned random MAC address\n");
2977         }
2978
2979         /* set default MTU */
2980         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2981
2982         /* Set desc */
2983         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2984
2985         /* Set default media status */
2986         priv->media_status_last = IFM_AVALID;
2987         priv->media_active_last = IFM_ETHER | IFM_AUTO |
2988             IFM_ETH_RXPAUSE | IFM_FDX;
2989
2990         /* setup default pauseframes configuration */
2991         mlx5e_setup_pauseframes(priv);
2992
2993         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
2994         if (err) {
2995                 eth_proto_cap = 0;
2996                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
2997                     __func__, err);
2998         }
2999
3000         /* Setup supported medias */
3001         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3002             mlx5e_media_change, mlx5e_media_status);
3003
3004         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3005                 if (mlx5e_mode_table[i].baudrate == 0)
3006                         continue;
3007                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3008                         ifmedia_add(&priv->media,
3009                             mlx5e_mode_table[i].subtype |
3010                             IFM_ETHER, 0, NULL);
3011                         ifmedia_add(&priv->media,
3012                             mlx5e_mode_table[i].subtype |
3013                             IFM_ETHER | IFM_FDX |
3014                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3015                 }
3016         }
3017
3018         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3019         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3020             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3021
3022         /* Set autoselect by default */
3023         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3024             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3025         ether_ifattach(ifp, dev_addr);
3026
3027         /* Register for VLAN events */
3028         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3029             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3030         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3031             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3032
3033         /* Link is down by default */
3034         if_link_state_change(ifp, LINK_STATE_DOWN);
3035
3036         mlx5e_enable_async_events(priv);
3037
3038         mlx5e_add_hw_stats(priv);
3039
3040         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3041             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3042             priv->stats.vport.arg);
3043
3044         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3045             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3046             priv->stats.pport.arg);
3047
3048         mlx5e_create_ethtool(priv);
3049
3050         mtx_lock(&priv->async_events_mtx);
3051         mlx5e_update_stats(priv);
3052         mtx_unlock(&priv->async_events_mtx);
3053
3054         return (priv);
3055
3056 err_dealloc_transport_domain:
3057         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3058
3059 err_dealloc_pd:
3060         mlx5_core_dealloc_pd(mdev, priv->pdn);
3061
3062 err_unmap_free_uar:
3063         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3064
3065 err_free_sysctl:
3066         sysctl_ctx_free(&priv->sysctl_ctx);
3067
3068         if_free(ifp);
3069
3070 err_free_priv:
3071         mlx5e_priv_mtx_destroy(priv);
3072         free(priv, M_MLX5EN);
3073         return (NULL);
3074 }
3075
3076 static void
3077 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3078 {
3079         struct mlx5e_priv *priv = vpriv;
3080         struct ifnet *ifp = priv->ifp;
3081
3082         /* don't allow more IOCTLs */
3083         priv->gone = 1;
3084
3085         /*
3086          * Clear the device description to avoid use after free,
3087          * because the bsddev is not destroyed when this module is
3088          * unloaded:
3089          */
3090         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3091
3092         /* XXX wait a bit to allow IOCTL handlers to complete */
3093         pause("W", hz);
3094
3095         /* stop watchdog timer */
3096         callout_drain(&priv->watchdog);
3097
3098         if (priv->vlan_attach != NULL)
3099                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3100         if (priv->vlan_detach != NULL)
3101                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3102
3103         /* make sure device gets closed */
3104         PRIV_LOCK(priv);
3105         mlx5e_close_locked(ifp);
3106         PRIV_UNLOCK(priv);
3107
3108         /* unregister device */
3109         ifmedia_removeall(&priv->media);
3110         ether_ifdetach(ifp);
3111         if_free(ifp);
3112
3113         /* destroy all remaining sysctl nodes */
3114         if (priv->sysctl_debug)
3115                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3116         sysctl_ctx_free(&priv->stats.vport.ctx);
3117         sysctl_ctx_free(&priv->stats.pport.ctx);
3118         sysctl_ctx_free(&priv->sysctl_ctx);
3119
3120         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3121         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3122         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3123         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3124         mlx5e_disable_async_events(priv);
3125         flush_scheduled_work();
3126         mlx5e_priv_mtx_destroy(priv);
3127         free(priv, M_MLX5EN);
3128 }
3129
3130 static void *
3131 mlx5e_get_ifp(void *vpriv)
3132 {
3133         struct mlx5e_priv *priv = vpriv;
3134
3135         return (priv->ifp);
3136 }
3137
3138 static struct mlx5_interface mlx5e_interface = {
3139         .add = mlx5e_create_ifp,
3140         .remove = mlx5e_destroy_ifp,
3141         .event = mlx5e_async_event,
3142         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3143         .get_dev = mlx5e_get_ifp,
3144 };
3145
3146 void
3147 mlx5e_init(void)
3148 {
3149         mlx5_register_interface(&mlx5e_interface);
3150 }
3151
3152 void
3153 mlx5e_cleanup(void)
3154 {
3155         mlx5_unregister_interface(&mlx5e_interface);
3156 }
3157
3158 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3159 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3160
3161 #if (__FreeBSD_version >= 1100000)
3162 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3163 #endif
3164 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3165 MODULE_VERSION(mlx5en, 1);