2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <machine/in_cksum.h>
32 mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq,
33 struct mlx5e_rx_wqe *wqe, u16 ix)
35 bus_dma_segment_t segs[1];
40 if (rq->mbuf[ix].mbuf != NULL)
43 mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rq->wqe_sz);
47 /* set initial mbuf length */
48 mb->m_pkthdr.len = mb->m_len = rq->wqe_sz;
50 /* get IP header aligned */
51 m_adj(mb, MLX5E_NET_IP_ALIGN);
53 err = -bus_dmamap_load_mbuf_sg(rq->dma_tag, rq->mbuf[ix].dma_map,
54 mb, segs, &nsegs, BUS_DMA_NOWAIT);
57 if (unlikely(nsegs != 1)) {
58 bus_dmamap_unload(rq->dma_tag, rq->mbuf[ix].dma_map);
62 wqe->data.addr = cpu_to_be64(segs[0].ds_addr);
64 rq->mbuf[ix].mbuf = mb;
65 rq->mbuf[ix].data = mb->m_data;
67 bus_dmamap_sync(rq->dma_tag, rq->mbuf[ix].dma_map,
77 mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
79 if (unlikely(rq->enabled == 0))
82 while (!mlx5_wq_ll_is_full(&rq->wq)) {
83 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, rq->wq.head);
85 if (unlikely(mlx5e_alloc_rx_wqe(rq, wqe, rq->wq.head)))
88 mlx5_wq_ll_push(&rq->wq, be16_to_cpu(wqe->next.next_wqe_index));
91 /* ensure wqes are visible to device before updating doorbell record */
94 mlx5_wq_ll_update_db_record(&rq->wq);
98 mlx5e_lro_update_hdr(struct mbuf *mb, struct mlx5_cqe64 *cqe)
100 /* TODO: consider vlans, ip options, ... */
101 struct ether_header *eh;
103 struct ip6_hdr *ip6 = NULL;
104 struct ip *ip4 = NULL;
108 eh = mtod(mb, struct ether_header *);
109 eh_type = ntohs(eh->ether_type);
111 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
112 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
113 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
115 /* TODO: consider vlan */
116 u16 tot_len = be32_to_cpu(cqe->byte_cnt) - ETHER_HDR_LEN;
120 ip4 = (struct ip *)(eh + 1);
121 th = (struct tcphdr *)(ip4 + 1);
124 ip6 = (struct ip6_hdr *)(eh + 1);
125 th = (struct tcphdr *)(ip6 + 1);
131 ts_ptr = (uint32_t *)(th + 1);
133 if (get_cqe_lro_tcppsh(cqe))
134 th->th_flags |= TH_PUSH;
137 th->th_flags |= TH_ACK;
138 th->th_ack = cqe->lro_ack_seq_num;
139 th->th_win = cqe->lro_tcp_win;
142 * FreeBSD handles only 32bit aligned timestamp right after
144 * +--------+--------+--------+--------+
145 * | NOP | NOP | TSopt | 10 |
146 * +--------+--------+--------+--------+
147 * | TSval timestamp |
148 * +--------+--------+--------+--------+
149 * | TSecr timestamp |
150 * +--------+--------+--------+--------+
152 if (get_cqe_lro_timestamp_valid(cqe) &&
153 (__predict_true(*ts_ptr) == ntohl(TCPOPT_NOP << 24 |
154 TCPOPT_NOP << 16 | TCPOPT_TIMESTAMP << 8 |
155 TCPOLEN_TIMESTAMP))) {
157 * cqe->timestamp is 64bit long.
158 * [0-31] - timestamp.
159 * [32-64] - timestamp echo replay.
161 ts_ptr[1] = *(uint32_t *)&cqe->timestamp;
162 ts_ptr[2] = *((uint32_t *)&cqe->timestamp + 1);
166 ip4->ip_ttl = cqe->lro_min_ttl;
167 ip4->ip_len = cpu_to_be16(tot_len);
169 ip4->ip_sum = in_cksum(mb, ip4->ip_hl << 2);
171 ip6->ip6_hlim = cqe->lro_min_ttl;
172 ip6->ip6_plen = cpu_to_be16(tot_len -
173 sizeof(struct ip6_hdr));
175 /* TODO: handle tcp checksum */
179 mlx5e_build_rx_mbuf(struct mlx5_cqe64 *cqe,
180 struct mlx5e_rq *rq, struct mbuf *mb,
183 struct ifnet *ifp = rq->ifp;
184 int lro_num_seg; /* HW LRO session aggregated packets counter */
186 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
187 if (lro_num_seg > 1) {
188 mlx5e_lro_update_hdr(mb, cqe);
189 rq->stats.lro_packets++;
190 rq->stats.lro_bytes += cqe_bcnt;
193 mb->m_pkthdr.len = mb->m_len = cqe_bcnt;
194 /* check if a Toeplitz hash was computed */
195 if (cqe->rss_hash_type != 0) {
196 mb->m_pkthdr.flowid = be32_to_cpu(cqe->rss_hash_result);
198 /* decode the RSS hash type */
199 switch (cqe->rss_hash_type &
200 (CQE_RSS_DST_HTYPE_L4 | CQE_RSS_DST_HTYPE_IP)) {
202 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV4):
203 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV4);
205 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV4):
206 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV4);
208 case CQE_RSS_DST_HTYPE_IPV4:
209 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV4);
212 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV6):
213 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV6);
215 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV6):
216 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV6);
218 case CQE_RSS_DST_HTYPE_IPV6:
219 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV6);
222 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE);
226 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE);
229 mb->m_pkthdr.flowid = rq->ix;
230 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE);
232 mb->m_pkthdr.rcvif = ifp;
234 if (likely(ifp->if_capenable & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) &&
235 ((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK)) ==
236 (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK))) {
237 mb->m_pkthdr.csum_flags =
238 CSUM_IP_CHECKED | CSUM_IP_VALID |
239 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
240 mb->m_pkthdr.csum_data = htons(0xffff);
242 rq->stats.csum_none++;
245 if (cqe_has_vlan(cqe)) {
246 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->vlan_info);
247 mb->m_flags |= M_VLANTAG;
252 mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data)
254 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, (cc & cq->wq.sz_m1)),
255 sizeof(struct mlx5_cqe64));
259 mlx5e_write_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data)
261 memcpy(mlx5_cqwq_get_wqe(&cq->wq, cc & cq->wq.sz_m1),
262 data, sizeof(struct mlx5_cqe64));
266 mlx5e_decompress_cqe(struct mlx5e_cq *cq, struct mlx5_cqe64 *title,
267 struct mlx5_mini_cqe8 *mini,
268 u16 wqe_counter, int i)
270 title->byte_cnt = mini->byte_cnt;
271 title->wqe_counter = cpu_to_be16((wqe_counter + i) & cq->wq.sz_m1);
272 title->check_sum = mini->checksum;
273 title->op_own = (title->op_own & 0xf0) |
274 (((cq->wq.cc + i) >> cq->wq.log_sz) & 1);
277 #define MLX5E_MINI_ARRAY_SZ 8
278 /* Make sure structs are not packet differently */
279 CTASSERT(sizeof(struct mlx5_cqe64) ==
280 sizeof(struct mlx5_mini_cqe8) * MLX5E_MINI_ARRAY_SZ);
282 mlx5e_decompress_cqes(struct mlx5e_cq *cq)
284 struct mlx5_mini_cqe8 mini_array[MLX5E_MINI_ARRAY_SZ];
285 struct mlx5_cqe64 title;
288 u16 title_wqe_counter;
290 mlx5e_read_cqe_slot(cq, cq->wq.cc, &title);
291 title_wqe_counter = be16_to_cpu(title.wqe_counter);
292 cqe_count = be32_to_cpu(title.byte_cnt);
294 /* Make sure we won't overflow */
295 KASSERT(cqe_count <= cq->wq.sz_m1,
296 ("%s: cqe_count %u > cq->wq.sz_m1 %u", __func__,
297 cqe_count, cq->wq.sz_m1));
299 mlx5e_read_cqe_slot(cq, cq->wq.cc + 1, mini_array);
301 mlx5e_decompress_cqe(cq, &title,
302 &mini_array[i % MLX5E_MINI_ARRAY_SZ],
303 title_wqe_counter, i);
304 mlx5e_write_cqe_slot(cq, cq->wq.cc + i, &title);
309 if (i % MLX5E_MINI_ARRAY_SZ == 0)
310 mlx5e_read_cqe_slot(cq, cq->wq.cc + i, mini_array);
315 mlx5e_poll_rx_cq(struct mlx5e_rq *rq, int budget)
317 #ifndef HAVE_TURBO_LRO
318 struct lro_entry *queued;
322 for (i = 0; i < budget; i++) {
323 struct mlx5e_rx_wqe *wqe;
324 struct mlx5_cqe64 *cqe;
326 __be16 wqe_counter_be;
330 cqe = mlx5e_get_cqe(&rq->cq);
334 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED)
335 mlx5e_decompress_cqes(&rq->cq);
337 mlx5_cqwq_pop(&rq->cq.wq);
339 wqe_counter_be = cqe->wqe_counter;
340 wqe_counter = be16_to_cpu(wqe_counter_be);
341 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
342 byte_cnt = be32_to_cpu(cqe->byte_cnt);
344 bus_dmamap_sync(rq->dma_tag,
345 rq->mbuf[wqe_counter].dma_map,
346 BUS_DMASYNC_POSTREAD);
348 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
353 if (MHLEN >= byte_cnt &&
354 (mb = m_gethdr(M_NOWAIT, MT_DATA)) != NULL) {
355 bcopy(rq->mbuf[wqe_counter].data, mtod(mb, caddr_t),
358 mb = rq->mbuf[wqe_counter].mbuf;
359 rq->mbuf[wqe_counter].mbuf = NULL; /* safety clear */
361 bus_dmamap_unload(rq->dma_tag,
362 rq->mbuf[wqe_counter].dma_map);
365 mlx5e_build_rx_mbuf(cqe, rq, mb, byte_cnt);
367 #ifdef HAVE_TURBO_LRO
368 if (mb->m_pkthdr.csum_flags == 0 ||
369 (rq->ifp->if_capenable & IFCAP_LRO) == 0 ||
370 rq->lro.mbuf == NULL) {
372 rq->ifp->if_input(rq->ifp, mb);
374 tcp_tlro_rx(&rq->lro, mb);
377 if (mb->m_pkthdr.csum_flags == 0 ||
378 (rq->ifp->if_capenable & IFCAP_LRO) == 0 ||
379 rq->lro.lro_cnt == 0 ||
380 tcp_lro_rx(&rq->lro, mb, 0) != 0) {
381 rq->ifp->if_input(rq->ifp, mb);
385 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
386 &wqe->next.next_wqe_index);
389 mlx5_cqwq_update_db_record(&rq->cq.wq);
391 /* ensure cq space is freed before enabling more cqes */
393 #ifndef HAVE_TURBO_LRO
394 while ((queued = SLIST_FIRST(&rq->lro.lro_active)) != NULL) {
395 SLIST_REMOVE_HEAD(&rq->lro.lro_active, next);
396 tcp_lro_flush(&rq->lro, queued);
403 mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq)
405 struct mlx5e_rq *rq = container_of(mcq, struct mlx5e_rq, cq.mcq);
408 #ifdef HAVE_PER_CQ_EVENT_PACKET
409 struct mbuf *mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rq->wqe_sz);
412 /* this code is used for debugging purpose only */
413 mb->m_pkthdr.len = mb->m_len = 15;
414 memset(mb->m_data, 255, 14);
415 mb->m_data[14] = rq->ix;
416 mb->m_pkthdr.rcvif = rq->ifp;
417 rq->ifp->if_input(rq->ifp, mb);
424 * Polling the entire CQ without posting new WQEs results in
425 * lack of receive WQEs during heavy traffic scenarios.
428 if (mlx5e_poll_rx_cq(rq, MLX5E_RX_BUDGET_MAX) !=
431 i += MLX5E_RX_BUDGET_MAX;
432 if (i >= MLX5E_BUDGET_MAX)
434 mlx5e_post_rx_wqes(rq);
436 mlx5e_post_rx_wqes(rq);
437 mlx5e_cq_arm(&rq->cq);
438 #ifdef HAVE_TURBO_LRO
439 tcp_tlro_flush(&rq->lro, 1);
441 mtx_unlock(&rq->mtx);