sys/dev/mlx5/mlx5_ifc.h

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_IFC_H
  29 #define MLX5_IFC_H
  30
  31 enum {
  32         MLX5_EVENT_TYPE_COMP                                       = 0x0,
  33         MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
  34         MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
  35         MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
  36         MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
  37         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
  38         MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
  39         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
  40         MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
  41         MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
  42         MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
  43         MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
  44         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
  45         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
  46         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
  47         MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
  48         MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
  49         MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
  50         MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
  51         MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
  52         MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
  53         MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
  54         MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
  55         MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
  56         MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
  57         MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
  58         MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
  59         MLX5_EVENT_TYPE_CMD                                        = 0xa,
  60         MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
  61         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd
  62 };
  63
  64 enum {
  65         MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
  66         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
  67         MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
  68         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
  69         MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
  70 };
  71
  72 enum {
  73         MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
  74 };
  75
  76 enum {
  77         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  78         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  79         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  80         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  81         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  82         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  83         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  84         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  85         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  86         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  87         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  88         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  89         MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
  90         MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
  91         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  92         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  93         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  94         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  95         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  96         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  97         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  98         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  99         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 100         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 101         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 102         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 103         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 104         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 105         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 106         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 107         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 108         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 109         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 110         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 111         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 112         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 113         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 114         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 115         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 116         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 117         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 118         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 119         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 120         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 121         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 122         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 123         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 124         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 125         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 126         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 127         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 128         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 129         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 130         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 131         MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 132         MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 133         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 134         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 135         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 136         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 137         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 138         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 139         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 140         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 142         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 143         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 145         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 146         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 147         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 148         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 149         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 150         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 151         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 152         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 153         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 154         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 155         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 156         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 157         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 158         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 159         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 160         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 161         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 162         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 163         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 164         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 165         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 166         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 167         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 168         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 169         MLX5_CMD_OP_NOP                           = 0x80d,
 170         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 171         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 172         MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 173         MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 174         MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 175         MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 176         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 177         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 178         MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 179         MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 180         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 181         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 182         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 183         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 184         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 185         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 186         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 187         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 188         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 189         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 190         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 191         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 192         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 193         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 194         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 195         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 196         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 197         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 198         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 199         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 200         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 201         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 202         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 203         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 204         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 205         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 206         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 207         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 208         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 209         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 210         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 211         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 212         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 213         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 214         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 215         MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 216         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 217         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 218         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 219         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 220         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 221         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 222         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 223         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 224         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 225         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 226         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 227         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 228         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 229         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 230         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 231         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 232         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 233         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 234         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 235         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 236         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 237         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 238         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 239         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 240 };
 241
 242 enum {
 243         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 244         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 245         MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 246         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 247         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 248         MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 249         MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 250         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 251         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 252         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 253         MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 254         MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 255 };
 256
 257 struct mlx5_ifc_flow_table_fields_supported_bits {
 258         u8         outer_dmac[0x1];
 259         u8         outer_smac[0x1];
 260         u8         outer_ether_type[0x1];
 261         u8         reserved_0[0x1];
 262         u8         outer_first_prio[0x1];
 263         u8         outer_first_cfi[0x1];
 264         u8         outer_first_vid[0x1];
 265         u8         reserved_1[0x1];
 266         u8         outer_second_prio[0x1];
 267         u8         outer_second_cfi[0x1];
 268         u8         outer_second_vid[0x1];
 269         u8         outer_ipv6_flow_label[0x1];
 270         u8         outer_sip[0x1];
 271         u8         outer_dip[0x1];
 272         u8         outer_frag[0x1];
 273         u8         outer_ip_protocol[0x1];
 274         u8         outer_ip_ecn[0x1];
 275         u8         outer_ip_dscp[0x1];
 276         u8         outer_udp_sport[0x1];
 277         u8         outer_udp_dport[0x1];
 278         u8         outer_tcp_sport[0x1];
 279         u8         outer_tcp_dport[0x1];
 280         u8         outer_tcp_flags[0x1];
 281         u8         outer_gre_protocol[0x1];
 282         u8         outer_gre_key[0x1];
 283         u8         outer_vxlan_vni[0x1];
 284         u8         outer_geneve_vni[0x1];
 285         u8         outer_geneve_oam[0x1];
 286         u8         outer_geneve_protocol_type[0x1];
 287         u8         outer_geneve_opt_len[0x1];
 288         u8         reserved_2[0x1];
 289         u8         source_eswitch_port[0x1];
 290
 291         u8         inner_dmac[0x1];
 292         u8         inner_smac[0x1];
 293         u8         inner_ether_type[0x1];
 294         u8         reserved_3[0x1];
 295         u8         inner_first_prio[0x1];
 296         u8         inner_first_cfi[0x1];
 297         u8         inner_first_vid[0x1];
 298         u8         reserved_4[0x1];
 299         u8         inner_second_prio[0x1];
 300         u8         inner_second_cfi[0x1];
 301         u8         inner_second_vid[0x1];
 302         u8         inner_ipv6_flow_label[0x1];
 303         u8         inner_sip[0x1];
 304         u8         inner_dip[0x1];
 305         u8         inner_frag[0x1];
 306         u8         inner_ip_protocol[0x1];
 307         u8         inner_ip_ecn[0x1];
 308         u8         inner_ip_dscp[0x1];
 309         u8         inner_udp_sport[0x1];
 310         u8         inner_udp_dport[0x1];
 311         u8         inner_tcp_sport[0x1];
 312         u8         inner_tcp_dport[0x1];
 313         u8         inner_tcp_flags[0x1];
 314         u8         reserved_5[0x9];
 315
 316         u8         reserved_6[0x1a];
 317         u8         bth_dst_qp[0x1];
 318         u8         reserved_7[0x4];
 319         u8         source_sqn[0x1];
 320
 321         u8         reserved_8[0x20];
 322 };
 323
 324 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 325         u8         ingress_general_high[0x20];
 326
 327         u8         ingress_general_low[0x20];
 328
 329         u8         ingress_policy_engine_high[0x20];
 330
 331         u8         ingress_policy_engine_low[0x20];
 332
 333         u8         ingress_vlan_membership_high[0x20];
 334
 335         u8         ingress_vlan_membership_low[0x20];
 336
 337         u8         ingress_tag_frame_type_high[0x20];
 338
 339         u8         ingress_tag_frame_type_low[0x20];
 340
 341         u8         egress_vlan_membership_high[0x20];
 342
 343         u8         egress_vlan_membership_low[0x20];
 344
 345         u8         loopback_filter_high[0x20];
 346
 347         u8         loopback_filter_low[0x20];
 348
 349         u8         egress_general_high[0x20];
 350
 351         u8         egress_general_low[0x20];
 352
 353         u8         reserved_at_1c0[0x40];
 354
 355         u8         egress_hoq_high[0x20];
 356
 357         u8         egress_hoq_low[0x20];
 358
 359         u8         port_isolation_high[0x20];
 360
 361         u8         port_isolation_low[0x20];
 362
 363         u8         egress_policy_engine_high[0x20];
 364
 365         u8         egress_policy_engine_low[0x20];
 366
 367         u8         ingress_tx_link_down_high[0x20];
 368
 369         u8         ingress_tx_link_down_low[0x20];
 370
 371         u8         egress_stp_filter_high[0x20];
 372
 373         u8         egress_stp_filter_low[0x20];
 374
 375         u8         egress_hoq_stall_high[0x20];
 376
 377         u8         egress_hoq_stall_low[0x20];
 378
 379         u8         reserved_at_340[0x440];
 380 };
 381 struct mlx5_ifc_flow_table_prop_layout_bits {
 382         u8         ft_support[0x1];
 383         u8         flow_tag[0x1];
 384         u8         flow_counter[0x1];
 385         u8         flow_modify_en[0x1];
 386         u8         modify_root[0x1];
 387         u8         reserved_0[0x1b];
 388
 389         u8         reserved_1[0x2];
 390         u8         log_max_ft_size[0x6];
 391         u8         reserved_2[0x10];
 392         u8         max_ft_level[0x8];
 393
 394         u8         reserved_3[0x20];
 395
 396         u8         reserved_4[0x18];
 397         u8         log_max_ft_num[0x8];
 398
 399         u8         reserved_5[0x10];
 400         u8         log_max_flow_counter[0x8];
 401         u8         log_max_destination[0x8];
 402
 403         u8         reserved_6[0x18];
 404         u8         log_max_flow[0x8];
 405
 406         u8         reserved_7[0x40];
 407
 408         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 409
 410         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 411 };
 412
 413 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 414         u8         send[0x1];
 415         u8         receive[0x1];
 416         u8         write[0x1];
 417         u8         read[0x1];
 418         u8         atomic[0x1];
 419         u8         srq_receive[0x1];
 420         u8         reserved_0[0x1a];
 421 };
 422
 423 struct mlx5_ifc_flow_counter_list_bits {
 424         u8         reserved_0[0x10];
 425         u8         flow_counter_id[0x10];
 426
 427         u8         reserved_1[0x20];
 428 };
 429
 430 enum {
 431         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 432         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 433         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 434         MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 435 };
 436
 437 struct mlx5_ifc_dest_format_struct_bits {
 438         u8         destination_type[0x8];
 439         u8         destination_id[0x18];
 440
 441         u8         reserved_0[0x20];
 442 };
 443
 444 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 445         u8         smac_47_16[0x20];
 446
 447         u8         smac_15_0[0x10];
 448         u8         ethertype[0x10];
 449
 450         u8         dmac_47_16[0x20];
 451
 452         u8         dmac_15_0[0x10];
 453         u8         first_prio[0x3];
 454         u8         first_cfi[0x1];
 455         u8         first_vid[0xc];
 456
 457         u8         ip_protocol[0x8];
 458         u8         ip_dscp[0x6];
 459         u8         ip_ecn[0x2];
 460         u8         cvlan_tag[0x1];
 461         u8         svlan_tag[0x1];
 462         u8         frag[0x1];
 463         u8         reserved_1[0x4];
 464         u8         tcp_flags[0x9];
 465
 466         u8         tcp_sport[0x10];
 467         u8         tcp_dport[0x10];
 468
 469         u8         reserved_2[0x20];
 470
 471         u8         udp_sport[0x10];
 472         u8         udp_dport[0x10];
 473
 474         u8         src_ip[4][0x20];
 475
 476         u8         dst_ip[4][0x20];
 477 };
 478
 479 struct mlx5_ifc_fte_match_set_misc_bits {
 480         u8         reserved_0[0x8];
 481         u8         source_sqn[0x18];
 482
 483         u8         reserved_1[0x10];
 484         u8         source_port[0x10];
 485
 486         u8         outer_second_prio[0x3];
 487         u8         outer_second_cfi[0x1];
 488         u8         outer_second_vid[0xc];
 489         u8         inner_second_prio[0x3];
 490         u8         inner_second_cfi[0x1];
 491         u8         inner_second_vid[0xc];
 492
 493         u8         outer_second_vlan_tag[0x1];
 494         u8         inner_second_vlan_tag[0x1];
 495         u8         reserved_2[0xe];
 496         u8         gre_protocol[0x10];
 497
 498         u8         gre_key_h[0x18];
 499         u8         gre_key_l[0x8];
 500
 501         u8         vxlan_vni[0x18];
 502         u8         reserved_3[0x8];
 503
 504         u8         geneve_vni[0x18];
 505         u8         reserved4[0x7];
 506         u8         geneve_oam[0x1];
 507
 508         u8         reserved_5[0xc];
 509         u8         outer_ipv6_flow_label[0x14];
 510
 511         u8         reserved_6[0xc];
 512         u8         inner_ipv6_flow_label[0x14];
 513
 514         u8         reserved_7[0xa];
 515         u8         geneve_opt_len[0x6];
 516         u8         geneve_protocol_type[0x10];
 517
 518         u8         reserved_8[0x8];
 519         u8         bth_dst_qp[0x18];
 520
 521         u8         reserved_9[0xa0];
 522 };
 523
 524 struct mlx5_ifc_cmd_pas_bits {
 525         u8         pa_h[0x20];
 526
 527         u8         pa_l[0x14];
 528         u8         reserved_0[0xc];
 529 };
 530
 531 struct mlx5_ifc_uint64_bits {
 532         u8         hi[0x20];
 533
 534         u8         lo[0x20];
 535 };
 536
 537 struct mlx5_ifc_application_prio_entry_bits {
 538         u8         reserved_0[0x8];
 539         u8         priority[0x3];
 540         u8         reserved_1[0x2];
 541         u8         sel[0x3];
 542         u8         protocol_id[0x10];
 543 };
 544
 545 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 546         u8         reserved_0[0x8];
 547         u8         ring_pi[0x10];
 548         u8         reserved_1[0x8];
 549 };
 550
 551 enum {
 552         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 553         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 554         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 555         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 556         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 557         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 558         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 559         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 560         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 561         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 562 };
 563
 564 struct mlx5_ifc_ads_bits {
 565         u8         fl[0x1];
 566         u8         free_ar[0x1];
 567         u8         reserved_0[0xe];
 568         u8         pkey_index[0x10];
 569
 570         u8         reserved_1[0x8];
 571         u8         grh[0x1];
 572         u8         mlid[0x7];
 573         u8         rlid[0x10];
 574
 575         u8         ack_timeout[0x5];
 576         u8         reserved_2[0x3];
 577         u8         src_addr_index[0x8];
 578         u8         log_rtm[0x4];
 579         u8         stat_rate[0x4];
 580         u8         hop_limit[0x8];
 581
 582         u8         reserved_3[0x4];
 583         u8         tclass[0x8];
 584         u8         flow_label[0x14];
 585
 586         u8         rgid_rip[16][0x8];
 587
 588         u8         reserved_4[0x4];
 589         u8         f_dscp[0x1];
 590         u8         f_ecn[0x1];
 591         u8         reserved_5[0x1];
 592         u8         f_eth_prio[0x1];
 593         u8         ecn[0x2];
 594         u8         dscp[0x6];
 595         u8         udp_sport[0x10];
 596
 597         u8         dei_cfi[0x1];
 598         u8         eth_prio[0x3];
 599         u8         sl[0x4];
 600         u8         port[0x8];
 601         u8         rmac_47_32[0x10];
 602
 603         u8         rmac_31_0[0x20];
 604 };
 605
 606 struct mlx5_ifc_diagnostic_counter_cap_bits {
 607         u8         sync[0x1];
 608         u8         reserved_0[0xf];
 609         u8         counter_id[0x10];
 610 };
 611
 612 struct mlx5_ifc_debug_cap_bits {
 613         u8         reserved_0[0x18];
 614         u8         log_max_samples[0x8];
 615
 616         u8         single[0x1];
 617         u8         repetitive[0x1];
 618         u8         health_mon_rx_activity[0x1];
 619         u8         reserved_1[0x15];
 620         u8         log_min_sample_period[0x8];
 621
 622         u8         reserved_2[0x1c0];
 623
 624         struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 625 };
 626
 627 struct mlx5_ifc_qos_cap_bits {
 628         u8         packet_pacing[0x1];
 629         u8         esw_scheduling[0x1];
 630         u8         esw_bw_share[0x1];
 631         u8         esw_rate_limit[0x1];
 632         u8         hll[0x1];
 633         u8         packet_pacing_burst_bound[0x1];
 634         u8         reserved_at_6[0x1a];
 635
 636         u8         reserved_at_20[0x20];
 637
 638         u8         packet_pacing_max_rate[0x20];
 639
 640         u8         packet_pacing_min_rate[0x20];
 641
 642         u8         reserved_at_80[0x10];
 643         u8         packet_pacing_rate_table_size[0x10];
 644
 645         u8         esw_element_type[0x10];
 646         u8         esw_tsar_type[0x10];
 647
 648         u8         reserved_at_c0[0x10];
 649         u8         max_qos_para_vport[0x10];
 650
 651         u8         max_tsar_bw_share[0x20];
 652
 653         u8         reserved_at_100[0x700];
 654 };
 655
 656 struct mlx5_ifc_snapshot_cap_bits {
 657         u8         reserved_0[0x1d];
 658         u8         suspend_qp_uc[0x1];
 659         u8         suspend_qp_ud[0x1];
 660         u8         suspend_qp_rc[0x1];
 661
 662         u8         reserved_1[0x1c];
 663         u8         restore_pd[0x1];
 664         u8         restore_uar[0x1];
 665         u8         restore_mkey[0x1];
 666         u8         restore_qp[0x1];
 667
 668         u8         reserved_2[0x1e];
 669         u8         named_mkey[0x1];
 670         u8         named_qp[0x1];
 671
 672         u8         reserved_3[0x7a0];
 673 };
 674
 675 struct mlx5_ifc_e_switch_cap_bits {
 676         u8         vport_svlan_strip[0x1];
 677         u8         vport_cvlan_strip[0x1];
 678         u8         vport_svlan_insert[0x1];
 679         u8         vport_cvlan_insert_if_not_exist[0x1];
 680         u8         vport_cvlan_insert_overwrite[0x1];
 681
 682         u8         reserved_0[0x19];
 683
 684         u8         nic_vport_node_guid_modify[0x1];
 685         u8         nic_vport_port_guid_modify[0x1];
 686
 687         u8         reserved_1[0x7e0];
 688 };
 689
 690 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 691         u8         reserved_0[0x200];
 692
 693         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 694
 695         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 696
 697         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 698
 699         u8         reserved_1[0x7800];
 700 };
 701
 702 struct mlx5_ifc_flow_table_nic_cap_bits {
 703         u8         reserved_0[0x200];
 704
 705         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 706
 707         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 708
 709         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 710
 711         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 712
 713         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 714
 715         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 716
 717         u8         reserved_1[0x7200];
 718 };
 719
 720 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 721         u8         csum_cap[0x1];
 722         u8         vlan_cap[0x1];
 723         u8         lro_cap[0x1];
 724         u8         lro_psh_flag[0x1];
 725         u8         lro_time_stamp[0x1];
 726         u8         lro_max_msg_sz_mode[0x2];
 727         u8         wqe_vlan_insert[0x1];
 728         u8         self_lb_en_modifiable[0x1];
 729         u8         self_lb_mc[0x1];
 730         u8         self_lb_uc[0x1];
 731         u8         max_lso_cap[0x5];
 732         u8         multi_pkt_send_wqe[0x2];
 733         u8         wqe_inline_mode[0x2];
 734         u8         rss_ind_tbl_cap[0x4];
 735         u8         reserved_1[0x3];
 736         u8         tunnel_lso_const_out_ip_id[0x1];
 737         u8         tunnel_lro_gre[0x1];
 738         u8         tunnel_lro_vxlan[0x1];
 739         u8         tunnel_statless_gre[0x1];
 740         u8         tunnel_stateless_vxlan[0x1];
 741
 742         u8         swp[0x1];
 743         u8         swp_csum[0x1];
 744         u8         swp_lso[0x1];
 745         u8         reserved_2[0x1b];
 746         u8         max_geneve_opt_len[0x1];
 747         u8         tunnel_stateless_geneve_rx[0x1];
 748
 749         u8         reserved_3[0x10];
 750         u8         lro_min_mss_size[0x10];
 751
 752         u8         reserved_4[0x120];
 753
 754         u8         lro_timer_supported_periods[4][0x20];
 755
 756         u8         reserved_5[0x600];
 757 };
 758
 759 enum {
 760         MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 761         MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 762         MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 763 };
 764
 765 struct mlx5_ifc_roce_cap_bits {
 766         u8         roce_apm[0x1];
 767         u8         rts2rts_primary_eth_prio[0x1];
 768         u8         roce_rx_allow_untagged[0x1];
 769         u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 770
 771         u8         reserved_0[0x1c];
 772
 773         u8         reserved_1[0x60];
 774
 775         u8         reserved_2[0xc];
 776         u8         l3_type[0x4];
 777         u8         reserved_3[0x8];
 778         u8         roce_version[0x8];
 779
 780         u8         reserved_4[0x10];
 781         u8         r_roce_dest_udp_port[0x10];
 782
 783         u8         r_roce_max_src_udp_port[0x10];
 784         u8         r_roce_min_src_udp_port[0x10];
 785
 786         u8         reserved_5[0x10];
 787         u8         roce_address_table_size[0x10];
 788
 789         u8         reserved_6[0x700];
 790 };
 791
 792 enum {
 793         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 794         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 795         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 796         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 797         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 798         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 799         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 800         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 801         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 802 };
 803
 804 enum {
 805         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 806         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 807         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 808         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 809         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 810         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 811         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 812         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 813         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 814 };
 815
 816 struct mlx5_ifc_atomic_caps_bits {
 817         u8         reserved_0[0x40];
 818
 819         u8         atomic_req_8B_endianess_mode[0x2];
 820         u8         reserved_1[0x4];
 821         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 822
 823         u8         reserved_2[0x19];
 824
 825         u8         reserved_3[0x20];
 826
 827         u8         reserved_4[0x10];
 828         u8         atomic_operations[0x10];
 829
 830         u8         reserved_5[0x10];
 831         u8         atomic_size_qp[0x10];
 832
 833         u8         reserved_6[0x10];
 834         u8         atomic_size_dc[0x10];
 835
 836         u8         reserved_7[0x720];
 837 };
 838
 839 struct mlx5_ifc_odp_cap_bits {
 840         u8         reserved_0[0x40];
 841
 842         u8         sig[0x1];
 843         u8         reserved_1[0x1f];
 844
 845         u8         reserved_2[0x20];
 846
 847         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 848
 849         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 850
 851         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 852
 853         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 854
 855         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
 856
 857         u8         reserved_3[0x6e0];
 858 };
 859
 860 enum {
 861         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 862         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 863         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 864         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 865         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 866 };
 867
 868 enum {
 869         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 870         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 871         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 872         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 873         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 874         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 875 };
 876
 877 enum {
 878         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 879         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 880 };
 881
 882 enum {
 883         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 884         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 885         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 886 };
 887
 888 struct mlx5_ifc_cmd_hca_cap_bits {
 889         u8         reserved_0[0x80];
 890
 891         u8         log_max_srq_sz[0x8];
 892         u8         log_max_qp_sz[0x8];
 893         u8         reserved_1[0xb];
 894         u8         log_max_qp[0x5];
 895
 896         u8         reserved_2[0xb];
 897         u8         log_max_srq[0x5];
 898         u8         reserved_3[0x10];
 899
 900         u8         reserved_4[0x8];
 901         u8         log_max_cq_sz[0x8];
 902         u8         reserved_5[0xb];
 903         u8         log_max_cq[0x5];
 904
 905         u8         log_max_eq_sz[0x8];
 906         u8         reserved_6[0x2];
 907         u8         log_max_mkey[0x6];
 908         u8         reserved_7[0xc];
 909         u8         log_max_eq[0x4];
 910
 911         u8         max_indirection[0x8];
 912         u8         reserved_8[0x1];
 913         u8         log_max_mrw_sz[0x7];
 914         u8         reserved_9[0x2];
 915         u8         log_max_bsf_list_size[0x6];
 916         u8         reserved_10[0x2];
 917         u8         log_max_klm_list_size[0x6];
 918
 919         u8         reserved_11[0xa];
 920         u8         log_max_ra_req_dc[0x6];
 921         u8         reserved_12[0xa];
 922         u8         log_max_ra_res_dc[0x6];
 923
 924         u8         reserved_13[0xa];
 925         u8         log_max_ra_req_qp[0x6];
 926         u8         reserved_14[0xa];
 927         u8         log_max_ra_res_qp[0x6];
 928
 929         u8         pad_cap[0x1];
 930         u8         cc_query_allowed[0x1];
 931         u8         cc_modify_allowed[0x1];
 932         u8         start_pad[0x1];
 933         u8         cache_line_128byte[0x1];
 934         u8         reserved_15[0xb];
 935         u8         gid_table_size[0x10];
 936
 937         u8         out_of_seq_cnt[0x1];
 938         u8         vport_counters[0x1];
 939         u8         retransmission_q_counters[0x1];
 940         u8         debug[0x1];
 941         u8         modify_rq_counters_set_id[0x1];
 942         u8         rq_delay_drop[0x1];
 943         u8         max_qp_cnt[0xa];
 944         u8         pkey_table_size[0x10];
 945
 946         u8         vport_group_manager[0x1];
 947         u8         vhca_group_manager[0x1];
 948         u8         ib_virt[0x1];
 949         u8         eth_virt[0x1];
 950         u8         reserved_17[0x1];
 951         u8         ets[0x1];
 952         u8         nic_flow_table[0x1];
 953         u8         eswitch_flow_table[0x1];
 954         u8         reserved_18[0x3];
 955         u8         local_ca_ack_delay[0x5];
 956         u8         port_module_event[0x1];
 957         u8         reserved_19[0x5];
 958         u8         port_type[0x2];
 959         u8         num_ports[0x8];
 960
 961         u8         snapshot[0x1];
 962         u8         reserved_20[0x2];
 963         u8         log_max_msg[0x5];
 964         u8         reserved_21[0x4];
 965         u8         max_tc[0x4];
 966         u8         temp_warn_event[0x1];
 967         u8         dcbx[0x1];
 968         u8         reserved_22[0x4];
 969         u8         rol_s[0x1];
 970         u8         rol_g[0x1];
 971         u8         reserved_23[0x1];
 972         u8         wol_s[0x1];
 973         u8         wol_g[0x1];
 974         u8         wol_a[0x1];
 975         u8         wol_b[0x1];
 976         u8         wol_m[0x1];
 977         u8         wol_u[0x1];
 978         u8         wol_p[0x1];
 979
 980         u8         stat_rate_support[0x10];
 981         u8         reserved_24[0xc];
 982         u8         cqe_version[0x4];
 983
 984         u8         compact_address_vector[0x1];
 985         u8         striding_rq[0x1];
 986         u8         reserved_25[0x1];
 987         u8         ipoib_enhanced_offloads[0x1];
 988         u8         ipoib_ipoib_offloads[0x1];
 989         u8         reserved_26[0x8];
 990         u8         dc_connect_qp[0x1];
 991         u8         dc_cnak_trace[0x1];
 992         u8         drain_sigerr[0x1];
 993         u8         cmdif_checksum[0x2];
 994         u8         sigerr_cqe[0x1];
 995         u8         reserved_27[0x1];
 996         u8         wq_signature[0x1];
 997         u8         sctr_data_cqe[0x1];
 998         u8         reserved_28[0x1];
 999         u8         sho[0x1];
1000         u8         tph[0x1];
1001         u8         rf[0x1];
1002         u8         dct[0x1];
1003         u8         qos[0x1];
1004         u8         eth_net_offloads[0x1];
1005         u8         roce[0x1];
1006         u8         atomic[0x1];
1007         u8         reserved_30[0x1];
1008
1009         u8         cq_oi[0x1];
1010         u8         cq_resize[0x1];
1011         u8         cq_moderation[0x1];
1012         u8         cq_period_mode_modify[0x1];
1013         u8         cq_invalidate[0x1];
1014         u8         reserved_at_225[0x1];
1015         u8         cq_eq_remap[0x1];
1016         u8         pg[0x1];
1017         u8         block_lb_mc[0x1];
1018         u8         exponential_backoff[0x1];
1019         u8         scqe_break_moderation[0x1];
1020         u8         cq_period_start_from_cqe[0x1];
1021         u8         cd[0x1];
1022         u8         atm[0x1];
1023         u8         apm[0x1];
1024         u8         reserved_32[0x7];
1025         u8         qkv[0x1];
1026         u8         pkv[0x1];
1027         u8         reserved_33[0x4];
1028         u8         xrc[0x1];
1029         u8         ud[0x1];
1030         u8         uc[0x1];
1031         u8         rc[0x1];
1032
1033         u8         reserved_34[0xa];
1034         u8         uar_sz[0x6];
1035         u8         reserved_35[0x8];
1036         u8         log_pg_sz[0x8];
1037
1038         u8         bf[0x1];
1039         u8         driver_version[0x1];
1040         u8         pad_tx_eth_packet[0x1];
1041         u8         reserved_36[0x8];
1042         u8         log_bf_reg_size[0x5];
1043         u8         reserved_37[0x10];
1044
1045         u8         num_of_diagnostic_counters[0x10];
1046         u8         max_wqe_sz_sq[0x10];
1047
1048         u8         reserved_38[0x10];
1049         u8         max_wqe_sz_rq[0x10];
1050
1051         u8         reserved_39[0x10];
1052         u8         max_wqe_sz_sq_dc[0x10];
1053
1054         u8         reserved_40[0x7];
1055         u8         max_qp_mcg[0x19];
1056
1057         u8         reserved_41[0x18];
1058         u8         log_max_mcg[0x8];
1059
1060         u8         reserved_42[0x3];
1061         u8         log_max_transport_domain[0x5];
1062         u8         reserved_43[0x3];
1063         u8         log_max_pd[0x5];
1064         u8         reserved_44[0xb];
1065         u8         log_max_xrcd[0x5];
1066
1067         u8         reserved_45[0x10];
1068         u8         max_flow_counter[0x10];
1069
1070         u8         reserved_46[0x3];
1071         u8         log_max_rq[0x5];
1072         u8         reserved_47[0x3];
1073         u8         log_max_sq[0x5];
1074         u8         reserved_48[0x3];
1075         u8         log_max_tir[0x5];
1076         u8         reserved_49[0x3];
1077         u8         log_max_tis[0x5];
1078
1079         u8         basic_cyclic_rcv_wqe[0x1];
1080         u8         reserved_50[0x2];
1081         u8         log_max_rmp[0x5];
1082         u8         reserved_51[0x3];
1083         u8         log_max_rqt[0x5];
1084         u8         reserved_52[0x3];
1085         u8         log_max_rqt_size[0x5];
1086         u8         reserved_53[0x3];
1087         u8         log_max_tis_per_sq[0x5];
1088
1089         u8         reserved_54[0x3];
1090         u8         log_max_stride_sz_rq[0x5];
1091         u8         reserved_55[0x3];
1092         u8         log_min_stride_sz_rq[0x5];
1093         u8         reserved_56[0x3];
1094         u8         log_max_stride_sz_sq[0x5];
1095         u8         reserved_57[0x3];
1096         u8         log_min_stride_sz_sq[0x5];
1097
1098         u8         reserved_58[0x1b];
1099         u8         log_max_wq_sz[0x5];
1100
1101         u8         nic_vport_change_event[0x1];
1102         u8         disable_local_lb[0x1];
1103         u8         reserved_59[0x9];
1104         u8         log_max_vlan_list[0x5];
1105         u8         reserved_60[0x3];
1106         u8         log_max_current_mc_list[0x5];
1107         u8         reserved_61[0x3];
1108         u8         log_max_current_uc_list[0x5];
1109
1110         u8         reserved_62[0x80];
1111
1112         u8         reserved_63[0x3];
1113         u8         log_max_l2_table[0x5];
1114         u8         reserved_64[0x8];
1115         u8         log_uar_page_sz[0x10];
1116
1117         u8         reserved_65[0x20];
1118
1119         u8         device_frequency_mhz[0x20];
1120
1121         u8         device_frequency_khz[0x20];
1122
1123         u8         reserved_66[0x80];
1124
1125         u8         log_max_atomic_size_qp[0x8];
1126         u8         reserved_67[0x10];
1127         u8         log_max_atomic_size_dc[0x8];
1128
1129         u8         reserved_68[0x1f];
1130         u8         cqe_compression[0x1];
1131
1132         u8         cqe_compression_timeout[0x10];
1133         u8         cqe_compression_max_num[0x10];
1134
1135         u8         reserved_69[0x220];
1136 };
1137
1138 enum mlx5_flow_destination_type {
1139         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1140         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1141         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1142 };
1143
1144 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1145         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1146         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1147         u8         reserved_0[0x40];
1148 };
1149
1150 struct mlx5_ifc_fte_match_param_bits {
1151         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1152
1153         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1154
1155         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1156
1157         u8         reserved_0[0xa00];
1158 };
1159
1160 enum {
1161         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1162         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1163         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1164         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1165         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1166 };
1167
1168 struct mlx5_ifc_rx_hash_field_select_bits {
1169         u8         l3_prot_type[0x1];
1170         u8         l4_prot_type[0x1];
1171         u8         selected_fields[0x1e];
1172 };
1173
1174 enum {
1175         MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1176         MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1177         MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1178         MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1179 };
1180
1181 enum rq_type {
1182         RQ_TYPE_NONE,
1183         RQ_TYPE_STRIDE,
1184 };
1185
1186 enum {
1187         MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1188         MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1189 };
1190
1191 struct mlx5_ifc_wq_bits {
1192         u8         wq_type[0x4];
1193         u8         wq_signature[0x1];
1194         u8         end_padding_mode[0x2];
1195         u8         cd_slave[0x1];
1196         u8         reserved_0[0x18];
1197
1198         u8         hds_skip_first_sge[0x1];
1199         u8         log2_hds_buf_size[0x3];
1200         u8         reserved_1[0x7];
1201         u8         page_offset[0x5];
1202         u8         lwm[0x10];
1203
1204         u8         reserved_2[0x8];
1205         u8         pd[0x18];
1206
1207         u8         reserved_3[0x8];
1208         u8         uar_page[0x18];
1209
1210         u8         dbr_addr[0x40];
1211
1212         u8         hw_counter[0x20];
1213
1214         u8         sw_counter[0x20];
1215
1216         u8         reserved_4[0xc];
1217         u8         log_wq_stride[0x4];
1218         u8         reserved_5[0x3];
1219         u8         log_wq_pg_sz[0x5];
1220         u8         reserved_6[0x3];
1221         u8         log_wq_sz[0x5];
1222
1223         u8         reserved_7[0x15];
1224         u8         single_wqe_log_num_of_strides[0x3];
1225         u8         two_byte_shift_en[0x1];
1226         u8         reserved_8[0x4];
1227         u8         single_stride_log_num_of_bytes[0x3];
1228
1229         u8         reserved_9[0x4c0];
1230
1231         struct mlx5_ifc_cmd_pas_bits pas[0];
1232 };
1233
1234 struct mlx5_ifc_rq_num_bits {
1235         u8         reserved_0[0x8];
1236         u8         rq_num[0x18];
1237 };
1238
1239 struct mlx5_ifc_mac_address_layout_bits {
1240         u8         reserved_0[0x10];
1241         u8         mac_addr_47_32[0x10];
1242
1243         u8         mac_addr_31_0[0x20];
1244 };
1245
1246 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1247         u8         reserved_0[0xa0];
1248
1249         u8         min_time_between_cnps[0x20];
1250
1251         u8         reserved_1[0x12];
1252         u8         cnp_dscp[0x6];
1253         u8         reserved_2[0x4];
1254         u8         cnp_prio_mode[0x1];
1255         u8         cnp_802p_prio[0x3];
1256
1257         u8         reserved_3[0x720];
1258 };
1259
1260 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1261         u8         reserved_0[0x60];
1262
1263         u8         reserved_1[0x4];
1264         u8         clamp_tgt_rate[0x1];
1265         u8         reserved_2[0x3];
1266         u8         clamp_tgt_rate_after_time_inc[0x1];
1267         u8         reserved_3[0x17];
1268
1269         u8         reserved_4[0x20];
1270
1271         u8         rpg_time_reset[0x20];
1272
1273         u8         rpg_byte_reset[0x20];
1274
1275         u8         rpg_threshold[0x20];
1276
1277         u8         rpg_max_rate[0x20];
1278
1279         u8         rpg_ai_rate[0x20];
1280
1281         u8         rpg_hai_rate[0x20];
1282
1283         u8         rpg_gd[0x20];
1284
1285         u8         rpg_min_dec_fac[0x20];
1286
1287         u8         rpg_min_rate[0x20];
1288
1289         u8         reserved_5[0xe0];
1290
1291         u8         rate_to_set_on_first_cnp[0x20];
1292
1293         u8         dce_tcp_g[0x20];
1294
1295         u8         dce_tcp_rtt[0x20];
1296
1297         u8         rate_reduce_monitor_period[0x20];
1298
1299         u8         reserved_6[0x20];
1300
1301         u8         initial_alpha_value[0x20];
1302
1303         u8         reserved_7[0x4a0];
1304 };
1305
1306 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1307         u8         reserved_0[0x80];
1308
1309         u8         rppp_max_rps[0x20];
1310
1311         u8         rpg_time_reset[0x20];
1312
1313         u8         rpg_byte_reset[0x20];
1314
1315         u8         rpg_threshold[0x20];
1316
1317         u8         rpg_max_rate[0x20];
1318
1319         u8         rpg_ai_rate[0x20];
1320
1321         u8         rpg_hai_rate[0x20];
1322
1323         u8         rpg_gd[0x20];
1324
1325         u8         rpg_min_dec_fac[0x20];
1326
1327         u8         rpg_min_rate[0x20];
1328
1329         u8         reserved_1[0x640];
1330 };
1331
1332 enum {
1333         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1334         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1335         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1336 };
1337
1338 struct mlx5_ifc_resize_field_select_bits {
1339         u8         resize_field_select[0x20];
1340 };
1341
1342 enum {
1343         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1344         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1345         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1346         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1347         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1348         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1349 };
1350
1351 struct mlx5_ifc_modify_field_select_bits {
1352         u8         modify_field_select[0x20];
1353 };
1354
1355 struct mlx5_ifc_field_select_r_roce_np_bits {
1356         u8         field_select_r_roce_np[0x20];
1357 };
1358
1359 enum {
1360         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1361         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1362         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1363         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1364         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1365         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1366         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1367         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1368         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1369         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1370         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1371         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1372         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1373         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1374         MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1375 };
1376
1377 struct mlx5_ifc_field_select_r_roce_rp_bits {
1378         u8         field_select_r_roce_rp[0x20];
1379 };
1380
1381 enum {
1382         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1383         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1384         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1385         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1386         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1387         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1388         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1389         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1390         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1391         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1392 };
1393
1394 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1395         u8         field_select_8021qaurp[0x20];
1396 };
1397
1398 struct mlx5_ifc_pptb_reg_bits {
1399         u8         reserved_0[0x2];
1400         u8         mm[0x2];
1401         u8         reserved_1[0x4];
1402         u8         local_port[0x8];
1403         u8         reserved_2[0x6];
1404         u8         cm[0x1];
1405         u8         um[0x1];
1406         u8         pm[0x8];
1407
1408         u8         prio7buff[0x4];
1409         u8         prio6buff[0x4];
1410         u8         prio5buff[0x4];
1411         u8         prio4buff[0x4];
1412         u8         prio3buff[0x4];
1413         u8         prio2buff[0x4];
1414         u8         prio1buff[0x4];
1415         u8         prio0buff[0x4];
1416
1417         u8         pm_msb[0x8];
1418         u8         reserved_3[0x10];
1419         u8         ctrl_buff[0x4];
1420         u8         untagged_buff[0x4];
1421 };
1422
1423 struct mlx5_ifc_dcbx_app_reg_bits {
1424         u8         reserved_0[0x8];
1425         u8         port_number[0x8];
1426         u8         reserved_1[0x10];
1427
1428         u8         reserved_2[0x1a];
1429         u8         num_app_prio[0x6];
1430
1431         u8         reserved_3[0x40];
1432
1433         struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1434 };
1435
1436 struct mlx5_ifc_dcbx_param_reg_bits {
1437         u8         dcbx_cee_cap[0x1];
1438         u8         dcbx_ieee_cap[0x1];
1439         u8         dcbx_standby_cap[0x1];
1440         u8         reserved_0[0x5];
1441         u8         port_number[0x8];
1442         u8         reserved_1[0xa];
1443         u8         max_application_table_size[0x6];
1444
1445         u8         reserved_2[0x15];
1446         u8         version_oper[0x3];
1447         u8         reserved_3[0x5];
1448         u8         version_admin[0x3];
1449
1450         u8         willing_admin[0x1];
1451         u8         reserved_4[0x3];
1452         u8         pfc_cap_oper[0x4];
1453         u8         reserved_5[0x4];
1454         u8         pfc_cap_admin[0x4];
1455         u8         reserved_6[0x4];
1456         u8         num_of_tc_oper[0x4];
1457         u8         reserved_7[0x4];
1458         u8         num_of_tc_admin[0x4];
1459
1460         u8         remote_willing[0x1];
1461         u8         reserved_8[0x3];
1462         u8         remote_pfc_cap[0x4];
1463         u8         reserved_9[0x14];
1464         u8         remote_num_of_tc[0x4];
1465
1466         u8         reserved_10[0x18];
1467         u8         error[0x8];
1468
1469         u8         reserved_11[0x160];
1470 };
1471
1472 struct mlx5_ifc_qhll_bits {
1473         u8         reserved_at_0[0x8];
1474         u8         local_port[0x8];
1475         u8         reserved_at_10[0x10];
1476
1477         u8         reserved_at_20[0x1b];
1478         u8         hll_time[0x5];
1479
1480         u8         stall_en[0x1];
1481         u8         reserved_at_41[0x1c];
1482         u8         stall_cnt[0x3];
1483 };
1484
1485 struct mlx5_ifc_qetcr_reg_bits {
1486         u8         operation_type[0x2];
1487         u8         cap_local_admin[0x1];
1488         u8         cap_remote_admin[0x1];
1489         u8         reserved_0[0x4];
1490         u8         port_number[0x8];
1491         u8         reserved_1[0x10];
1492
1493         u8         reserved_2[0x20];
1494
1495         u8         tc[8][0x40];
1496
1497         u8         global_configuration[0x40];
1498 };
1499
1500 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1501         u8         queue_address_63_32[0x20];
1502
1503         u8         queue_address_31_12[0x14];
1504         u8         reserved_0[0x6];
1505         u8         log_size[0x6];
1506
1507         struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1508
1509         u8         reserved_1[0x8];
1510         u8         queue_number[0x18];
1511
1512         u8         q_key[0x20];
1513
1514         u8         reserved_2[0x10];
1515         u8         pkey_index[0x10];
1516
1517         u8         reserved_3[0x40];
1518 };
1519
1520 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1521         u8         reserved_0[0x8];
1522         u8         cq_ci[0x10];
1523         u8         reserved_1[0x8];
1524 };
1525
1526 enum {
1527         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1528         MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1529 };
1530
1531 enum {
1532         MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1533         MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1534         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1535         MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1536 };
1537
1538 struct mlx5_ifc_nodnic_event_word_bits {
1539         u8         driver_reset_needed[0x1];
1540         u8         port_management_change_event[0x1];
1541         u8         reserved_0[0x19];
1542         u8         link_type[0x1];
1543         u8         port_state[0x4];
1544 };
1545
1546 struct mlx5_ifc_nic_vport_change_event_bits {
1547         u8         reserved_0[0x10];
1548         u8         vport_num[0x10];
1549
1550         u8         reserved_1[0xc0];
1551 };
1552
1553 struct mlx5_ifc_pages_req_event_bits {
1554         u8         reserved_0[0x10];
1555         u8         function_id[0x10];
1556
1557         u8         num_pages[0x20];
1558
1559         u8         reserved_1[0xa0];
1560 };
1561
1562 struct mlx5_ifc_cmd_inter_comp_event_bits {
1563         u8         command_completion_vector[0x20];
1564
1565         u8         reserved_0[0xc0];
1566 };
1567
1568 struct mlx5_ifc_stall_vl_event_bits {
1569         u8         reserved_0[0x18];
1570         u8         port_num[0x1];
1571         u8         reserved_1[0x3];
1572         u8         vl[0x4];
1573
1574         u8         reserved_2[0xa0];
1575 };
1576
1577 struct mlx5_ifc_db_bf_congestion_event_bits {
1578         u8         event_subtype[0x8];
1579         u8         reserved_0[0x8];
1580         u8         congestion_level[0x8];
1581         u8         reserved_1[0x8];
1582
1583         u8         reserved_2[0xa0];
1584 };
1585
1586 struct mlx5_ifc_gpio_event_bits {
1587         u8         reserved_0[0x60];
1588
1589         u8         gpio_event_hi[0x20];
1590
1591         u8         gpio_event_lo[0x20];
1592
1593         u8         reserved_1[0x40];
1594 };
1595
1596 struct mlx5_ifc_port_state_change_event_bits {
1597         u8         reserved_0[0x40];
1598
1599         u8         port_num[0x4];
1600         u8         reserved_1[0x1c];
1601
1602         u8         reserved_2[0x80];
1603 };
1604
1605 struct mlx5_ifc_dropped_packet_logged_bits {
1606         u8         reserved_0[0xe0];
1607 };
1608
1609 enum {
1610         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1611         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1612 };
1613
1614 struct mlx5_ifc_cq_error_bits {
1615         u8         reserved_0[0x8];
1616         u8         cqn[0x18];
1617
1618         u8         reserved_1[0x20];
1619
1620         u8         reserved_2[0x18];
1621         u8         syndrome[0x8];
1622
1623         u8         reserved_3[0x80];
1624 };
1625
1626 struct mlx5_ifc_rdma_page_fault_event_bits {
1627         u8         bytes_commited[0x20];
1628
1629         u8         r_key[0x20];
1630
1631         u8         reserved_0[0x10];
1632         u8         packet_len[0x10];
1633
1634         u8         rdma_op_len[0x20];
1635
1636         u8         rdma_va[0x40];
1637
1638         u8         reserved_1[0x5];
1639         u8         rdma[0x1];
1640         u8         write[0x1];
1641         u8         requestor[0x1];
1642         u8         qp_number[0x18];
1643 };
1644
1645 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1646         u8         bytes_committed[0x20];
1647
1648         u8         reserved_0[0x10];
1649         u8         wqe_index[0x10];
1650
1651         u8         reserved_1[0x10];
1652         u8         len[0x10];
1653
1654         u8         reserved_2[0x60];
1655
1656         u8         reserved_3[0x5];
1657         u8         rdma[0x1];
1658         u8         write_read[0x1];
1659         u8         requestor[0x1];
1660         u8         qpn[0x18];
1661 };
1662
1663 enum {
1664         MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1665         MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1666         MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1667 };
1668
1669 struct mlx5_ifc_qp_events_bits {
1670         u8         reserved_0[0xa0];
1671
1672         u8         type[0x8];
1673         u8         reserved_1[0x18];
1674
1675         u8         reserved_2[0x8];
1676         u8         qpn_rqn_sqn[0x18];
1677 };
1678
1679 struct mlx5_ifc_dct_events_bits {
1680         u8         reserved_0[0xc0];
1681
1682         u8         reserved_1[0x8];
1683         u8         dct_number[0x18];
1684 };
1685
1686 struct mlx5_ifc_comp_event_bits {
1687         u8         reserved_0[0xc0];
1688
1689         u8         reserved_1[0x8];
1690         u8         cq_number[0x18];
1691 };
1692
1693 struct mlx5_ifc_fw_version_bits {
1694         u8         major[0x10];
1695         u8         reserved_0[0x10];
1696
1697         u8         minor[0x10];
1698         u8         subminor[0x10];
1699
1700         u8         second[0x8];
1701         u8         minute[0x8];
1702         u8         hour[0x8];
1703         u8         reserved_1[0x8];
1704
1705         u8         year[0x10];
1706         u8         month[0x8];
1707         u8         day[0x8];
1708 };
1709
1710 enum {
1711         MLX5_QPC_STATE_RST        = 0x0,
1712         MLX5_QPC_STATE_INIT       = 0x1,
1713         MLX5_QPC_STATE_RTR        = 0x2,
1714         MLX5_QPC_STATE_RTS        = 0x3,
1715         MLX5_QPC_STATE_SQER       = 0x4,
1716         MLX5_QPC_STATE_SQD        = 0x5,
1717         MLX5_QPC_STATE_ERR        = 0x6,
1718         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1719 };
1720
1721 enum {
1722         MLX5_QPC_ST_RC            = 0x0,
1723         MLX5_QPC_ST_UC            = 0x1,
1724         MLX5_QPC_ST_UD            = 0x2,
1725         MLX5_QPC_ST_XRC           = 0x3,
1726         MLX5_QPC_ST_DCI           = 0x5,
1727         MLX5_QPC_ST_QP0           = 0x7,
1728         MLX5_QPC_ST_QP1           = 0x8,
1729         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1730         MLX5_QPC_ST_REG_UMR       = 0xc,
1731 };
1732
1733 enum {
1734         MLX5_QP_PM_ARMED            = 0x0,
1735         MLX5_QP_PM_REARM            = 0x1,
1736         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1737         MLX5_QP_PM_MIGRATED         = 0x3,
1738 };
1739
1740 enum {
1741         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1742         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1743 };
1744
1745 enum {
1746         MLX5_QPC_MTU_256_BYTES        = 0x1,
1747         MLX5_QPC_MTU_512_BYTES        = 0x2,
1748         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1749         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1750         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1751         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1752 };
1753
1754 enum {
1755         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1756         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1757         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1758         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1759         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1760         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1761         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1762         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1763 };
1764
1765 enum {
1766         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1767         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1768         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1769 };
1770
1771 enum {
1772         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1773         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1774         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1775 };
1776
1777 struct mlx5_ifc_qpc_bits {
1778         u8         state[0x4];
1779         u8         reserved_0[0x4];
1780         u8         st[0x8];
1781         u8         reserved_1[0x3];
1782         u8         pm_state[0x2];
1783         u8         reserved_2[0x7];
1784         u8         end_padding_mode[0x2];
1785         u8         reserved_3[0x2];
1786
1787         u8         wq_signature[0x1];
1788         u8         block_lb_mc[0x1];
1789         u8         atomic_like_write_en[0x1];
1790         u8         latency_sensitive[0x1];
1791         u8         reserved_4[0x1];
1792         u8         drain_sigerr[0x1];
1793         u8         reserved_5[0x2];
1794         u8         pd[0x18];
1795
1796         u8         mtu[0x3];
1797         u8         log_msg_max[0x5];
1798         u8         reserved_6[0x1];
1799         u8         log_rq_size[0x4];
1800         u8         log_rq_stride[0x3];
1801         u8         no_sq[0x1];
1802         u8         log_sq_size[0x4];
1803         u8         reserved_7[0x6];
1804         u8         rlky[0x1];
1805         u8         ulp_stateless_offload_mode[0x4];
1806
1807         u8         counter_set_id[0x8];
1808         u8         uar_page[0x18];
1809
1810         u8         reserved_8[0x8];
1811         u8         user_index[0x18];
1812
1813         u8         reserved_9[0x3];
1814         u8         log_page_size[0x5];
1815         u8         remote_qpn[0x18];
1816
1817         struct mlx5_ifc_ads_bits primary_address_path;
1818
1819         struct mlx5_ifc_ads_bits secondary_address_path;
1820
1821         u8         log_ack_req_freq[0x4];
1822         u8         reserved_10[0x4];
1823         u8         log_sra_max[0x3];
1824         u8         reserved_11[0x2];
1825         u8         retry_count[0x3];
1826         u8         rnr_retry[0x3];
1827         u8         reserved_12[0x1];
1828         u8         fre[0x1];
1829         u8         cur_rnr_retry[0x3];
1830         u8         cur_retry_count[0x3];
1831         u8         reserved_13[0x5];
1832
1833         u8         reserved_14[0x20];
1834
1835         u8         reserved_15[0x8];
1836         u8         next_send_psn[0x18];
1837
1838         u8         reserved_16[0x8];
1839         u8         cqn_snd[0x18];
1840
1841         u8         reserved_17[0x40];
1842
1843         u8         reserved_18[0x8];
1844         u8         last_acked_psn[0x18];
1845
1846         u8         reserved_19[0x8];
1847         u8         ssn[0x18];
1848
1849         u8         reserved_20[0x8];
1850         u8         log_rra_max[0x3];
1851         u8         reserved_21[0x1];
1852         u8         atomic_mode[0x4];
1853         u8         rre[0x1];
1854         u8         rwe[0x1];
1855         u8         rae[0x1];
1856         u8         reserved_22[0x1];
1857         u8         page_offset[0x6];
1858         u8         reserved_23[0x3];
1859         u8         cd_slave_receive[0x1];
1860         u8         cd_slave_send[0x1];
1861         u8         cd_master[0x1];
1862
1863         u8         reserved_24[0x3];
1864         u8         min_rnr_nak[0x5];
1865         u8         next_rcv_psn[0x18];
1866
1867         u8         reserved_25[0x8];
1868         u8         xrcd[0x18];
1869
1870         u8         reserved_26[0x8];
1871         u8         cqn_rcv[0x18];
1872
1873         u8         dbr_addr[0x40];
1874
1875         u8         q_key[0x20];
1876
1877         u8         reserved_27[0x5];
1878         u8         rq_type[0x3];
1879         u8         srqn_rmpn[0x18];
1880
1881         u8         reserved_28[0x8];
1882         u8         rmsn[0x18];
1883
1884         u8         hw_sq_wqebb_counter[0x10];
1885         u8         sw_sq_wqebb_counter[0x10];
1886
1887         u8         hw_rq_counter[0x20];
1888
1889         u8         sw_rq_counter[0x20];
1890
1891         u8         reserved_29[0x20];
1892
1893         u8         reserved_30[0xf];
1894         u8         cgs[0x1];
1895         u8         cs_req[0x8];
1896         u8         cs_res[0x8];
1897
1898         u8         dc_access_key[0x40];
1899
1900         u8         rdma_active[0x1];
1901         u8         comm_est[0x1];
1902         u8         suspended[0x1];
1903         u8         reserved_31[0x5];
1904         u8         send_msg_psn[0x18];
1905
1906         u8         reserved_32[0x8];
1907         u8         rcv_msg_psn[0x18];
1908
1909         u8         rdma_va[0x40];
1910
1911         u8         rdma_key[0x20];
1912
1913         u8         reserved_33[0x20];
1914 };
1915
1916 struct mlx5_ifc_roce_addr_layout_bits {
1917         u8         source_l3_address[16][0x8];
1918
1919         u8         reserved_0[0x3];
1920         u8         vlan_valid[0x1];
1921         u8         vlan_id[0xc];
1922         u8         source_mac_47_32[0x10];
1923
1924         u8         source_mac_31_0[0x20];
1925
1926         u8         reserved_1[0x14];
1927         u8         roce_l3_type[0x4];
1928         u8         roce_version[0x8];
1929
1930         u8         reserved_2[0x20];
1931 };
1932
1933 struct mlx5_ifc_rdbc_bits {
1934         u8         reserved_0[0x1c];
1935         u8         type[0x4];
1936
1937         u8         reserved_1[0x20];
1938
1939         u8         reserved_2[0x8];
1940         u8         psn[0x18];
1941
1942         u8         rkey[0x20];
1943
1944         u8         address[0x40];
1945
1946         u8         byte_count[0x20];
1947
1948         u8         reserved_3[0x20];
1949
1950         u8         atomic_resp[32][0x8];
1951 };
1952
1953 enum {
1954         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1955         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1956         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1957         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
1958 };
1959
1960 struct mlx5_ifc_flow_context_bits {
1961         u8         reserved_0[0x20];
1962
1963         u8         group_id[0x20];
1964
1965         u8         reserved_1[0x8];
1966         u8         flow_tag[0x18];
1967
1968         u8         reserved_2[0x10];
1969         u8         action[0x10];
1970
1971         u8         reserved_3[0x8];
1972         u8         destination_list_size[0x18];
1973
1974         u8         reserved_4[0x8];
1975         u8         flow_counter_list_size[0x18];
1976
1977         u8         reserved_5[0x140];
1978
1979         struct mlx5_ifc_fte_match_param_bits match_value;
1980
1981         u8         reserved_6[0x600];
1982
1983         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
1984 };
1985
1986 enum {
1987         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1988         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1989 };
1990
1991 struct mlx5_ifc_xrc_srqc_bits {
1992         u8         state[0x4];
1993         u8         log_xrc_srq_size[0x4];
1994         u8         reserved_0[0x18];
1995
1996         u8         wq_signature[0x1];
1997         u8         cont_srq[0x1];
1998         u8         reserved_1[0x1];
1999         u8         rlky[0x1];
2000         u8         basic_cyclic_rcv_wqe[0x1];
2001         u8         log_rq_stride[0x3];
2002         u8         xrcd[0x18];
2003
2004         u8         page_offset[0x6];
2005         u8         reserved_2[0x2];
2006         u8         cqn[0x18];
2007
2008         u8         reserved_3[0x20];
2009
2010         u8         reserved_4[0x2];
2011         u8         log_page_size[0x6];
2012         u8         user_index[0x18];
2013
2014         u8         reserved_5[0x20];
2015
2016         u8         reserved_6[0x8];
2017         u8         pd[0x18];
2018
2019         u8         lwm[0x10];
2020         u8         wqe_cnt[0x10];
2021
2022         u8         reserved_7[0x40];
2023
2024         u8         db_record_addr_h[0x20];
2025
2026         u8         db_record_addr_l[0x1e];
2027         u8         reserved_8[0x2];
2028
2029         u8         reserved_9[0x80];
2030 };
2031
2032 struct mlx5_ifc_traffic_counter_bits {
2033         u8         packets[0x40];
2034
2035         u8         octets[0x40];
2036 };
2037
2038 struct mlx5_ifc_tisc_bits {
2039         u8         reserved_0[0xc];
2040         u8         prio[0x4];
2041         u8         reserved_1[0x10];
2042
2043         u8         reserved_2[0x100];
2044
2045         u8         reserved_3[0x8];
2046         u8         transport_domain[0x18];
2047
2048         u8         reserved_4[0x8];
2049         u8         underlay_qpn[0x18];
2050
2051         u8         reserved_5[0x3a0];
2052 };
2053
2054 enum {
2055         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2056         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2057 };
2058
2059 enum {
2060         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2061         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2062 };
2063
2064 enum {
2065         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2066         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2067         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2068 };
2069
2070 enum {
2071         MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2072         MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2073 };
2074
2075 struct mlx5_ifc_tirc_bits {
2076         u8         reserved_0[0x20];
2077
2078         u8         disp_type[0x4];
2079         u8         reserved_1[0x1c];
2080
2081         u8         reserved_2[0x40];
2082
2083         u8         reserved_3[0x4];
2084         u8         lro_timeout_period_usecs[0x10];
2085         u8         lro_enable_mask[0x4];
2086         u8         lro_max_msg_sz[0x8];
2087
2088         u8         reserved_4[0x40];
2089
2090         u8         reserved_5[0x8];
2091         u8         inline_rqn[0x18];
2092
2093         u8         rx_hash_symmetric[0x1];
2094         u8         reserved_6[0x1];
2095         u8         tunneled_offload_en[0x1];
2096         u8         reserved_7[0x5];
2097         u8         indirect_table[0x18];
2098
2099         u8         rx_hash_fn[0x4];
2100         u8         reserved_8[0x2];
2101         u8         self_lb_en[0x2];
2102         u8         transport_domain[0x18];
2103
2104         u8         rx_hash_toeplitz_key[10][0x20];
2105
2106         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2107
2108         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2109
2110         u8         reserved_9[0x4c0];
2111 };
2112
2113 enum {
2114         MLX5_SRQC_STATE_GOOD   = 0x0,
2115         MLX5_SRQC_STATE_ERROR  = 0x1,
2116 };
2117
2118 struct mlx5_ifc_srqc_bits {
2119         u8         state[0x4];
2120         u8         log_srq_size[0x4];
2121         u8         reserved_0[0x18];
2122
2123         u8         wq_signature[0x1];
2124         u8         cont_srq[0x1];
2125         u8         reserved_1[0x1];
2126         u8         rlky[0x1];
2127         u8         reserved_2[0x1];
2128         u8         log_rq_stride[0x3];
2129         u8         xrcd[0x18];
2130
2131         u8         page_offset[0x6];
2132         u8         reserved_3[0x2];
2133         u8         cqn[0x18];
2134
2135         u8         reserved_4[0x20];
2136
2137         u8         reserved_5[0x2];
2138         u8         log_page_size[0x6];
2139         u8         reserved_6[0x18];
2140
2141         u8         reserved_7[0x20];
2142
2143         u8         reserved_8[0x8];
2144         u8         pd[0x18];
2145
2146         u8         lwm[0x10];
2147         u8         wqe_cnt[0x10];
2148
2149         u8         reserved_9[0x40];
2150
2151         u8         db_record_addr_h[0x20];
2152
2153         u8         db_record_addr_l[0x1e];
2154         u8         reserved_10[0x2];
2155
2156         u8         reserved_11[0x80];
2157 };
2158
2159 enum {
2160         MLX5_SQC_STATE_RST  = 0x0,
2161         MLX5_SQC_STATE_RDY  = 0x1,
2162         MLX5_SQC_STATE_ERR  = 0x3,
2163 };
2164
2165 struct mlx5_ifc_sqc_bits {
2166         u8         rlkey[0x1];
2167         u8         cd_master[0x1];
2168         u8         fre[0x1];
2169         u8         flush_in_error_en[0x1];
2170         u8         allow_multi_pkt_send_wqe[0x1];
2171         u8         min_wqe_inline_mode[0x3];
2172         u8         state[0x4];
2173         u8         reg_umr[0x1];
2174         u8         allow_swp[0x1];
2175         u8         reserved_0[0x12];
2176
2177         u8         reserved_1[0x8];
2178         u8         user_index[0x18];
2179
2180         u8         reserved_2[0x8];
2181         u8         cqn[0x18];
2182
2183         u8         reserved_3[0x80];
2184
2185         u8         qos_para_vport_number[0x10];
2186         u8         packet_pacing_rate_limit_index[0x10];
2187
2188         u8         tis_lst_sz[0x10];
2189         u8         reserved_4[0x10];
2190
2191         u8         reserved_5[0x40];
2192
2193         u8         reserved_6[0x8];
2194         u8         tis_num_0[0x18];
2195
2196         struct mlx5_ifc_wq_bits wq;
2197 };
2198
2199 enum {
2200         MLX5_TSAR_TYPE_DWRR = 0,
2201         MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2202         MLX5_TSAR_TYPE_ETS = 2
2203 };
2204
2205 struct mlx5_ifc_tsar_element_attributes_bits {
2206         u8         reserved_0[0x8];
2207         u8         tsar_type[0x8];
2208         u8         reserved_1[0x10];
2209 };
2210
2211 struct mlx5_ifc_vport_element_attributes_bits {
2212         u8         reserved_0[0x10];
2213         u8         vport_number[0x10];
2214 };
2215
2216 struct mlx5_ifc_vport_tc_element_attributes_bits {
2217         u8         traffic_class[0x10];
2218         u8         vport_number[0x10];
2219 };
2220
2221 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2222         u8         reserved_0[0x0C];
2223         u8         traffic_class[0x04];
2224         u8         qos_para_vport_number[0x10];
2225 };
2226
2227 enum {
2228         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2229         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2230         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2231         MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2232 };
2233
2234 struct mlx5_ifc_scheduling_context_bits {
2235         u8         element_type[0x8];
2236         u8         reserved_at_8[0x18];
2237
2238         u8         element_attributes[0x20];
2239
2240         u8         parent_element_id[0x20];
2241
2242         u8         reserved_at_60[0x40];
2243
2244         u8         bw_share[0x20];
2245
2246         u8         max_average_bw[0x20];
2247
2248         u8         reserved_at_e0[0x120];
2249 };
2250
2251 struct mlx5_ifc_rqtc_bits {
2252         u8         reserved_0[0xa0];
2253
2254         u8         reserved_1[0x10];
2255         u8         rqt_max_size[0x10];
2256
2257         u8         reserved_2[0x10];
2258         u8         rqt_actual_size[0x10];
2259
2260         u8         reserved_3[0x6a0];
2261
2262         struct mlx5_ifc_rq_num_bits rq_num[0];
2263 };
2264
2265 enum {
2266         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2267         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2268 };
2269
2270 enum {
2271         MLX5_RQC_STATE_RST  = 0x0,
2272         MLX5_RQC_STATE_RDY  = 0x1,
2273         MLX5_RQC_STATE_ERR  = 0x3,
2274 };
2275
2276 enum {
2277         MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2278         MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2279 };
2280
2281 struct mlx5_ifc_rqc_bits {
2282         u8         rlkey[0x1];
2283         u8         delay_drop_en[0x1];
2284         u8         scatter_fcs[0x1];
2285         u8         vlan_strip_disable[0x1];
2286         u8         mem_rq_type[0x4];
2287         u8         state[0x4];
2288         u8         reserved_1[0x1];
2289         u8         flush_in_error_en[0x1];
2290         u8         reserved_2[0x12];
2291
2292         u8         reserved_3[0x8];
2293         u8         user_index[0x18];
2294
2295         u8         reserved_4[0x8];
2296         u8         cqn[0x18];
2297
2298         u8         counter_set_id[0x8];
2299         u8         reserved_5[0x18];
2300
2301         u8         reserved_6[0x8];
2302         u8         rmpn[0x18];
2303
2304         u8         reserved_7[0xe0];
2305
2306         struct mlx5_ifc_wq_bits wq;
2307 };
2308
2309 enum {
2310         MLX5_RMPC_STATE_RDY  = 0x1,
2311         MLX5_RMPC_STATE_ERR  = 0x3,
2312 };
2313
2314 struct mlx5_ifc_rmpc_bits {
2315         u8         reserved_0[0x8];
2316         u8         state[0x4];
2317         u8         reserved_1[0x14];
2318
2319         u8         basic_cyclic_rcv_wqe[0x1];
2320         u8         reserved_2[0x1f];
2321
2322         u8         reserved_3[0x140];
2323
2324         struct mlx5_ifc_wq_bits wq;
2325 };
2326
2327 enum {
2328         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2329         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2330         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2331 };
2332
2333 struct mlx5_ifc_nic_vport_context_bits {
2334         u8         reserved_0[0x5];
2335         u8         min_wqe_inline_mode[0x3];
2336         u8         reserved_1[0x15];
2337         u8         disable_mc_local_lb[0x1];
2338         u8         disable_uc_local_lb[0x1];
2339         u8         roce_en[0x1];
2340
2341         u8         arm_change_event[0x1];
2342         u8         reserved_2[0x1a];
2343         u8         event_on_mtu[0x1];
2344         u8         event_on_promisc_change[0x1];
2345         u8         event_on_vlan_change[0x1];
2346         u8         event_on_mc_address_change[0x1];
2347         u8         event_on_uc_address_change[0x1];
2348
2349         u8         reserved_3[0xe0];
2350
2351         u8         reserved_4[0x10];
2352         u8         mtu[0x10];
2353
2354         u8         system_image_guid[0x40];
2355
2356         u8         port_guid[0x40];
2357
2358         u8         node_guid[0x40];
2359
2360         u8         reserved_5[0x140];
2361
2362         u8         qkey_violation_counter[0x10];
2363         u8         reserved_6[0x10];
2364
2365         u8         reserved_7[0x420];
2366
2367         u8         promisc_uc[0x1];
2368         u8         promisc_mc[0x1];
2369         u8         promisc_all[0x1];
2370         u8         reserved_8[0x2];
2371         u8         allowed_list_type[0x3];
2372         u8         reserved_9[0xc];
2373         u8         allowed_list_size[0xc];
2374
2375         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2376
2377         u8         reserved_10[0x20];
2378
2379         u8         current_uc_mac_address[0][0x40];
2380 };
2381
2382 enum {
2383         MLX5_ACCESS_MODE_PA        = 0x0,
2384         MLX5_ACCESS_MODE_MTT       = 0x1,
2385         MLX5_ACCESS_MODE_KLM       = 0x2,
2386 };
2387
2388 struct mlx5_ifc_mkc_bits {
2389         u8         reserved_0[0x1];
2390         u8         free[0x1];
2391         u8         reserved_1[0xd];
2392         u8         small_fence_on_rdma_read_response[0x1];
2393         u8         umr_en[0x1];
2394         u8         a[0x1];
2395         u8         rw[0x1];
2396         u8         rr[0x1];
2397         u8         lw[0x1];
2398         u8         lr[0x1];
2399         u8         access_mode[0x2];
2400         u8         reserved_2[0x8];
2401
2402         u8         qpn[0x18];
2403         u8         mkey_7_0[0x8];
2404
2405         u8         reserved_3[0x20];
2406
2407         u8         length64[0x1];
2408         u8         bsf_en[0x1];
2409         u8         sync_umr[0x1];
2410         u8         reserved_4[0x2];
2411         u8         expected_sigerr_count[0x1];
2412         u8         reserved_5[0x1];
2413         u8         en_rinval[0x1];
2414         u8         pd[0x18];
2415
2416         u8         start_addr[0x40];
2417
2418         u8         len[0x40];
2419
2420         u8         bsf_octword_size[0x20];
2421
2422         u8         reserved_6[0x80];
2423
2424         u8         translations_octword_size[0x20];
2425
2426         u8         reserved_7[0x1b];
2427         u8         log_page_size[0x5];
2428
2429         u8         reserved_8[0x20];
2430 };
2431
2432 struct mlx5_ifc_pkey_bits {
2433         u8         reserved_0[0x10];
2434         u8         pkey[0x10];
2435 };
2436
2437 struct mlx5_ifc_array128_auto_bits {
2438         u8         array128_auto[16][0x8];
2439 };
2440
2441 enum {
2442         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2443         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2444         MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2445 };
2446
2447 enum {
2448         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2449         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2450         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2451         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2452         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2453         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2454         MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2455 };
2456
2457 enum {
2458         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2459         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2460         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2461 };
2462
2463 enum {
2464         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2465         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2466         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2467         MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2468 };
2469
2470 enum {
2471         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2472         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2473         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2474         MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2475 };
2476
2477 struct mlx5_ifc_hca_vport_context_bits {
2478         u8         field_select[0x20];
2479
2480         u8         reserved_0[0xe0];
2481
2482         u8         sm_virt_aware[0x1];
2483         u8         has_smi[0x1];
2484         u8         has_raw[0x1];
2485         u8         grh_required[0x1];
2486         u8         reserved_1[0x1];
2487         u8         min_wqe_inline_mode[0x3];
2488         u8         reserved_2[0x8];
2489         u8         port_physical_state[0x4];
2490         u8         vport_state_policy[0x4];
2491         u8         port_state[0x4];
2492         u8         vport_state[0x4];
2493
2494         u8         reserved_3[0x20];
2495
2496         u8         system_image_guid[0x40];
2497
2498         u8         port_guid[0x40];
2499
2500         u8         node_guid[0x40];
2501
2502         u8         cap_mask1[0x20];
2503
2504         u8         cap_mask1_field_select[0x20];
2505
2506         u8         cap_mask2[0x20];
2507
2508         u8         cap_mask2_field_select[0x20];
2509
2510         u8         reserved_4[0x80];
2511
2512         u8         lid[0x10];
2513         u8         reserved_5[0x4];
2514         u8         init_type_reply[0x4];
2515         u8         lmc[0x3];
2516         u8         subnet_timeout[0x5];
2517
2518         u8         sm_lid[0x10];
2519         u8         sm_sl[0x4];
2520         u8         reserved_6[0xc];
2521
2522         u8         qkey_violation_counter[0x10];
2523         u8         pkey_violation_counter[0x10];
2524
2525         u8         reserved_7[0xca0];
2526 };
2527
2528 union mlx5_ifc_hca_cap_union_bits {
2529         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2530         struct mlx5_ifc_odp_cap_bits odp_cap;
2531         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2532         struct mlx5_ifc_roce_cap_bits roce_cap;
2533         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2534         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2535         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2536         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2537         struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2538         struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2539         struct mlx5_ifc_qos_cap_bits qos_cap;
2540         u8         reserved_0[0x8000];
2541 };
2542
2543 struct mlx5_ifc_esw_vport_context_bits {
2544         u8         reserved_0[0x3];
2545         u8         vport_svlan_strip[0x1];
2546         u8         vport_cvlan_strip[0x1];
2547         u8         vport_svlan_insert[0x1];
2548         u8         vport_cvlan_insert[0x2];
2549         u8         reserved_1[0x18];
2550
2551         u8         reserved_2[0x20];
2552
2553         u8         svlan_cfi[0x1];
2554         u8         svlan_pcp[0x3];
2555         u8         svlan_id[0xc];
2556         u8         cvlan_cfi[0x1];
2557         u8         cvlan_pcp[0x3];
2558         u8         cvlan_id[0xc];
2559
2560         u8         reserved_3[0x7a0];
2561 };
2562
2563 enum {
2564         MLX5_EQC_STATUS_OK                = 0x0,
2565         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2566 };
2567
2568 enum {
2569         MLX5_EQ_STATE_ARMED = 0x9,
2570         MLX5_EQ_STATE_FIRED = 0xa,
2571 };
2572
2573 struct mlx5_ifc_eqc_bits {
2574         u8         status[0x4];
2575         u8         reserved_0[0x9];
2576         u8         ec[0x1];
2577         u8         oi[0x1];
2578         u8         reserved_1[0x5];
2579         u8         st[0x4];
2580         u8         reserved_2[0x8];
2581
2582         u8         reserved_3[0x20];
2583
2584         u8         reserved_4[0x14];
2585         u8         page_offset[0x6];
2586         u8         reserved_5[0x6];
2587
2588         u8         reserved_6[0x3];
2589         u8         log_eq_size[0x5];
2590         u8         uar_page[0x18];
2591
2592         u8         reserved_7[0x20];
2593
2594         u8         reserved_8[0x18];
2595         u8         intr[0x8];
2596
2597         u8         reserved_9[0x3];
2598         u8         log_page_size[0x5];
2599         u8         reserved_10[0x18];
2600
2601         u8         reserved_11[0x60];
2602
2603         u8         reserved_12[0x8];
2604         u8         consumer_counter[0x18];
2605
2606         u8         reserved_13[0x8];
2607         u8         producer_counter[0x18];
2608
2609         u8         reserved_14[0x80];
2610 };
2611
2612 enum {
2613         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2614         MLX5_DCTC_STATE_DRAINING  = 0x1,
2615         MLX5_DCTC_STATE_DRAINED   = 0x2,
2616 };
2617
2618 enum {
2619         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2620         MLX5_DCTC_CS_RES_NA         = 0x1,
2621         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2622 };
2623
2624 enum {
2625         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2626         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2627         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2628         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2629         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2630 };
2631
2632 struct mlx5_ifc_dctc_bits {
2633         u8         reserved_0[0x4];
2634         u8         state[0x4];
2635         u8         reserved_1[0x18];
2636
2637         u8         reserved_2[0x8];
2638         u8         user_index[0x18];
2639
2640         u8         reserved_3[0x8];
2641         u8         cqn[0x18];
2642
2643         u8         counter_set_id[0x8];
2644         u8         atomic_mode[0x4];
2645         u8         rre[0x1];
2646         u8         rwe[0x1];
2647         u8         rae[0x1];
2648         u8         atomic_like_write_en[0x1];
2649         u8         latency_sensitive[0x1];
2650         u8         rlky[0x1];
2651         u8         reserved_4[0xe];
2652
2653         u8         reserved_5[0x8];
2654         u8         cs_res[0x8];
2655         u8         reserved_6[0x3];
2656         u8         min_rnr_nak[0x5];
2657         u8         reserved_7[0x8];
2658
2659         u8         reserved_8[0x8];
2660         u8         srqn[0x18];
2661
2662         u8         reserved_9[0x8];
2663         u8         pd[0x18];
2664
2665         u8         tclass[0x8];
2666         u8         reserved_10[0x4];
2667         u8         flow_label[0x14];
2668
2669         u8         dc_access_key[0x40];
2670
2671         u8         reserved_11[0x5];
2672         u8         mtu[0x3];
2673         u8         port[0x8];
2674         u8         pkey_index[0x10];
2675
2676         u8         reserved_12[0x8];
2677         u8         my_addr_index[0x8];
2678         u8         reserved_13[0x8];
2679         u8         hop_limit[0x8];
2680
2681         u8         dc_access_key_violation_count[0x20];
2682
2683         u8         reserved_14[0x14];
2684         u8         dei_cfi[0x1];
2685         u8         eth_prio[0x3];
2686         u8         ecn[0x2];
2687         u8         dscp[0x6];
2688
2689         u8         reserved_15[0x40];
2690 };
2691
2692 enum {
2693         MLX5_CQC_STATUS_OK             = 0x0,
2694         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2695         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2696 };
2697
2698 enum {
2699         CQE_SIZE_64                = 0x0,
2700         CQE_SIZE_128               = 0x1,
2701 };
2702
2703 enum {
2704         MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2705         MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2706 };
2707
2708 enum {
2709         MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2710         MLX5_CQ_STATE_ARMED                               = 0x9,
2711         MLX5_CQ_STATE_FIRED                               = 0xa,
2712 };
2713
2714 struct mlx5_ifc_cqc_bits {
2715         u8         status[0x4];
2716         u8         reserved_0[0x4];
2717         u8         cqe_sz[0x3];
2718         u8         cc[0x1];
2719         u8         reserved_1[0x1];
2720         u8         scqe_break_moderation_en[0x1];
2721         u8         oi[0x1];
2722         u8         cq_period_mode[0x2];
2723         u8         cqe_compression_en[0x1];
2724         u8         mini_cqe_res_format[0x2];
2725         u8         st[0x4];
2726         u8         reserved_2[0x8];
2727
2728         u8         reserved_3[0x20];
2729
2730         u8         reserved_4[0x14];
2731         u8         page_offset[0x6];
2732         u8         reserved_5[0x6];
2733
2734         u8         reserved_6[0x3];
2735         u8         log_cq_size[0x5];
2736         u8         uar_page[0x18];
2737
2738         u8         reserved_7[0x4];
2739         u8         cq_period[0xc];
2740         u8         cq_max_count[0x10];
2741
2742         u8         reserved_8[0x18];
2743         u8         c_eqn[0x8];
2744
2745         u8         reserved_9[0x3];
2746         u8         log_page_size[0x5];
2747         u8         reserved_10[0x18];
2748
2749         u8         reserved_11[0x20];
2750
2751         u8         reserved_12[0x8];
2752         u8         last_notified_index[0x18];
2753
2754         u8         reserved_13[0x8];
2755         u8         last_solicit_index[0x18];
2756
2757         u8         reserved_14[0x8];
2758         u8         consumer_counter[0x18];
2759
2760         u8         reserved_15[0x8];
2761         u8         producer_counter[0x18];
2762
2763         u8         reserved_16[0x40];
2764
2765         u8         dbr_addr[0x40];
2766 };
2767
2768 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2769         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2770         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2771         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2772         u8         reserved_0[0x800];
2773 };
2774
2775 struct mlx5_ifc_query_adapter_param_block_bits {
2776         u8         reserved_0[0xc0];
2777
2778         u8         reserved_1[0x8];
2779         u8         ieee_vendor_id[0x18];
2780
2781         u8         reserved_2[0x10];
2782         u8         vsd_vendor_id[0x10];
2783
2784         u8         vsd[208][0x8];
2785
2786         u8         vsd_contd_psid[16][0x8];
2787 };
2788
2789 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2790         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2791         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2792         u8         reserved_0[0x20];
2793 };
2794
2795 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2796         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2797         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2798         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2799         u8         reserved_0[0x20];
2800 };
2801
2802 struct mlx5_ifc_bufferx_reg_bits {
2803         u8         reserved_0[0x6];
2804         u8         lossy[0x1];
2805         u8         epsb[0x1];
2806         u8         reserved_1[0xc];
2807         u8         size[0xc];
2808
2809         u8         xoff_threshold[0x10];
2810         u8         xon_threshold[0x10];
2811 };
2812
2813 struct mlx5_ifc_config_item_bits {
2814         u8         valid[0x2];
2815         u8         reserved_0[0x2];
2816         u8         header_type[0x2];
2817         u8         reserved_1[0x2];
2818         u8         default_location[0x1];
2819         u8         reserved_2[0x7];
2820         u8         version[0x4];
2821         u8         reserved_3[0x3];
2822         u8         length[0x9];
2823
2824         u8         type[0x20];
2825
2826         u8         reserved_4[0x10];
2827         u8         crc16[0x10];
2828 };
2829
2830 struct mlx5_ifc_nodnic_port_config_reg_bits {
2831         struct mlx5_ifc_nodnic_event_word_bits event;
2832
2833         u8         network_en[0x1];
2834         u8         dma_en[0x1];
2835         u8         promisc_en[0x1];
2836         u8         promisc_multicast_en[0x1];
2837         u8         reserved_0[0x17];
2838         u8         receive_filter_en[0x5];
2839
2840         u8         reserved_1[0x10];
2841         u8         mac_47_32[0x10];
2842
2843         u8         mac_31_0[0x20];
2844
2845         u8         receive_filters_mgid_mac[64][0x8];
2846
2847         u8         gid[16][0x8];
2848
2849         u8         reserved_2[0x10];
2850         u8         lid[0x10];
2851
2852         u8         reserved_3[0xc];
2853         u8         sm_sl[0x4];
2854         u8         sm_lid[0x10];
2855
2856         u8         completion_address_63_32[0x20];
2857
2858         u8         completion_address_31_12[0x14];
2859         u8         reserved_4[0x6];
2860         u8         log_cq_size[0x6];
2861
2862         u8         working_buffer_address_63_32[0x20];
2863
2864         u8         working_buffer_address_31_12[0x14];
2865         u8         reserved_5[0xc];
2866
2867         struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2868
2869         u8         pkey_index[0x10];
2870         u8         pkey[0x10];
2871
2872         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2873
2874         struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2875
2876         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2877
2878         struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2879
2880         u8         reserved_6[0x400];
2881 };
2882
2883 union mlx5_ifc_event_auto_bits {
2884         struct mlx5_ifc_comp_event_bits comp_event;
2885         struct mlx5_ifc_dct_events_bits dct_events;
2886         struct mlx5_ifc_qp_events_bits qp_events;
2887         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2888         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2889         struct mlx5_ifc_cq_error_bits cq_error;
2890         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2891         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2892         struct mlx5_ifc_gpio_event_bits gpio_event;
2893         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2894         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2895         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2896         struct mlx5_ifc_pages_req_event_bits pages_req_event;
2897         struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2898         u8         reserved_0[0xe0];
2899 };
2900
2901 struct mlx5_ifc_health_buffer_bits {
2902         u8         reserved_0[0x100];
2903
2904         u8         assert_existptr[0x20];
2905
2906         u8         assert_callra[0x20];
2907
2908         u8         reserved_1[0x40];
2909
2910         u8         fw_version[0x20];
2911
2912         u8         hw_id[0x20];
2913
2914         u8         reserved_2[0x20];
2915
2916         u8         irisc_index[0x8];
2917         u8         synd[0x8];
2918         u8         ext_synd[0x10];
2919 };
2920
2921 struct mlx5_ifc_register_loopback_control_bits {
2922         u8         no_lb[0x1];
2923         u8         reserved_0[0x7];
2924         u8         port[0x8];
2925         u8         reserved_1[0x10];
2926
2927         u8         reserved_2[0x60];
2928 };
2929
2930 struct mlx5_ifc_lrh_bits {
2931         u8      vl[4];
2932         u8      lver[4];
2933         u8      sl[4];
2934         u8      reserved2[2];
2935         u8      lnh[2];
2936         u8      dlid[16];
2937         u8      reserved5[5];
2938         u8      pkt_len[11];
2939         u8      slid[16];
2940 };
2941
2942 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
2943         u8         reserved_0[0x40];
2944
2945         u8         reserved_1[0x10];
2946         u8         rol_mode[0x8];
2947         u8         wol_mode[0x8];
2948 };
2949
2950 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
2951         u8         reserved_0[0x40];
2952
2953         u8         rol_mode_valid[0x1];
2954         u8         wol_mode_valid[0x1];
2955         u8         reserved_1[0xe];
2956         u8         rol_mode[0x8];
2957         u8         wol_mode[0x8];
2958
2959         u8         reserved_2[0x7a0];
2960 };
2961
2962 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
2963         u8         virtual_mac_en[0x1];
2964         u8         mac_aux_v[0x1];
2965         u8         reserved_0[0x1e];
2966
2967         u8         reserved_1[0x40];
2968
2969         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2970
2971         u8         reserved_2[0x760];
2972 };
2973
2974 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
2975         u8         virtual_mac_en[0x1];
2976         u8         mac_aux_v[0x1];
2977         u8         reserved_0[0x1e];
2978
2979         struct mlx5_ifc_mac_address_layout_bits permanent_mac;
2980
2981         struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2982
2983         u8         reserved_1[0x760];
2984 };
2985
2986 struct mlx5_ifc_icmd_query_fw_info_out_bits {
2987         struct mlx5_ifc_fw_version_bits fw_version;
2988
2989         u8         reserved_0[0x10];
2990         u8         hash_signature[0x10];
2991
2992         u8         psid[16][0x8];
2993
2994         u8         reserved_1[0x6e0];
2995 };
2996
2997 struct mlx5_ifc_icmd_query_cap_in_bits {
2998         u8         reserved_0[0x10];
2999         u8         capability_group[0x10];
3000 };
3001
3002 struct mlx5_ifc_icmd_query_cap_general_bits {
3003         u8         nv_access[0x1];
3004         u8         fw_info_psid[0x1];
3005         u8         reserved_0[0x1e];
3006
3007         u8         reserved_1[0x16];
3008         u8         rol_s[0x1];
3009         u8         rol_g[0x1];
3010         u8         reserved_2[0x1];
3011         u8         wol_s[0x1];
3012         u8         wol_g[0x1];
3013         u8         wol_a[0x1];
3014         u8         wol_b[0x1];
3015         u8         wol_m[0x1];
3016         u8         wol_u[0x1];
3017         u8         wol_p[0x1];
3018 };
3019
3020 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3021         u8         status[0x8];
3022         u8         reserved_0[0x18];
3023
3024         u8         reserved_1[0x7e0];
3025 };
3026
3027 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3028         u8         status[0x8];
3029         u8         reserved_0[0x18];
3030
3031         u8         reserved_1[0x7e0];
3032 };
3033
3034 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3035         u8         address_hi[0x20];
3036
3037         u8         address_lo[0x20];
3038
3039         u8         reserved_0[0x7c0];
3040 };
3041
3042 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3043         u8         reserved_0[0x20];
3044
3045         u8         address_hi[0x20];
3046
3047         u8         address_lo[0x20];
3048
3049         u8         reserved_1[0x7a0];
3050 };
3051
3052 struct mlx5_ifc_icmd_access_reg_out_bits {
3053         u8         reserved_0[0x11];
3054         u8         status[0x7];
3055         u8         reserved_1[0x8];
3056
3057         u8         register_id[0x10];
3058         u8         reserved_2[0x10];
3059
3060         u8         reserved_3[0x40];
3061
3062         u8         reserved_4[0x5];
3063         u8         len[0xb];
3064         u8         reserved_5[0x10];
3065
3066         u8         register_data[0][0x20];
3067 };
3068
3069 enum {
3070         MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3071         MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3072 };
3073
3074 struct mlx5_ifc_icmd_access_reg_in_bits {
3075         u8         constant_1[0x5];
3076         u8         constant_2[0xb];
3077         u8         reserved_0[0x10];
3078
3079         u8         register_id[0x10];
3080         u8         reserved_1[0x1];
3081         u8         method[0x7];
3082         u8         constant_3[0x8];
3083
3084         u8         reserved_2[0x40];
3085
3086         u8         constant_4[0x5];
3087         u8         len[0xb];
3088         u8         reserved_3[0x10];
3089
3090         u8         register_data[0][0x20];
3091 };
3092
3093 struct mlx5_ifc_teardown_hca_out_bits {
3094         u8         status[0x8];
3095         u8         reserved_0[0x18];
3096
3097         u8         syndrome[0x20];
3098
3099         u8         reserved_1[0x40];
3100 };
3101
3102 enum {
3103         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3104         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3105 };
3106
3107 struct mlx5_ifc_teardown_hca_in_bits {
3108         u8         opcode[0x10];
3109         u8         reserved_0[0x10];
3110
3111         u8         reserved_1[0x10];
3112         u8         op_mod[0x10];
3113
3114         u8         reserved_2[0x10];
3115         u8         profile[0x10];
3116
3117         u8         reserved_3[0x20];
3118 };
3119
3120 struct mlx5_ifc_set_delay_drop_params_out_bits {
3121         u8         status[0x8];
3122         u8         reserved_at_8[0x18];
3123
3124         u8         syndrome[0x20];
3125
3126         u8         reserved_at_40[0x40];
3127 };
3128
3129 struct mlx5_ifc_set_delay_drop_params_in_bits {
3130         u8         opcode[0x10];
3131         u8         reserved_at_10[0x10];
3132
3133         u8         reserved_at_20[0x10];
3134         u8         op_mod[0x10];
3135
3136         u8         reserved_at_40[0x20];
3137
3138         u8         reserved_at_60[0x10];
3139         u8         delay_drop_timeout[0x10];
3140 };
3141
3142 struct mlx5_ifc_query_delay_drop_params_out_bits {
3143         u8         status[0x8];
3144         u8         reserved_at_8[0x18];
3145
3146         u8         syndrome[0x20];
3147
3148         u8         reserved_at_40[0x20];
3149
3150         u8         reserved_at_60[0x10];
3151         u8         delay_drop_timeout[0x10];
3152 };
3153
3154 struct mlx5_ifc_query_delay_drop_params_in_bits {
3155         u8         opcode[0x10];
3156         u8         reserved_at_10[0x10];
3157
3158         u8         reserved_at_20[0x10];
3159         u8         op_mod[0x10];
3160
3161         u8         reserved_at_40[0x40];
3162 };
3163
3164 struct mlx5_ifc_suspend_qp_out_bits {
3165         u8         status[0x8];
3166         u8         reserved_0[0x18];
3167
3168         u8         syndrome[0x20];
3169
3170         u8         reserved_1[0x40];
3171 };
3172
3173 struct mlx5_ifc_suspend_qp_in_bits {
3174         u8         opcode[0x10];
3175         u8         reserved_0[0x10];
3176
3177         u8         reserved_1[0x10];
3178         u8         op_mod[0x10];
3179
3180         u8         reserved_2[0x8];
3181         u8         qpn[0x18];
3182
3183         u8         reserved_3[0x20];
3184 };
3185
3186 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3187         u8         status[0x8];
3188         u8         reserved_0[0x18];
3189
3190         u8         syndrome[0x20];
3191
3192         u8         reserved_1[0x40];
3193 };
3194
3195 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3196         u8         opcode[0x10];
3197         u8         reserved_0[0x10];
3198
3199         u8         reserved_1[0x10];
3200         u8         op_mod[0x10];
3201
3202         u8         reserved_2[0x8];
3203         u8         qpn[0x18];
3204
3205         u8         reserved_3[0x20];
3206
3207         u8         opt_param_mask[0x20];
3208
3209         u8         reserved_4[0x20];
3210
3211         struct mlx5_ifc_qpc_bits qpc;
3212
3213         u8         reserved_5[0x80];
3214 };
3215
3216 struct mlx5_ifc_sqd2rts_qp_out_bits {
3217         u8         status[0x8];
3218         u8         reserved_0[0x18];
3219
3220         u8         syndrome[0x20];
3221
3222         u8         reserved_1[0x40];
3223 };
3224
3225 struct mlx5_ifc_sqd2rts_qp_in_bits {
3226         u8         opcode[0x10];
3227         u8         reserved_0[0x10];
3228
3229         u8         reserved_1[0x10];
3230         u8         op_mod[0x10];
3231
3232         u8         reserved_2[0x8];
3233         u8         qpn[0x18];
3234
3235         u8         reserved_3[0x20];
3236
3237         u8         opt_param_mask[0x20];
3238
3239         u8         reserved_4[0x20];
3240
3241         struct mlx5_ifc_qpc_bits qpc;
3242
3243         u8         reserved_5[0x80];
3244 };
3245
3246 struct mlx5_ifc_set_wol_rol_out_bits {
3247         u8         status[0x8];
3248         u8         reserved_0[0x18];
3249
3250         u8         syndrome[0x20];
3251
3252         u8         reserved_1[0x40];
3253 };
3254
3255 struct mlx5_ifc_set_wol_rol_in_bits {
3256         u8         opcode[0x10];
3257         u8         reserved_0[0x10];
3258
3259         u8         reserved_1[0x10];
3260         u8         op_mod[0x10];
3261
3262         u8         rol_mode_valid[0x1];
3263         u8         wol_mode_valid[0x1];
3264         u8         reserved_2[0xe];
3265         u8         rol_mode[0x8];
3266         u8         wol_mode[0x8];
3267
3268         u8         reserved_3[0x20];
3269 };
3270
3271 struct mlx5_ifc_set_roce_address_out_bits {
3272         u8         status[0x8];
3273         u8         reserved_0[0x18];
3274
3275         u8         syndrome[0x20];
3276
3277         u8         reserved_1[0x40];
3278 };
3279
3280 struct mlx5_ifc_set_roce_address_in_bits {
3281         u8         opcode[0x10];
3282         u8         reserved_0[0x10];
3283
3284         u8         reserved_1[0x10];
3285         u8         op_mod[0x10];
3286
3287         u8         roce_address_index[0x10];
3288         u8         reserved_2[0x10];
3289
3290         u8         reserved_3[0x20];
3291
3292         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3293 };
3294
3295 struct mlx5_ifc_set_rdb_out_bits {
3296         u8         status[0x8];
3297         u8         reserved_0[0x18];
3298
3299         u8         syndrome[0x20];
3300
3301         u8         reserved_1[0x40];
3302 };
3303
3304 struct mlx5_ifc_set_rdb_in_bits {
3305         u8         opcode[0x10];
3306         u8         reserved_0[0x10];
3307
3308         u8         reserved_1[0x10];
3309         u8         op_mod[0x10];
3310
3311         u8         reserved_2[0x8];
3312         u8         qpn[0x18];
3313
3314         u8         reserved_3[0x18];
3315         u8         rdb_list_size[0x8];
3316
3317         struct mlx5_ifc_rdbc_bits rdb_context[0];
3318 };
3319
3320 struct mlx5_ifc_set_mad_demux_out_bits {
3321         u8         status[0x8];
3322         u8         reserved_0[0x18];
3323
3324         u8         syndrome[0x20];
3325
3326         u8         reserved_1[0x40];
3327 };
3328
3329 enum {
3330         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3331         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3332 };
3333
3334 struct mlx5_ifc_set_mad_demux_in_bits {
3335         u8         opcode[0x10];
3336         u8         reserved_0[0x10];
3337
3338         u8         reserved_1[0x10];
3339         u8         op_mod[0x10];
3340
3341         u8         reserved_2[0x20];
3342
3343         u8         reserved_3[0x6];
3344         u8         demux_mode[0x2];
3345         u8         reserved_4[0x18];
3346 };
3347
3348 struct mlx5_ifc_set_l2_table_entry_out_bits {
3349         u8         status[0x8];
3350         u8         reserved_0[0x18];
3351
3352         u8         syndrome[0x20];
3353
3354         u8         reserved_1[0x40];
3355 };
3356
3357 struct mlx5_ifc_set_l2_table_entry_in_bits {
3358         u8         opcode[0x10];
3359         u8         reserved_0[0x10];
3360
3361         u8         reserved_1[0x10];
3362         u8         op_mod[0x10];
3363
3364         u8         reserved_2[0x60];
3365
3366         u8         reserved_3[0x8];
3367         u8         table_index[0x18];
3368
3369         u8         reserved_4[0x20];
3370
3371         u8         reserved_5[0x13];
3372         u8         vlan_valid[0x1];
3373         u8         vlan[0xc];
3374
3375         struct mlx5_ifc_mac_address_layout_bits mac_address;
3376
3377         u8         reserved_6[0xc0];
3378 };
3379
3380 struct mlx5_ifc_set_issi_out_bits {
3381         u8         status[0x8];
3382         u8         reserved_0[0x18];
3383
3384         u8         syndrome[0x20];
3385
3386         u8         reserved_1[0x40];
3387 };
3388
3389 struct mlx5_ifc_set_issi_in_bits {
3390         u8         opcode[0x10];
3391         u8         reserved_0[0x10];
3392
3393         u8         reserved_1[0x10];
3394         u8         op_mod[0x10];
3395
3396         u8         reserved_2[0x10];
3397         u8         current_issi[0x10];
3398
3399         u8         reserved_3[0x20];
3400 };
3401
3402 struct mlx5_ifc_set_hca_cap_out_bits {
3403         u8         status[0x8];
3404         u8         reserved_0[0x18];
3405
3406         u8         syndrome[0x20];
3407
3408         u8         reserved_1[0x40];
3409 };
3410
3411 struct mlx5_ifc_set_hca_cap_in_bits {
3412         u8         opcode[0x10];
3413         u8         reserved_0[0x10];
3414
3415         u8         reserved_1[0x10];
3416         u8         op_mod[0x10];
3417
3418         u8         reserved_2[0x40];
3419
3420         union mlx5_ifc_hca_cap_union_bits capability;
3421 };
3422
3423 enum {
3424         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION                  = 0x0,
3425         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG                = 0x1,
3426         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST        = 0x2,
3427         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS           = 0x3
3428 };
3429
3430 struct mlx5_ifc_set_flow_table_root_out_bits {
3431         u8         status[0x8];
3432         u8         reserved_0[0x18];
3433
3434         u8         syndrome[0x20];
3435
3436         u8         reserved_1[0x40];
3437 };
3438
3439 struct mlx5_ifc_set_flow_table_root_in_bits {
3440         u8         opcode[0x10];
3441         u8         reserved_0[0x10];
3442
3443         u8         reserved_1[0x10];
3444         u8         op_mod[0x10];
3445
3446         u8         other_vport[0x1];
3447         u8         reserved_2[0xf];
3448         u8         vport_number[0x10];
3449
3450         u8         reserved_3[0x20];
3451
3452         u8         table_type[0x8];
3453         u8         reserved_4[0x18];
3454
3455         u8         reserved_5[0x8];
3456         u8         table_id[0x18];
3457
3458         u8         reserved_6[0x8];
3459         u8         underlay_qpn[0x18];
3460
3461         u8         reserved_7[0x120];
3462 };
3463
3464 struct mlx5_ifc_set_fte_out_bits {
3465         u8         status[0x8];
3466         u8         reserved_0[0x18];
3467
3468         u8         syndrome[0x20];
3469
3470         u8         reserved_1[0x40];
3471 };
3472
3473 struct mlx5_ifc_set_fte_in_bits {
3474         u8         opcode[0x10];
3475         u8         reserved_0[0x10];
3476
3477         u8         reserved_1[0x10];
3478         u8         op_mod[0x10];
3479
3480         u8         other_vport[0x1];
3481         u8         reserved_2[0xf];
3482         u8         vport_number[0x10];
3483
3484         u8         reserved_3[0x20];
3485
3486         u8         table_type[0x8];
3487         u8         reserved_4[0x18];
3488
3489         u8         reserved_5[0x8];
3490         u8         table_id[0x18];
3491
3492         u8         reserved_6[0x18];
3493         u8         modify_enable_mask[0x8];
3494
3495         u8         reserved_7[0x20];
3496
3497         u8         flow_index[0x20];
3498
3499         u8         reserved_8[0xe0];
3500
3501         struct mlx5_ifc_flow_context_bits flow_context;
3502 };
3503
3504 struct mlx5_ifc_set_driver_version_out_bits {
3505         u8         status[0x8];
3506         u8         reserved_0[0x18];
3507
3508         u8         syndrome[0x20];
3509
3510         u8         reserved_1[0x40];
3511 };
3512
3513 struct mlx5_ifc_set_driver_version_in_bits {
3514         u8         opcode[0x10];
3515         u8         reserved_0[0x10];
3516
3517         u8         reserved_1[0x10];
3518         u8         op_mod[0x10];
3519
3520         u8         reserved_2[0x40];
3521
3522         u8         driver_version[64][0x8];
3523 };
3524
3525 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3526         u8         status[0x8];
3527         u8         reserved_0[0x18];
3528
3529         u8         syndrome[0x20];
3530
3531         u8         reserved_1[0x40];
3532 };
3533
3534 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3535         u8         opcode[0x10];
3536         u8         reserved_0[0x10];
3537
3538         u8         reserved_1[0x10];
3539         u8         op_mod[0x10];
3540
3541         u8         enable[0x1];
3542         u8         reserved_2[0x1f];
3543
3544         u8         reserved_3[0x160];
3545
3546         struct mlx5_ifc_cmd_pas_bits pas;
3547 };
3548
3549 struct mlx5_ifc_set_burst_size_out_bits {
3550         u8         status[0x8];
3551         u8         reserved_0[0x18];
3552
3553         u8         syndrome[0x20];
3554
3555         u8         reserved_1[0x40];
3556 };
3557
3558 struct mlx5_ifc_set_burst_size_in_bits {
3559         u8         opcode[0x10];
3560         u8         reserved_0[0x10];
3561
3562         u8         reserved_1[0x10];
3563         u8         op_mod[0x10];
3564
3565         u8         reserved_2[0x20];
3566
3567         u8         reserved_3[0x9];
3568         u8         device_burst_size[0x17];
3569 };
3570
3571 struct mlx5_ifc_rts2rts_qp_out_bits {
3572         u8         status[0x8];
3573         u8         reserved_0[0x18];
3574
3575         u8         syndrome[0x20];
3576
3577         u8         reserved_1[0x40];
3578 };
3579
3580 struct mlx5_ifc_rts2rts_qp_in_bits {
3581         u8         opcode[0x10];
3582         u8         reserved_0[0x10];
3583
3584         u8         reserved_1[0x10];
3585         u8         op_mod[0x10];
3586
3587         u8         reserved_2[0x8];
3588         u8         qpn[0x18];
3589
3590         u8         reserved_3[0x20];
3591
3592         u8         opt_param_mask[0x20];
3593
3594         u8         reserved_4[0x20];
3595
3596         struct mlx5_ifc_qpc_bits qpc;
3597
3598         u8         reserved_5[0x80];
3599 };
3600
3601 struct mlx5_ifc_rtr2rts_qp_out_bits {
3602         u8         status[0x8];
3603         u8         reserved_0[0x18];
3604
3605         u8         syndrome[0x20];
3606
3607         u8         reserved_1[0x40];
3608 };
3609
3610 struct mlx5_ifc_rtr2rts_qp_in_bits {
3611         u8         opcode[0x10];
3612         u8         reserved_0[0x10];
3613
3614         u8         reserved_1[0x10];
3615         u8         op_mod[0x10];
3616
3617         u8         reserved_2[0x8];
3618         u8         qpn[0x18];
3619
3620         u8         reserved_3[0x20];
3621
3622         u8         opt_param_mask[0x20];
3623
3624         u8         reserved_4[0x20];
3625
3626         struct mlx5_ifc_qpc_bits qpc;
3627
3628         u8         reserved_5[0x80];
3629 };
3630
3631 struct mlx5_ifc_rst2init_qp_out_bits {
3632         u8         status[0x8];
3633         u8         reserved_0[0x18];
3634
3635         u8         syndrome[0x20];
3636
3637         u8         reserved_1[0x40];
3638 };
3639
3640 struct mlx5_ifc_rst2init_qp_in_bits {
3641         u8         opcode[0x10];
3642         u8         reserved_0[0x10];
3643
3644         u8         reserved_1[0x10];
3645         u8         op_mod[0x10];
3646
3647         u8         reserved_2[0x8];
3648         u8         qpn[0x18];
3649
3650         u8         reserved_3[0x20];
3651
3652         u8         opt_param_mask[0x20];
3653
3654         u8         reserved_4[0x20];
3655
3656         struct mlx5_ifc_qpc_bits qpc;
3657
3658         u8         reserved_5[0x80];
3659 };
3660
3661 struct mlx5_ifc_resume_qp_out_bits {
3662         u8         status[0x8];
3663         u8         reserved_0[0x18];
3664
3665         u8         syndrome[0x20];
3666
3667         u8         reserved_1[0x40];
3668 };
3669
3670 struct mlx5_ifc_resume_qp_in_bits {
3671         u8         opcode[0x10];
3672         u8         reserved_0[0x10];
3673
3674         u8         reserved_1[0x10];
3675         u8         op_mod[0x10];
3676
3677         u8         reserved_2[0x8];
3678         u8         qpn[0x18];
3679
3680         u8         reserved_3[0x20];
3681 };
3682
3683 struct mlx5_ifc_query_xrc_srq_out_bits {
3684         u8         status[0x8];
3685         u8         reserved_0[0x18];
3686
3687         u8         syndrome[0x20];
3688
3689         u8         reserved_1[0x40];
3690
3691         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3692
3693         u8         reserved_2[0x600];
3694
3695         u8         pas[0][0x40];
3696 };
3697
3698 struct mlx5_ifc_query_xrc_srq_in_bits {
3699         u8         opcode[0x10];
3700         u8         reserved_0[0x10];
3701
3702         u8         reserved_1[0x10];
3703         u8         op_mod[0x10];
3704
3705         u8         reserved_2[0x8];
3706         u8         xrc_srqn[0x18];
3707
3708         u8         reserved_3[0x20];
3709 };
3710
3711 struct mlx5_ifc_query_wol_rol_out_bits {
3712         u8         status[0x8];
3713         u8         reserved_0[0x18];
3714
3715         u8         syndrome[0x20];
3716
3717         u8         reserved_1[0x10];
3718         u8         rol_mode[0x8];
3719         u8         wol_mode[0x8];
3720
3721         u8         reserved_2[0x20];
3722 };
3723
3724 struct mlx5_ifc_query_wol_rol_in_bits {
3725         u8         opcode[0x10];
3726         u8         reserved_0[0x10];
3727
3728         u8         reserved_1[0x10];
3729         u8         op_mod[0x10];
3730
3731         u8         reserved_2[0x40];
3732 };
3733
3734 enum {
3735         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3736         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3737 };
3738
3739 struct mlx5_ifc_query_vport_state_out_bits {
3740         u8         status[0x8];
3741         u8         reserved_0[0x18];
3742
3743         u8         syndrome[0x20];
3744
3745         u8         reserved_1[0x20];
3746
3747         u8         reserved_2[0x18];
3748         u8         admin_state[0x4];
3749         u8         state[0x4];
3750 };
3751
3752 enum {
3753         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3754         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3755         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3756 };
3757
3758 struct mlx5_ifc_query_vport_state_in_bits {
3759         u8         opcode[0x10];
3760         u8         reserved_0[0x10];
3761
3762         u8         reserved_1[0x10];
3763         u8         op_mod[0x10];
3764
3765         u8         other_vport[0x1];
3766         u8         reserved_2[0xf];
3767         u8         vport_number[0x10];
3768
3769         u8         reserved_3[0x20];
3770 };
3771
3772 struct mlx5_ifc_query_vport_counter_out_bits {
3773         u8         status[0x8];
3774         u8         reserved_0[0x18];
3775
3776         u8         syndrome[0x20];
3777
3778         u8         reserved_1[0x40];
3779
3780         struct mlx5_ifc_traffic_counter_bits received_errors;
3781
3782         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3783
3784         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3785
3786         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3787
3788         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3789
3790         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3791
3792         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3793
3794         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3795
3796         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3797
3798         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3799
3800         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3801
3802         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3803
3804         u8         reserved_2[0xa00];
3805 };
3806
3807 enum {
3808         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3809 };
3810
3811 struct mlx5_ifc_query_vport_counter_in_bits {
3812         u8         opcode[0x10];
3813         u8         reserved_0[0x10];
3814
3815         u8         reserved_1[0x10];
3816         u8         op_mod[0x10];
3817
3818         u8         other_vport[0x1];
3819         u8         reserved_2[0xb];
3820         u8         port_num[0x4];
3821         u8         vport_number[0x10];
3822
3823         u8         reserved_3[0x60];
3824
3825         u8         clear[0x1];
3826         u8         reserved_4[0x1f];
3827
3828         u8         reserved_5[0x20];
3829 };
3830
3831 struct mlx5_ifc_query_tis_out_bits {
3832         u8         status[0x8];
3833         u8         reserved_0[0x18];
3834
3835         u8         syndrome[0x20];
3836
3837         u8         reserved_1[0x40];
3838
3839         struct mlx5_ifc_tisc_bits tis_context;
3840 };
3841
3842 struct mlx5_ifc_query_tis_in_bits {
3843         u8         opcode[0x10];
3844         u8         reserved_0[0x10];
3845
3846         u8         reserved_1[0x10];
3847         u8         op_mod[0x10];
3848
3849         u8         reserved_2[0x8];
3850         u8         tisn[0x18];
3851
3852         u8         reserved_3[0x20];
3853 };
3854
3855 struct mlx5_ifc_query_tir_out_bits {
3856         u8         status[0x8];
3857         u8         reserved_0[0x18];
3858
3859         u8         syndrome[0x20];
3860
3861         u8         reserved_1[0xc0];
3862
3863         struct mlx5_ifc_tirc_bits tir_context;
3864 };
3865
3866 struct mlx5_ifc_query_tir_in_bits {
3867         u8         opcode[0x10];
3868         u8         reserved_0[0x10];
3869
3870         u8         reserved_1[0x10];
3871         u8         op_mod[0x10];
3872
3873         u8         reserved_2[0x8];
3874         u8         tirn[0x18];
3875
3876         u8         reserved_3[0x20];
3877 };
3878
3879 struct mlx5_ifc_query_srq_out_bits {
3880         u8         status[0x8];
3881         u8         reserved_0[0x18];
3882
3883         u8         syndrome[0x20];
3884
3885         u8         reserved_1[0x40];
3886
3887         struct mlx5_ifc_srqc_bits srq_context_entry;
3888
3889         u8         reserved_2[0x600];
3890
3891         u8         pas[0][0x40];
3892 };
3893
3894 struct mlx5_ifc_query_srq_in_bits {
3895         u8         opcode[0x10];
3896         u8         reserved_0[0x10];
3897
3898         u8         reserved_1[0x10];
3899         u8         op_mod[0x10];
3900
3901         u8         reserved_2[0x8];
3902         u8         srqn[0x18];
3903
3904         u8         reserved_3[0x20];
3905 };
3906
3907 struct mlx5_ifc_query_sq_out_bits {
3908         u8         status[0x8];
3909         u8         reserved_0[0x18];
3910
3911         u8         syndrome[0x20];
3912
3913         u8         reserved_1[0xc0];
3914
3915         struct mlx5_ifc_sqc_bits sq_context;
3916 };
3917
3918 struct mlx5_ifc_query_sq_in_bits {
3919         u8         opcode[0x10];
3920         u8         reserved_0[0x10];
3921
3922         u8         reserved_1[0x10];
3923         u8         op_mod[0x10];
3924
3925         u8         reserved_2[0x8];
3926         u8         sqn[0x18];
3927
3928         u8         reserved_3[0x20];
3929 };
3930
3931 struct mlx5_ifc_query_special_contexts_out_bits {
3932         u8         status[0x8];
3933         u8         reserved_0[0x18];
3934
3935         u8         syndrome[0x20];
3936
3937         u8         reserved_1[0x20];
3938
3939         u8         resd_lkey[0x20];
3940 };
3941
3942 struct mlx5_ifc_query_special_contexts_in_bits {
3943         u8         opcode[0x10];
3944         u8         reserved_0[0x10];
3945
3946         u8         reserved_1[0x10];
3947         u8         op_mod[0x10];
3948
3949         u8         reserved_2[0x40];
3950 };
3951
3952 struct mlx5_ifc_query_scheduling_element_out_bits {
3953         u8         status[0x8];
3954         u8         reserved_at_8[0x18];
3955
3956         u8         syndrome[0x20];
3957
3958         u8         reserved_at_40[0xc0];
3959
3960         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3961
3962         u8         reserved_at_300[0x100];
3963 };
3964
3965 enum {
3966         MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
3967 };
3968
3969 struct mlx5_ifc_query_scheduling_element_in_bits {
3970         u8         opcode[0x10];
3971         u8         reserved_at_10[0x10];
3972
3973         u8         reserved_at_20[0x10];
3974         u8         op_mod[0x10];
3975
3976         u8         scheduling_hierarchy[0x8];
3977         u8         reserved_at_48[0x18];
3978
3979         u8         scheduling_element_id[0x20];
3980
3981         u8         reserved_at_80[0x180];
3982 };
3983
3984 struct mlx5_ifc_query_rqt_out_bits {
3985         u8         status[0x8];
3986         u8         reserved_0[0x18];
3987
3988         u8         syndrome[0x20];
3989
3990         u8         reserved_1[0xc0];
3991
3992         struct mlx5_ifc_rqtc_bits rqt_context;
3993 };
3994
3995 struct mlx5_ifc_query_rqt_in_bits {
3996         u8         opcode[0x10];
3997         u8         reserved_0[0x10];
3998
3999         u8         reserved_1[0x10];
4000         u8         op_mod[0x10];
4001
4002         u8         reserved_2[0x8];
4003         u8         rqtn[0x18];
4004
4005         u8         reserved_3[0x20];
4006 };
4007
4008 struct mlx5_ifc_query_rq_out_bits {
4009         u8         status[0x8];
4010         u8         reserved_0[0x18];
4011
4012         u8         syndrome[0x20];
4013
4014         u8         reserved_1[0xc0];
4015
4016         struct mlx5_ifc_rqc_bits rq_context;
4017 };
4018
4019 struct mlx5_ifc_query_rq_in_bits {
4020         u8         opcode[0x10];
4021         u8         reserved_0[0x10];
4022
4023         u8         reserved_1[0x10];
4024         u8         op_mod[0x10];
4025
4026         u8         reserved_2[0x8];
4027         u8         rqn[0x18];
4028
4029         u8         reserved_3[0x20];
4030 };
4031
4032 struct mlx5_ifc_query_roce_address_out_bits {
4033         u8         status[0x8];
4034         u8         reserved_0[0x18];
4035
4036         u8         syndrome[0x20];
4037
4038         u8         reserved_1[0x40];
4039
4040         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4041 };
4042
4043 struct mlx5_ifc_query_roce_address_in_bits {
4044         u8         opcode[0x10];
4045         u8         reserved_0[0x10];
4046
4047         u8         reserved_1[0x10];
4048         u8         op_mod[0x10];
4049
4050         u8         roce_address_index[0x10];
4051         u8         reserved_2[0x10];
4052
4053         u8         reserved_3[0x20];
4054 };
4055
4056 struct mlx5_ifc_query_rmp_out_bits {
4057         u8         status[0x8];
4058         u8         reserved_0[0x18];
4059
4060         u8         syndrome[0x20];
4061
4062         u8         reserved_1[0xc0];
4063
4064         struct mlx5_ifc_rmpc_bits rmp_context;
4065 };
4066
4067 struct mlx5_ifc_query_rmp_in_bits {
4068         u8         opcode[0x10];
4069         u8         reserved_0[0x10];
4070
4071         u8         reserved_1[0x10];
4072         u8         op_mod[0x10];
4073
4074         u8         reserved_2[0x8];
4075         u8         rmpn[0x18];
4076
4077         u8         reserved_3[0x20];
4078 };
4079
4080 struct mlx5_ifc_query_rdb_out_bits {
4081         u8         status[0x8];
4082         u8         reserved_0[0x18];
4083
4084         u8         syndrome[0x20];
4085
4086         u8         reserved_1[0x20];
4087
4088         u8         reserved_2[0x18];
4089         u8         rdb_list_size[0x8];
4090
4091         struct mlx5_ifc_rdbc_bits rdb_context[0];
4092 };
4093
4094 struct mlx5_ifc_query_rdb_in_bits {
4095         u8         opcode[0x10];
4096         u8         reserved_0[0x10];
4097
4098         u8         reserved_1[0x10];
4099         u8         op_mod[0x10];
4100
4101         u8         reserved_2[0x8];
4102         u8         qpn[0x18];
4103
4104         u8         reserved_3[0x20];
4105 };
4106
4107 struct mlx5_ifc_query_qp_out_bits {
4108         u8         status[0x8];
4109         u8         reserved_0[0x18];
4110
4111         u8         syndrome[0x20];
4112
4113         u8         reserved_1[0x40];
4114
4115         u8         opt_param_mask[0x20];
4116
4117         u8         reserved_2[0x20];
4118
4119         struct mlx5_ifc_qpc_bits qpc;
4120
4121         u8         reserved_3[0x80];
4122
4123         u8         pas[0][0x40];
4124 };
4125
4126 struct mlx5_ifc_query_qp_in_bits {
4127         u8         opcode[0x10];
4128         u8         reserved_0[0x10];
4129
4130         u8         reserved_1[0x10];
4131         u8         op_mod[0x10];
4132
4133         u8         reserved_2[0x8];
4134         u8         qpn[0x18];
4135
4136         u8         reserved_3[0x20];
4137 };
4138
4139 struct mlx5_ifc_query_q_counter_out_bits {
4140         u8         status[0x8];
4141         u8         reserved_0[0x18];
4142
4143         u8         syndrome[0x20];
4144
4145         u8         reserved_1[0x40];
4146
4147         u8         rx_write_requests[0x20];
4148
4149         u8         reserved_2[0x20];
4150
4151         u8         rx_read_requests[0x20];
4152
4153         u8         reserved_3[0x20];
4154
4155         u8         rx_atomic_requests[0x20];
4156
4157         u8         reserved_4[0x20];
4158
4159         u8         rx_dct_connect[0x20];
4160
4161         u8         reserved_5[0x20];
4162
4163         u8         out_of_buffer[0x20];
4164
4165         u8         reserved_7[0x20];
4166
4167         u8         out_of_sequence[0x20];
4168
4169         u8         reserved_8[0x20];
4170
4171         u8         duplicate_request[0x20];
4172
4173         u8         reserved_9[0x20];
4174
4175         u8         rnr_nak_retry_err[0x20];
4176
4177         u8         reserved_10[0x20];
4178
4179         u8         packet_seq_err[0x20];
4180
4181         u8         reserved_11[0x20];
4182
4183         u8         implied_nak_seq_err[0x20];
4184
4185         u8         reserved_12[0x20];
4186
4187         u8         local_ack_timeout_err[0x20];
4188
4189         u8         reserved_13[0x20];
4190
4191         u8         resp_rnr_nak[0x20];
4192
4193         u8         reserved_14[0x20];
4194
4195         u8         req_rnr_retries_exceeded[0x20];
4196
4197         u8         reserved_15[0x460];
4198 };
4199
4200 struct mlx5_ifc_query_q_counter_in_bits {
4201         u8         opcode[0x10];
4202         u8         reserved_0[0x10];
4203
4204         u8         reserved_1[0x10];
4205         u8         op_mod[0x10];
4206
4207         u8         reserved_2[0x80];
4208
4209         u8         clear[0x1];
4210         u8         reserved_3[0x1f];
4211
4212         u8         reserved_4[0x18];
4213         u8         counter_set_id[0x8];
4214 };
4215
4216 struct mlx5_ifc_query_pages_out_bits {
4217         u8         status[0x8];
4218         u8         reserved_0[0x18];
4219
4220         u8         syndrome[0x20];
4221
4222         u8         reserved_1[0x10];
4223         u8         function_id[0x10];
4224
4225         u8         num_pages[0x20];
4226 };
4227
4228 enum {
4229         MLX5_BOOT_PAGES                           = 0x1,
4230         MLX5_INIT_PAGES                           = 0x2,
4231         MLX5_POST_INIT_PAGES                      = 0x3,
4232 };
4233
4234 struct mlx5_ifc_query_pages_in_bits {
4235         u8         opcode[0x10];
4236         u8         reserved_0[0x10];
4237
4238         u8         reserved_1[0x10];
4239         u8         op_mod[0x10];
4240
4241         u8         reserved_2[0x10];
4242         u8         function_id[0x10];
4243
4244         u8         reserved_3[0x20];
4245 };
4246
4247 struct mlx5_ifc_query_nic_vport_context_out_bits {
4248         u8         status[0x8];
4249         u8         reserved_0[0x18];
4250
4251         u8         syndrome[0x20];
4252
4253         u8         reserved_1[0x40];
4254
4255         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4256 };
4257
4258 struct mlx5_ifc_query_nic_vport_context_in_bits {
4259         u8         opcode[0x10];
4260         u8         reserved_0[0x10];
4261
4262         u8         reserved_1[0x10];
4263         u8         op_mod[0x10];
4264
4265         u8         other_vport[0x1];
4266         u8         reserved_2[0xf];
4267         u8         vport_number[0x10];
4268
4269         u8         reserved_3[0x5];
4270         u8         allowed_list_type[0x3];
4271         u8         reserved_4[0x18];
4272 };
4273
4274 struct mlx5_ifc_query_mkey_out_bits {
4275         u8         status[0x8];
4276         u8         reserved_0[0x18];
4277
4278         u8         syndrome[0x20];
4279
4280         u8         reserved_1[0x40];
4281
4282         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4283
4284         u8         reserved_2[0x600];
4285
4286         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4287
4288         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4289 };
4290
4291 struct mlx5_ifc_query_mkey_in_bits {
4292         u8         opcode[0x10];
4293         u8         reserved_0[0x10];
4294
4295         u8         reserved_1[0x10];
4296         u8         op_mod[0x10];
4297
4298         u8         reserved_2[0x8];
4299         u8         mkey_index[0x18];
4300
4301         u8         pg_access[0x1];
4302         u8         reserved_3[0x1f];
4303 };
4304
4305 struct mlx5_ifc_query_mad_demux_out_bits {
4306         u8         status[0x8];
4307         u8         reserved_0[0x18];
4308
4309         u8         syndrome[0x20];
4310
4311         u8         reserved_1[0x40];
4312
4313         u8         mad_dumux_parameters_block[0x20];
4314 };
4315
4316 struct mlx5_ifc_query_mad_demux_in_bits {
4317         u8         opcode[0x10];
4318         u8         reserved_0[0x10];
4319
4320         u8         reserved_1[0x10];
4321         u8         op_mod[0x10];
4322
4323         u8         reserved_2[0x40];
4324 };
4325
4326 struct mlx5_ifc_query_l2_table_entry_out_bits {
4327         u8         status[0x8];
4328         u8         reserved_0[0x18];
4329
4330         u8         syndrome[0x20];
4331
4332         u8         reserved_1[0xa0];
4333
4334         u8         reserved_2[0x13];
4335         u8         vlan_valid[0x1];
4336         u8         vlan[0xc];
4337
4338         struct mlx5_ifc_mac_address_layout_bits mac_address;
4339
4340         u8         reserved_3[0xc0];
4341 };
4342
4343 struct mlx5_ifc_query_l2_table_entry_in_bits {
4344         u8         opcode[0x10];
4345         u8         reserved_0[0x10];
4346
4347         u8         reserved_1[0x10];
4348         u8         op_mod[0x10];
4349
4350         u8         reserved_2[0x60];
4351
4352         u8         reserved_3[0x8];
4353         u8         table_index[0x18];
4354
4355         u8         reserved_4[0x140];
4356 };
4357
4358 struct mlx5_ifc_query_issi_out_bits {
4359         u8         status[0x8];
4360         u8         reserved_0[0x18];
4361
4362         u8         syndrome[0x20];
4363
4364         u8         reserved_1[0x10];
4365         u8         current_issi[0x10];
4366
4367         u8         reserved_2[0xa0];
4368
4369         u8         supported_issi_reserved[76][0x8];
4370         u8         supported_issi_dw0[0x20];
4371 };
4372
4373 struct mlx5_ifc_query_issi_in_bits {
4374         u8         opcode[0x10];
4375         u8         reserved_0[0x10];
4376
4377         u8         reserved_1[0x10];
4378         u8         op_mod[0x10];
4379
4380         u8         reserved_2[0x40];
4381 };
4382
4383 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4384         u8         status[0x8];
4385         u8         reserved_0[0x18];
4386
4387         u8         syndrome[0x20];
4388
4389         u8         reserved_1[0x40];
4390
4391         struct mlx5_ifc_pkey_bits pkey[0];
4392 };
4393
4394 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4395         u8         opcode[0x10];
4396         u8         reserved_0[0x10];
4397
4398         u8         reserved_1[0x10];
4399         u8         op_mod[0x10];
4400
4401         u8         other_vport[0x1];
4402         u8         reserved_2[0xb];
4403         u8         port_num[0x4];
4404         u8         vport_number[0x10];
4405
4406         u8         reserved_3[0x10];
4407         u8         pkey_index[0x10];
4408 };
4409
4410 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4411         u8         status[0x8];
4412         u8         reserved_0[0x18];
4413
4414         u8         syndrome[0x20];
4415
4416         u8         reserved_1[0x20];
4417
4418         u8         gids_num[0x10];
4419         u8         reserved_2[0x10];
4420
4421         struct mlx5_ifc_array128_auto_bits gid[0];
4422 };
4423
4424 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4425         u8         opcode[0x10];
4426         u8         reserved_0[0x10];
4427
4428         u8         reserved_1[0x10];
4429         u8         op_mod[0x10];
4430
4431         u8         other_vport[0x1];
4432         u8         reserved_2[0xb];
4433         u8         port_num[0x4];
4434         u8         vport_number[0x10];
4435
4436         u8         reserved_3[0x10];
4437         u8         gid_index[0x10];
4438 };
4439
4440 struct mlx5_ifc_query_hca_vport_context_out_bits {
4441         u8         status[0x8];
4442         u8         reserved_0[0x18];
4443
4444         u8         syndrome[0x20];
4445
4446         u8         reserved_1[0x40];
4447
4448         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4449 };
4450
4451 struct mlx5_ifc_query_hca_vport_context_in_bits {
4452         u8         opcode[0x10];
4453         u8         reserved_0[0x10];
4454
4455         u8         reserved_1[0x10];
4456         u8         op_mod[0x10];
4457
4458         u8         other_vport[0x1];
4459         u8         reserved_2[0xb];
4460         u8         port_num[0x4];
4461         u8         vport_number[0x10];
4462
4463         u8         reserved_3[0x20];
4464 };
4465
4466 struct mlx5_ifc_query_hca_cap_out_bits {
4467         u8         status[0x8];
4468         u8         reserved_0[0x18];
4469
4470         u8         syndrome[0x20];
4471
4472         u8         reserved_1[0x40];
4473
4474         union mlx5_ifc_hca_cap_union_bits capability;
4475 };
4476
4477 struct mlx5_ifc_query_hca_cap_in_bits {
4478         u8         opcode[0x10];
4479         u8         reserved_0[0x10];
4480
4481         u8         reserved_1[0x10];
4482         u8         op_mod[0x10];
4483
4484         u8         reserved_2[0x40];
4485 };
4486
4487 struct mlx5_ifc_query_flow_table_out_bits {
4488         u8         status[0x8];
4489         u8         reserved_0[0x18];
4490
4491         u8         syndrome[0x20];
4492
4493         u8         reserved_1[0x80];
4494
4495         u8         reserved_2[0x8];
4496         u8         level[0x8];
4497         u8         reserved_3[0x8];
4498         u8         log_size[0x8];
4499
4500         u8         reserved_4[0x120];
4501 };
4502
4503 struct mlx5_ifc_query_flow_table_in_bits {
4504         u8         opcode[0x10];
4505         u8         reserved_0[0x10];
4506
4507         u8         reserved_1[0x10];
4508         u8         op_mod[0x10];
4509
4510         u8         other_vport[0x1];
4511         u8         reserved_2[0xf];
4512         u8         vport_number[0x10];
4513
4514         u8         reserved_3[0x20];
4515
4516         u8         table_type[0x8];
4517         u8         reserved_4[0x18];
4518
4519         u8         reserved_5[0x8];
4520         u8         table_id[0x18];
4521
4522         u8         reserved_6[0x140];
4523 };
4524
4525 struct mlx5_ifc_query_fte_out_bits {
4526         u8         status[0x8];
4527         u8         reserved_0[0x18];
4528
4529         u8         syndrome[0x20];
4530
4531         u8         reserved_1[0x1c0];
4532
4533         struct mlx5_ifc_flow_context_bits flow_context;
4534 };
4535
4536 struct mlx5_ifc_query_fte_in_bits {
4537         u8         opcode[0x10];
4538         u8         reserved_0[0x10];
4539
4540         u8         reserved_1[0x10];
4541         u8         op_mod[0x10];
4542
4543         u8         other_vport[0x1];
4544         u8         reserved_2[0xf];
4545         u8         vport_number[0x10];
4546
4547         u8         reserved_3[0x20];
4548
4549         u8         table_type[0x8];
4550         u8         reserved_4[0x18];
4551
4552         u8         reserved_5[0x8];
4553         u8         table_id[0x18];
4554
4555         u8         reserved_6[0x40];
4556
4557         u8         flow_index[0x20];
4558
4559         u8         reserved_7[0xe0];
4560 };
4561
4562 enum {
4563         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4564         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4565         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4566 };
4567
4568 struct mlx5_ifc_query_flow_group_out_bits {
4569         u8         status[0x8];
4570         u8         reserved_0[0x18];
4571
4572         u8         syndrome[0x20];
4573
4574         u8         reserved_1[0xa0];
4575
4576         u8         start_flow_index[0x20];
4577
4578         u8         reserved_2[0x20];
4579
4580         u8         end_flow_index[0x20];
4581
4582         u8         reserved_3[0xa0];
4583
4584         u8         reserved_4[0x18];
4585         u8         match_criteria_enable[0x8];
4586
4587         struct mlx5_ifc_fte_match_param_bits match_criteria;
4588
4589         u8         reserved_5[0xe00];
4590 };
4591
4592 struct mlx5_ifc_query_flow_group_in_bits {
4593         u8         opcode[0x10];
4594         u8         reserved_0[0x10];
4595
4596         u8         reserved_1[0x10];
4597         u8         op_mod[0x10];
4598
4599         u8         other_vport[0x1];
4600         u8         reserved_2[0xf];
4601         u8         vport_number[0x10];
4602
4603         u8         reserved_3[0x20];
4604
4605         u8         table_type[0x8];
4606         u8         reserved_4[0x18];
4607
4608         u8         reserved_5[0x8];
4609         u8         table_id[0x18];
4610
4611         u8         group_id[0x20];
4612
4613         u8         reserved_6[0x120];
4614 };
4615
4616 struct mlx5_ifc_query_flow_counter_out_bits {
4617         u8         status[0x8];
4618         u8         reserved_0[0x18];
4619
4620         u8         syndrome[0x20];
4621
4622         u8         reserved_1[0x40];
4623
4624         struct mlx5_ifc_traffic_counter_bits flow_statistics;
4625
4626         u8         reserved_2[0x700];
4627 };
4628
4629 struct mlx5_ifc_query_flow_counter_in_bits {
4630         u8         opcode[0x10];
4631         u8         reserved_0[0x10];
4632
4633         u8         reserved_1[0x10];
4634         u8         op_mod[0x10];
4635
4636         u8         reserved_2[0x80];
4637
4638         u8         clear[0x1];
4639         u8         reserved_3[0x1f];
4640
4641         u8         reserved_4[0x10];
4642         u8         flow_counter_id[0x10];
4643 };
4644
4645 struct mlx5_ifc_query_esw_vport_context_out_bits {
4646         u8         status[0x8];
4647         u8         reserved_0[0x18];
4648
4649         u8         syndrome[0x20];
4650
4651         u8         reserved_1[0x40];
4652
4653         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4654 };
4655
4656 struct mlx5_ifc_query_esw_vport_context_in_bits {
4657         u8         opcode[0x10];
4658         u8         reserved_0[0x10];
4659
4660         u8         reserved_1[0x10];
4661         u8         op_mod[0x10];
4662
4663         u8         other_vport[0x1];
4664         u8         reserved_2[0xf];
4665         u8         vport_number[0x10];
4666
4667         u8         reserved_3[0x20];
4668 };
4669
4670 struct mlx5_ifc_query_eq_out_bits {
4671         u8         status[0x8];
4672         u8         reserved_0[0x18];
4673
4674         u8         syndrome[0x20];
4675
4676         u8         reserved_1[0x40];
4677
4678         struct mlx5_ifc_eqc_bits eq_context_entry;
4679
4680         u8         reserved_2[0x40];
4681
4682         u8         event_bitmask[0x40];
4683
4684         u8         reserved_3[0x580];
4685
4686         u8         pas[0][0x40];
4687 };
4688
4689 struct mlx5_ifc_query_eq_in_bits {
4690         u8         opcode[0x10];
4691         u8         reserved_0[0x10];
4692
4693         u8         reserved_1[0x10];
4694         u8         op_mod[0x10];
4695
4696         u8         reserved_2[0x18];
4697         u8         eq_number[0x8];
4698
4699         u8         reserved_3[0x20];
4700 };
4701
4702 struct mlx5_ifc_query_dct_out_bits {
4703         u8         status[0x8];
4704         u8         reserved_0[0x18];
4705
4706         u8         syndrome[0x20];
4707
4708         u8         reserved_1[0x40];
4709
4710         struct mlx5_ifc_dctc_bits dct_context_entry;
4711
4712         u8         reserved_2[0x180];
4713 };
4714
4715 struct mlx5_ifc_query_dct_in_bits {
4716         u8         opcode[0x10];
4717         u8         reserved_0[0x10];
4718
4719         u8         reserved_1[0x10];
4720         u8         op_mod[0x10];
4721
4722         u8         reserved_2[0x8];
4723         u8         dctn[0x18];
4724
4725         u8         reserved_3[0x20];
4726 };
4727
4728 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4729         u8         status[0x8];
4730         u8         reserved_0[0x18];
4731
4732         u8         syndrome[0x20];
4733
4734         u8         enable[0x1];
4735         u8         reserved_1[0x1f];
4736
4737         u8         reserved_2[0x160];
4738
4739         struct mlx5_ifc_cmd_pas_bits pas;
4740 };
4741
4742 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_0[0x10];
4745
4746         u8         reserved_1[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_2[0x40];
4750 };
4751
4752 struct mlx5_ifc_query_cq_out_bits {
4753         u8         status[0x8];
4754         u8         reserved_0[0x18];
4755
4756         u8         syndrome[0x20];
4757
4758         u8         reserved_1[0x40];
4759
4760         struct mlx5_ifc_cqc_bits cq_context;
4761
4762         u8         reserved_2[0x600];
4763
4764         u8         pas[0][0x40];
4765 };
4766
4767 struct mlx5_ifc_query_cq_in_bits {
4768         u8         opcode[0x10];
4769         u8         reserved_0[0x10];
4770
4771         u8         reserved_1[0x10];
4772         u8         op_mod[0x10];
4773
4774         u8         reserved_2[0x8];
4775         u8         cqn[0x18];
4776
4777         u8         reserved_3[0x20];
4778 };
4779
4780 struct mlx5_ifc_query_cong_status_out_bits {
4781         u8         status[0x8];
4782         u8         reserved_0[0x18];
4783
4784         u8         syndrome[0x20];
4785
4786         u8         reserved_1[0x20];
4787
4788         u8         enable[0x1];
4789         u8         tag_enable[0x1];
4790         u8         reserved_2[0x1e];
4791 };
4792
4793 struct mlx5_ifc_query_cong_status_in_bits {
4794         u8         opcode[0x10];
4795         u8         reserved_0[0x10];
4796
4797         u8         reserved_1[0x10];
4798         u8         op_mod[0x10];
4799
4800         u8         reserved_2[0x18];
4801         u8         priority[0x4];
4802         u8         cong_protocol[0x4];
4803
4804         u8         reserved_3[0x20];
4805 };
4806
4807 struct mlx5_ifc_query_cong_statistics_out_bits {
4808         u8         status[0x8];
4809         u8         reserved_0[0x18];
4810
4811         u8         syndrome[0x20];
4812
4813         u8         reserved_1[0x40];
4814
4815         u8         cur_flows[0x20];
4816
4817         u8         sum_flows[0x20];
4818
4819         u8         cnp_ignored_high[0x20];
4820
4821         u8         cnp_ignored_low[0x20];
4822
4823         u8         cnp_handled_high[0x20];
4824
4825         u8         cnp_handled_low[0x20];
4826
4827         u8         reserved_2[0x100];
4828
4829         u8         time_stamp_high[0x20];
4830
4831         u8         time_stamp_low[0x20];
4832
4833         u8         accumulators_period[0x20];
4834
4835         u8         ecn_marked_roce_packets_high[0x20];
4836
4837         u8         ecn_marked_roce_packets_low[0x20];
4838
4839         u8         cnps_sent_high[0x20];
4840
4841         u8         cnps_sent_low[0x20];
4842
4843         u8         reserved_3[0x560];
4844 };
4845
4846 struct mlx5_ifc_query_cong_statistics_in_bits {
4847         u8         opcode[0x10];
4848         u8         reserved_0[0x10];
4849
4850         u8         reserved_1[0x10];
4851         u8         op_mod[0x10];
4852
4853         u8         clear[0x1];
4854         u8         reserved_2[0x1f];
4855
4856         u8         reserved_3[0x20];
4857 };
4858
4859 struct mlx5_ifc_query_cong_params_out_bits {
4860         u8         status[0x8];
4861         u8         reserved_0[0x18];
4862
4863         u8         syndrome[0x20];
4864
4865         u8         reserved_1[0x40];
4866
4867         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4868 };
4869
4870 struct mlx5_ifc_query_cong_params_in_bits {
4871         u8         opcode[0x10];
4872         u8         reserved_0[0x10];
4873
4874         u8         reserved_1[0x10];
4875         u8         op_mod[0x10];
4876
4877         u8         reserved_2[0x1c];
4878         u8         cong_protocol[0x4];
4879
4880         u8         reserved_3[0x20];
4881 };
4882
4883 struct mlx5_ifc_query_burst_size_out_bits {
4884         u8         status[0x8];
4885         u8         reserved_0[0x18];
4886
4887         u8         syndrome[0x20];
4888
4889         u8         reserved_1[0x20];
4890
4891         u8         reserved_2[0x9];
4892         u8         device_burst_size[0x17];
4893 };
4894
4895 struct mlx5_ifc_query_burst_size_in_bits {
4896         u8         opcode[0x10];
4897         u8         reserved_0[0x10];
4898
4899         u8         reserved_1[0x10];
4900         u8         op_mod[0x10];
4901
4902         u8         reserved_2[0x40];
4903 };
4904
4905 struct mlx5_ifc_query_adapter_out_bits {
4906         u8         status[0x8];
4907         u8         reserved_0[0x18];
4908
4909         u8         syndrome[0x20];
4910
4911         u8         reserved_1[0x40];
4912
4913         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4914 };
4915
4916 struct mlx5_ifc_query_adapter_in_bits {
4917         u8         opcode[0x10];
4918         u8         reserved_0[0x10];
4919
4920         u8         reserved_1[0x10];
4921         u8         op_mod[0x10];
4922
4923         u8         reserved_2[0x40];
4924 };
4925
4926 struct mlx5_ifc_qp_2rst_out_bits {
4927         u8         status[0x8];
4928         u8         reserved_0[0x18];
4929
4930         u8         syndrome[0x20];
4931
4932         u8         reserved_1[0x40];
4933 };
4934
4935 struct mlx5_ifc_qp_2rst_in_bits {
4936         u8         opcode[0x10];
4937         u8         reserved_0[0x10];
4938
4939         u8         reserved_1[0x10];
4940         u8         op_mod[0x10];
4941
4942         u8         reserved_2[0x8];
4943         u8         qpn[0x18];
4944
4945         u8         reserved_3[0x20];
4946 };
4947
4948 struct mlx5_ifc_qp_2err_out_bits {
4949         u8         status[0x8];
4950         u8         reserved_0[0x18];
4951
4952         u8         syndrome[0x20];
4953
4954         u8         reserved_1[0x40];
4955 };
4956
4957 struct mlx5_ifc_qp_2err_in_bits {
4958         u8         opcode[0x10];
4959         u8         reserved_0[0x10];
4960
4961         u8         reserved_1[0x10];
4962         u8         op_mod[0x10];
4963
4964         u8         reserved_2[0x8];
4965         u8         qpn[0x18];
4966
4967         u8         reserved_3[0x20];
4968 };
4969
4970 struct mlx5_ifc_para_vport_element_bits {
4971         u8         reserved_at_0[0xc];
4972         u8         traffic_class[0x4];
4973         u8         qos_para_vport_number[0x10];
4974 };
4975
4976 struct mlx5_ifc_page_fault_resume_out_bits {
4977         u8         status[0x8];
4978         u8         reserved_0[0x18];
4979
4980         u8         syndrome[0x20];
4981
4982         u8         reserved_1[0x40];
4983 };
4984
4985 struct mlx5_ifc_page_fault_resume_in_bits {
4986         u8         opcode[0x10];
4987         u8         reserved_0[0x10];
4988
4989         u8         reserved_1[0x10];
4990         u8         op_mod[0x10];
4991
4992         u8         error[0x1];
4993         u8         reserved_2[0x4];
4994         u8         rdma[0x1];
4995         u8         read_write[0x1];
4996         u8         req_res[0x1];
4997         u8         qpn[0x18];
4998
4999         u8         reserved_3[0x20];
5000 };
5001
5002 struct mlx5_ifc_nop_out_bits {
5003         u8         status[0x8];
5004         u8         reserved_0[0x18];
5005
5006         u8         syndrome[0x20];
5007
5008         u8         reserved_1[0x40];
5009 };
5010
5011 struct mlx5_ifc_nop_in_bits {
5012         u8         opcode[0x10];
5013         u8         reserved_0[0x10];
5014
5015         u8         reserved_1[0x10];
5016         u8         op_mod[0x10];
5017
5018         u8         reserved_2[0x40];
5019 };
5020
5021 struct mlx5_ifc_modify_vport_state_out_bits {
5022         u8         status[0x8];
5023         u8         reserved_0[0x18];
5024
5025         u8         syndrome[0x20];
5026
5027         u8         reserved_1[0x40];
5028 };
5029
5030 enum {
5031         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5032         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5033         MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5034 };
5035
5036 enum {
5037         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5038         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5039         MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5040 };
5041
5042 struct mlx5_ifc_modify_vport_state_in_bits {
5043         u8         opcode[0x10];
5044         u8         reserved_0[0x10];
5045
5046         u8         reserved_1[0x10];
5047         u8         op_mod[0x10];
5048
5049         u8         other_vport[0x1];
5050         u8         reserved_2[0xf];
5051         u8         vport_number[0x10];
5052
5053         u8         reserved_3[0x18];
5054         u8         admin_state[0x4];
5055         u8         reserved_4[0x4];
5056 };
5057
5058 struct mlx5_ifc_modify_tis_out_bits {
5059         u8         status[0x8];
5060         u8         reserved_0[0x18];
5061
5062         u8         syndrome[0x20];
5063
5064         u8         reserved_1[0x40];
5065 };
5066
5067 struct mlx5_ifc_modify_tis_in_bits {
5068         u8         opcode[0x10];
5069         u8         reserved_0[0x10];
5070
5071         u8         reserved_1[0x10];
5072         u8         op_mod[0x10];
5073
5074         u8         reserved_2[0x8];
5075         u8         tisn[0x18];
5076
5077         u8         reserved_3[0x20];
5078
5079         u8         modify_bitmask[0x40];
5080
5081         u8         reserved_4[0x40];
5082
5083         struct mlx5_ifc_tisc_bits ctx;
5084 };
5085
5086 struct mlx5_ifc_modify_tir_out_bits {
5087         u8         status[0x8];
5088         u8         reserved_0[0x18];
5089
5090         u8         syndrome[0x20];
5091
5092         u8         reserved_1[0x40];
5093 };
5094
5095 enum
5096 {
5097         MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5098         MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =          0x1 << 1
5099 };
5100
5101 struct mlx5_ifc_modify_tir_in_bits {
5102         u8         opcode[0x10];
5103         u8         reserved_0[0x10];
5104
5105         u8         reserved_1[0x10];
5106         u8         op_mod[0x10];
5107
5108         u8         reserved_2[0x8];
5109         u8         tirn[0x18];
5110
5111         u8         reserved_3[0x20];
5112
5113         u8         modify_bitmask[0x40];
5114
5115         u8         reserved_4[0x40];
5116
5117         struct mlx5_ifc_tirc_bits tir_context;
5118 };
5119
5120 struct mlx5_ifc_modify_sq_out_bits {
5121         u8         status[0x8];
5122         u8         reserved_0[0x18];
5123
5124         u8         syndrome[0x20];
5125
5126         u8         reserved_1[0x40];
5127 };
5128
5129 struct mlx5_ifc_modify_sq_in_bits {
5130         u8         opcode[0x10];
5131         u8         reserved_0[0x10];
5132
5133         u8         reserved_1[0x10];
5134         u8         op_mod[0x10];
5135
5136         u8         sq_state[0x4];
5137         u8         reserved_2[0x4];
5138         u8         sqn[0x18];
5139
5140         u8         reserved_3[0x20];
5141
5142         u8         modify_bitmask[0x40];
5143
5144         u8         reserved_4[0x40];
5145
5146         struct mlx5_ifc_sqc_bits ctx;
5147 };
5148
5149 struct mlx5_ifc_modify_scheduling_element_out_bits {
5150         u8         status[0x8];
5151         u8         reserved_at_8[0x18];
5152
5153         u8         syndrome[0x20];
5154
5155         u8         reserved_at_40[0x1c0];
5156 };
5157
5158 enum {
5159         MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5160 };
5161
5162 enum {
5163         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5164         MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5165 };
5166
5167 struct mlx5_ifc_modify_scheduling_element_in_bits {
5168         u8         opcode[0x10];
5169         u8         reserved_at_10[0x10];
5170
5171         u8         reserved_at_20[0x10];
5172         u8         op_mod[0x10];
5173
5174         u8         scheduling_hierarchy[0x8];
5175         u8         reserved_at_48[0x18];
5176
5177         u8         scheduling_element_id[0x20];
5178
5179         u8         reserved_at_80[0x20];
5180
5181         u8         modify_bitmask[0x20];
5182
5183         u8         reserved_at_c0[0x40];
5184
5185         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5186
5187         u8         reserved_at_300[0x100];
5188 };
5189
5190 struct mlx5_ifc_modify_rqt_out_bits {
5191         u8         status[0x8];
5192         u8         reserved_0[0x18];
5193
5194         u8         syndrome[0x20];
5195
5196         u8         reserved_1[0x40];
5197 };
5198
5199 struct mlx5_ifc_modify_rqt_in_bits {
5200         u8         opcode[0x10];
5201         u8         reserved_0[0x10];
5202
5203         u8         reserved_1[0x10];
5204         u8         op_mod[0x10];
5205
5206         u8         reserved_2[0x8];
5207         u8         rqtn[0x18];
5208
5209         u8         reserved_3[0x20];
5210
5211         u8         modify_bitmask[0x40];
5212
5213         u8         reserved_4[0x40];
5214
5215         struct mlx5_ifc_rqtc_bits ctx;
5216 };
5217
5218 struct mlx5_ifc_modify_rq_out_bits {
5219         u8         status[0x8];
5220         u8         reserved_0[0x18];
5221
5222         u8         syndrome[0x20];
5223
5224         u8         reserved_1[0x40];
5225 };
5226
5227 struct mlx5_ifc_rq_bitmask_bits {
5228         u8         reserved[0x20];
5229
5230         u8         reserved1[0x1e];
5231         u8         vlan_strip_disable[0x1];
5232         u8         reserved2[0x1];
5233 };
5234
5235 struct mlx5_ifc_modify_rq_in_bits {
5236         u8         opcode[0x10];
5237         u8         reserved_0[0x10];
5238
5239         u8         reserved_1[0x10];
5240         u8         op_mod[0x10];
5241
5242         u8         rq_state[0x4];
5243         u8         reserved_2[0x4];
5244         u8         rqn[0x18];
5245
5246         u8         reserved_3[0x20];
5247
5248         struct mlx5_ifc_rq_bitmask_bits bitmask;
5249
5250         u8         reserved_4[0x40];
5251
5252         struct mlx5_ifc_rqc_bits ctx;
5253 };
5254
5255 struct mlx5_ifc_modify_rmp_out_bits {
5256         u8         status[0x8];
5257         u8         reserved_0[0x18];
5258
5259         u8         syndrome[0x20];
5260
5261         u8         reserved_1[0x40];
5262 };
5263
5264 struct mlx5_ifc_rmp_bitmask_bits {
5265         u8         reserved[0x20];
5266
5267         u8         reserved1[0x1f];
5268         u8         lwm[0x1];
5269 };
5270
5271 struct mlx5_ifc_modify_rmp_in_bits {
5272         u8         opcode[0x10];
5273         u8         reserved_0[0x10];
5274
5275         u8         reserved_1[0x10];
5276         u8         op_mod[0x10];
5277
5278         u8         rmp_state[0x4];
5279         u8         reserved_2[0x4];
5280         u8         rmpn[0x18];
5281
5282         u8         reserved_3[0x20];
5283
5284         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5285
5286         u8         reserved_4[0x40];
5287
5288         struct mlx5_ifc_rmpc_bits ctx;
5289 };
5290
5291 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5292         u8         status[0x8];
5293         u8         reserved_0[0x18];
5294
5295         u8         syndrome[0x20];
5296
5297         u8         reserved_1[0x40];
5298 };
5299
5300 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5301         u8         reserved_0[0x14];
5302         u8         disable_uc_local_lb[0x1];
5303         u8         disable_mc_local_lb[0x1];
5304         u8         node_guid[0x1];
5305         u8         port_guid[0x1];
5306         u8         min_wqe_inline_mode[0x1];
5307         u8         mtu[0x1];
5308         u8         change_event[0x1];
5309         u8         promisc[0x1];
5310         u8         permanent_address[0x1];
5311         u8         addresses_list[0x1];
5312         u8         roce_en[0x1];
5313         u8         reserved_1[0x1];
5314 };
5315
5316 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5317         u8         opcode[0x10];
5318         u8         reserved_0[0x10];
5319
5320         u8         reserved_1[0x10];
5321         u8         op_mod[0x10];
5322
5323         u8         other_vport[0x1];
5324         u8         reserved_2[0xf];
5325         u8         vport_number[0x10];
5326
5327         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5328
5329         u8         reserved_3[0x780];
5330
5331         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5332 };
5333
5334 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5335         u8         status[0x8];
5336         u8         reserved_0[0x18];
5337
5338         u8         syndrome[0x20];
5339
5340         u8         reserved_1[0x40];
5341 };
5342
5343 struct mlx5_ifc_grh_bits {
5344         u8      ip_version[4];
5345         u8      traffic_class[8];
5346         u8      flow_label[20];
5347         u8      payload_length[16];
5348         u8      next_header[8];
5349         u8      hop_limit[8];
5350         u8      sgid[128];
5351         u8      dgid[128];
5352 };
5353
5354 struct mlx5_ifc_bth_bits {
5355         u8      opcode[8];
5356         u8      se[1];
5357         u8      migreq[1];
5358         u8      pad_count[2];
5359         u8      tver[4];
5360         u8      p_key[16];
5361         u8      reserved8[8];
5362         u8      dest_qp[24];
5363         u8      ack_req[1];
5364         u8      reserved7[7];
5365         u8      psn[24];
5366 };
5367
5368 struct mlx5_ifc_aeth_bits {
5369         u8      syndrome[8];
5370         u8      msn[24];
5371 };
5372
5373 struct mlx5_ifc_dceth_bits {
5374         u8      reserved0[8];
5375         u8      session_id[24];
5376         u8      reserved1[8];
5377         u8      dci_dct[24];
5378 };
5379
5380 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5381         u8         opcode[0x10];
5382         u8         reserved_0[0x10];
5383
5384         u8         reserved_1[0x10];
5385         u8         op_mod[0x10];
5386
5387         u8         other_vport[0x1];
5388         u8         reserved_2[0xb];
5389         u8         port_num[0x4];
5390         u8         vport_number[0x10];
5391
5392         u8         reserved_3[0x20];
5393
5394         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5395 };
5396
5397 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5398         u8         status[0x8];
5399         u8         reserved_0[0x18];
5400
5401         u8         syndrome[0x20];
5402
5403         u8         reserved_1[0x40];
5404 };
5405
5406 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5407         u8         reserved[0x1c];
5408         u8         vport_cvlan_insert[0x1];
5409         u8         vport_svlan_insert[0x1];
5410         u8         vport_cvlan_strip[0x1];
5411         u8         vport_svlan_strip[0x1];
5412 };
5413
5414 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5415         u8         opcode[0x10];
5416         u8         reserved_0[0x10];
5417
5418         u8         reserved_1[0x10];
5419         u8         op_mod[0x10];
5420
5421         u8         other_vport[0x1];
5422         u8         reserved_2[0xf];
5423         u8         vport_number[0x10];
5424
5425         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5426
5427         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5428 };
5429
5430 struct mlx5_ifc_modify_cq_out_bits {
5431         u8         status[0x8];
5432         u8         reserved_0[0x18];
5433
5434         u8         syndrome[0x20];
5435
5436         u8         reserved_1[0x40];
5437 };
5438
5439 enum {
5440         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5441         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5442 };
5443
5444 struct mlx5_ifc_modify_cq_in_bits {
5445         u8         opcode[0x10];
5446         u8         reserved_0[0x10];
5447
5448         u8         reserved_1[0x10];
5449         u8         op_mod[0x10];
5450
5451         u8         reserved_2[0x8];
5452         u8         cqn[0x18];
5453
5454         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5455
5456         struct mlx5_ifc_cqc_bits cq_context;
5457
5458         u8         reserved_3[0x600];
5459
5460         u8         pas[0][0x40];
5461 };
5462
5463 struct mlx5_ifc_modify_cong_status_out_bits {
5464         u8         status[0x8];
5465         u8         reserved_0[0x18];
5466
5467         u8         syndrome[0x20];
5468
5469         u8         reserved_1[0x40];
5470 };
5471
5472 struct mlx5_ifc_modify_cong_status_in_bits {
5473         u8         opcode[0x10];
5474         u8         reserved_0[0x10];
5475
5476         u8         reserved_1[0x10];
5477         u8         op_mod[0x10];
5478
5479         u8         reserved_2[0x18];
5480         u8         priority[0x4];
5481         u8         cong_protocol[0x4];
5482
5483         u8         enable[0x1];
5484         u8         tag_enable[0x1];
5485         u8         reserved_3[0x1e];
5486 };
5487
5488 struct mlx5_ifc_modify_cong_params_out_bits {
5489         u8         status[0x8];
5490         u8         reserved_0[0x18];
5491
5492         u8         syndrome[0x20];
5493
5494         u8         reserved_1[0x40];
5495 };
5496
5497 struct mlx5_ifc_modify_cong_params_in_bits {
5498         u8         opcode[0x10];
5499         u8         reserved_0[0x10];
5500
5501         u8         reserved_1[0x10];
5502         u8         op_mod[0x10];
5503
5504         u8         reserved_2[0x1c];
5505         u8         cong_protocol[0x4];
5506
5507         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5508
5509         u8         reserved_3[0x80];
5510
5511         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5512 };
5513
5514 struct mlx5_ifc_manage_pages_out_bits {
5515         u8         status[0x8];
5516         u8         reserved_0[0x18];
5517
5518         u8         syndrome[0x20];
5519
5520         u8         output_num_entries[0x20];
5521
5522         u8         reserved_1[0x20];
5523
5524         u8         pas[0][0x40];
5525 };
5526
5527 enum {
5528         MLX5_PAGES_CANT_GIVE                            = 0x0,
5529         MLX5_PAGES_GIVE                                 = 0x1,
5530         MLX5_PAGES_TAKE                                 = 0x2,
5531 };
5532
5533 struct mlx5_ifc_manage_pages_in_bits {
5534         u8         opcode[0x10];
5535         u8         reserved_0[0x10];
5536
5537         u8         reserved_1[0x10];
5538         u8         op_mod[0x10];
5539
5540         u8         reserved_2[0x10];
5541         u8         function_id[0x10];
5542
5543         u8         input_num_entries[0x20];
5544
5545         u8         pas[0][0x40];
5546 };
5547
5548 struct mlx5_ifc_mad_ifc_out_bits {
5549         u8         status[0x8];
5550         u8         reserved_0[0x18];
5551
5552         u8         syndrome[0x20];
5553
5554         u8         reserved_1[0x40];
5555
5556         u8         response_mad_packet[256][0x8];
5557 };
5558
5559 struct mlx5_ifc_mad_ifc_in_bits {
5560         u8         opcode[0x10];
5561         u8         reserved_0[0x10];
5562
5563         u8         reserved_1[0x10];
5564         u8         op_mod[0x10];
5565
5566         u8         remote_lid[0x10];
5567         u8         reserved_2[0x8];
5568         u8         port[0x8];
5569
5570         u8         reserved_3[0x20];
5571
5572         u8         mad[256][0x8];
5573 };
5574
5575 struct mlx5_ifc_init_hca_out_bits {
5576         u8         status[0x8];
5577         u8         reserved_0[0x18];
5578
5579         u8         syndrome[0x20];
5580
5581         u8         reserved_1[0x40];
5582 };
5583
5584 enum {
5585         MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
5586         MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
5587 };
5588
5589 struct mlx5_ifc_init_hca_in_bits {
5590         u8         opcode[0x10];
5591         u8         reserved_0[0x10];
5592
5593         u8         reserved_1[0x10];
5594         u8         op_mod[0x10];
5595
5596         u8         reserved_2[0x40];
5597 };
5598
5599 struct mlx5_ifc_init2rtr_qp_out_bits {
5600         u8         status[0x8];
5601         u8         reserved_0[0x18];
5602
5603         u8         syndrome[0x20];
5604
5605         u8         reserved_1[0x40];
5606 };
5607
5608 struct mlx5_ifc_init2rtr_qp_in_bits {
5609         u8         opcode[0x10];
5610         u8         reserved_0[0x10];
5611
5612         u8         reserved_1[0x10];
5613         u8         op_mod[0x10];
5614
5615         u8         reserved_2[0x8];
5616         u8         qpn[0x18];
5617
5618         u8         reserved_3[0x20];
5619
5620         u8         opt_param_mask[0x20];
5621
5622         u8         reserved_4[0x20];
5623
5624         struct mlx5_ifc_qpc_bits qpc;
5625
5626         u8         reserved_5[0x80];
5627 };
5628
5629 struct mlx5_ifc_init2init_qp_out_bits {
5630         u8         status[0x8];
5631         u8         reserved_0[0x18];
5632
5633         u8         syndrome[0x20];
5634
5635         u8         reserved_1[0x40];
5636 };
5637
5638 struct mlx5_ifc_init2init_qp_in_bits {
5639         u8         opcode[0x10];
5640         u8         reserved_0[0x10];
5641
5642         u8         reserved_1[0x10];
5643         u8         op_mod[0x10];
5644
5645         u8         reserved_2[0x8];
5646         u8         qpn[0x18];
5647
5648         u8         reserved_3[0x20];
5649
5650         u8         opt_param_mask[0x20];
5651
5652         u8         reserved_4[0x20];
5653
5654         struct mlx5_ifc_qpc_bits qpc;
5655
5656         u8         reserved_5[0x80];
5657 };
5658
5659 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5660         u8         status[0x8];
5661         u8         reserved_0[0x18];
5662
5663         u8         syndrome[0x20];
5664
5665         u8         reserved_1[0x40];
5666
5667         u8         packet_headers_log[128][0x8];
5668
5669         u8         packet_syndrome[64][0x8];
5670 };
5671
5672 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5673         u8         opcode[0x10];
5674         u8         reserved_0[0x10];
5675
5676         u8         reserved_1[0x10];
5677         u8         op_mod[0x10];
5678
5679         u8         reserved_2[0x40];
5680 };
5681
5682 struct mlx5_ifc_gen_eqe_in_bits {
5683         u8         opcode[0x10];
5684         u8         reserved_0[0x10];
5685
5686         u8         reserved_1[0x10];
5687         u8         op_mod[0x10];
5688
5689         u8         reserved_2[0x18];
5690         u8         eq_number[0x8];
5691
5692         u8         reserved_3[0x20];
5693
5694         u8         eqe[64][0x8];
5695 };
5696
5697 struct mlx5_ifc_gen_eq_out_bits {
5698         u8         status[0x8];
5699         u8         reserved_0[0x18];
5700
5701         u8         syndrome[0x20];
5702
5703         u8         reserved_1[0x40];
5704 };
5705
5706 struct mlx5_ifc_enable_hca_out_bits {
5707         u8         status[0x8];
5708         u8         reserved_0[0x18];
5709
5710         u8         syndrome[0x20];
5711
5712         u8         reserved_1[0x20];
5713 };
5714
5715 struct mlx5_ifc_enable_hca_in_bits {
5716         u8         opcode[0x10];
5717         u8         reserved_0[0x10];
5718
5719         u8         reserved_1[0x10];
5720         u8         op_mod[0x10];
5721
5722         u8         reserved_2[0x10];
5723         u8         function_id[0x10];
5724
5725         u8         reserved_3[0x20];
5726 };
5727
5728 struct mlx5_ifc_drain_dct_out_bits {
5729         u8         status[0x8];
5730         u8         reserved_0[0x18];
5731
5732         u8         syndrome[0x20];
5733
5734         u8         reserved_1[0x40];
5735 };
5736
5737 struct mlx5_ifc_drain_dct_in_bits {
5738         u8         opcode[0x10];
5739         u8         reserved_0[0x10];
5740
5741         u8         reserved_1[0x10];
5742         u8         op_mod[0x10];
5743
5744         u8         reserved_2[0x8];
5745         u8         dctn[0x18];
5746
5747         u8         reserved_3[0x20];
5748 };
5749
5750 struct mlx5_ifc_disable_hca_out_bits {
5751         u8         status[0x8];
5752         u8         reserved_0[0x18];
5753
5754         u8         syndrome[0x20];
5755
5756         u8         reserved_1[0x20];
5757 };
5758
5759 struct mlx5_ifc_disable_hca_in_bits {
5760         u8         opcode[0x10];
5761         u8         reserved_0[0x10];
5762
5763         u8         reserved_1[0x10];
5764         u8         op_mod[0x10];
5765
5766         u8         reserved_2[0x10];
5767         u8         function_id[0x10];
5768
5769         u8         reserved_3[0x20];
5770 };
5771
5772 struct mlx5_ifc_detach_from_mcg_out_bits {
5773         u8         status[0x8];
5774         u8         reserved_0[0x18];
5775
5776         u8         syndrome[0x20];
5777
5778         u8         reserved_1[0x40];
5779 };
5780
5781 struct mlx5_ifc_detach_from_mcg_in_bits {
5782         u8         opcode[0x10];
5783         u8         reserved_0[0x10];
5784
5785         u8         reserved_1[0x10];
5786         u8         op_mod[0x10];
5787
5788         u8         reserved_2[0x8];
5789         u8         qpn[0x18];
5790
5791         u8         reserved_3[0x20];
5792
5793         u8         multicast_gid[16][0x8];
5794 };
5795
5796 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5797         u8         status[0x8];
5798         u8         reserved_0[0x18];
5799
5800         u8         syndrome[0x20];
5801
5802         u8         reserved_1[0x40];
5803 };
5804
5805 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5806         u8         opcode[0x10];
5807         u8         reserved_0[0x10];
5808
5809         u8         reserved_1[0x10];
5810         u8         op_mod[0x10];
5811
5812         u8         reserved_2[0x8];
5813         u8         xrc_srqn[0x18];
5814
5815         u8         reserved_3[0x20];
5816 };
5817
5818 struct mlx5_ifc_destroy_tis_out_bits {
5819         u8         status[0x8];
5820         u8         reserved_0[0x18];
5821
5822         u8         syndrome[0x20];
5823
5824         u8         reserved_1[0x40];
5825 };
5826
5827 struct mlx5_ifc_destroy_tis_in_bits {
5828         u8         opcode[0x10];
5829         u8         reserved_0[0x10];
5830
5831         u8         reserved_1[0x10];
5832         u8         op_mod[0x10];
5833
5834         u8         reserved_2[0x8];
5835         u8         tisn[0x18];
5836
5837         u8         reserved_3[0x20];
5838 };
5839
5840 struct mlx5_ifc_destroy_tir_out_bits {
5841         u8         status[0x8];
5842         u8         reserved_0[0x18];
5843
5844         u8         syndrome[0x20];
5845
5846         u8         reserved_1[0x40];
5847 };
5848
5849 struct mlx5_ifc_destroy_tir_in_bits {
5850         u8         opcode[0x10];
5851         u8         reserved_0[0x10];
5852
5853         u8         reserved_1[0x10];
5854         u8         op_mod[0x10];
5855
5856         u8         reserved_2[0x8];
5857         u8         tirn[0x18];
5858
5859         u8         reserved_3[0x20];
5860 };
5861
5862 struct mlx5_ifc_destroy_srq_out_bits {
5863         u8         status[0x8];
5864         u8         reserved_0[0x18];
5865
5866         u8         syndrome[0x20];
5867
5868         u8         reserved_1[0x40];
5869 };
5870
5871 struct mlx5_ifc_destroy_srq_in_bits {
5872         u8         opcode[0x10];
5873         u8         reserved_0[0x10];
5874
5875         u8         reserved_1[0x10];
5876         u8         op_mod[0x10];
5877
5878         u8         reserved_2[0x8];
5879         u8         srqn[0x18];
5880
5881         u8         reserved_3[0x20];
5882 };
5883
5884 struct mlx5_ifc_destroy_sq_out_bits {
5885         u8         status[0x8];
5886         u8         reserved_0[0x18];
5887
5888         u8         syndrome[0x20];
5889
5890         u8         reserved_1[0x40];
5891 };
5892
5893 struct mlx5_ifc_destroy_sq_in_bits {
5894         u8         opcode[0x10];
5895         u8         reserved_0[0x10];
5896
5897         u8         reserved_1[0x10];
5898         u8         op_mod[0x10];
5899
5900         u8         reserved_2[0x8];
5901         u8         sqn[0x18];
5902
5903         u8         reserved_3[0x20];
5904 };
5905
5906 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5907         u8         status[0x8];
5908         u8         reserved_at_8[0x18];
5909
5910         u8         syndrome[0x20];
5911
5912         u8         reserved_at_40[0x1c0];
5913 };
5914
5915 enum {
5916         MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5917 };
5918
5919 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5920         u8         opcode[0x10];
5921         u8         reserved_at_10[0x10];
5922
5923         u8         reserved_at_20[0x10];
5924         u8         op_mod[0x10];
5925
5926         u8         scheduling_hierarchy[0x8];
5927         u8         reserved_at_48[0x18];
5928
5929         u8         scheduling_element_id[0x20];
5930
5931         u8         reserved_at_80[0x180];
5932 };
5933
5934 struct mlx5_ifc_destroy_rqt_out_bits {
5935         u8         status[0x8];
5936         u8         reserved_0[0x18];
5937
5938         u8         syndrome[0x20];
5939
5940         u8         reserved_1[0x40];
5941 };
5942
5943 struct mlx5_ifc_destroy_rqt_in_bits {
5944         u8         opcode[0x10];
5945         u8         reserved_0[0x10];
5946
5947         u8         reserved_1[0x10];
5948         u8         op_mod[0x10];
5949
5950         u8         reserved_2[0x8];
5951         u8         rqtn[0x18];
5952
5953         u8         reserved_3[0x20];
5954 };
5955
5956 struct mlx5_ifc_destroy_rq_out_bits {
5957         u8         status[0x8];
5958         u8         reserved_0[0x18];
5959
5960         u8         syndrome[0x20];
5961
5962         u8         reserved_1[0x40];
5963 };
5964
5965 struct mlx5_ifc_destroy_rq_in_bits {
5966         u8         opcode[0x10];
5967         u8         reserved_0[0x10];
5968
5969         u8         reserved_1[0x10];
5970         u8         op_mod[0x10];
5971
5972         u8         reserved_2[0x8];
5973         u8         rqn[0x18];
5974
5975         u8         reserved_3[0x20];
5976 };
5977
5978 struct mlx5_ifc_destroy_rmp_out_bits {
5979         u8         status[0x8];
5980         u8         reserved_0[0x18];
5981
5982         u8         syndrome[0x20];
5983
5984         u8         reserved_1[0x40];
5985 };
5986
5987 struct mlx5_ifc_destroy_rmp_in_bits {
5988         u8         opcode[0x10];
5989         u8         reserved_0[0x10];
5990
5991         u8         reserved_1[0x10];
5992         u8         op_mod[0x10];
5993
5994         u8         reserved_2[0x8];
5995         u8         rmpn[0x18];
5996
5997         u8         reserved_3[0x20];
5998 };
5999
6000 struct mlx5_ifc_destroy_qp_out_bits {
6001         u8         status[0x8];
6002         u8         reserved_0[0x18];
6003
6004         u8         syndrome[0x20];
6005
6006         u8         reserved_1[0x40];
6007 };
6008
6009 struct mlx5_ifc_destroy_qp_in_bits {
6010         u8         opcode[0x10];
6011         u8         reserved_0[0x10];
6012
6013         u8         reserved_1[0x10];
6014         u8         op_mod[0x10];
6015
6016         u8         reserved_2[0x8];
6017         u8         qpn[0x18];
6018
6019         u8         reserved_3[0x20];
6020 };
6021
6022 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6023         u8         status[0x8];
6024         u8         reserved_at_8[0x18];
6025
6026         u8         syndrome[0x20];
6027
6028         u8         reserved_at_40[0x1c0];
6029 };
6030
6031 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6032         u8         opcode[0x10];
6033         u8         reserved_at_10[0x10];
6034
6035         u8         reserved_at_20[0x10];
6036         u8         op_mod[0x10];
6037
6038         u8         reserved_at_40[0x20];
6039
6040         u8         reserved_at_60[0x10];
6041         u8         qos_para_vport_number[0x10];
6042
6043         u8         reserved_at_80[0x180];
6044 };
6045
6046 struct mlx5_ifc_destroy_psv_out_bits {
6047         u8         status[0x8];
6048         u8         reserved_0[0x18];
6049
6050         u8         syndrome[0x20];
6051
6052         u8         reserved_1[0x40];
6053 };
6054
6055 struct mlx5_ifc_destroy_psv_in_bits {
6056         u8         opcode[0x10];
6057         u8         reserved_0[0x10];
6058
6059         u8         reserved_1[0x10];
6060         u8         op_mod[0x10];
6061
6062         u8         reserved_2[0x8];
6063         u8         psvn[0x18];
6064
6065         u8         reserved_3[0x20];
6066 };
6067
6068 struct mlx5_ifc_destroy_mkey_out_bits {
6069         u8         status[0x8];
6070         u8         reserved_0[0x18];
6071
6072         u8         syndrome[0x20];
6073
6074         u8         reserved_1[0x40];
6075 };
6076
6077 struct mlx5_ifc_destroy_mkey_in_bits {
6078         u8         opcode[0x10];
6079         u8         reserved_0[0x10];
6080
6081         u8         reserved_1[0x10];
6082         u8         op_mod[0x10];
6083
6084         u8         reserved_2[0x8];
6085         u8         mkey_index[0x18];
6086
6087         u8         reserved_3[0x20];
6088 };
6089
6090 struct mlx5_ifc_destroy_flow_table_out_bits {
6091         u8         status[0x8];
6092         u8         reserved_0[0x18];
6093
6094         u8         syndrome[0x20];
6095
6096         u8         reserved_1[0x40];
6097 };
6098
6099 struct mlx5_ifc_destroy_flow_table_in_bits {
6100         u8         opcode[0x10];
6101         u8         reserved_0[0x10];
6102
6103         u8         reserved_1[0x10];
6104         u8         op_mod[0x10];
6105
6106         u8         other_vport[0x1];
6107         u8         reserved_2[0xf];
6108         u8         vport_number[0x10];
6109
6110         u8         reserved_3[0x20];
6111
6112         u8         table_type[0x8];
6113         u8         reserved_4[0x18];
6114
6115         u8         reserved_5[0x8];
6116         u8         table_id[0x18];
6117
6118         u8         reserved_6[0x140];
6119 };
6120
6121 struct mlx5_ifc_destroy_flow_group_out_bits {
6122         u8         status[0x8];
6123         u8         reserved_0[0x18];
6124
6125         u8         syndrome[0x20];
6126
6127         u8         reserved_1[0x40];
6128 };
6129
6130 struct mlx5_ifc_destroy_flow_group_in_bits {
6131         u8         opcode[0x10];
6132         u8         reserved_0[0x10];
6133
6134         u8         reserved_1[0x10];
6135         u8         op_mod[0x10];
6136
6137         u8         other_vport[0x1];
6138         u8         reserved_2[0xf];
6139         u8         vport_number[0x10];
6140
6141         u8         reserved_3[0x20];
6142
6143         u8         table_type[0x8];
6144         u8         reserved_4[0x18];
6145
6146         u8         reserved_5[0x8];
6147         u8         table_id[0x18];
6148
6149         u8         group_id[0x20];
6150
6151         u8         reserved_6[0x120];
6152 };
6153
6154 struct mlx5_ifc_destroy_eq_out_bits {
6155         u8         status[0x8];
6156         u8         reserved_0[0x18];
6157
6158         u8         syndrome[0x20];
6159
6160         u8         reserved_1[0x40];
6161 };
6162
6163 struct mlx5_ifc_destroy_eq_in_bits {
6164         u8         opcode[0x10];
6165         u8         reserved_0[0x10];
6166
6167         u8         reserved_1[0x10];
6168         u8         op_mod[0x10];
6169
6170         u8         reserved_2[0x18];
6171         u8         eq_number[0x8];
6172
6173         u8         reserved_3[0x20];
6174 };
6175
6176 struct mlx5_ifc_destroy_dct_out_bits {
6177         u8         status[0x8];
6178         u8         reserved_0[0x18];
6179
6180         u8         syndrome[0x20];
6181
6182         u8         reserved_1[0x40];
6183 };
6184
6185 struct mlx5_ifc_destroy_dct_in_bits {
6186         u8         opcode[0x10];
6187         u8         reserved_0[0x10];
6188
6189         u8         reserved_1[0x10];
6190         u8         op_mod[0x10];
6191
6192         u8         reserved_2[0x8];
6193         u8         dctn[0x18];
6194
6195         u8         reserved_3[0x20];
6196 };
6197
6198 struct mlx5_ifc_destroy_cq_out_bits {
6199         u8         status[0x8];
6200         u8         reserved_0[0x18];
6201
6202         u8         syndrome[0x20];
6203
6204         u8         reserved_1[0x40];
6205 };
6206
6207 struct mlx5_ifc_destroy_cq_in_bits {
6208         u8         opcode[0x10];
6209         u8         reserved_0[0x10];
6210
6211         u8         reserved_1[0x10];
6212         u8         op_mod[0x10];
6213
6214         u8         reserved_2[0x8];
6215         u8         cqn[0x18];
6216
6217         u8         reserved_3[0x20];
6218 };
6219
6220 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6221         u8         status[0x8];
6222         u8         reserved_0[0x18];
6223
6224         u8         syndrome[0x20];
6225
6226         u8         reserved_1[0x40];
6227 };
6228
6229 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6230         u8         opcode[0x10];
6231         u8         reserved_0[0x10];
6232
6233         u8         reserved_1[0x10];
6234         u8         op_mod[0x10];
6235
6236         u8         reserved_2[0x20];
6237
6238         u8         reserved_3[0x10];
6239         u8         vxlan_udp_port[0x10];
6240 };
6241
6242 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6243         u8         status[0x8];
6244         u8         reserved_0[0x18];
6245
6246         u8         syndrome[0x20];
6247
6248         u8         reserved_1[0x40];
6249 };
6250
6251 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6252         u8         opcode[0x10];
6253         u8         reserved_0[0x10];
6254
6255         u8         reserved_1[0x10];
6256         u8         op_mod[0x10];
6257
6258         u8         reserved_2[0x60];
6259
6260         u8         reserved_3[0x8];
6261         u8         table_index[0x18];
6262
6263         u8         reserved_4[0x140];
6264 };
6265
6266 struct mlx5_ifc_delete_fte_out_bits {
6267         u8         status[0x8];
6268         u8         reserved_0[0x18];
6269
6270         u8         syndrome[0x20];
6271
6272         u8         reserved_1[0x40];
6273 };
6274
6275 struct mlx5_ifc_delete_fte_in_bits {
6276         u8         opcode[0x10];
6277         u8         reserved_0[0x10];
6278
6279         u8         reserved_1[0x10];
6280         u8         op_mod[0x10];
6281
6282         u8         other_vport[0x1];
6283         u8         reserved_2[0xf];
6284         u8         vport_number[0x10];
6285
6286         u8         reserved_3[0x20];
6287
6288         u8         table_type[0x8];
6289         u8         reserved_4[0x18];
6290
6291         u8         reserved_5[0x8];
6292         u8         table_id[0x18];
6293
6294         u8         reserved_6[0x40];
6295
6296         u8         flow_index[0x20];
6297
6298         u8         reserved_7[0xe0];
6299 };
6300
6301 struct mlx5_ifc_dealloc_xrcd_out_bits {
6302         u8         status[0x8];
6303         u8         reserved_0[0x18];
6304
6305         u8         syndrome[0x20];
6306
6307         u8         reserved_1[0x40];
6308 };
6309
6310 struct mlx5_ifc_dealloc_xrcd_in_bits {
6311         u8         opcode[0x10];
6312         u8         reserved_0[0x10];
6313
6314         u8         reserved_1[0x10];
6315         u8         op_mod[0x10];
6316
6317         u8         reserved_2[0x8];
6318         u8         xrcd[0x18];
6319
6320         u8         reserved_3[0x20];
6321 };
6322
6323 struct mlx5_ifc_dealloc_uar_out_bits {
6324         u8         status[0x8];
6325         u8         reserved_0[0x18];
6326
6327         u8         syndrome[0x20];
6328
6329         u8         reserved_1[0x40];
6330 };
6331
6332 struct mlx5_ifc_dealloc_uar_in_bits {
6333         u8         opcode[0x10];
6334         u8         reserved_0[0x10];
6335
6336         u8         reserved_1[0x10];
6337         u8         op_mod[0x10];
6338
6339         u8         reserved_2[0x8];
6340         u8         uar[0x18];
6341
6342         u8         reserved_3[0x20];
6343 };
6344
6345 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6346         u8         status[0x8];
6347         u8         reserved_0[0x18];
6348
6349         u8         syndrome[0x20];
6350
6351         u8         reserved_1[0x40];
6352 };
6353
6354 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6355         u8         opcode[0x10];
6356         u8         reserved_0[0x10];
6357
6358         u8         reserved_1[0x10];
6359         u8         op_mod[0x10];
6360
6361         u8         reserved_2[0x8];
6362         u8         transport_domain[0x18];
6363
6364         u8         reserved_3[0x20];
6365 };
6366
6367 struct mlx5_ifc_dealloc_q_counter_out_bits {
6368         u8         status[0x8];
6369         u8         reserved_0[0x18];
6370
6371         u8         syndrome[0x20];
6372
6373         u8         reserved_1[0x40];
6374 };
6375
6376 struct mlx5_ifc_counter_id_bits {
6377         u8         reserved[0x10];
6378         u8         counter_id[0x10];
6379 };
6380
6381 struct mlx5_ifc_diagnostic_params_context_bits {
6382         u8         num_of_counters[0x10];
6383         u8         reserved_2[0x8];
6384         u8         log_num_of_samples[0x8];
6385
6386         u8         single[0x1];
6387         u8         repetitive[0x1];
6388         u8         sync[0x1];
6389         u8         clear[0x1];
6390         u8         on_demand[0x1];
6391         u8         enable[0x1];
6392         u8         reserved_3[0x12];
6393         u8         log_sample_period[0x8];
6394
6395         u8         reserved_4[0x80];
6396
6397         struct mlx5_ifc_counter_id_bits counter_id[0];
6398 };
6399
6400 struct mlx5_ifc_set_diagnostic_params_in_bits {
6401         u8         opcode[0x10];
6402         u8         reserved_0[0x10];
6403
6404         u8         reserved_1[0x10];
6405         u8         op_mod[0x10];
6406
6407         struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6408 };
6409
6410 struct mlx5_ifc_set_diagnostic_params_out_bits {
6411         u8         status[0x8];
6412         u8         reserved_0[0x18];
6413
6414         u8         syndrome[0x20];
6415
6416         u8         reserved_1[0x40];
6417 };
6418
6419 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6420         u8         opcode[0x10];
6421         u8         reserved_0[0x10];
6422
6423         u8         reserved_1[0x10];
6424         u8         op_mod[0x10];
6425
6426         u8         num_of_samples[0x10];
6427         u8         sample_index[0x10];
6428
6429         u8         reserved_2[0x20];
6430 };
6431
6432 struct mlx5_ifc_diagnostic_counter_bits {
6433         u8         counter_id[0x10];
6434         u8         sample_id[0x10];
6435
6436         u8         time_stamp_31_0[0x20];
6437
6438         u8         counter_value_h[0x20];
6439
6440         u8         counter_value_l[0x20];
6441 };
6442
6443 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6444         u8         status[0x8];
6445         u8         reserved_0[0x18];
6446
6447         u8         syndrome[0x20];
6448
6449         u8         reserved_1[0x40];
6450
6451         struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6452 };
6453
6454 struct mlx5_ifc_dealloc_q_counter_in_bits {
6455         u8         opcode[0x10];
6456         u8         reserved_0[0x10];
6457
6458         u8         reserved_1[0x10];
6459         u8         op_mod[0x10];
6460
6461         u8         reserved_2[0x18];
6462         u8         counter_set_id[0x8];
6463
6464         u8         reserved_3[0x20];
6465 };
6466
6467 struct mlx5_ifc_dealloc_pd_out_bits {
6468         u8         status[0x8];
6469         u8         reserved_0[0x18];
6470
6471         u8         syndrome[0x20];
6472
6473         u8         reserved_1[0x40];
6474 };
6475
6476 struct mlx5_ifc_dealloc_pd_in_bits {
6477         u8         opcode[0x10];
6478         u8         reserved_0[0x10];
6479
6480         u8         reserved_1[0x10];
6481         u8         op_mod[0x10];
6482
6483         u8         reserved_2[0x8];
6484         u8         pd[0x18];
6485
6486         u8         reserved_3[0x20];
6487 };
6488
6489 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6490         u8         status[0x8];
6491         u8         reserved_0[0x18];
6492
6493         u8         syndrome[0x20];
6494
6495         u8         reserved_1[0x40];
6496 };
6497
6498 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6499         u8         opcode[0x10];
6500         u8         reserved_0[0x10];
6501
6502         u8         reserved_1[0x10];
6503         u8         op_mod[0x10];
6504
6505         u8         reserved_2[0x10];
6506         u8         flow_counter_id[0x10];
6507
6508         u8         reserved_3[0x20];
6509 };
6510
6511 struct mlx5_ifc_deactivate_tracer_out_bits {
6512         u8         status[0x8];
6513         u8         reserved_0[0x18];
6514
6515         u8         syndrome[0x20];
6516
6517         u8         reserved_1[0x40];
6518 };
6519
6520 struct mlx5_ifc_deactivate_tracer_in_bits {
6521         u8         opcode[0x10];
6522         u8         reserved_0[0x10];
6523
6524         u8         reserved_1[0x10];
6525         u8         op_mod[0x10];
6526
6527         u8         mkey[0x20];
6528
6529         u8         reserved_2[0x20];
6530 };
6531
6532 struct mlx5_ifc_create_xrc_srq_out_bits {
6533         u8         status[0x8];
6534         u8         reserved_0[0x18];
6535
6536         u8         syndrome[0x20];
6537
6538         u8         reserved_1[0x8];
6539         u8         xrc_srqn[0x18];
6540
6541         u8         reserved_2[0x20];
6542 };
6543
6544 struct mlx5_ifc_create_xrc_srq_in_bits {
6545         u8         opcode[0x10];
6546         u8         reserved_0[0x10];
6547
6548         u8         reserved_1[0x10];
6549         u8         op_mod[0x10];
6550
6551         u8         reserved_2[0x40];
6552
6553         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6554
6555         u8         reserved_3[0x600];
6556
6557         u8         pas[0][0x40];
6558 };
6559
6560 struct mlx5_ifc_create_tis_out_bits {
6561         u8         status[0x8];
6562         u8         reserved_0[0x18];
6563
6564         u8         syndrome[0x20];
6565
6566         u8         reserved_1[0x8];
6567         u8         tisn[0x18];
6568
6569         u8         reserved_2[0x20];
6570 };
6571
6572 struct mlx5_ifc_create_tis_in_bits {
6573         u8         opcode[0x10];
6574         u8         reserved_0[0x10];
6575
6576         u8         reserved_1[0x10];
6577         u8         op_mod[0x10];
6578
6579         u8         reserved_2[0xc0];
6580
6581         struct mlx5_ifc_tisc_bits ctx;
6582 };
6583
6584 struct mlx5_ifc_create_tir_out_bits {
6585         u8         status[0x8];
6586         u8         reserved_0[0x18];
6587
6588         u8         syndrome[0x20];
6589
6590         u8         reserved_1[0x8];
6591         u8         tirn[0x18];
6592
6593         u8         reserved_2[0x20];
6594 };
6595
6596 struct mlx5_ifc_create_tir_in_bits {
6597         u8         opcode[0x10];
6598         u8         reserved_0[0x10];
6599
6600         u8         reserved_1[0x10];
6601         u8         op_mod[0x10];
6602
6603         u8         reserved_2[0xc0];
6604
6605         struct mlx5_ifc_tirc_bits tir_context;
6606 };
6607
6608 struct mlx5_ifc_create_srq_out_bits {
6609         u8         status[0x8];
6610         u8         reserved_0[0x18];
6611
6612         u8         syndrome[0x20];
6613
6614         u8         reserved_1[0x8];
6615         u8         srqn[0x18];
6616
6617         u8         reserved_2[0x20];
6618 };
6619
6620 struct mlx5_ifc_create_srq_in_bits {
6621         u8         opcode[0x10];
6622         u8         reserved_0[0x10];
6623
6624         u8         reserved_1[0x10];
6625         u8         op_mod[0x10];
6626
6627         u8         reserved_2[0x40];
6628
6629         struct mlx5_ifc_srqc_bits srq_context_entry;
6630
6631         u8         reserved_3[0x600];
6632
6633         u8         pas[0][0x40];
6634 };
6635
6636 struct mlx5_ifc_create_sq_out_bits {
6637         u8         status[0x8];
6638         u8         reserved_0[0x18];
6639
6640         u8         syndrome[0x20];
6641
6642         u8         reserved_1[0x8];
6643         u8         sqn[0x18];
6644
6645         u8         reserved_2[0x20];
6646 };
6647
6648 struct mlx5_ifc_create_sq_in_bits {
6649         u8         opcode[0x10];
6650         u8         reserved_0[0x10];
6651
6652         u8         reserved_1[0x10];
6653         u8         op_mod[0x10];
6654
6655         u8         reserved_2[0xc0];
6656
6657         struct mlx5_ifc_sqc_bits ctx;
6658 };
6659
6660 struct mlx5_ifc_create_scheduling_element_out_bits {
6661         u8         status[0x8];
6662         u8         reserved_at_8[0x18];
6663
6664         u8         syndrome[0x20];
6665
6666         u8         reserved_at_40[0x40];
6667
6668         u8         scheduling_element_id[0x20];
6669
6670         u8         reserved_at_a0[0x160];
6671 };
6672
6673 enum {
6674         MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6675 };
6676
6677 struct mlx5_ifc_create_scheduling_element_in_bits {
6678         u8         opcode[0x10];
6679         u8         reserved_at_10[0x10];
6680
6681         u8         reserved_at_20[0x10];
6682         u8         op_mod[0x10];
6683
6684         u8         scheduling_hierarchy[0x8];
6685         u8         reserved_at_48[0x18];
6686
6687         u8         reserved_at_60[0xa0];
6688
6689         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6690
6691         u8         reserved_at_300[0x100];
6692 };
6693
6694 struct mlx5_ifc_create_rqt_out_bits {
6695         u8         status[0x8];
6696         u8         reserved_0[0x18];
6697
6698         u8         syndrome[0x20];
6699
6700         u8         reserved_1[0x8];
6701         u8         rqtn[0x18];
6702
6703         u8         reserved_2[0x20];
6704 };
6705
6706 struct mlx5_ifc_create_rqt_in_bits {
6707         u8         opcode[0x10];
6708         u8         reserved_0[0x10];
6709
6710         u8         reserved_1[0x10];
6711         u8         op_mod[0x10];
6712
6713         u8         reserved_2[0xc0];
6714
6715         struct mlx5_ifc_rqtc_bits rqt_context;
6716 };
6717
6718 struct mlx5_ifc_create_rq_out_bits {
6719         u8         status[0x8];
6720         u8         reserved_0[0x18];
6721
6722         u8         syndrome[0x20];
6723
6724         u8         reserved_1[0x8];
6725         u8         rqn[0x18];
6726
6727         u8         reserved_2[0x20];
6728 };
6729
6730 struct mlx5_ifc_create_rq_in_bits {
6731         u8         opcode[0x10];
6732         u8         reserved_0[0x10];
6733
6734         u8         reserved_1[0x10];
6735         u8         op_mod[0x10];
6736
6737         u8         reserved_2[0xc0];
6738
6739         struct mlx5_ifc_rqc_bits ctx;
6740 };
6741
6742 struct mlx5_ifc_create_rmp_out_bits {
6743         u8         status[0x8];
6744         u8         reserved_0[0x18];
6745
6746         u8         syndrome[0x20];
6747
6748         u8         reserved_1[0x8];
6749         u8         rmpn[0x18];
6750
6751         u8         reserved_2[0x20];
6752 };
6753
6754 struct mlx5_ifc_create_rmp_in_bits {
6755         u8         opcode[0x10];
6756         u8         reserved_0[0x10];
6757
6758         u8         reserved_1[0x10];
6759         u8         op_mod[0x10];
6760
6761         u8         reserved_2[0xc0];
6762
6763         struct mlx5_ifc_rmpc_bits ctx;
6764 };
6765
6766 struct mlx5_ifc_create_qp_out_bits {
6767         u8         status[0x8];
6768         u8         reserved_0[0x18];
6769
6770         u8         syndrome[0x20];
6771
6772         u8         reserved_1[0x8];
6773         u8         qpn[0x18];
6774
6775         u8         reserved_2[0x20];
6776 };
6777
6778 struct mlx5_ifc_create_qp_in_bits {
6779         u8         opcode[0x10];
6780         u8         reserved_0[0x10];
6781
6782         u8         reserved_1[0x10];
6783         u8         op_mod[0x10];
6784
6785         u8         reserved_2[0x8];
6786         u8         input_qpn[0x18];
6787
6788         u8         reserved_3[0x20];
6789
6790         u8         opt_param_mask[0x20];
6791
6792         u8         reserved_4[0x20];
6793
6794         struct mlx5_ifc_qpc_bits qpc;
6795
6796         u8         reserved_5[0x80];
6797
6798         u8         pas[0][0x40];
6799 };
6800
6801 struct mlx5_ifc_create_qos_para_vport_out_bits {
6802         u8         status[0x8];
6803         u8         reserved_at_8[0x18];
6804
6805         u8         syndrome[0x20];
6806
6807         u8         reserved_at_40[0x20];
6808
6809         u8         reserved_at_60[0x10];
6810         u8         qos_para_vport_number[0x10];
6811
6812         u8         reserved_at_80[0x180];
6813 };
6814
6815 struct mlx5_ifc_create_qos_para_vport_in_bits {
6816         u8         opcode[0x10];
6817         u8         reserved_at_10[0x10];
6818
6819         u8         reserved_at_20[0x10];
6820         u8         op_mod[0x10];
6821
6822         u8         reserved_at_40[0x1c0];
6823 };
6824
6825 struct mlx5_ifc_create_psv_out_bits {
6826         u8         status[0x8];
6827         u8         reserved_0[0x18];
6828
6829         u8         syndrome[0x20];
6830
6831         u8         reserved_1[0x40];
6832
6833         u8         reserved_2[0x8];
6834         u8         psv0_index[0x18];
6835
6836         u8         reserved_3[0x8];
6837         u8         psv1_index[0x18];
6838
6839         u8         reserved_4[0x8];
6840         u8         psv2_index[0x18];
6841
6842         u8         reserved_5[0x8];
6843         u8         psv3_index[0x18];
6844 };
6845
6846 struct mlx5_ifc_create_psv_in_bits {
6847         u8         opcode[0x10];
6848         u8         reserved_0[0x10];
6849
6850         u8         reserved_1[0x10];
6851         u8         op_mod[0x10];
6852
6853         u8         num_psv[0x4];
6854         u8         reserved_2[0x4];
6855         u8         pd[0x18];
6856
6857         u8         reserved_3[0x20];
6858 };
6859
6860 struct mlx5_ifc_create_mkey_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_0[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         reserved_1[0x8];
6867         u8         mkey_index[0x18];
6868
6869         u8         reserved_2[0x20];
6870 };
6871
6872 struct mlx5_ifc_create_mkey_in_bits {
6873         u8         opcode[0x10];
6874         u8         reserved_0[0x10];
6875
6876         u8         reserved_1[0x10];
6877         u8         op_mod[0x10];
6878
6879         u8         reserved_2[0x20];
6880
6881         u8         pg_access[0x1];
6882         u8         reserved_3[0x1f];
6883
6884         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6885
6886         u8         reserved_4[0x80];
6887
6888         u8         translations_octword_actual_size[0x20];
6889
6890         u8         reserved_5[0x560];
6891
6892         u8         klm_pas_mtt[0][0x20];
6893 };
6894
6895 struct mlx5_ifc_create_flow_table_out_bits {
6896         u8         status[0x8];
6897         u8         reserved_0[0x18];
6898
6899         u8         syndrome[0x20];
6900
6901         u8         reserved_1[0x8];
6902         u8         table_id[0x18];
6903
6904         u8         reserved_2[0x20];
6905 };
6906
6907 struct mlx5_ifc_create_flow_table_in_bits {
6908         u8         opcode[0x10];
6909         u8         reserved_0[0x10];
6910
6911         u8         reserved_1[0x10];
6912         u8         op_mod[0x10];
6913
6914         u8         other_vport[0x1];
6915         u8         reserved_2[0xf];
6916         u8         vport_number[0x10];
6917
6918         u8         reserved_3[0x20];
6919
6920         u8         table_type[0x8];
6921         u8         reserved_4[0x18];
6922
6923         u8         reserved_5[0x20];
6924
6925         u8         reserved_6[0x8];
6926         u8         level[0x8];
6927         u8         reserved_7[0x8];
6928         u8         log_size[0x8];
6929
6930         u8         reserved_8[0x120];
6931 };
6932
6933 struct mlx5_ifc_create_flow_group_out_bits {
6934         u8         status[0x8];
6935         u8         reserved_0[0x18];
6936
6937         u8         syndrome[0x20];
6938
6939         u8         reserved_1[0x8];
6940         u8         group_id[0x18];
6941
6942         u8         reserved_2[0x20];
6943 };
6944
6945 enum {
6946         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6947         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6948         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6949 };
6950
6951 struct mlx5_ifc_create_flow_group_in_bits {
6952         u8         opcode[0x10];
6953         u8         reserved_0[0x10];
6954
6955         u8         reserved_1[0x10];
6956         u8         op_mod[0x10];
6957
6958         u8         other_vport[0x1];
6959         u8         reserved_2[0xf];
6960         u8         vport_number[0x10];
6961
6962         u8         reserved_3[0x20];
6963
6964         u8         table_type[0x8];
6965         u8         reserved_4[0x18];
6966
6967         u8         reserved_5[0x8];
6968         u8         table_id[0x18];
6969
6970         u8         reserved_6[0x20];
6971
6972         u8         start_flow_index[0x20];
6973
6974         u8         reserved_7[0x20];
6975
6976         u8         end_flow_index[0x20];
6977
6978         u8         reserved_8[0xa0];
6979
6980         u8         reserved_9[0x18];
6981         u8         match_criteria_enable[0x8];
6982
6983         struct mlx5_ifc_fte_match_param_bits match_criteria;
6984
6985         u8         reserved_10[0xe00];
6986 };
6987
6988 struct mlx5_ifc_create_eq_out_bits {
6989         u8         status[0x8];
6990         u8         reserved_0[0x18];
6991
6992         u8         syndrome[0x20];
6993
6994         u8         reserved_1[0x18];
6995         u8         eq_number[0x8];
6996
6997         u8         reserved_2[0x20];
6998 };
6999
7000 struct mlx5_ifc_create_eq_in_bits {
7001         u8         opcode[0x10];
7002         u8         reserved_0[0x10];
7003
7004         u8         reserved_1[0x10];
7005         u8         op_mod[0x10];
7006
7007         u8         reserved_2[0x40];
7008
7009         struct mlx5_ifc_eqc_bits eq_context_entry;
7010
7011         u8         reserved_3[0x40];
7012
7013         u8         event_bitmask[0x40];
7014
7015         u8         reserved_4[0x580];
7016
7017         u8         pas[0][0x40];
7018 };
7019
7020 struct mlx5_ifc_create_dct_out_bits {
7021         u8         status[0x8];
7022         u8         reserved_0[0x18];
7023
7024         u8         syndrome[0x20];
7025
7026         u8         reserved_1[0x8];
7027         u8         dctn[0x18];
7028
7029         u8         reserved_2[0x20];
7030 };
7031
7032 struct mlx5_ifc_create_dct_in_bits {
7033         u8         opcode[0x10];
7034         u8         reserved_0[0x10];
7035
7036         u8         reserved_1[0x10];
7037         u8         op_mod[0x10];
7038
7039         u8         reserved_2[0x40];
7040
7041         struct mlx5_ifc_dctc_bits dct_context_entry;
7042
7043         u8         reserved_3[0x180];
7044 };
7045
7046 struct mlx5_ifc_create_cq_out_bits {
7047         u8         status[0x8];
7048         u8         reserved_0[0x18];
7049
7050         u8         syndrome[0x20];
7051
7052         u8         reserved_1[0x8];
7053         u8         cqn[0x18];
7054
7055         u8         reserved_2[0x20];
7056 };
7057
7058 struct mlx5_ifc_create_cq_in_bits {
7059         u8         opcode[0x10];
7060         u8         reserved_0[0x10];
7061
7062         u8         reserved_1[0x10];
7063         u8         op_mod[0x10];
7064
7065         u8         reserved_2[0x40];
7066
7067         struct mlx5_ifc_cqc_bits cq_context;
7068
7069         u8         reserved_3[0x600];
7070
7071         u8         pas[0][0x40];
7072 };
7073
7074 struct mlx5_ifc_config_int_moderation_out_bits {
7075         u8         status[0x8];
7076         u8         reserved_0[0x18];
7077
7078         u8         syndrome[0x20];
7079
7080         u8         reserved_1[0x4];
7081         u8         min_delay[0xc];
7082         u8         int_vector[0x10];
7083
7084         u8         reserved_2[0x20];
7085 };
7086
7087 enum {
7088         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7089         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7090 };
7091
7092 struct mlx5_ifc_config_int_moderation_in_bits {
7093         u8         opcode[0x10];
7094         u8         reserved_0[0x10];
7095
7096         u8         reserved_1[0x10];
7097         u8         op_mod[0x10];
7098
7099         u8         reserved_2[0x4];
7100         u8         min_delay[0xc];
7101         u8         int_vector[0x10];
7102
7103         u8         reserved_3[0x20];
7104 };
7105
7106 struct mlx5_ifc_attach_to_mcg_out_bits {
7107         u8         status[0x8];
7108         u8         reserved_0[0x18];
7109
7110         u8         syndrome[0x20];
7111
7112         u8         reserved_1[0x40];
7113 };
7114
7115 struct mlx5_ifc_attach_to_mcg_in_bits {
7116         u8         opcode[0x10];
7117         u8         reserved_0[0x10];
7118
7119         u8         reserved_1[0x10];
7120         u8         op_mod[0x10];
7121
7122         u8         reserved_2[0x8];
7123         u8         qpn[0x18];
7124
7125         u8         reserved_3[0x20];
7126
7127         u8         multicast_gid[16][0x8];
7128 };
7129
7130 struct mlx5_ifc_arm_xrc_srq_out_bits {
7131         u8         status[0x8];
7132         u8         reserved_0[0x18];
7133
7134         u8         syndrome[0x20];
7135
7136         u8         reserved_1[0x40];
7137 };
7138
7139 enum {
7140         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7141 };
7142
7143 struct mlx5_ifc_arm_xrc_srq_in_bits {
7144         u8         opcode[0x10];
7145         u8         reserved_0[0x10];
7146
7147         u8         reserved_1[0x10];
7148         u8         op_mod[0x10];
7149
7150         u8         reserved_2[0x8];
7151         u8         xrc_srqn[0x18];
7152
7153         u8         reserved_3[0x10];
7154         u8         lwm[0x10];
7155 };
7156
7157 struct mlx5_ifc_arm_rq_out_bits {
7158         u8         status[0x8];
7159         u8         reserved_0[0x18];
7160
7161         u8         syndrome[0x20];
7162
7163         u8         reserved_1[0x40];
7164 };
7165
7166 enum {
7167         MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7168 };
7169
7170 struct mlx5_ifc_arm_rq_in_bits {
7171         u8         opcode[0x10];
7172         u8         reserved_0[0x10];
7173
7174         u8         reserved_1[0x10];
7175         u8         op_mod[0x10];
7176
7177         u8         reserved_2[0x8];
7178         u8         srq_number[0x18];
7179
7180         u8         reserved_3[0x10];
7181         u8         lwm[0x10];
7182 };
7183
7184 struct mlx5_ifc_arm_dct_out_bits {
7185         u8         status[0x8];
7186         u8         reserved_0[0x18];
7187
7188         u8         syndrome[0x20];
7189
7190         u8         reserved_1[0x40];
7191 };
7192
7193 struct mlx5_ifc_arm_dct_in_bits {
7194         u8         opcode[0x10];
7195         u8         reserved_0[0x10];
7196
7197         u8         reserved_1[0x10];
7198         u8         op_mod[0x10];
7199
7200         u8         reserved_2[0x8];
7201         u8         dctn[0x18];
7202
7203         u8         reserved_3[0x20];
7204 };
7205
7206 struct mlx5_ifc_alloc_xrcd_out_bits {
7207         u8         status[0x8];
7208         u8         reserved_0[0x18];
7209
7210         u8         syndrome[0x20];
7211
7212         u8         reserved_1[0x8];
7213         u8         xrcd[0x18];
7214
7215         u8         reserved_2[0x20];
7216 };
7217
7218 struct mlx5_ifc_alloc_xrcd_in_bits {
7219         u8         opcode[0x10];
7220         u8         reserved_0[0x10];
7221
7222         u8         reserved_1[0x10];
7223         u8         op_mod[0x10];
7224
7225         u8         reserved_2[0x40];
7226 };
7227
7228 struct mlx5_ifc_alloc_uar_out_bits {
7229         u8         status[0x8];
7230         u8         reserved_0[0x18];
7231
7232         u8         syndrome[0x20];
7233
7234         u8         reserved_1[0x8];
7235         u8         uar[0x18];
7236
7237         u8         reserved_2[0x20];
7238 };
7239
7240 struct mlx5_ifc_alloc_uar_in_bits {
7241         u8         opcode[0x10];
7242         u8         reserved_0[0x10];
7243
7244         u8         reserved_1[0x10];
7245         u8         op_mod[0x10];
7246
7247         u8         reserved_2[0x40];
7248 };
7249
7250 struct mlx5_ifc_alloc_transport_domain_out_bits {
7251         u8         status[0x8];
7252         u8         reserved_0[0x18];
7253
7254         u8         syndrome[0x20];
7255
7256         u8         reserved_1[0x8];
7257         u8         transport_domain[0x18];
7258
7259         u8         reserved_2[0x20];
7260 };
7261
7262 struct mlx5_ifc_alloc_transport_domain_in_bits {
7263         u8         opcode[0x10];
7264         u8         reserved_0[0x10];
7265
7266         u8         reserved_1[0x10];
7267         u8         op_mod[0x10];
7268
7269         u8         reserved_2[0x40];
7270 };
7271
7272 struct mlx5_ifc_alloc_q_counter_out_bits {
7273         u8         status[0x8];
7274         u8         reserved_0[0x18];
7275
7276         u8         syndrome[0x20];
7277
7278         u8         reserved_1[0x18];
7279         u8         counter_set_id[0x8];
7280
7281         u8         reserved_2[0x20];
7282 };
7283
7284 struct mlx5_ifc_alloc_q_counter_in_bits {
7285         u8         opcode[0x10];
7286         u8         reserved_0[0x10];
7287
7288         u8         reserved_1[0x10];
7289         u8         op_mod[0x10];
7290
7291         u8         reserved_2[0x40];
7292 };
7293
7294 struct mlx5_ifc_alloc_pd_out_bits {
7295         u8         status[0x8];
7296         u8         reserved_0[0x18];
7297
7298         u8         syndrome[0x20];
7299
7300         u8         reserved_1[0x8];
7301         u8         pd[0x18];
7302
7303         u8         reserved_2[0x20];
7304 };
7305
7306 struct mlx5_ifc_alloc_pd_in_bits {
7307         u8         opcode[0x10];
7308         u8         reserved_0[0x10];
7309
7310         u8         reserved_1[0x10];
7311         u8         op_mod[0x10];
7312
7313         u8         reserved_2[0x40];
7314 };
7315
7316 struct mlx5_ifc_alloc_flow_counter_out_bits {
7317         u8         status[0x8];
7318         u8         reserved_0[0x18];
7319
7320         u8         syndrome[0x20];
7321
7322         u8         reserved_1[0x10];
7323         u8         flow_counter_id[0x10];
7324
7325         u8         reserved_2[0x20];
7326 };
7327
7328 struct mlx5_ifc_alloc_flow_counter_in_bits {
7329         u8         opcode[0x10];
7330         u8         reserved_0[0x10];
7331
7332         u8         reserved_1[0x10];
7333         u8         op_mod[0x10];
7334
7335         u8         reserved_2[0x40];
7336 };
7337
7338 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7339         u8         status[0x8];
7340         u8         reserved_0[0x18];
7341
7342         u8         syndrome[0x20];
7343
7344         u8         reserved_1[0x40];
7345 };
7346
7347 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7348         u8         opcode[0x10];
7349         u8         reserved_0[0x10];
7350
7351         u8         reserved_1[0x10];
7352         u8         op_mod[0x10];
7353
7354         u8         reserved_2[0x20];
7355
7356         u8         reserved_3[0x10];
7357         u8         vxlan_udp_port[0x10];
7358 };
7359
7360 struct mlx5_ifc_activate_tracer_out_bits {
7361         u8         status[0x8];
7362         u8         reserved_0[0x18];
7363
7364         u8         syndrome[0x20];
7365
7366         u8         reserved_1[0x40];
7367 };
7368
7369 struct mlx5_ifc_activate_tracer_in_bits {
7370         u8         opcode[0x10];
7371         u8         reserved_0[0x10];
7372
7373         u8         reserved_1[0x10];
7374         u8         op_mod[0x10];
7375
7376         u8         mkey[0x20];
7377
7378         u8         reserved_2[0x20];
7379 };
7380
7381 struct mlx5_ifc_set_rate_limit_out_bits {
7382         u8         status[0x8];
7383         u8         reserved_at_8[0x18];
7384
7385         u8         syndrome[0x20];
7386
7387         u8         reserved_at_40[0x40];
7388 };
7389
7390 struct mlx5_ifc_set_rate_limit_in_bits {
7391         u8         opcode[0x10];
7392         u8         reserved_at_10[0x10];
7393
7394         u8         reserved_at_20[0x10];
7395         u8         op_mod[0x10];
7396
7397         u8         reserved_at_40[0x10];
7398         u8         rate_limit_index[0x10];
7399
7400         u8         reserved_at_60[0x20];
7401
7402         u8         rate_limit[0x20];
7403         u8         burst_upper_bound[0x20];
7404 };
7405
7406 struct mlx5_ifc_access_register_out_bits {
7407         u8         status[0x8];
7408         u8         reserved_0[0x18];
7409
7410         u8         syndrome[0x20];
7411
7412         u8         reserved_1[0x40];
7413
7414         u8         register_data[0][0x20];
7415 };
7416
7417 enum {
7418         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7419         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7420 };
7421
7422 struct mlx5_ifc_access_register_in_bits {
7423         u8         opcode[0x10];
7424         u8         reserved_0[0x10];
7425
7426         u8         reserved_1[0x10];
7427         u8         op_mod[0x10];
7428
7429         u8         reserved_2[0x10];
7430         u8         register_id[0x10];
7431
7432         u8         argument[0x20];
7433
7434         u8         register_data[0][0x20];
7435 };
7436
7437 struct mlx5_ifc_sltp_reg_bits {
7438         u8         status[0x4];
7439         u8         version[0x4];
7440         u8         local_port[0x8];
7441         u8         pnat[0x2];
7442         u8         reserved_0[0x2];
7443         u8         lane[0x4];
7444         u8         reserved_1[0x8];
7445
7446         u8         reserved_2[0x20];
7447
7448         u8         reserved_3[0x7];
7449         u8         polarity[0x1];
7450         u8         ob_tap0[0x8];
7451         u8         ob_tap1[0x8];
7452         u8         ob_tap2[0x8];
7453
7454         u8         reserved_4[0xc];
7455         u8         ob_preemp_mode[0x4];
7456         u8         ob_reg[0x8];
7457         u8         ob_bias[0x8];
7458
7459         u8         reserved_5[0x20];
7460 };
7461
7462 struct mlx5_ifc_slrp_reg_bits {
7463         u8         status[0x4];
7464         u8         version[0x4];
7465         u8         local_port[0x8];
7466         u8         pnat[0x2];
7467         u8         reserved_0[0x2];
7468         u8         lane[0x4];
7469         u8         reserved_1[0x8];
7470
7471         u8         ib_sel[0x2];
7472         u8         reserved_2[0x11];
7473         u8         dp_sel[0x1];
7474         u8         dp90sel[0x4];
7475         u8         mix90phase[0x8];
7476
7477         u8         ffe_tap0[0x8];
7478         u8         ffe_tap1[0x8];
7479         u8         ffe_tap2[0x8];
7480         u8         ffe_tap3[0x8];
7481
7482         u8         ffe_tap4[0x8];
7483         u8         ffe_tap5[0x8];
7484         u8         ffe_tap6[0x8];
7485         u8         ffe_tap7[0x8];
7486
7487         u8         ffe_tap8[0x8];
7488         u8         mixerbias_tap_amp[0x8];
7489         u8         reserved_3[0x7];
7490         u8         ffe_tap_en[0x9];
7491
7492         u8         ffe_tap_offset0[0x8];
7493         u8         ffe_tap_offset1[0x8];
7494         u8         slicer_offset0[0x10];
7495
7496         u8         mixer_offset0[0x10];
7497         u8         mixer_offset1[0x10];
7498
7499         u8         mixerbgn_inp[0x8];
7500         u8         mixerbgn_inn[0x8];
7501         u8         mixerbgn_refp[0x8];
7502         u8         mixerbgn_refn[0x8];
7503
7504         u8         sel_slicer_lctrl_h[0x1];
7505         u8         sel_slicer_lctrl_l[0x1];
7506         u8         reserved_4[0x1];
7507         u8         ref_mixer_vreg[0x5];
7508         u8         slicer_gctrl[0x8];
7509         u8         lctrl_input[0x8];
7510         u8         mixer_offset_cm1[0x8];
7511
7512         u8         common_mode[0x6];
7513         u8         reserved_5[0x1];
7514         u8         mixer_offset_cm0[0x9];
7515         u8         reserved_6[0x7];
7516         u8         slicer_offset_cm[0x9];
7517 };
7518
7519 struct mlx5_ifc_slrg_reg_bits {
7520         u8         status[0x4];
7521         u8         version[0x4];
7522         u8         local_port[0x8];
7523         u8         pnat[0x2];
7524         u8         reserved_0[0x2];
7525         u8         lane[0x4];
7526         u8         reserved_1[0x8];
7527
7528         u8         time_to_link_up[0x10];
7529         u8         reserved_2[0xc];
7530         u8         grade_lane_speed[0x4];
7531
7532         u8         grade_version[0x8];
7533         u8         grade[0x18];
7534
7535         u8         reserved_3[0x4];
7536         u8         height_grade_type[0x4];
7537         u8         height_grade[0x18];
7538
7539         u8         height_dz[0x10];
7540         u8         height_dv[0x10];
7541
7542         u8         reserved_4[0x10];
7543         u8         height_sigma[0x10];
7544
7545         u8         reserved_5[0x20];
7546
7547         u8         reserved_6[0x4];
7548         u8         phase_grade_type[0x4];
7549         u8         phase_grade[0x18];
7550
7551         u8         reserved_7[0x8];
7552         u8         phase_eo_pos[0x8];
7553         u8         reserved_8[0x8];
7554         u8         phase_eo_neg[0x8];
7555
7556         u8         ffe_set_tested[0x10];
7557         u8         test_errors_per_lane[0x10];
7558 };
7559
7560 struct mlx5_ifc_pvlc_reg_bits {
7561         u8         reserved_0[0x8];
7562         u8         local_port[0x8];
7563         u8         reserved_1[0x10];
7564
7565         u8         reserved_2[0x1c];
7566         u8         vl_hw_cap[0x4];
7567
7568         u8         reserved_3[0x1c];
7569         u8         vl_admin[0x4];
7570
7571         u8         reserved_4[0x1c];
7572         u8         vl_operational[0x4];
7573 };
7574
7575 struct mlx5_ifc_pude_reg_bits {
7576         u8         swid[0x8];
7577         u8         local_port[0x8];
7578         u8         reserved_0[0x4];
7579         u8         admin_status[0x4];
7580         u8         reserved_1[0x4];
7581         u8         oper_status[0x4];
7582
7583         u8         reserved_2[0x60];
7584 };
7585
7586 enum {
7587         MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
7588         MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
7589 };
7590
7591 struct mlx5_ifc_ptys_reg_bits {
7592         u8         reserved_0[0x1];
7593         u8         an_disable_admin[0x1];
7594         u8         an_disable_cap[0x1];
7595         u8         reserved_1[0x4];
7596         u8         force_tx_aba_param[0x1];
7597         u8         local_port[0x8];
7598         u8         reserved_2[0xd];
7599         u8         proto_mask[0x3];
7600
7601         u8         an_status[0x4];
7602         u8         reserved_3[0xc];
7603         u8         data_rate_oper[0x10];
7604
7605         u8         fc_proto_capability[0x20];
7606
7607         u8         eth_proto_capability[0x20];
7608
7609         u8         ib_link_width_capability[0x10];
7610         u8         ib_proto_capability[0x10];
7611
7612         u8         fc_proto_admin[0x20];
7613
7614         u8         eth_proto_admin[0x20];
7615
7616         u8         ib_link_width_admin[0x10];
7617         u8         ib_proto_admin[0x10];
7618
7619         u8         fc_proto_oper[0x20];
7620
7621         u8         eth_proto_oper[0x20];
7622
7623         u8         ib_link_width_oper[0x10];
7624         u8         ib_proto_oper[0x10];
7625
7626         u8         reserved_4[0x20];
7627
7628         u8         eth_proto_lp_advertise[0x20];
7629
7630         u8         reserved_5[0x60];
7631 };
7632
7633 struct mlx5_ifc_ptas_reg_bits {
7634         u8         reserved_0[0x20];
7635
7636         u8         algorithm_options[0x10];
7637         u8         reserved_1[0x4];
7638         u8         repetitions_mode[0x4];
7639         u8         num_of_repetitions[0x8];
7640
7641         u8         grade_version[0x8];
7642         u8         height_grade_type[0x4];
7643         u8         phase_grade_type[0x4];
7644         u8         height_grade_weight[0x8];
7645         u8         phase_grade_weight[0x8];
7646
7647         u8         gisim_measure_bits[0x10];
7648         u8         adaptive_tap_measure_bits[0x10];
7649
7650         u8         ber_bath_high_error_threshold[0x10];
7651         u8         ber_bath_mid_error_threshold[0x10];
7652
7653         u8         ber_bath_low_error_threshold[0x10];
7654         u8         one_ratio_high_threshold[0x10];
7655
7656         u8         one_ratio_high_mid_threshold[0x10];
7657         u8         one_ratio_low_mid_threshold[0x10];
7658
7659         u8         one_ratio_low_threshold[0x10];
7660         u8         ndeo_error_threshold[0x10];
7661
7662         u8         mixer_offset_step_size[0x10];
7663         u8         reserved_2[0x8];
7664         u8         mix90_phase_for_voltage_bath[0x8];
7665
7666         u8         mixer_offset_start[0x10];
7667         u8         mixer_offset_end[0x10];
7668
7669         u8         reserved_3[0x15];
7670         u8         ber_test_time[0xb];
7671 };
7672
7673 struct mlx5_ifc_pspa_reg_bits {
7674         u8         swid[0x8];
7675         u8         local_port[0x8];
7676         u8         sub_port[0x8];
7677         u8         reserved_0[0x8];
7678
7679         u8         reserved_1[0x20];
7680 };
7681
7682 struct mlx5_ifc_ppsc_reg_bits {
7683         u8         reserved_0[0x8];
7684         u8         local_port[0x8];
7685         u8         reserved_1[0x10];
7686
7687         u8         reserved_2[0x60];
7688
7689         u8         reserved_3[0x1c];
7690         u8         wrps_admin[0x4];
7691
7692         u8         reserved_4[0x1c];
7693         u8         wrps_status[0x4];
7694
7695         u8         up_th_vld[0x1];
7696         u8         down_th_vld[0x1];
7697         u8         reserved_5[0x6];
7698         u8         up_threshold[0x8];
7699         u8         reserved_6[0x8];
7700         u8         down_threshold[0x8];
7701
7702         u8         reserved_7[0x20];
7703
7704         u8         reserved_8[0x1c];
7705         u8         srps_admin[0x4];
7706
7707         u8         reserved_9[0x60];
7708 };
7709
7710 struct mlx5_ifc_pplr_reg_bits {
7711         u8         reserved_0[0x8];
7712         u8         local_port[0x8];
7713         u8         reserved_1[0x10];
7714
7715         u8         reserved_2[0x8];
7716         u8         lb_cap[0x8];
7717         u8         reserved_3[0x8];
7718         u8         lb_en[0x8];
7719 };
7720
7721 struct mlx5_ifc_pplm_reg_bits {
7722         u8         reserved_0[0x8];
7723         u8         local_port[0x8];
7724         u8         reserved_1[0x10];
7725
7726         u8         reserved_2[0x20];
7727
7728         u8         port_profile_mode[0x8];
7729         u8         static_port_profile[0x8];
7730         u8         active_port_profile[0x8];
7731         u8         reserved_3[0x8];
7732
7733         u8         retransmission_active[0x8];
7734         u8         fec_mode_active[0x18];
7735
7736         u8         reserved_4[0x10];
7737         u8         v_100g_fec_override_cap[0x4];
7738         u8         v_50g_fec_override_cap[0x4];
7739         u8         v_25g_fec_override_cap[0x4];
7740         u8         v_10g_40g_fec_override_cap[0x4];
7741
7742         u8         reserved_5[0x10];
7743         u8         v_100g_fec_override_admin[0x4];
7744         u8         v_50g_fec_override_admin[0x4];
7745         u8         v_25g_fec_override_admin[0x4];
7746         u8         v_10g_40g_fec_override_admin[0x4];
7747 };
7748
7749 struct mlx5_ifc_ppll_reg_bits {
7750         u8         num_pll_groups[0x8];
7751         u8         pll_group[0x8];
7752         u8         reserved_0[0x4];
7753         u8         num_plls[0x4];
7754         u8         reserved_1[0x8];
7755
7756         u8         reserved_2[0x1f];
7757         u8         ae[0x1];
7758
7759         u8         pll_status[4][0x40];
7760 };
7761
7762 struct mlx5_ifc_ppad_reg_bits {
7763         u8         reserved_0[0x3];
7764         u8         single_mac[0x1];
7765         u8         reserved_1[0x4];
7766         u8         local_port[0x8];
7767         u8         mac_47_32[0x10];
7768
7769         u8         mac_31_0[0x20];
7770
7771         u8         reserved_2[0x40];
7772 };
7773
7774 struct mlx5_ifc_pmtu_reg_bits {
7775         u8         reserved_0[0x8];
7776         u8         local_port[0x8];
7777         u8         reserved_1[0x10];
7778
7779         u8         max_mtu[0x10];
7780         u8         reserved_2[0x10];
7781
7782         u8         admin_mtu[0x10];
7783         u8         reserved_3[0x10];
7784
7785         u8         oper_mtu[0x10];
7786         u8         reserved_4[0x10];
7787 };
7788
7789 struct mlx5_ifc_pmpr_reg_bits {
7790         u8         reserved_0[0x8];
7791         u8         module[0x8];
7792         u8         reserved_1[0x10];
7793
7794         u8         reserved_2[0x18];
7795         u8         attenuation_5g[0x8];
7796
7797         u8         reserved_3[0x18];
7798         u8         attenuation_7g[0x8];
7799
7800         u8         reserved_4[0x18];
7801         u8         attenuation_12g[0x8];
7802 };
7803
7804 struct mlx5_ifc_pmpe_reg_bits {
7805         u8         reserved_0[0x8];
7806         u8         module[0x8];
7807         u8         reserved_1[0xc];
7808         u8         module_status[0x4];
7809
7810         u8         reserved_2[0x14];
7811         u8         error_type[0x4];
7812         u8         reserved_3[0x8];
7813
7814         u8         reserved_4[0x40];
7815 };
7816
7817 struct mlx5_ifc_pmpc_reg_bits {
7818         u8         module_state_updated[32][0x8];
7819 };
7820
7821 struct mlx5_ifc_pmlpn_reg_bits {
7822         u8         reserved_0[0x4];
7823         u8         mlpn_status[0x4];
7824         u8         local_port[0x8];
7825         u8         reserved_1[0x10];
7826
7827         u8         e[0x1];
7828         u8         reserved_2[0x1f];
7829 };
7830
7831 struct mlx5_ifc_pmlp_reg_bits {
7832         u8         rxtx[0x1];
7833         u8         reserved_0[0x7];
7834         u8         local_port[0x8];
7835         u8         reserved_1[0x8];
7836         u8         width[0x8];
7837
7838         u8         lane0_module_mapping[0x20];
7839
7840         u8         lane1_module_mapping[0x20];
7841
7842         u8         lane2_module_mapping[0x20];
7843
7844         u8         lane3_module_mapping[0x20];
7845
7846         u8         reserved_2[0x160];
7847 };
7848
7849 struct mlx5_ifc_pmaos_reg_bits {
7850         u8         reserved_0[0x8];
7851         u8         module[0x8];
7852         u8         reserved_1[0x4];
7853         u8         admin_status[0x4];
7854         u8         reserved_2[0x4];
7855         u8         oper_status[0x4];
7856
7857         u8         ase[0x1];
7858         u8         ee[0x1];
7859         u8         reserved_3[0x12];
7860         u8         error_type[0x4];
7861         u8         reserved_4[0x6];
7862         u8         e[0x2];
7863
7864         u8         reserved_5[0x40];
7865 };
7866
7867 struct mlx5_ifc_plpc_reg_bits {
7868         u8         reserved_0[0x4];
7869         u8         profile_id[0xc];
7870         u8         reserved_1[0x4];
7871         u8         proto_mask[0x4];
7872         u8         reserved_2[0x8];
7873
7874         u8         reserved_3[0x10];
7875         u8         lane_speed[0x10];
7876
7877         u8         reserved_4[0x17];
7878         u8         lpbf[0x1];
7879         u8         fec_mode_policy[0x8];
7880
7881         u8         retransmission_capability[0x8];
7882         u8         fec_mode_capability[0x18];
7883
7884         u8         retransmission_support_admin[0x8];
7885         u8         fec_mode_support_admin[0x18];
7886
7887         u8         retransmission_request_admin[0x8];
7888         u8         fec_mode_request_admin[0x18];
7889
7890         u8         reserved_5[0x80];
7891 };
7892
7893 struct mlx5_ifc_pll_status_data_bits {
7894         u8         reserved_0[0x1];
7895         u8         lock_cal[0x1];
7896         u8         lock_status[0x2];
7897         u8         reserved_1[0x2];
7898         u8         algo_f_ctrl[0xa];
7899         u8         analog_algo_num_var[0x6];
7900         u8         f_ctrl_measure[0xa];
7901
7902         u8         reserved_2[0x2];
7903         u8         analog_var[0x6];
7904         u8         reserved_3[0x2];
7905         u8         high_var[0x6];
7906         u8         reserved_4[0x2];
7907         u8         low_var[0x6];
7908         u8         reserved_5[0x2];
7909         u8         mid_val[0x6];
7910 };
7911
7912 struct mlx5_ifc_plib_reg_bits {
7913         u8         reserved_0[0x8];
7914         u8         local_port[0x8];
7915         u8         reserved_1[0x8];
7916         u8         ib_port[0x8];
7917
7918         u8         reserved_2[0x60];
7919 };
7920
7921 struct mlx5_ifc_plbf_reg_bits {
7922         u8         reserved_0[0x8];
7923         u8         local_port[0x8];
7924         u8         reserved_1[0xd];
7925         u8         lbf_mode[0x3];
7926
7927         u8         reserved_2[0x20];
7928 };
7929
7930 struct mlx5_ifc_pipg_reg_bits {
7931         u8         reserved_0[0x8];
7932         u8         local_port[0x8];
7933         u8         reserved_1[0x10];
7934
7935         u8         dic[0x1];
7936         u8         reserved_2[0x19];
7937         u8         ipg[0x4];
7938         u8         reserved_3[0x2];
7939 };
7940
7941 struct mlx5_ifc_pifr_reg_bits {
7942         u8         reserved_0[0x8];
7943         u8         local_port[0x8];
7944         u8         reserved_1[0x10];
7945
7946         u8         reserved_2[0xe0];
7947
7948         u8         port_filter[8][0x20];
7949
7950         u8         port_filter_update_en[8][0x20];
7951 };
7952
7953 struct mlx5_ifc_phys_layer_cntrs_bits {
7954         u8         time_since_last_clear_high[0x20];
7955
7956         u8         time_since_last_clear_low[0x20];
7957
7958         u8         symbol_errors_high[0x20];
7959
7960         u8         symbol_errors_low[0x20];
7961
7962         u8         sync_headers_errors_high[0x20];
7963
7964         u8         sync_headers_errors_low[0x20];
7965
7966         u8         edpl_bip_errors_lane0_high[0x20];
7967
7968         u8         edpl_bip_errors_lane0_low[0x20];
7969
7970         u8         edpl_bip_errors_lane1_high[0x20];
7971
7972         u8         edpl_bip_errors_lane1_low[0x20];
7973
7974         u8         edpl_bip_errors_lane2_high[0x20];
7975
7976         u8         edpl_bip_errors_lane2_low[0x20];
7977
7978         u8         edpl_bip_errors_lane3_high[0x20];
7979
7980         u8         edpl_bip_errors_lane3_low[0x20];
7981
7982         u8         fc_fec_corrected_blocks_lane0_high[0x20];
7983
7984         u8         fc_fec_corrected_blocks_lane0_low[0x20];
7985
7986         u8         fc_fec_corrected_blocks_lane1_high[0x20];
7987
7988         u8         fc_fec_corrected_blocks_lane1_low[0x20];
7989
7990         u8         fc_fec_corrected_blocks_lane2_high[0x20];
7991
7992         u8         fc_fec_corrected_blocks_lane2_low[0x20];
7993
7994         u8         fc_fec_corrected_blocks_lane3_high[0x20];
7995
7996         u8         fc_fec_corrected_blocks_lane3_low[0x20];
7997
7998         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
7999
8000         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8001
8002         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8003
8004         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8005
8006         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8007
8008         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8009
8010         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8011
8012         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8013
8014         u8         rs_fec_corrected_blocks_high[0x20];
8015
8016         u8         rs_fec_corrected_blocks_low[0x20];
8017
8018         u8         rs_fec_uncorrectable_blocks_high[0x20];
8019
8020         u8         rs_fec_uncorrectable_blocks_low[0x20];
8021
8022         u8         rs_fec_no_errors_blocks_high[0x20];
8023
8024         u8         rs_fec_no_errors_blocks_low[0x20];
8025
8026         u8         rs_fec_single_error_blocks_high[0x20];
8027
8028         u8         rs_fec_single_error_blocks_low[0x20];
8029
8030         u8         rs_fec_corrected_symbols_total_high[0x20];
8031
8032         u8         rs_fec_corrected_symbols_total_low[0x20];
8033
8034         u8         rs_fec_corrected_symbols_lane0_high[0x20];
8035
8036         u8         rs_fec_corrected_symbols_lane0_low[0x20];
8037
8038         u8         rs_fec_corrected_symbols_lane1_high[0x20];
8039
8040         u8         rs_fec_corrected_symbols_lane1_low[0x20];
8041
8042         u8         rs_fec_corrected_symbols_lane2_high[0x20];
8043
8044         u8         rs_fec_corrected_symbols_lane2_low[0x20];
8045
8046         u8         rs_fec_corrected_symbols_lane3_high[0x20];
8047
8048         u8         rs_fec_corrected_symbols_lane3_low[0x20];
8049
8050         u8         link_down_events[0x20];
8051
8052         u8         successful_recovery_events[0x20];
8053
8054         u8         reserved_0[0x180];
8055 };
8056
8057 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8058         u8         time_since_last_clear_high[0x20];
8059
8060         u8         time_since_last_clear_low[0x20];
8061
8062         u8         phy_received_bits_high[0x20];
8063
8064         u8         phy_received_bits_low[0x20];
8065
8066         u8         phy_symbol_errors_high[0x20];
8067
8068         u8         phy_symbol_errors_low[0x20];
8069
8070         u8         phy_corrected_bits_high[0x20];
8071
8072         u8         phy_corrected_bits_low[0x20];
8073
8074         u8         phy_corrected_bits_lane0_high[0x20];
8075
8076         u8         phy_corrected_bits_lane0_low[0x20];
8077
8078         u8         phy_corrected_bits_lane1_high[0x20];
8079
8080         u8         phy_corrected_bits_lane1_low[0x20];
8081
8082         u8         phy_corrected_bits_lane2_high[0x20];
8083
8084         u8         phy_corrected_bits_lane2_low[0x20];
8085
8086         u8         phy_corrected_bits_lane3_high[0x20];
8087
8088         u8         phy_corrected_bits_lane3_low[0x20];
8089
8090         u8         reserved_at_200[0x5c0];
8091 };
8092
8093 struct mlx5_ifc_infiniband_port_cntrs_bits {
8094         u8         symbol_error_counter[0x10];
8095         u8         link_error_recovery_counter[0x8];
8096         u8         link_downed_counter[0x8];
8097
8098         u8         port_rcv_errors[0x10];
8099         u8         port_rcv_remote_physical_errors[0x10];
8100
8101         u8         port_rcv_switch_relay_errors[0x10];
8102         u8         port_xmit_discards[0x10];
8103
8104         u8         port_xmit_constraint_errors[0x8];
8105         u8         port_rcv_constraint_errors[0x8];
8106         u8         reserved_0[0x8];
8107         u8         local_link_integrity_errors[0x4];
8108         u8         excessive_buffer_overrun_errors[0x4];
8109
8110         u8         reserved_1[0x10];
8111         u8         vl_15_dropped[0x10];
8112
8113         u8         port_xmit_data[0x20];
8114
8115         u8         port_rcv_data[0x20];
8116
8117         u8         port_xmit_pkts[0x20];
8118
8119         u8         port_rcv_pkts[0x20];
8120
8121         u8         port_xmit_wait[0x20];
8122
8123         u8         reserved_2[0x680];
8124 };
8125
8126 struct mlx5_ifc_phrr_reg_bits {
8127         u8         clr[0x1];
8128         u8         reserved_0[0x7];
8129         u8         local_port[0x8];
8130         u8         reserved_1[0x10];
8131
8132         u8         hist_group[0x8];
8133         u8         reserved_2[0x10];
8134         u8         hist_id[0x8];
8135
8136         u8         reserved_3[0x40];
8137
8138         u8         time_since_last_clear_high[0x20];
8139
8140         u8         time_since_last_clear_low[0x20];
8141
8142         u8         bin[10][0x20];
8143 };
8144
8145 struct mlx5_ifc_phbr_for_prio_reg_bits {
8146         u8         reserved_0[0x18];
8147         u8         prio[0x8];
8148 };
8149
8150 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8151         u8         reserved_0[0x18];
8152         u8         tclass[0x8];
8153 };
8154
8155 struct mlx5_ifc_phbr_binding_reg_bits {
8156         u8         opcode[0x4];
8157         u8         reserved_0[0x4];
8158         u8         local_port[0x8];
8159         u8         pnat[0x2];
8160         u8         reserved_1[0xe];
8161
8162         u8         hist_group[0x8];
8163         u8         reserved_2[0x10];
8164         u8         hist_id[0x8];
8165
8166         u8         reserved_3[0x10];
8167         u8         hist_type[0x10];
8168
8169         u8         hist_parameters[0x20];
8170
8171         u8         hist_min_value[0x20];
8172
8173         u8         hist_max_value[0x20];
8174
8175         u8         sample_time[0x20];
8176 };
8177
8178 enum {
8179         MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8180         MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8181 };
8182
8183 struct mlx5_ifc_pfcc_reg_bits {
8184         u8         dcbx_operation_type[0x2];
8185         u8         cap_local_admin[0x1];
8186         u8         cap_remote_admin[0x1];
8187         u8         reserved_0[0x4];
8188         u8         local_port[0x8];
8189         u8         pnat[0x2];
8190         u8         reserved_1[0xc];
8191         u8         shl_cap[0x1];
8192         u8         shl_opr[0x1];
8193
8194         u8         ppan[0x4];
8195         u8         reserved_2[0x4];
8196         u8         prio_mask_tx[0x8];
8197         u8         reserved_3[0x8];
8198         u8         prio_mask_rx[0x8];
8199
8200         u8         pptx[0x1];
8201         u8         aptx[0x1];
8202         u8         reserved_4[0x6];
8203         u8         pfctx[0x8];
8204         u8         reserved_5[0x8];
8205         u8         cbftx[0x8];
8206
8207         u8         pprx[0x1];
8208         u8         aprx[0x1];
8209         u8         reserved_6[0x6];
8210         u8         pfcrx[0x8];
8211         u8         reserved_7[0x8];
8212         u8         cbfrx[0x8];
8213
8214         u8         device_stall_minor_watermark[0x10];
8215         u8         device_stall_critical_watermark[0x10];
8216
8217         u8         reserved_8[0x60];
8218 };
8219
8220 struct mlx5_ifc_pelc_reg_bits {
8221         u8         op[0x4];
8222         u8         reserved_0[0x4];
8223         u8         local_port[0x8];
8224         u8         reserved_1[0x10];
8225
8226         u8         op_admin[0x8];
8227         u8         op_capability[0x8];
8228         u8         op_request[0x8];
8229         u8         op_active[0x8];
8230
8231         u8         admin[0x40];
8232
8233         u8         capability[0x40];
8234
8235         u8         request[0x40];
8236
8237         u8         active[0x40];
8238
8239         u8         reserved_2[0x80];
8240 };
8241
8242 struct mlx5_ifc_peir_reg_bits {
8243         u8         reserved_0[0x8];
8244         u8         local_port[0x8];
8245         u8         reserved_1[0x10];
8246
8247         u8         reserved_2[0xc];
8248         u8         error_count[0x4];
8249         u8         reserved_3[0x10];
8250
8251         u8         reserved_4[0xc];
8252         u8         lane[0x4];
8253         u8         reserved_5[0x8];
8254         u8         error_type[0x8];
8255 };
8256
8257 struct mlx5_ifc_pcap_reg_bits {
8258         u8         reserved_0[0x8];
8259         u8         local_port[0x8];
8260         u8         reserved_1[0x10];
8261
8262         u8         port_capability_mask[4][0x20];
8263 };
8264
8265 struct mlx5_ifc_pbmc_reg_bits {
8266         u8         reserved_0[0x8];
8267         u8         local_port[0x8];
8268         u8         reserved_1[0x10];
8269
8270         u8         xoff_timer_value[0x10];
8271         u8         xoff_refresh[0x10];
8272
8273         u8         reserved_2[0x10];
8274         u8         port_buffer_size[0x10];
8275
8276         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8277
8278         u8         reserved_3[0x40];
8279
8280         u8         port_shared_buffer[0x40];
8281 };
8282
8283 struct mlx5_ifc_paos_reg_bits {
8284         u8         swid[0x8];
8285         u8         local_port[0x8];
8286         u8         reserved_0[0x4];
8287         u8         admin_status[0x4];
8288         u8         reserved_1[0x4];
8289         u8         oper_status[0x4];
8290
8291         u8         ase[0x1];
8292         u8         ee[0x1];
8293         u8         reserved_2[0x1c];
8294         u8         e[0x2];
8295
8296         u8         reserved_3[0x40];
8297 };
8298
8299 struct mlx5_ifc_pamp_reg_bits {
8300         u8         reserved_0[0x8];
8301         u8         opamp_group[0x8];
8302         u8         reserved_1[0xc];
8303         u8         opamp_group_type[0x4];
8304
8305         u8         start_index[0x10];
8306         u8         reserved_2[0x4];
8307         u8         num_of_indices[0xc];
8308
8309         u8         index_data[18][0x10];
8310 };
8311
8312 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
8313         u8         llr_rx_cells_high[0x20];
8314
8315         u8         llr_rx_cells_low[0x20];
8316
8317         u8         llr_rx_error_high[0x20];
8318
8319         u8         llr_rx_error_low[0x20];
8320
8321         u8         llr_rx_crc_error_high[0x20];
8322
8323         u8         llr_rx_crc_error_low[0x20];
8324
8325         u8         llr_tx_cells_high[0x20];
8326
8327         u8         llr_tx_cells_low[0x20];
8328
8329         u8         llr_tx_ret_cells_high[0x20];
8330
8331         u8         llr_tx_ret_cells_low[0x20];
8332
8333         u8         llr_tx_ret_events_high[0x20];
8334
8335         u8         llr_tx_ret_events_low[0x20];
8336
8337         u8         reserved_0[0x640];
8338 };
8339
8340 struct mlx5_ifc_lane_2_module_mapping_bits {
8341         u8         reserved_0[0x6];
8342         u8         rx_lane[0x2];
8343         u8         reserved_1[0x6];
8344         u8         tx_lane[0x2];
8345         u8         reserved_2[0x8];
8346         u8         module[0x8];
8347 };
8348
8349 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
8350         u8         transmit_queue_high[0x20];
8351
8352         u8         transmit_queue_low[0x20];
8353
8354         u8         reserved_0[0x780];
8355 };
8356
8357 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
8358         u8         no_buffer_discard_uc_high[0x20];
8359
8360         u8         no_buffer_discard_uc_low[0x20];
8361
8362         u8         wred_discard_high[0x20];
8363
8364         u8         wred_discard_low[0x20];
8365
8366         u8         reserved_0[0x740];
8367 };
8368
8369 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
8370         u8         rx_octets_high[0x20];
8371
8372         u8         rx_octets_low[0x20];
8373
8374         u8         reserved_0[0xc0];
8375
8376         u8         rx_frames_high[0x20];
8377
8378         u8         rx_frames_low[0x20];
8379
8380         u8         tx_octets_high[0x20];
8381
8382         u8         tx_octets_low[0x20];
8383
8384         u8         reserved_1[0xc0];
8385
8386         u8         tx_frames_high[0x20];
8387
8388         u8         tx_frames_low[0x20];
8389
8390         u8         rx_pause_high[0x20];
8391
8392         u8         rx_pause_low[0x20];
8393
8394         u8         rx_pause_duration_high[0x20];
8395
8396         u8         rx_pause_duration_low[0x20];
8397
8398         u8         tx_pause_high[0x20];
8399
8400         u8         tx_pause_low[0x20];
8401
8402         u8         tx_pause_duration_high[0x20];
8403
8404         u8         tx_pause_duration_low[0x20];
8405
8406         u8         rx_pause_transition_high[0x20];
8407
8408         u8         rx_pause_transition_low[0x20];
8409
8410         u8         rx_discards_high[0x20];
8411
8412         u8         rx_discards_low[0x20];
8413
8414         u8         device_stall_minor_watermark_cnt_high[0x20];
8415
8416         u8         device_stall_minor_watermark_cnt_low[0x20];
8417
8418         u8         device_stall_critical_watermark_cnt_high[0x20];
8419
8420         u8         device_stall_critical_watermark_cnt_low[0x20];
8421
8422         u8         reserved_2[0x340];
8423 };
8424
8425 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
8426         u8         port_transmit_wait_high[0x20];
8427
8428         u8         port_transmit_wait_low[0x20];
8429
8430         u8         ecn_marked_high[0x20];
8431
8432         u8         ecn_marked_low[0x20];
8433
8434         u8         no_buffer_discard_mc_high[0x20];
8435
8436         u8         no_buffer_discard_mc_low[0x20];
8437
8438         u8         reserved_0[0x700];
8439 };
8440
8441 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
8442         u8         a_frames_transmitted_ok_high[0x20];
8443
8444         u8         a_frames_transmitted_ok_low[0x20];
8445
8446         u8         a_frames_received_ok_high[0x20];
8447
8448         u8         a_frames_received_ok_low[0x20];
8449
8450         u8         a_frame_check_sequence_errors_high[0x20];
8451
8452         u8         a_frame_check_sequence_errors_low[0x20];
8453
8454         u8         a_alignment_errors_high[0x20];
8455
8456         u8         a_alignment_errors_low[0x20];
8457
8458         u8         a_octets_transmitted_ok_high[0x20];
8459
8460         u8         a_octets_transmitted_ok_low[0x20];
8461
8462         u8         a_octets_received_ok_high[0x20];
8463
8464         u8         a_octets_received_ok_low[0x20];
8465
8466         u8         a_multicast_frames_xmitted_ok_high[0x20];
8467
8468         u8         a_multicast_frames_xmitted_ok_low[0x20];
8469
8470         u8         a_broadcast_frames_xmitted_ok_high[0x20];
8471
8472         u8         a_broadcast_frames_xmitted_ok_low[0x20];
8473
8474         u8         a_multicast_frames_received_ok_high[0x20];
8475
8476         u8         a_multicast_frames_received_ok_low[0x20];
8477
8478         u8         a_broadcast_frames_recieved_ok_high[0x20];
8479
8480         u8         a_broadcast_frames_recieved_ok_low[0x20];
8481
8482         u8         a_in_range_length_errors_high[0x20];
8483
8484         u8         a_in_range_length_errors_low[0x20];
8485
8486         u8         a_out_of_range_length_field_high[0x20];
8487
8488         u8         a_out_of_range_length_field_low[0x20];
8489
8490         u8         a_frame_too_long_errors_high[0x20];
8491
8492         u8         a_frame_too_long_errors_low[0x20];
8493
8494         u8         a_symbol_error_during_carrier_high[0x20];
8495
8496         u8         a_symbol_error_during_carrier_low[0x20];
8497
8498         u8         a_mac_control_frames_transmitted_high[0x20];
8499
8500         u8         a_mac_control_frames_transmitted_low[0x20];
8501
8502         u8         a_mac_control_frames_received_high[0x20];
8503
8504         u8         a_mac_control_frames_received_low[0x20];
8505
8506         u8         a_unsupported_opcodes_received_high[0x20];
8507
8508         u8         a_unsupported_opcodes_received_low[0x20];
8509
8510         u8         a_pause_mac_ctrl_frames_received_high[0x20];
8511
8512         u8         a_pause_mac_ctrl_frames_received_low[0x20];
8513
8514         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
8515
8516         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
8517
8518         u8         reserved_0[0x300];
8519 };
8520
8521 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
8522         u8         dot3stats_alignment_errors_high[0x20];
8523
8524         u8         dot3stats_alignment_errors_low[0x20];
8525
8526         u8         dot3stats_fcs_errors_high[0x20];
8527
8528         u8         dot3stats_fcs_errors_low[0x20];
8529
8530         u8         dot3stats_single_collision_frames_high[0x20];
8531
8532         u8         dot3stats_single_collision_frames_low[0x20];
8533
8534         u8         dot3stats_multiple_collision_frames_high[0x20];
8535
8536         u8         dot3stats_multiple_collision_frames_low[0x20];
8537
8538         u8         dot3stats_sqe_test_errors_high[0x20];
8539
8540         u8         dot3stats_sqe_test_errors_low[0x20];
8541
8542         u8         dot3stats_deferred_transmissions_high[0x20];
8543
8544         u8         dot3stats_deferred_transmissions_low[0x20];
8545
8546         u8         dot3stats_late_collisions_high[0x20];
8547
8548         u8         dot3stats_late_collisions_low[0x20];
8549
8550         u8         dot3stats_excessive_collisions_high[0x20];
8551
8552         u8         dot3stats_excessive_collisions_low[0x20];
8553
8554         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
8555
8556         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
8557
8558         u8         dot3stats_carrier_sense_errors_high[0x20];
8559
8560         u8         dot3stats_carrier_sense_errors_low[0x20];
8561
8562         u8         dot3stats_frame_too_longs_high[0x20];
8563
8564         u8         dot3stats_frame_too_longs_low[0x20];
8565
8566         u8         dot3stats_internal_mac_receive_errors_high[0x20];
8567
8568         u8         dot3stats_internal_mac_receive_errors_low[0x20];
8569
8570         u8         dot3stats_symbol_errors_high[0x20];
8571
8572         u8         dot3stats_symbol_errors_low[0x20];
8573
8574         u8         dot3control_in_unknown_opcodes_high[0x20];
8575
8576         u8         dot3control_in_unknown_opcodes_low[0x20];
8577
8578         u8         dot3in_pause_frames_high[0x20];
8579
8580         u8         dot3in_pause_frames_low[0x20];
8581
8582         u8         dot3out_pause_frames_high[0x20];
8583
8584         u8         dot3out_pause_frames_low[0x20];
8585
8586         u8         reserved_0[0x3c0];
8587 };
8588
8589 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
8590         u8         if_in_octets_high[0x20];
8591
8592         u8         if_in_octets_low[0x20];
8593
8594         u8         if_in_ucast_pkts_high[0x20];
8595
8596         u8         if_in_ucast_pkts_low[0x20];
8597
8598         u8         if_in_discards_high[0x20];
8599
8600         u8         if_in_discards_low[0x20];
8601
8602         u8         if_in_errors_high[0x20];
8603
8604         u8         if_in_errors_low[0x20];
8605
8606         u8         if_in_unknown_protos_high[0x20];
8607
8608         u8         if_in_unknown_protos_low[0x20];
8609
8610         u8         if_out_octets_high[0x20];
8611
8612         u8         if_out_octets_low[0x20];
8613
8614         u8         if_out_ucast_pkts_high[0x20];
8615
8616         u8         if_out_ucast_pkts_low[0x20];
8617
8618         u8         if_out_discards_high[0x20];
8619
8620         u8         if_out_discards_low[0x20];
8621
8622         u8         if_out_errors_high[0x20];
8623
8624         u8         if_out_errors_low[0x20];
8625
8626         u8         if_in_multicast_pkts_high[0x20];
8627
8628         u8         if_in_multicast_pkts_low[0x20];
8629
8630         u8         if_in_broadcast_pkts_high[0x20];
8631
8632         u8         if_in_broadcast_pkts_low[0x20];
8633
8634         u8         if_out_multicast_pkts_high[0x20];
8635
8636         u8         if_out_multicast_pkts_low[0x20];
8637
8638         u8         if_out_broadcast_pkts_high[0x20];
8639
8640         u8         if_out_broadcast_pkts_low[0x20];
8641
8642         u8         reserved_0[0x480];
8643 };
8644
8645 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
8646         u8         ether_stats_drop_events_high[0x20];
8647
8648         u8         ether_stats_drop_events_low[0x20];
8649
8650         u8         ether_stats_octets_high[0x20];
8651
8652         u8         ether_stats_octets_low[0x20];
8653
8654         u8         ether_stats_pkts_high[0x20];
8655
8656         u8         ether_stats_pkts_low[0x20];
8657
8658         u8         ether_stats_broadcast_pkts_high[0x20];
8659
8660         u8         ether_stats_broadcast_pkts_low[0x20];
8661
8662         u8         ether_stats_multicast_pkts_high[0x20];
8663
8664         u8         ether_stats_multicast_pkts_low[0x20];
8665
8666         u8         ether_stats_crc_align_errors_high[0x20];
8667
8668         u8         ether_stats_crc_align_errors_low[0x20];
8669
8670         u8         ether_stats_undersize_pkts_high[0x20];
8671
8672         u8         ether_stats_undersize_pkts_low[0x20];
8673
8674         u8         ether_stats_oversize_pkts_high[0x20];
8675
8676         u8         ether_stats_oversize_pkts_low[0x20];
8677
8678         u8         ether_stats_fragments_high[0x20];
8679
8680         u8         ether_stats_fragments_low[0x20];
8681
8682         u8         ether_stats_jabbers_high[0x20];
8683
8684         u8         ether_stats_jabbers_low[0x20];
8685
8686         u8         ether_stats_collisions_high[0x20];
8687
8688         u8         ether_stats_collisions_low[0x20];
8689
8690         u8         ether_stats_pkts64octets_high[0x20];
8691
8692         u8         ether_stats_pkts64octets_low[0x20];
8693
8694         u8         ether_stats_pkts65to127octets_high[0x20];
8695
8696         u8         ether_stats_pkts65to127octets_low[0x20];
8697
8698         u8         ether_stats_pkts128to255octets_high[0x20];
8699
8700         u8         ether_stats_pkts128to255octets_low[0x20];
8701
8702         u8         ether_stats_pkts256to511octets_high[0x20];
8703
8704         u8         ether_stats_pkts256to511octets_low[0x20];
8705
8706         u8         ether_stats_pkts512to1023octets_high[0x20];
8707
8708         u8         ether_stats_pkts512to1023octets_low[0x20];
8709
8710         u8         ether_stats_pkts1024to1518octets_high[0x20];
8711
8712         u8         ether_stats_pkts1024to1518octets_low[0x20];
8713
8714         u8         ether_stats_pkts1519to2047octets_high[0x20];
8715
8716         u8         ether_stats_pkts1519to2047octets_low[0x20];
8717
8718         u8         ether_stats_pkts2048to4095octets_high[0x20];
8719
8720         u8         ether_stats_pkts2048to4095octets_low[0x20];
8721
8722         u8         ether_stats_pkts4096to8191octets_high[0x20];
8723
8724         u8         ether_stats_pkts4096to8191octets_low[0x20];
8725
8726         u8         ether_stats_pkts8192to10239octets_high[0x20];
8727
8728         u8         ether_stats_pkts8192to10239octets_low[0x20];
8729
8730         u8         reserved_0[0x280];
8731 };
8732
8733 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
8734         u8         symbol_error_counter[0x10];
8735         u8         link_error_recovery_counter[0x8];
8736         u8         link_downed_counter[0x8];
8737
8738         u8         port_rcv_errors[0x10];
8739         u8         port_rcv_remote_physical_errors[0x10];
8740
8741         u8         port_rcv_switch_relay_errors[0x10];
8742         u8         port_xmit_discards[0x10];
8743
8744         u8         port_xmit_constraint_errors[0x8];
8745         u8         port_rcv_constraint_errors[0x8];
8746         u8         reserved_0[0x8];
8747         u8         local_link_integrity_errors[0x4];
8748         u8         excessive_buffer_overrun_errors[0x4];
8749
8750         u8         reserved_1[0x10];
8751         u8         vl_15_dropped[0x10];
8752
8753         u8         port_xmit_data[0x20];
8754
8755         u8         port_rcv_data[0x20];
8756
8757         u8         port_xmit_pkts[0x20];
8758
8759         u8         port_rcv_pkts[0x20];
8760
8761         u8         port_xmit_wait[0x20];
8762
8763         u8         reserved_2[0x680];
8764 };
8765
8766 struct mlx5_ifc_trc_tlb_reg_bits {
8767         u8         reserved_0[0x80];
8768
8769         u8         tlb_addr[0][0x40];
8770 };
8771
8772 struct mlx5_ifc_trc_read_fifo_reg_bits {
8773         u8         reserved_0[0x10];
8774         u8         requested_event_num[0x10];
8775
8776         u8         reserved_1[0x20];
8777
8778         u8         reserved_2[0x10];
8779         u8         acual_event_num[0x10];
8780
8781         u8         reserved_3[0x20];
8782
8783         u8         event[0][0x40];
8784 };
8785
8786 struct mlx5_ifc_trc_lock_reg_bits {
8787         u8         reserved_0[0x1f];
8788         u8         lock[0x1];
8789
8790         u8         reserved_1[0x60];
8791 };
8792
8793 struct mlx5_ifc_trc_filter_reg_bits {
8794         u8         status[0x1];
8795         u8         reserved_0[0xf];
8796         u8         filter_index[0x10];
8797
8798         u8         reserved_1[0x20];
8799
8800         u8         filter_val[0x20];
8801
8802         u8         reserved_2[0x1a0];
8803 };
8804
8805 struct mlx5_ifc_trc_event_reg_bits {
8806         u8         status[0x1];
8807         u8         reserved_0[0xf];
8808         u8         event_index[0x10];
8809
8810         u8         reserved_1[0x20];
8811
8812         u8         event_id[0x20];
8813
8814         u8         event_selector_val[0x10];
8815         u8         event_selector_size[0x10];
8816
8817         u8         reserved_2[0x180];
8818 };
8819
8820 struct mlx5_ifc_trc_conf_reg_bits {
8821         u8         limit_en[0x1];
8822         u8         reserved_0[0x3];
8823         u8         dump_mode[0x4];
8824         u8         reserved_1[0x15];
8825         u8         state[0x3];
8826
8827         u8         reserved_2[0x20];
8828
8829         u8         limit_event_index[0x20];
8830
8831         u8         mkey[0x20];
8832
8833         u8         fifo_ready_ev_num[0x20];
8834
8835         u8         reserved_3[0x160];
8836 };
8837
8838 struct mlx5_ifc_trc_cap_reg_bits {
8839         u8         reserved_0[0x18];
8840         u8         dump_mode[0x8];
8841
8842         u8         reserved_1[0x20];
8843
8844         u8         num_of_events[0x10];
8845         u8         num_of_filters[0x10];
8846
8847         u8         fifo_size[0x20];
8848
8849         u8         tlb_size[0x10];
8850         u8         event_size[0x10];
8851
8852         u8         reserved_2[0x160];
8853 };
8854
8855 struct mlx5_ifc_set_node_in_bits {
8856         u8         node_description[64][0x8];
8857 };
8858
8859 struct mlx5_ifc_register_power_settings_bits {
8860         u8         reserved_0[0x18];
8861         u8         power_settings_level[0x8];
8862
8863         u8         reserved_1[0x60];
8864 };
8865
8866 struct mlx5_ifc_register_host_endianess_bits {
8867         u8         he[0x1];
8868         u8         reserved_0[0x1f];
8869
8870         u8         reserved_1[0x60];
8871 };
8872
8873 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
8874         u8         physical_address[0x40];
8875 };
8876
8877 struct mlx5_ifc_qtct_reg_bits {
8878         u8         operation_type[0x2];
8879         u8         cap_local_admin[0x1];
8880         u8         cap_remote_admin[0x1];
8881         u8         reserved_0[0x4];
8882         u8         port_number[0x8];
8883         u8         reserved_1[0xd];
8884         u8         prio[0x3];
8885
8886         u8         reserved_2[0x1d];
8887         u8         tclass[0x3];
8888 };
8889
8890 struct mlx5_ifc_qpdp_reg_bits {
8891         u8         reserved_0[0x8];
8892         u8         port_number[0x8];
8893         u8         reserved_1[0x10];
8894
8895         u8         reserved_2[0x1d];
8896         u8         pprio[0x3];
8897 };
8898
8899 struct mlx5_ifc_port_info_ro_fields_param_bits {
8900         u8         reserved_0[0x8];
8901         u8         port[0x8];
8902         u8         max_gid[0x10];
8903
8904         u8         reserved_1[0x20];
8905
8906         u8         port_guid[0x40];
8907 };
8908
8909 struct mlx5_ifc_nvqc_reg_bits {
8910         u8         type[0x20];
8911
8912         u8         reserved_0[0x18];
8913         u8         version[0x4];
8914         u8         reserved_1[0x2];
8915         u8         support_wr[0x1];
8916         u8         support_rd[0x1];
8917 };
8918
8919 struct mlx5_ifc_nvia_reg_bits {
8920         u8         reserved_0[0x1d];
8921         u8         target[0x3];
8922
8923         u8         reserved_1[0x20];
8924 };
8925
8926 struct mlx5_ifc_nvdi_reg_bits {
8927         struct mlx5_ifc_config_item_bits configuration_item_header;
8928 };
8929
8930 struct mlx5_ifc_nvda_reg_bits {
8931         struct mlx5_ifc_config_item_bits configuration_item_header;
8932
8933         u8         configuration_item_data[0x20];
8934 };
8935
8936 struct mlx5_ifc_node_info_ro_fields_param_bits {
8937         u8         system_image_guid[0x40];
8938
8939         u8         reserved_0[0x40];
8940
8941         u8         node_guid[0x40];
8942
8943         u8         reserved_1[0x10];
8944         u8         max_pkey[0x10];
8945
8946         u8         reserved_2[0x20];
8947 };
8948
8949 struct mlx5_ifc_ets_tcn_config_reg_bits {
8950         u8         g[0x1];
8951         u8         b[0x1];
8952         u8         r[0x1];
8953         u8         reserved_0[0x9];
8954         u8         group[0x4];
8955         u8         reserved_1[0x9];
8956         u8         bw_allocation[0x7];
8957
8958         u8         reserved_2[0xc];
8959         u8         max_bw_units[0x4];
8960         u8         reserved_3[0x8];
8961         u8         max_bw_value[0x8];
8962 };
8963
8964 struct mlx5_ifc_ets_global_config_reg_bits {
8965         u8         reserved_0[0x2];
8966         u8         r[0x1];
8967         u8         reserved_1[0x1d];
8968
8969         u8         reserved_2[0xc];
8970         u8         max_bw_units[0x4];
8971         u8         reserved_3[0x8];
8972         u8         max_bw_value[0x8];
8973 };
8974
8975 struct mlx5_ifc_nodnic_mac_filters_bits {
8976         struct mlx5_ifc_mac_address_layout_bits mac_filter0;
8977
8978         struct mlx5_ifc_mac_address_layout_bits mac_filter1;
8979
8980         struct mlx5_ifc_mac_address_layout_bits mac_filter2;
8981
8982         struct mlx5_ifc_mac_address_layout_bits mac_filter3;
8983
8984         struct mlx5_ifc_mac_address_layout_bits mac_filter4;
8985
8986         u8         reserved_0[0xc0];
8987 };
8988
8989 struct mlx5_ifc_nodnic_gid_filters_bits {
8990         u8         mgid_filter0[16][0x8];
8991
8992         u8         mgid_filter1[16][0x8];
8993
8994         u8         mgid_filter2[16][0x8];
8995
8996         u8         mgid_filter3[16][0x8];
8997 };
8998
8999 enum {
9000         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9001         MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9002 };
9003
9004 enum {
9005         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9006         MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9007 };
9008
9009 struct mlx5_ifc_nodnic_config_reg_bits {
9010         u8         no_dram_nic_revision[0x8];
9011         u8         hardware_format[0x8];
9012         u8         support_receive_filter[0x1];
9013         u8         support_promisc_filter[0x1];
9014         u8         support_promisc_multicast_filter[0x1];
9015         u8         reserved_0[0x2];
9016         u8         log_working_buffer_size[0x3];
9017         u8         log_pkey_table_size[0x4];
9018         u8         reserved_1[0x3];
9019         u8         num_ports[0x1];
9020
9021         u8         reserved_2[0x2];
9022         u8         log_max_ring_size[0x6];
9023         u8         reserved_3[0x18];
9024
9025         u8         lkey[0x20];
9026
9027         u8         cqe_format[0x4];
9028         u8         reserved_4[0x1c];
9029
9030         u8         node_guid[0x40];
9031
9032         u8         reserved_5[0x740];
9033
9034         struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9035
9036         struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9037 };
9038
9039 struct mlx5_ifc_vlan_layout_bits {
9040         u8         reserved_0[0x14];
9041         u8         vlan[0xc];
9042
9043         u8         reserved_1[0x20];
9044 };
9045
9046 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9047         u8         reserved_0[0x20];
9048
9049         u8         mkey[0x20];
9050
9051         u8         addressh_63_32[0x20];
9052
9053         u8         addressl_31_0[0x20];
9054 };
9055
9056 struct mlx5_ifc_ud_adrs_vector_bits {
9057         u8         dc_key[0x40];
9058
9059         u8         ext[0x1];
9060         u8         reserved_0[0x7];
9061         u8         destination_qp_dct[0x18];
9062
9063         u8         static_rate[0x4];
9064         u8         sl_eth_prio[0x4];
9065         u8         fl[0x1];
9066         u8         mlid[0x7];
9067         u8         rlid_udp_sport[0x10];
9068
9069         u8         reserved_1[0x20];
9070
9071         u8         rmac_47_16[0x20];
9072
9073         u8         rmac_15_0[0x10];
9074         u8         tclass[0x8];
9075         u8         hop_limit[0x8];
9076
9077         u8         reserved_2[0x1];
9078         u8         grh[0x1];
9079         u8         reserved_3[0x2];
9080         u8         src_addr_index[0x8];
9081         u8         flow_label[0x14];
9082
9083         u8         rgid_rip[16][0x8];
9084 };
9085
9086 struct mlx5_ifc_port_module_event_bits {
9087         u8         reserved_0[0x8];
9088         u8         module[0x8];
9089         u8         reserved_1[0xc];
9090         u8         module_status[0x4];
9091
9092         u8         reserved_2[0x14];
9093         u8         error_type[0x4];
9094         u8         reserved_3[0x8];
9095
9096         u8         reserved_4[0xa0];
9097 };
9098
9099 struct mlx5_ifc_icmd_control_bits {
9100         u8         opcode[0x10];
9101         u8         status[0x8];
9102         u8         reserved_0[0x7];
9103         u8         busy[0x1];
9104 };
9105
9106 struct mlx5_ifc_eqe_bits {
9107         u8         reserved_0[0x8];
9108         u8         event_type[0x8];
9109         u8         reserved_1[0x8];
9110         u8         event_sub_type[0x8];
9111
9112         u8         reserved_2[0xe0];
9113
9114         union mlx5_ifc_event_auto_bits event_data;
9115
9116         u8         reserved_3[0x10];
9117         u8         signature[0x8];
9118         u8         reserved_4[0x7];
9119         u8         owner[0x1];
9120 };
9121
9122 enum {
9123         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9124 };
9125
9126 struct mlx5_ifc_cmd_queue_entry_bits {
9127         u8         type[0x8];
9128         u8         reserved_0[0x18];
9129
9130         u8         input_length[0x20];
9131
9132         u8         input_mailbox_pointer_63_32[0x20];
9133
9134         u8         input_mailbox_pointer_31_9[0x17];
9135         u8         reserved_1[0x9];
9136
9137         u8         command_input_inline_data[16][0x8];
9138
9139         u8         command_output_inline_data[16][0x8];
9140
9141         u8         output_mailbox_pointer_63_32[0x20];
9142
9143         u8         output_mailbox_pointer_31_9[0x17];
9144         u8         reserved_2[0x9];
9145
9146         u8         output_length[0x20];
9147
9148         u8         token[0x8];
9149         u8         signature[0x8];
9150         u8         reserved_3[0x8];
9151         u8         status[0x7];
9152         u8         ownership[0x1];
9153 };
9154
9155 struct mlx5_ifc_cmd_out_bits {
9156         u8         status[0x8];
9157         u8         reserved_0[0x18];
9158
9159         u8         syndrome[0x20];
9160
9161         u8         command_output[0x20];
9162 };
9163
9164 struct mlx5_ifc_cmd_in_bits {
9165         u8         opcode[0x10];
9166         u8         reserved_0[0x10];
9167
9168         u8         reserved_1[0x10];
9169         u8         op_mod[0x10];
9170
9171         u8         command[0][0x20];
9172 };
9173
9174 struct mlx5_ifc_cmd_if_box_bits {
9175         u8         mailbox_data[512][0x8];
9176
9177         u8         reserved_0[0x180];
9178
9179         u8         next_pointer_63_32[0x20];
9180
9181         u8         next_pointer_31_10[0x16];
9182         u8         reserved_1[0xa];
9183
9184         u8         block_number[0x20];
9185
9186         u8         reserved_2[0x8];
9187         u8         token[0x8];
9188         u8         ctrl_signature[0x8];
9189         u8         signature[0x8];
9190 };
9191
9192 struct mlx5_ifc_mtt_bits {
9193         u8         ptag_63_32[0x20];
9194
9195         u8         ptag_31_8[0x18];
9196         u8         reserved_0[0x6];
9197         u8         wr_en[0x1];
9198         u8         rd_en[0x1];
9199 };
9200
9201 struct mlx5_ifc_vendor_specific_cap_bits {
9202         u8         type[0x8];
9203         u8         length[0x8];
9204         u8         next_pointer[0x8];
9205         u8         capability_id[0x8];
9206
9207         u8         status[0x3];
9208         u8         reserved_0[0xd];
9209         u8         space[0x10];
9210
9211         u8         counter[0x20];
9212
9213         u8         semaphore[0x20];
9214
9215         u8         flag[0x1];
9216         u8         reserved_1[0x1];
9217         u8         address[0x1e];
9218
9219         u8         data[0x20];
9220 };
9221
9222 enum {
9223         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9224         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9225         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9226 };
9227
9228 enum {
9229         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9230         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9231         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9232 };
9233
9234 enum {
9235         MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
9236         MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
9237         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
9238         MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
9239         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
9240         MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
9241         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
9242         MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
9243         MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
9244         MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
9245         MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
9246 };
9247
9248 struct mlx5_ifc_initial_seg_bits {
9249         u8         fw_rev_minor[0x10];
9250         u8         fw_rev_major[0x10];
9251
9252         u8         cmd_interface_rev[0x10];
9253         u8         fw_rev_subminor[0x10];
9254
9255         u8         reserved_0[0x40];
9256
9257         u8         cmdq_phy_addr_63_32[0x20];
9258
9259         u8         cmdq_phy_addr_31_12[0x14];
9260         u8         reserved_1[0x2];
9261         u8         nic_interface[0x2];
9262         u8         log_cmdq_size[0x4];
9263         u8         log_cmdq_stride[0x4];
9264
9265         u8         command_doorbell_vector[0x20];
9266
9267         u8         reserved_2[0xf00];
9268
9269         u8         initializing[0x1];
9270         u8         reserved_3[0x4];
9271         u8         nic_interface_supported[0x3];
9272         u8         reserved_4[0x18];
9273
9274         struct mlx5_ifc_health_buffer_bits health_buffer;
9275
9276         u8         no_dram_nic_offset[0x20];
9277
9278         u8         reserved_5[0x6de0];
9279
9280         u8         internal_timer_h[0x20];
9281
9282         u8         internal_timer_l[0x20];
9283
9284         u8         reserved_6[0x20];
9285
9286         u8         reserved_7[0x1f];
9287         u8         clear_int[0x1];
9288
9289         u8         health_syndrome[0x8];
9290         u8         health_counter[0x18];
9291
9292         u8         reserved_8[0x17fc0];
9293 };
9294
9295 union mlx5_ifc_icmd_interface_document_bits {
9296         struct mlx5_ifc_fw_version_bits fw_version;
9297         struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
9298         struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
9299         struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
9300         struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
9301         struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
9302         struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
9303         struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
9304         struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
9305         struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
9306         struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
9307         struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
9308         struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
9309         struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
9310         u8         reserved_0[0x42c0];
9311 };
9312
9313 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
9314         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9315         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9316         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9317         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9318         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9319         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9320         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9321         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9322         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
9323         struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
9324         u8         reserved_0[0x7c0];
9325 };
9326
9327 struct mlx5_ifc_ppcnt_reg_bits {
9328         u8         swid[0x8];
9329         u8         local_port[0x8];
9330         u8         pnat[0x2];
9331         u8         reserved_0[0x8];
9332         u8         grp[0x6];
9333
9334         u8         clr[0x1];
9335         u8         reserved_1[0x1c];
9336         u8         prio_tc[0x3];
9337
9338         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9339 };
9340
9341 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
9342         u8         life_time_counter_high[0x20];
9343
9344         u8         life_time_counter_low[0x20];
9345
9346         u8         rx_errors[0x20];
9347
9348         u8         tx_errors[0x20];
9349
9350         u8         l0_to_recovery_eieos[0x20];
9351
9352         u8         l0_to_recovery_ts[0x20];
9353
9354         u8         l0_to_recovery_framing[0x20];
9355
9356         u8         l0_to_recovery_retrain[0x20];
9357
9358         u8         crc_error_dllp[0x20];
9359
9360         u8         crc_error_tlp[0x20];
9361
9362         u8         reserved_0[0x680];
9363 };
9364
9365 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
9366         u8         life_time_counter_high[0x20];
9367
9368         u8         life_time_counter_low[0x20];
9369
9370         u8         time_to_boot_image_start[0x20];
9371
9372         u8         time_to_link_image[0x20];
9373
9374         u8         calibration_time[0x20];
9375
9376         u8         time_to_first_perst[0x20];
9377
9378         u8         time_to_detect_state[0x20];
9379
9380         u8         time_to_l0[0x20];
9381
9382         u8         time_to_crs_en[0x20];
9383
9384         u8         time_to_plastic_image_start[0x20];
9385
9386         u8         time_to_iron_image_start[0x20];
9387
9388         u8         perst_handler[0x20];
9389
9390         u8         times_in_l1[0x20];
9391
9392         u8         times_in_l23[0x20];
9393
9394         u8         dl_down[0x20];
9395
9396         u8         config_cycle1usec[0x20];
9397
9398         u8         config_cycle2to7usec[0x20];
9399
9400         u8         config_cycle8to15usec[0x20];
9401
9402         u8         config_cycle16to63usec[0x20];
9403
9404         u8         config_cycle64usec[0x20];
9405
9406         u8         correctable_err_msg_sent[0x20];
9407
9408         u8         non_fatal_err_msg_sent[0x20];
9409
9410         u8         fatal_err_msg_sent[0x20];
9411
9412         u8         reserved_0[0x4e0];
9413 };
9414
9415 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
9416         u8         life_time_counter_high[0x20];
9417
9418         u8         life_time_counter_low[0x20];
9419
9420         u8         error_counter_lane0[0x20];
9421
9422         u8         error_counter_lane1[0x20];
9423
9424         u8         error_counter_lane2[0x20];
9425
9426         u8         error_counter_lane3[0x20];
9427
9428         u8         error_counter_lane4[0x20];
9429
9430         u8         error_counter_lane5[0x20];
9431
9432         u8         error_counter_lane6[0x20];
9433
9434         u8         error_counter_lane7[0x20];
9435
9436         u8         error_counter_lane8[0x20];
9437
9438         u8         error_counter_lane9[0x20];
9439
9440         u8         error_counter_lane10[0x20];
9441
9442         u8         error_counter_lane11[0x20];
9443
9444         u8         error_counter_lane12[0x20];
9445
9446         u8         error_counter_lane13[0x20];
9447
9448         u8         error_counter_lane14[0x20];
9449
9450         u8         error_counter_lane15[0x20];
9451
9452         u8         reserved_0[0x580];
9453 };
9454
9455 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
9456         struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
9457         struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
9458         struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
9459         u8         reserved_0[0xf8];
9460 };
9461
9462 struct mlx5_ifc_mpcnt_reg_bits {
9463         u8         reserved_0[0x8];
9464         u8         pcie_index[0x8];
9465         u8         reserved_1[0xa];
9466         u8         grp[0x6];
9467
9468         u8         clr[0x1];
9469         u8         reserved_2[0x1f];
9470
9471         union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
9472 };
9473
9474 union mlx5_ifc_ports_control_registers_document_bits {
9475         struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
9476         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9477         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9478         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9479         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9480         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9481         struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
9482         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9483         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9484         struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
9485         struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
9486         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9487         struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
9488         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9489         struct mlx5_ifc_paos_reg_bits paos_reg;
9490         struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
9491         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9492         struct mlx5_ifc_peir_reg_bits peir_reg;
9493         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9494         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9495         struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
9496         struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
9497         struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
9498         struct mlx5_ifc_phrr_reg_bits phrr_reg;
9499         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9500         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9501         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9502         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9503         struct mlx5_ifc_plib_reg_bits plib_reg;
9504         struct mlx5_ifc_pll_status_data_bits pll_status_data;
9505         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9506         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9507         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9508         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9509         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9510         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9511         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9512         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9513         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9514         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9515         struct mlx5_ifc_ppll_reg_bits ppll_reg;
9516         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9517         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9518         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9519         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9520         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9521         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9522         struct mlx5_ifc_pude_reg_bits pude_reg;
9523         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9524         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9525         struct mlx5_ifc_slrp_reg_bits slrp_reg;
9526         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9527         u8         reserved_0[0x7880];
9528 };
9529
9530 union mlx5_ifc_debug_enhancements_document_bits {
9531         struct mlx5_ifc_health_buffer_bits health_buffer;
9532         u8         reserved_0[0x200];
9533 };
9534
9535 union mlx5_ifc_no_dram_nic_document_bits {
9536         struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
9537         struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
9538         struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
9539         struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
9540         struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
9541         struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
9542         struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
9543         struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
9544         u8         reserved_0[0x3160];
9545 };
9546
9547 union mlx5_ifc_uplink_pci_interface_document_bits {
9548         struct mlx5_ifc_initial_seg_bits initial_seg;
9549         struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
9550         u8         reserved_0[0x20120];
9551 };
9552
9553
9554 #endif /* MLX5_IFC_H */