2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
46 #include <dev/pci/pcivar.h>
50 #include <cam/cam_ccb.h>
51 #include <cam/cam_sim.h>
52 #include <cam/cam_xpt_sim.h>
53 #include <cam/cam_debug.h>
55 /* local prototypes */
56 static int mvs_ch_init(device_t dev);
57 static int mvs_ch_deinit(device_t dev);
58 static int mvs_ch_suspend(device_t dev);
59 static int mvs_ch_resume(device_t dev);
60 static void mvs_dmainit(device_t dev);
61 static void mvs_dmasetupc_cb(void *xsc,
62 bus_dma_segment_t *segs, int nsegs, int error);
63 static void mvs_dmafini(device_t dev);
64 static void mvs_slotsalloc(device_t dev);
65 static void mvs_slotsfree(device_t dev);
66 static void mvs_setup_edma_queues(device_t dev);
67 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode);
68 static void mvs_ch_pm(void *arg);
69 static void mvs_ch_intr_locked(void *data);
70 static void mvs_ch_intr(void *data);
71 static void mvs_reset(device_t dev);
72 static void mvs_softreset(device_t dev, union ccb *ccb);
74 static int mvs_sata_connect(struct mvs_channel *ch);
75 static int mvs_sata_phy_reset(device_t dev);
76 static int mvs_wait(device_t dev, u_int s, u_int c, int t);
77 static void mvs_tfd_read(device_t dev, union ccb *ccb);
78 static void mvs_tfd_write(device_t dev, union ccb *ccb);
79 static void mvs_legacy_intr(device_t dev, int poll);
80 static void mvs_crbq_intr(device_t dev);
81 static void mvs_begin_transaction(device_t dev, union ccb *ccb);
82 static void mvs_legacy_execute_transaction(struct mvs_slot *slot);
83 static void mvs_timeout(struct mvs_slot *slot);
84 static void mvs_dmasetprd(void *arg,
85 bus_dma_segment_t *segs, int nsegs, int error);
86 static void mvs_requeue_frozen(device_t dev);
87 static void mvs_execute_transaction(struct mvs_slot *slot);
88 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et);
90 static void mvs_issue_recovery(device_t dev);
91 static void mvs_process_read_log(device_t dev, union ccb *ccb);
92 static void mvs_process_request_sense(device_t dev, union ccb *ccb);
94 static void mvsaction(struct cam_sim *sim, union ccb *ccb);
95 static void mvspoll(struct cam_sim *sim);
97 static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers");
99 #define recovery_type spriv_field0
100 #define RECOVERY_NONE 0
101 #define RECOVERY_READ_LOG 1
102 #define RECOVERY_REQUEST_SENSE 2
103 #define recovery_slot spriv_field1
106 mvs_ch_probe(device_t dev)
109 device_set_desc_copy(dev, "Marvell SATA channel");
114 mvs_ch_attach(device_t dev)
116 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev));
117 struct mvs_channel *ch = device_get_softc(dev);
118 struct cam_devq *devq;
119 int rid, error, i, sata_rev = 0;
122 ch->unit = (intptr_t)device_get_ivars(dev);
123 ch->quirks = ctlr->quirks;
124 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF);
125 resource_int_value(device_get_name(dev),
126 device_get_unit(dev), "pm_level", &ch->pm_level);
127 if (ch->pm_level > 3)
128 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
129 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
130 resource_int_value(device_get_name(dev),
131 device_get_unit(dev), "sata_rev", &sata_rev);
132 for (i = 0; i < 16; i++) {
133 ch->user[i].revision = sata_rev;
134 ch->user[i].mode = 0;
135 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048;
136 ch->user[i].tags = MVS_MAX_SLOTS;
137 ch->curr[i] = ch->user[i];
139 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
140 CTS_SATA_CAPS_H_APST |
141 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
143 ch->user[i].caps |= CTS_SATA_CAPS_H_AN;
146 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
154 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
155 &rid, RF_SHAREABLE | RF_ACTIVE))) {
156 device_printf(dev, "Unable to map interrupt\n");
160 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
161 mvs_ch_intr_locked, dev, &ch->ih))) {
162 device_printf(dev, "Unable to setup interrupt\n");
166 /* Create the device queue for our SIM. */
167 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1);
169 device_printf(dev, "Unable to allocate simq\n");
173 /* Construct SIM entry */
174 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch,
175 device_get_unit(dev), &ch->mtx,
176 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1,
178 if (ch->sim == NULL) {
180 device_printf(dev, "unable to allocate sim\n");
184 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
185 device_printf(dev, "unable to register xpt bus\n");
189 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
190 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
191 device_printf(dev, "unable to create path\n");
195 if (ch->pm_level > 3) {
196 callout_reset(&ch->pm_timer,
197 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
200 mtx_unlock(&ch->mtx);
204 xpt_bus_deregister(cam_sim_path(ch->sim));
206 cam_sim_free(ch->sim, /*free_devq*/TRUE);
208 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
210 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
211 mtx_unlock(&ch->mtx);
212 mtx_destroy(&ch->mtx);
217 mvs_ch_detach(device_t dev)
219 struct mvs_channel *ch = device_get_softc(dev);
222 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
223 /* Forget about reset. */
226 xpt_release_simq(ch->sim, TRUE);
228 xpt_free_path(ch->path);
229 xpt_bus_deregister(cam_sim_path(ch->sim));
230 cam_sim_free(ch->sim, /*free_devq*/TRUE);
231 mtx_unlock(&ch->mtx);
233 if (ch->pm_level > 3)
234 callout_drain(&ch->pm_timer);
235 callout_drain(&ch->reset_timer);
236 bus_teardown_intr(dev, ch->r_irq, ch->ih);
237 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
243 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
244 mtx_destroy(&ch->mtx);
249 mvs_ch_init(device_t dev)
251 struct mvs_channel *ch = device_get_softc(dev);
254 /* Disable port interrupts */
255 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
257 ch->curr_mode = MVS_EDMA_UNKNOWN;
258 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
259 /* Clear and configure FIS interrupts. */
260 ATA_OUTL(ch->r_mem, SATA_FISIC, 0);
261 reg = ATA_INL(ch->r_mem, SATA_FISC);
262 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
263 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
264 reg = ATA_INL(ch->r_mem, SATA_FISIM);
265 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
266 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
267 /* Clear SATA error register. */
268 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
269 /* Clear any outstanding error interrupts. */
270 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
271 /* Unmask all error interrupts */
272 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
277 mvs_ch_deinit(device_t dev)
279 struct mvs_channel *ch = device_get_softc(dev);
282 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
283 /* Disable port interrupts. */
284 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
289 mvs_ch_suspend(device_t dev)
291 struct mvs_channel *ch = device_get_softc(dev);
294 xpt_freeze_simq(ch->sim, 1);
296 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100);
297 /* Forget about reset. */
300 callout_stop(&ch->reset_timer);
301 xpt_release_simq(ch->sim, TRUE);
304 mtx_unlock(&ch->mtx);
309 mvs_ch_resume(device_t dev)
311 struct mvs_channel *ch = device_get_softc(dev);
316 xpt_release_simq(ch->sim, TRUE);
317 mtx_unlock(&ch->mtx);
321 struct mvs_dc_cb_args {
327 mvs_dmainit(device_t dev)
329 struct mvs_channel *ch = device_get_softc(dev);
330 struct mvs_dc_cb_args dcba;
332 /* EDMA command request area. */
333 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
334 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
335 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE,
336 0, NULL, NULL, &ch->dma.workrq_tag))
338 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0,
339 &ch->dma.workrq_map))
341 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map,
342 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
344 bus_dmamem_free(ch->dma.workrq_tag,
345 ch->dma.workrq, ch->dma.workrq_map);
348 ch->dma.workrq_bus = dcba.maddr;
349 /* EDMA command response area. */
350 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0,
351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
352 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE,
353 0, NULL, NULL, &ch->dma.workrp_tag))
355 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0,
356 &ch->dma.workrp_map))
358 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map,
359 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
361 bus_dmamem_free(ch->dma.workrp_tag,
362 ch->dma.workrp, ch->dma.workrp_map);
365 ch->dma.workrp_bus = dcba.maddr;
367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX,
368 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
370 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS,
371 MVS_SG_ENTRIES, MVS_EPRD_MAX,
372 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
378 device_printf(dev, "WARNING - DMA initialization failed\n");
383 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
385 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc;
387 if (!(dcba->error = error))
388 dcba->maddr = segs[0].ds_addr;
392 mvs_dmafini(device_t dev)
394 struct mvs_channel *ch = device_get_softc(dev);
396 if (ch->dma.data_tag) {
397 bus_dma_tag_destroy(ch->dma.data_tag);
398 ch->dma.data_tag = NULL;
400 if (ch->dma.workrp_bus) {
401 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map);
402 bus_dmamem_free(ch->dma.workrp_tag,
403 ch->dma.workrp, ch->dma.workrp_map);
404 ch->dma.workrp_bus = 0;
405 ch->dma.workrp_map = NULL;
406 ch->dma.workrp = NULL;
408 if (ch->dma.workrp_tag) {
409 bus_dma_tag_destroy(ch->dma.workrp_tag);
410 ch->dma.workrp_tag = NULL;
412 if (ch->dma.workrq_bus) {
413 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map);
414 bus_dmamem_free(ch->dma.workrq_tag,
415 ch->dma.workrq, ch->dma.workrq_map);
416 ch->dma.workrq_bus = 0;
417 ch->dma.workrq_map = NULL;
418 ch->dma.workrq = NULL;
420 if (ch->dma.workrq_tag) {
421 bus_dma_tag_destroy(ch->dma.workrq_tag);
422 ch->dma.workrq_tag = NULL;
427 mvs_slotsalloc(device_t dev)
429 struct mvs_channel *ch = device_get_softc(dev);
432 /* Alloc and setup command/dma slots */
433 bzero(ch->slot, sizeof(ch->slot));
434 for (i = 0; i < MVS_MAX_SLOTS; i++) {
435 struct mvs_slot *slot = &ch->slot[i];
439 slot->state = MVS_SLOT_EMPTY;
441 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
443 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
444 device_printf(ch->dev, "FAILURE - create data_map\n");
449 mvs_slotsfree(device_t dev)
451 struct mvs_channel *ch = device_get_softc(dev);
454 /* Free all dma slots */
455 for (i = 0; i < MVS_MAX_SLOTS; i++) {
456 struct mvs_slot *slot = &ch->slot[i];
458 callout_drain(&slot->timeout);
459 if (slot->dma.data_map) {
460 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
461 slot->dma.data_map = NULL;
467 mvs_setup_edma_queues(device_t dev)
469 struct mvs_channel *ch = device_get_softc(dev);
472 /* Requests queue. */
473 work = ch->dma.workrq_bus;
474 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32);
475 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff);
476 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff);
477 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
478 BUS_DMASYNC_PREWRITE);
479 /* Reponses queue. */
480 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE);
481 work = ch->dma.workrp_bus;
482 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32);
483 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff);
484 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff);
485 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
486 BUS_DMASYNC_PREREAD);
492 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode)
494 struct mvs_channel *ch = device_get_softc(dev);
496 uint32_t ecfg, fcfg, hc, ltm, unkn;
498 if (mode == ch->curr_mode)
500 /* If we are running, we should stop first. */
501 if (ch->curr_mode != MVS_EDMA_OFF) {
502 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA);
504 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) {
506 if (timeout++ > 1000) {
507 device_printf(dev, "stopping EDMA engine failed\n");
512 ch->curr_mode = mode;
515 /* Report mode to controller. Needed for correct CCC operation. */
516 MVS_EDMA(device_get_parent(dev), dev, mode);
517 /* Configure new mode. */
518 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN;
519 if (ch->pm_present) {
520 ecfg |= EDMA_CFG_EMASKRXPM;
521 if (ch->quirks & MVS_Q_GENIIE) {
522 ecfg |= EDMA_CFG_EEDMAFBS;
526 if (ch->quirks & MVS_Q_GENI)
527 ecfg |= EDMA_CFG_ERDBSZ;
528 else if (ch->quirks & MVS_Q_GENII)
529 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN;
530 if (ch->quirks & MVS_Q_CT)
531 ecfg |= EDMA_CFG_ECUTTHROUGHEN;
532 if (mode != MVS_EDMA_OFF)
533 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN;
534 if (mode == MVS_EDMA_QUEUED)
535 ecfg |= EDMA_CFG_EQUE;
536 else if (mode == MVS_EDMA_NCQ)
537 ecfg |= EDMA_CFG_ESATANATVCMDQUE;
538 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg);
539 mvs_setup_edma_queues(dev);
540 if (ch->quirks & MVS_Q_GENIIE) {
541 /* Configure FBS-related registers */
542 fcfg = ATA_INL(ch->r_mem, SATA_FISC);
543 ltm = ATA_INL(ch->r_mem, SATA_LTM);
544 hc = ATA_INL(ch->r_mem, EDMA_HC);
545 if (ch->fbs_enabled) {
546 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP;
547 if (mode == MVS_EDMA_NCQ) {
548 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
549 hc &= ~EDMA_IE_EDEVERR;
551 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0;
552 hc |= EDMA_IE_EDEVERR;
556 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP;
557 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
558 hc |= EDMA_IE_EDEVERR;
561 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg);
562 ATA_OUTL(ch->r_mem, SATA_LTM, ltm);
563 ATA_OUTL(ch->r_mem, EDMA_HC, hc);
564 /* This is some magic, required to handle several DRQs
566 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD);
567 if (mode == MVS_EDMA_OFF)
571 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn);
574 if (mode != MVS_EDMA_OFF)
575 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA);
578 devclass_t mvs_devclass;
579 devclass_t mvsch_devclass;
580 static device_method_t mvsch_methods[] = {
581 DEVMETHOD(device_probe, mvs_ch_probe),
582 DEVMETHOD(device_attach, mvs_ch_attach),
583 DEVMETHOD(device_detach, mvs_ch_detach),
584 DEVMETHOD(device_suspend, mvs_ch_suspend),
585 DEVMETHOD(device_resume, mvs_ch_resume),
588 static driver_t mvsch_driver = {
591 sizeof(struct mvs_channel)
593 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0);
594 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0);
597 mvs_phy_check_events(device_t dev, u_int32_t serr)
599 struct mvs_channel *ch = device_get_softc(dev);
601 if (ch->pm_level == 0) {
602 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS);
606 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
607 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
608 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) {
609 device_printf(dev, "CONNECT requested\n");
611 device_printf(dev, "DISCONNECT requested\n");
614 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
616 if (xpt_create_path(&ccb->ccb_h.path, NULL,
617 cam_sim_path(ch->sim),
618 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
627 mvs_notify_events(device_t dev)
629 struct mvs_channel *ch = device_get_softc(dev);
630 struct cam_path *dpath;
634 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */
635 fis = ATA_INL(ch->r_mem, SATA_FISDW0);
636 if ((fis & 0x80ff) == 0x80a1)
637 d = (fis & 0x0f00) >> 8;
639 d = ch->pm_present ? 15 : 0;
641 device_printf(dev, "SNTF %d\n", d);
642 if (xpt_create_path(&dpath, NULL,
643 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) {
644 xpt_async(AC_SCSI_AEN, dpath, NULL);
645 xpt_free_path(dpath);
650 mvs_ch_intr_locked(void *data)
652 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
653 device_t dev = (device_t)arg->arg;
654 struct mvs_channel *ch = device_get_softc(dev);
657 xpt_batch_start(ch->sim);
659 xpt_batch_done(ch->sim);
660 mtx_unlock(&ch->mtx);
666 device_t dev = (device_t)arg;
667 struct mvs_channel *ch = device_get_softc(dev);
670 if (ch->numrslots != 0)
672 /* If we are idle - request power state transition. */
673 work = ATA_INL(ch->r_mem, SATA_SC);
674 work &= ~SATA_SC_SPM_MASK;
675 if (ch->pm_level == 4)
676 work |= SATA_SC_SPM_PARTIAL;
678 work |= SATA_SC_SPM_SLUMBER;
679 ATA_OUTL(ch->r_mem, SATA_SC, work);
683 mvs_ch_pm_wake(device_t dev)
685 struct mvs_channel *ch = device_get_softc(dev);
689 work = ATA_INL(ch->r_mem, SATA_SS);
690 if (work & SATA_SS_IPM_ACTIVE)
692 /* If we are not in active state - request power state transition. */
693 work = ATA_INL(ch->r_mem, SATA_SC);
694 work &= ~SATA_SC_SPM_MASK;
695 work |= SATA_SC_SPM_ACTIVE;
696 ATA_OUTL(ch->r_mem, SATA_SC, work);
697 /* Wait for transition to happen. */
698 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 &&
705 mvs_ch_intr(void *data)
707 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
708 device_t dev = (device_t)arg->arg;
709 struct mvs_channel *ch = device_get_softc(dev);
710 uint32_t iec, serr = 0, fisic = 0;
711 enum mvs_err_type et;
712 int i, ccs, port = -1, selfdis = 0;
713 int edma = (ch->numtslots != 0 || ch->numdslots != 0);
715 /* New item in response queue. */
716 if ((arg->cause & 2) && edma)
718 /* Some error or special event. */
719 if (arg->cause & 1) {
720 iec = ATA_INL(ch->r_mem, EDMA_IEC);
721 if (iec & EDMA_IE_SERRINT) {
722 serr = ATA_INL(ch->r_mem, SATA_SE);
723 ATA_OUTL(ch->r_mem, SATA_SE, serr);
725 /* EDMA self-disabled due to error. */
726 if (iec & EDMA_IE_ESELFDIS)
728 /* Transport interrupt. */
729 if (iec & EDMA_IE_ETRANSINT) {
730 /* For Gen-I this bit means self-disable. */
731 if (ch->quirks & MVS_Q_GENI)
733 /* For Gen-II this bit means SDB-N. */
734 else if (ch->quirks & MVS_Q_GENII)
735 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1;
736 else /* For Gen-IIe - read FIS interrupt cause. */
737 fisic = ATA_INL(ch->r_mem, SATA_FISIC);
740 ch->curr_mode = MVS_EDMA_UNKNOWN;
741 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec);
742 /* Interface errors or Device error. */
743 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) {
745 if (ch->numpslots != 0) {
748 if (ch->quirks & MVS_Q_GENIIE)
749 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S));
751 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S));
752 /* Check if error is one-PMP-port-specific, */
753 if (ch->fbs_enabled) {
754 /* Which ports were active. */
755 for (i = 0; i < 16; i++) {
756 if (ch->numrslotspd[i] == 0)
760 else if (port != i) {
765 /* If several ports were active and EDMA still enabled -
766 * other ports are probably unaffected and may continue.
768 if (port == -2 && !selfdis) {
769 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16;
771 if (port != (fls(p) - 1))
776 mvs_requeue_frozen(dev);
777 for (i = 0; i < MVS_MAX_SLOTS; i++) {
778 /* XXX: reqests in loading state. */
779 if (((ch->rslots >> i) & 1) == 0)
782 ch->slot[i].ccb->ccb_h.target_id != port)
784 if (iec & EDMA_IE_EDEVERR) { /* Device error. */
786 if (ch->numtslots == 0) {
787 /* Untagged operation. */
791 et = MVS_ERR_INNOCENT;
793 /* Tagged operation. */
800 } else if (iec & 0xfc1e9000) {
801 if (ch->numtslots == 0 &&
802 i != ccs && port != -2)
803 et = MVS_ERR_INNOCENT;
807 et = MVS_ERR_INVALID;
808 mvs_end_transaction(&ch->slot[i], et);
812 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1)
813 mvs_notify_events(dev);
815 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic);
816 /* Process hot-plug. */
817 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) ||
818 (serr & SATA_SE_PHY_CHANGED))
819 mvs_phy_check_events(dev, serr);
821 /* Legacy mode device interrupt. */
822 if ((arg->cause & 2) && !edma)
823 mvs_legacy_intr(dev, arg->cause & 4);
827 mvs_getstatus(device_t dev, int clear)
829 struct mvs_channel *ch = device_get_softc(dev);
830 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT);
833 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR))
836 status |= ATA_S_BUSY;
842 mvs_legacy_intr(device_t dev, int poll)
844 struct mvs_channel *ch = device_get_softc(dev);
845 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */
846 union ccb *ccb = slot->ccb;
847 enum mvs_err_type et = MVS_ERR_NONE;
849 u_int length, resid, size;
851 uint8_t status, ireason;
853 /* Clear interrupt and get status. */
854 status = mvs_getstatus(dev, 1);
855 if (slot->state < MVS_SLOT_RUNNING)
857 port = ccb->ccb_h.target_id & 0x0f;
858 /* Wait a bit for late !BUSY status update. */
859 if (status & ATA_S_BUSY) {
863 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) {
865 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY)
869 /* If we got an error, we are done. */
870 if (status & ATA_S_ERROR) {
874 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */
875 ccb->ataio.res.status = status;
876 /* Are we moving data? */
877 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
878 /* If data read command - get them. */
879 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
880 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
881 device_printf(dev, "timeout waiting for read DRQ\n");
882 et = MVS_ERR_TIMEOUT;
883 xpt_freeze_simq(ch->sim, 1);
884 ch->toslots |= (1 << slot->slot);
887 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
888 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
889 ch->transfersize / 2);
891 /* Update how far we've gotten. */
892 ch->donecount += ch->transfersize;
893 /* Do we need more? */
894 if (ccb->ataio.dxfer_len > ch->donecount) {
895 /* Set this transfer size according to HW capabilities */
896 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount,
898 /* If data write command - put them */
899 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
900 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
902 "timeout waiting for write DRQ\n");
903 et = MVS_ERR_TIMEOUT;
904 xpt_freeze_simq(ch->sim, 1);
905 ch->toslots |= (1 << slot->slot);
908 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
909 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
910 ch->transfersize / 2);
913 /* If data read command, return & wait for interrupt */
914 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
918 } else if (ch->basic_dma) { /* ATAPI DMA */
919 if (status & ATA_S_DWF)
921 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR)
923 /* Stop basic DMA. */
924 ATA_OUTL(ch->r_mem, DMA_C, 0);
926 } else { /* ATAPI PIO */
927 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) |
928 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8);
929 size = min(ch->transfersize, length);
930 ireason = ATA_INB(ch->r_mem,ATA_IREASON);
931 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) |
932 (status & ATA_S_DRQ)) {
935 device_printf(dev, "ATAPI CMDOUT\n");
936 /* Return wait for interrupt */
940 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
941 device_printf(dev, "trying to write on read buffer\n");
946 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
947 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
949 for (resid = ch->transfersize + (size & 1);
950 resid < length; resid += sizeof(int16_t))
951 ATA_OUTW(ch->r_mem, ATA_DATA, 0);
952 ch->donecount += length;
953 /* Set next transfer size according to HW capabilities */
954 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
955 ch->curr[ccb->ccb_h.target_id].bytecount);
956 /* Return wait for interrupt */
960 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
961 device_printf(dev, "trying to read on write buffer\n");
966 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
967 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
971 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1);
972 ((uint8_t *)ccb->csio.data_ptr + ch->donecount +
973 (size & ~1))[0] = buf[0];
975 for (resid = ch->transfersize + (size & 1);
976 resid < length; resid += sizeof(int16_t))
977 ATA_INW(ch->r_mem, ATA_DATA);
978 ch->donecount += length;
979 /* Set next transfer size according to HW capabilities */
980 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
981 ch->curr[ccb->ccb_h.target_id].bytecount);
982 /* Return wait for interrupt */
985 case ATAPI_P_DONEDRQ:
987 "WARNING - DONEDRQ non conformant device\n");
988 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
989 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
990 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
992 ch->donecount += length;
994 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
995 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
996 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
998 ch->donecount += length;
1006 if (status & (ATA_S_ERROR | ATA_S_DWF))
1011 device_printf(dev, "unknown transfer phase"
1012 " (status %02x, ireason %02x)\n",
1019 mvs_end_transaction(slot, et);
1023 mvs_crbq_intr(device_t dev)
1025 struct mvs_channel *ch = device_get_softc(dev);
1026 struct mvs_crpb *crpb;
1028 int in_idx, fin_idx, cin_idx, slot;
1032 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1034 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1035 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >>
1036 EDMA_RESQP_ERPQP_SHIFT;
1037 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1038 BUS_DMASYNC_POSTREAD);
1039 fin_idx = cin_idx = ch->in_idx;
1040 ch->in_idx = in_idx;
1041 while (in_idx != cin_idx) {
1042 crpb = (struct mvs_crpb *)
1043 (ch->dma.workrp + MVS_CRPB_OFFSET +
1044 (MVS_CRPB_SIZE * cin_idx));
1045 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK;
1046 flags = le16toh(crpb->rspflg);
1048 * Handle only successfull completions here.
1049 * Errors will be handled by main intr handler.
1051 #if defined(__i386__) || defined(__amd64__)
1052 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) {
1053 device_printf(dev, "Unfilled CRPB "
1054 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1055 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots);
1058 if (ch->numtslots != 0 ||
1059 (flags & EDMA_IE_EDEVERR) == 0) {
1060 #if defined(__i386__) || defined(__amd64__)
1062 crpb->rspflg = 0xffff;
1064 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) {
1065 ccb = ch->slot[slot].ccb;
1066 ccb->ataio.res.status =
1067 (flags & MVS_CRPB_ATASTS_MASK) >>
1068 MVS_CRPB_ATASTS_SHIFT;
1069 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE);
1071 device_printf(dev, "Unused tag in CRPB "
1072 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1073 cin_idx, fin_idx, in_idx, slot, flags,
1078 "CRPB with error %d tag %d flags %04x\n",
1079 cin_idx, slot, flags);
1081 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1);
1083 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1084 BUS_DMASYNC_PREREAD);
1085 if (cin_idx == ch->in_idx) {
1086 ATA_OUTL(ch->r_mem, EDMA_RESQOP,
1087 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT));
1091 /* Must be called with channel locked. */
1093 mvs_check_collision(device_t dev, union ccb *ccb)
1095 struct mvs_channel *ch = device_get_softc(dev);
1097 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1099 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1100 /* Can't mix NCQ and non-NCQ DMA commands. */
1101 if (ch->numdslots != 0)
1103 /* Can't mix NCQ and PIO commands. */
1104 if (ch->numpslots != 0)
1106 /* If we have no FBS */
1107 if (!ch->fbs_enabled) {
1108 /* Tagged command while tagged to other target is active. */
1109 if (ch->numtslots != 0 &&
1110 ch->taggedtarget != ccb->ccb_h.target_id)
1114 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1115 /* Can't mix non-NCQ DMA and NCQ commands. */
1116 if (ch->numtslots != 0)
1118 /* Can't mix non-NCQ DMA and PIO commands. */
1119 if (ch->numpslots != 0)
1123 /* Can't mix PIO with anything. */
1124 if (ch->numrslots != 0)
1127 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1128 /* Atomic command while anything active. */
1129 if (ch->numrslots != 0)
1132 } else { /* ATAPI */
1133 /* ATAPI goes without EDMA, so can't mix it with anything. */
1134 if (ch->numrslots != 0)
1137 /* We have some atomic command running. */
1138 if (ch->aslots != 0)
1144 mvs_tfd_read(device_t dev, union ccb *ccb)
1146 struct mvs_channel *ch = device_get_softc(dev);
1147 struct ata_res *res = &ccb->ataio.res;
1149 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT);
1150 res->error = ATA_INB(ch->r_mem, ATA_ERROR);
1151 res->device = ATA_INB(ch->r_mem, ATA_DRIVE);
1152 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB);
1153 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT);
1154 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR);
1155 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1156 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1157 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
1158 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT);
1159 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR);
1160 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1161 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1165 mvs_tfd_write(device_t dev, union ccb *ccb)
1167 struct mvs_channel *ch = device_get_softc(dev);
1168 struct ata_cmd *cmd = &ccb->ataio.cmd;
1170 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device);
1171 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control);
1172 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp);
1173 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features);
1174 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp);
1175 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count);
1176 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp);
1177 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low);
1178 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp);
1179 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid);
1180 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp);
1181 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high);
1182 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command);
1186 /* Must be called with channel locked. */
1188 mvs_begin_transaction(device_t dev, union ccb *ccb)
1190 struct mvs_channel *ch = device_get_softc(dev);
1191 struct mvs_slot *slot;
1194 if (ch->pm_level > 0)
1195 mvs_ch_pm_wake(dev);
1196 /* Softreset is a special case. */
1197 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1198 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1199 mvs_softreset(dev, ccb);
1202 /* Choose empty slot. */
1203 slotn = ffs(~ch->oslots) - 1;
1204 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1205 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1206 if (ch->quirks & MVS_Q_GENIIE)
1207 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1;
1212 /* Occupy chosen slot. */
1213 slot = &ch->slot[slotn];
1216 /* Stop PM timer. */
1217 if (ch->numrslots == 0 && ch->pm_level > 3)
1218 callout_stop(&ch->pm_timer);
1219 /* Update channel stats. */
1220 ch->oslots |= (1 << slot->slot);
1222 ch->numrslotspd[ccb->ccb_h.target_id]++;
1223 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1224 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1225 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag);
1227 ch->numtslotspd[ccb->ccb_h.target_id]++;
1228 ch->taggedtarget = ccb->ccb_h.target_id;
1229 mvs_set_edma_mode(dev, MVS_EDMA_NCQ);
1230 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1232 mvs_set_edma_mode(dev, MVS_EDMA_ON);
1235 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1237 if (ccb->ataio.cmd.flags &
1238 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1239 ch->aslots |= (1 << slot->slot);
1242 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1243 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes;
1245 /* Use ATAPI DMA only for commands without under-/overruns. */
1246 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1247 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA &&
1248 (ch->quirks & MVS_Q_SOC) == 0 &&
1260 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1262 if (ch->numpslots == 0 || ch->basic_dma) {
1263 slot->state = MVS_SLOT_LOADING;
1264 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map,
1265 ccb, mvs_dmasetprd, slot, 0);
1267 mvs_legacy_execute_transaction(slot);
1270 /* Locked by busdma engine. */
1272 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1274 struct mvs_slot *slot = arg;
1275 struct mvs_channel *ch = device_get_softc(slot->dev);
1276 struct mvs_eprd *eprd;
1280 device_printf(slot->dev, "DMA load error\n");
1281 mvs_end_transaction(slot, MVS_ERR_INVALID);
1284 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n"));
1285 /* If there is only one segment - no need to use S/G table on Gen-IIe. */
1286 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) {
1287 slot->dma.addr = segs[0].ds_addr;
1288 slot->dma.len = segs[0].ds_len;
1291 /* Get a piece of the workspace for this EPRD */
1292 eprd = (struct mvs_eprd *)
1293 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot));
1294 /* Fill S/G table */
1295 for (i = 0; i < nsegs; i++) {
1296 eprd[i].prdbal = htole32(segs[i].ds_addr);
1297 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK);
1298 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16);
1300 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF);
1302 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1303 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1304 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1306 mvs_legacy_execute_transaction(slot);
1308 mvs_execute_transaction(slot);
1312 mvs_legacy_execute_transaction(struct mvs_slot *slot)
1314 device_t dev = slot->dev;
1315 struct mvs_channel *ch = device_get_softc(dev);
1317 union ccb *ccb = slot->ccb;
1318 int port = ccb->ccb_h.target_id & 0x0f;
1321 slot->state = MVS_SLOT_RUNNING;
1322 ch->rslots |= (1 << slot->slot);
1323 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
1324 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1325 mvs_tfd_write(dev, ccb);
1326 /* Device reset doesn't interrupt. */
1327 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) {
1328 int timeout = 1000000;
1331 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS);
1332 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--);
1333 mvs_legacy_intr(dev, 1);
1337 if (ccb->ataio.cmd.command == ATA_READ_MUL ||
1338 ccb->ataio.cmd.command == ATA_READ_MUL48 ||
1339 ccb->ataio.cmd.command == ATA_WRITE_MUL ||
1340 ccb->ataio.cmd.command == ATA_WRITE_MUL48) {
1341 ch->transfersize = min(ccb->ataio.dxfer_len,
1342 ch->curr[port].bytecount);
1344 ch->transfersize = min(ccb->ataio.dxfer_len, 512);
1345 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE)
1347 /* If data write command - output the data */
1348 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1349 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
1351 "timeout waiting for write DRQ\n");
1352 xpt_freeze_simq(ch->sim, 1);
1353 ch->toslots |= (1 << slot->slot);
1354 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1357 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1358 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
1359 ch->transfersize / 2);
1363 ch->transfersize = min(ccb->csio.dxfer_len,
1364 ch->curr[port].bytecount);
1365 /* Write ATA PACKET command. */
1366 if (ch->basic_dma) {
1367 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA);
1368 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0);
1369 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0);
1371 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0);
1372 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize);
1373 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8);
1375 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD);
1377 /* Wait for ready to write ATAPI command block */
1378 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) {
1379 device_printf(dev, "timeout waiting for ATAPI !BUSY\n");
1380 xpt_freeze_simq(ch->sim, 1);
1381 ch->toslots |= (1 << slot->slot);
1382 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1387 int reason = ATA_INB(ch->r_mem, ATA_IREASON);
1388 int status = ATA_INB(ch->r_mem, ATA_STATUS);
1390 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
1391 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
1397 "timeout waiting for ATAPI command ready\n");
1398 xpt_freeze_simq(ch->sim, 1);
1399 ch->toslots |= (1 << slot->slot);
1400 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1403 /* Write ATAPI command. */
1404 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1405 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1406 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes),
1407 ch->curr[port].atapi / 2);
1409 if (ch->basic_dma) {
1410 /* Start basic DMA. */
1411 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET +
1412 (MVS_EPRD_SIZE * slot->slot);
1413 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd);
1414 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16);
1415 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START |
1416 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ?
1420 /* Start command execution timeout */
1421 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000,
1422 (timeout_t*)mvs_timeout, slot);
1425 /* Must be called with channel locked. */
1427 mvs_execute_transaction(struct mvs_slot *slot)
1429 device_t dev = slot->dev;
1430 struct mvs_channel *ch = device_get_softc(dev);
1432 struct mvs_crqb *crqb;
1433 struct mvs_crqb_gen2e *crqb2e;
1434 union ccb *ccb = slot->ccb;
1435 int port = ccb->ccb_h.target_id & 0x0f;
1438 /* Get address of the prepared EPRD */
1439 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot);
1440 /* Prepare CRQB. Gen IIe uses different CRQB format. */
1441 if (ch->quirks & MVS_Q_GENIIE) {
1442 crqb2e = (struct mvs_crqb_gen2e *)
1443 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1444 crqb2e->ctrlflg = htole32(
1445 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) |
1446 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) |
1447 (port << MVS_CRQB2E_PMP_SHIFT) |
1448 (slot->slot << MVS_CRQB2E_HTAG_SHIFT));
1449 /* If there is only one segment - no need to use S/G table. */
1450 if (slot->dma.addr != 0) {
1451 eprd = slot->dma.addr;
1452 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD);
1453 crqb2e->drbc = slot->dma.len;
1455 crqb2e->cprdbl = htole32(eprd);
1456 crqb2e->cprdbh = htole32((eprd >> 16) >> 16);
1459 crqb2e->cmd[2] = ccb->ataio.cmd.command;
1460 crqb2e->cmd[3] = ccb->ataio.cmd.features;
1461 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low;
1462 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid;
1463 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high;
1464 crqb2e->cmd[7] = ccb->ataio.cmd.device;
1465 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp;
1466 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp;
1467 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp;
1468 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp;
1469 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1470 crqb2e->cmd[12] = slot->tag << 3;
1471 crqb2e->cmd[13] = 0;
1473 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count;
1474 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp;
1476 crqb2e->cmd[14] = 0;
1477 crqb2e->cmd[15] = 0;
1479 crqb = (struct mvs_crqb *)
1480 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1481 crqb->cprdbl = htole32(eprd);
1482 crqb->cprdbh = htole32((eprd >> 16) >> 16);
1483 crqb->ctrlflg = htole16(
1484 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) |
1485 (slot->slot << MVS_CRQB_TAG_SHIFT) |
1486 (port << MVS_CRQB_PMP_SHIFT));
1489 * Controller can handle only 11 of 12 ATA registers,
1490 * so we have to choose which one to skip.
1492 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1493 crqb->cmd[i++] = ccb->ataio.cmd.features_exp;
1494 crqb->cmd[i++] = 0x11;
1496 crqb->cmd[i++] = ccb->ataio.cmd.features;
1497 crqb->cmd[i++] = 0x11;
1498 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1499 crqb->cmd[i++] = slot->tag << 3;
1500 crqb->cmd[i++] = 0x12;
1502 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp;
1503 crqb->cmd[i++] = 0x12;
1504 crqb->cmd[i++] = ccb->ataio.cmd.sector_count;
1505 crqb->cmd[i++] = 0x12;
1507 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp;
1508 crqb->cmd[i++] = 0x13;
1509 crqb->cmd[i++] = ccb->ataio.cmd.lba_low;
1510 crqb->cmd[i++] = 0x13;
1511 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp;
1512 crqb->cmd[i++] = 0x14;
1513 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid;
1514 crqb->cmd[i++] = 0x14;
1515 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp;
1516 crqb->cmd[i++] = 0x15;
1517 crqb->cmd[i++] = ccb->ataio.cmd.lba_high;
1518 crqb->cmd[i++] = 0x15;
1519 crqb->cmd[i++] = ccb->ataio.cmd.device;
1520 crqb->cmd[i++] = 0x16;
1521 crqb->cmd[i++] = ccb->ataio.cmd.command;
1522 crqb->cmd[i++] = 0x97;
1524 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1525 BUS_DMASYNC_PREWRITE);
1526 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1527 BUS_DMASYNC_PREREAD);
1528 slot->state = MVS_SLOT_RUNNING;
1529 ch->rslots |= (1 << slot->slot);
1530 /* Issue command to the controller. */
1531 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1);
1532 ATA_OUTL(ch->r_mem, EDMA_REQQIP,
1533 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1534 /* Start command execution timeout */
1535 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000,
1536 (timeout_t*)mvs_timeout, slot);
1540 /* Must be called with channel locked. */
1542 mvs_process_timeout(device_t dev)
1544 struct mvs_channel *ch = device_get_softc(dev);
1547 mtx_assert(&ch->mtx, MA_OWNED);
1548 /* Handle the rest of commands. */
1549 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1550 /* Do we have a running request on slot? */
1551 if (ch->slot[i].state < MVS_SLOT_RUNNING)
1553 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT);
1557 /* Must be called with channel locked. */
1559 mvs_rearm_timeout(device_t dev)
1561 struct mvs_channel *ch = device_get_softc(dev);
1564 mtx_assert(&ch->mtx, MA_OWNED);
1565 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1566 struct mvs_slot *slot = &ch->slot[i];
1568 /* Do we have a running request on slot? */
1569 if (slot->state < MVS_SLOT_RUNNING)
1571 if ((ch->toslots & (1 << i)) == 0)
1573 callout_reset(&slot->timeout,
1574 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1575 (timeout_t*)mvs_timeout, slot);
1579 /* Locked by callout mechanism. */
1581 mvs_timeout(struct mvs_slot *slot)
1583 device_t dev = slot->dev;
1584 struct mvs_channel *ch = device_get_softc(dev);
1586 /* Check for stale timeout. */
1587 if (slot->state < MVS_SLOT_RUNNING)
1589 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1590 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x "
1591 "dma_c %08x dma_s %08x rs %08x status %02x\n",
1592 ATA_INL(ch->r_mem, EDMA_IEC),
1593 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE),
1594 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C),
1595 ATA_INL(ch->r_mem, DMA_S), ch->rslots,
1596 ATA_INB(ch->r_mem, ATA_ALTSTAT));
1597 /* Handle frozen command. */
1598 mvs_requeue_frozen(dev);
1599 /* We wait for other commands timeout and pray. */
1600 if (ch->toslots == 0)
1601 xpt_freeze_simq(ch->sim, 1);
1602 ch->toslots |= (1 << slot->slot);
1603 if ((ch->rslots & ~ch->toslots) == 0)
1604 mvs_process_timeout(dev);
1606 device_printf(dev, " ... waiting for slots %08x\n",
1607 ch->rslots & ~ch->toslots);
1610 /* Must be called with channel locked. */
1612 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
1614 device_t dev = slot->dev;
1615 struct mvs_channel *ch = device_get_softc(dev);
1616 union ccb *ccb = slot->ccb;
1619 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1620 BUS_DMASYNC_POSTWRITE);
1621 /* Read result registers to the result struct
1622 * May be incorrect if several commands finished same time,
1623 * so read only when sure or have to.
1625 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1626 struct ata_res *res = &ccb->ataio.res;
1628 if ((et == MVS_ERR_TFE) ||
1629 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1630 mvs_tfd_read(dev, ccb);
1632 bzero(res, sizeof(*res));
1634 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1636 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount;
1638 if (ch->numpslots == 0 || ch->basic_dma) {
1639 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1640 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1641 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1642 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1643 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1646 if (et != MVS_ERR_NONE)
1647 ch->eslots |= (1 << slot->slot);
1648 /* In case of error, freeze device for proper recovery. */
1649 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) &&
1650 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1651 xpt_freeze_devq(ccb->ccb_h.path, 1);
1652 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1654 /* Set proper result status. */
1655 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1658 ccb->ccb_h.status |= CAM_REQ_CMP;
1659 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1660 ccb->csio.scsi_status = SCSI_STATUS_OK;
1662 case MVS_ERR_INVALID:
1664 ccb->ccb_h.status |= CAM_REQ_INVALID;
1666 case MVS_ERR_INNOCENT:
1667 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1671 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1672 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1673 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1675 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1680 if (!ch->recoverycmd) {
1681 xpt_freeze_simq(ch->sim, 1);
1682 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1683 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1685 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1687 case MVS_ERR_TIMEOUT:
1688 if (!ch->recoverycmd) {
1689 xpt_freeze_simq(ch->sim, 1);
1690 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1691 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1693 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1697 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1700 ch->oslots &= ~(1 << slot->slot);
1701 ch->rslots &= ~(1 << slot->slot);
1702 ch->aslots &= ~(1 << slot->slot);
1703 slot->state = MVS_SLOT_EMPTY;
1705 /* Update channel stats. */
1707 ch->numrslotspd[ccb->ccb_h.target_id]--;
1708 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1709 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1710 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag);
1712 ch->numtslotspd[ccb->ccb_h.target_id]--;
1713 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1722 /* Cancel timeout state if request completed normally. */
1723 if (et != MVS_ERR_TIMEOUT) {
1724 lastto = (ch->toslots == (1 << slot->slot));
1725 ch->toslots &= ~(1 << slot->slot);
1727 xpt_release_simq(ch->sim, TRUE);
1729 /* If it was our READ LOG command - process it. */
1730 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1731 mvs_process_read_log(dev, ccb);
1732 /* If it was our REQUEST SENSE command - process it. */
1733 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1734 mvs_process_request_sense(dev, ccb);
1735 /* If it was NCQ or ATAPI command error, put result on hold. */
1736 } else if (et == MVS_ERR_NCQ ||
1737 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1738 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1739 ch->hold[slot->slot] = ccb;
1740 ch->holdtag[slot->slot] = slot->tag;
1744 /* If we have no other active commands, ... */
1745 if (ch->rslots == 0) {
1746 /* if there was fatal error - reset port. */
1747 if (ch->toslots != 0 || ch->fatalerr) {
1750 /* if we have slots in error, we can reinit port. */
1751 if (ch->eslots != 0) {
1752 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1755 /* if there commands on hold, we can do READ LOG. */
1756 if (!ch->recoverycmd && ch->numhslots)
1757 mvs_issue_recovery(dev);
1759 /* If all the rest of commands are in timeout - give them chance. */
1760 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1761 et != MVS_ERR_TIMEOUT)
1762 mvs_rearm_timeout(dev);
1763 /* Unfreeze frozen command. */
1764 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
1765 union ccb *fccb = ch->frozen;
1767 mvs_begin_transaction(dev, fccb);
1768 xpt_release_simq(ch->sim, TRUE);
1770 /* Start PM timer. */
1771 if (ch->numrslots == 0 && ch->pm_level > 3 &&
1772 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1773 callout_schedule(&ch->pm_timer,
1774 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1779 mvs_issue_recovery(device_t dev)
1781 struct mvs_channel *ch = device_get_softc(dev);
1783 struct ccb_ataio *ataio;
1784 struct ccb_scsiio *csio;
1787 /* Find some held command. */
1788 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1792 ccb = xpt_alloc_ccb_nowait();
1794 device_printf(dev, "Unable to allocate recovery command\n");
1796 /* We can't do anything -- complete held commands. */
1797 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1798 if (ch->hold[i] == NULL)
1800 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1801 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
1802 xpt_done(ch->hold[i]);
1809 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
1810 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1812 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
1813 ccb->ccb_h.func_code = XPT_ATA_IO;
1814 ccb->ccb_h.flags = CAM_DIR_IN;
1815 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1816 ataio = &ccb->ataio;
1817 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT);
1818 if (ataio->data_ptr == NULL) {
1821 "Unable to allocate memory for READ LOG command\n");
1824 ataio->dxfer_len = 512;
1825 bzero(&ataio->cmd, sizeof(ataio->cmd));
1826 ataio->cmd.flags = CAM_ATAIO_48BIT;
1827 ataio->cmd.command = 0x2F; /* READ LOG EXT */
1828 ataio->cmd.sector_count = 1;
1829 ataio->cmd.sector_count_exp = 0;
1830 ataio->cmd.lba_low = 0x10;
1831 ataio->cmd.lba_mid = 0;
1832 ataio->cmd.lba_mid_exp = 0;
1835 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
1836 ccb->ccb_h.recovery_slot = i;
1837 ccb->ccb_h.func_code = XPT_SCSI_IO;
1838 ccb->ccb_h.flags = CAM_DIR_IN;
1839 ccb->ccb_h.status = 0;
1840 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1842 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
1843 csio->dxfer_len = ch->hold[i]->csio.sense_len;
1845 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
1846 csio->cdb_io.cdb_bytes[0] = 0x03;
1847 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
1849 /* Freeze SIM while doing recovery. */
1850 ch->recoverycmd = 1;
1851 xpt_freeze_simq(ch->sim, 1);
1852 mvs_begin_transaction(dev, ccb);
1856 mvs_process_read_log(device_t dev, union ccb *ccb)
1858 struct mvs_channel *ch = device_get_softc(dev);
1860 struct ata_res *res;
1863 ch->recoverycmd = 0;
1865 data = ccb->ataio.data_ptr;
1866 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
1867 (data[0] & 0x80) == 0) {
1868 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1871 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1873 if ((data[0] & 0x1F) == ch->holdtag[i]) {
1874 res = &ch->hold[i]->ataio.res;
1875 res->status = data[2];
1876 res->error = data[3];
1877 res->lba_low = data[4];
1878 res->lba_mid = data[5];
1879 res->lba_high = data[6];
1880 res->device = data[7];
1881 res->lba_low_exp = data[8];
1882 res->lba_mid_exp = data[9];
1883 res->lba_high_exp = data[10];
1884 res->sector_count = data[12];
1885 res->sector_count_exp = data[13];
1887 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1888 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
1890 xpt_done(ch->hold[i]);
1895 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
1896 device_printf(dev, "Error while READ LOG EXT\n");
1897 else if ((data[0] & 0x80) == 0) {
1899 "Non-queued command error in READ LOG EXT\n");
1901 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1904 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1906 xpt_done(ch->hold[i]);
1911 free(ccb->ataio.data_ptr, M_MVS);
1913 xpt_release_simq(ch->sim, TRUE);
1917 mvs_process_request_sense(device_t dev, union ccb *ccb)
1919 struct mvs_channel *ch = device_get_softc(dev);
1922 ch->recoverycmd = 0;
1924 i = ccb->ccb_h.recovery_slot;
1925 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
1926 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
1928 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1929 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
1931 xpt_done(ch->hold[i]);
1935 xpt_release_simq(ch->sim, TRUE);
1939 mvs_wait(device_t dev, u_int s, u_int c, int t)
1944 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) {
1947 device_printf(dev, "Wait status %02x\n", st);
1957 mvs_requeue_frozen(device_t dev)
1959 struct mvs_channel *ch = device_get_softc(dev);
1960 union ccb *fccb = ch->frozen;
1964 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1965 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1966 xpt_freeze_devq(fccb->ccb_h.path, 1);
1967 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1974 mvs_reset_to(void *arg)
1977 struct mvs_channel *ch = device_get_softc(dev);
1980 if (ch->resetting == 0)
1983 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) {
1986 "MVS reset: device ready after %dms\n",
1987 (310 - ch->resetting) * 100);
1990 xpt_release_simq(ch->sim, TRUE);
1993 if (ch->resetting == 0) {
1995 "MVS reset: device not ready after 31000ms\n");
1996 xpt_release_simq(ch->sim, TRUE);
1999 callout_schedule(&ch->reset_timer, hz / 10);
2003 mvs_errata(device_t dev)
2005 struct mvs_channel *ch = device_get_softc(dev);
2008 if (ch->quirks & MVS_Q_SOC65) {
2009 val = ATA_INL(ch->r_mem, SATA_PHYM3);
2010 val &= ~(0x3 << 27); /* SELMUPF = 1 */
2012 val &= ~(0x3 << 29); /* SELMUPI = 1 */
2014 ATA_OUTL(ch->r_mem, SATA_PHYM3, val);
2016 val = ATA_INL(ch->r_mem, SATA_PHYM4);
2017 val &= ~0x1; /* SATU_OD8 = 0 */
2018 val |= (0x1 << 16); /* reserved bit 16 = 1 */
2019 ATA_OUTL(ch->r_mem, SATA_PHYM4, val);
2021 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2);
2022 val &= ~0xf; /* TXAMP[3:0] = 8 */
2024 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2025 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val);
2027 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1);
2028 val &= ~0xf; /* TXAMP[3:0] = 8 */
2030 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2031 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val);
2036 mvs_reset(device_t dev)
2038 struct mvs_channel *ch = device_get_softc(dev);
2041 xpt_freeze_simq(ch->sim, 1);
2043 device_printf(dev, "MVS reset...\n");
2044 /* Forget about previous reset. */
2045 if (ch->resetting) {
2047 callout_stop(&ch->reset_timer);
2048 xpt_release_simq(ch->sim, TRUE);
2050 /* Requeue freezed command. */
2051 mvs_requeue_frozen(dev);
2052 /* Kill the engine and requeue all running commands. */
2053 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2054 ATA_OUTL(ch->r_mem, DMA_C, 0);
2055 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2056 /* Do we have a running request on slot? */
2057 if (ch->slot[i].state < MVS_SLOT_RUNNING)
2059 /* XXX; Commands in loading state. */
2060 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT);
2062 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2065 xpt_done(ch->hold[i]);
2069 if (ch->toslots != 0)
2070 xpt_release_simq(ch->sim, TRUE);
2075 /* Tell the XPT about the event */
2076 xpt_async(AC_BUS_RESET, ch->path, NULL);
2077 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
2078 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST);
2080 ATA_OUTL(ch->r_mem, EDMA_CMD, 0);
2082 /* Reset and reconnect PHY, */
2083 if (!mvs_sata_phy_reset(dev)) {
2085 device_printf(dev, "MVS reset: device not found\n");
2087 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2088 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2089 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2090 xpt_release_simq(ch->sim, TRUE);
2094 device_printf(dev, "MVS reset: device found\n");
2095 /* Wait for clearing busy status. */
2096 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ,
2097 dumping ? 31000 : 0)) < 0) {
2100 "MVS reset: device not ready after 31000ms\n");
2102 ch->resetting = 310;
2103 } else if (bootverbose)
2104 device_printf(dev, "MVS reset: device ready after %dms\n", i);
2106 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2107 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2108 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2110 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev);
2112 xpt_release_simq(ch->sim, TRUE);
2116 mvs_softreset(device_t dev, union ccb *ccb)
2118 struct mvs_channel *ch = device_get_softc(dev);
2119 int port = ccb->ccb_h.target_id & 0x0f;
2123 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2124 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
2125 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2127 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2128 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2129 /* Wait for clearing busy status. */
2130 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) {
2131 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2134 status = mvs_getstatus(dev, 0);
2135 if (status & ATA_S_ERROR)
2136 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2138 ccb->ccb_h.status |= CAM_REQ_CMP;
2139 if (status & ATA_S_DRQ)
2144 mvs_tfd_read(dev, ccb);
2147 * XXX: If some device on PMP failed to soft-reset,
2148 * try to recover by sending dummy soft-reset to PMP.
2150 if (stuck && ch->pm_present && port != 15) {
2151 ATA_OUTB(ch->r_mem, SATA_SATAICTL,
2152 15 << SATA_SATAICTL_PMPTX_SHIFT);
2153 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2155 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2156 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout);
2163 mvs_sata_connect(struct mvs_channel *ch)
2166 int timeout, found = 0;
2168 /* Wait up to 100ms for "connect well" */
2169 for (timeout = 0; timeout < 1000 ; timeout++) {
2170 status = ATA_INL(ch->r_mem, SATA_SS);
2171 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE)
2173 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
2174 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
2175 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE))
2177 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) {
2179 device_printf(ch->dev, "SATA offline status=%08x\n",
2184 if (found == 0 && timeout >= 100)
2188 if (timeout >= 1000 || !found) {
2190 device_printf(ch->dev,
2191 "SATA connect timeout time=%dus status=%08x\n",
2192 timeout * 100, status);
2197 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2198 timeout * 100, status);
2200 /* Clear SATA error register */
2201 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2206 mvs_sata_phy_reset(device_t dev)
2208 struct mvs_channel *ch = device_get_softc(dev);
2212 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2214 val = SATA_SC_SPD_SPEED_GEN1;
2215 else if (sata_rev == 2)
2216 val = SATA_SC_SPD_SPEED_GEN2;
2217 else if (sata_rev == 3)
2218 val = SATA_SC_SPD_SPEED_GEN3;
2221 ATA_OUTL(ch->r_mem, SATA_SC,
2222 SATA_SC_DET_RESET | val |
2223 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER);
2225 ATA_OUTL(ch->r_mem, SATA_SC,
2226 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2227 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER)));
2228 if (!mvs_sata_connect(ch)) {
2229 if (ch->pm_level > 0)
2230 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE);
2237 mvs_check_ids(device_t dev, union ccb *ccb)
2239 struct mvs_channel *ch = device_get_softc(dev);
2241 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) {
2242 ccb->ccb_h.status = CAM_TID_INVALID;
2246 if (ccb->ccb_h.target_lun != 0) {
2247 ccb->ccb_h.status = CAM_LUN_INVALID;
2255 mvsaction(struct cam_sim *sim, union ccb *ccb)
2257 device_t dev, parent;
2258 struct mvs_channel *ch;
2260 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n",
2261 ccb->ccb_h.func_code));
2263 ch = (struct mvs_channel *)cam_sim_softc(sim);
2265 switch (ccb->ccb_h.func_code) {
2266 /* Common cases first */
2267 case XPT_ATA_IO: /* Execute the requested I/O operation */
2269 if (mvs_check_ids(dev, ccb))
2271 if (ch->devices == 0 ||
2272 (ch->pm_present == 0 &&
2273 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2274 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2277 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2278 /* Check for command collision. */
2279 if (mvs_check_collision(dev, ccb)) {
2280 /* Freeze command. */
2282 /* We have only one frozen slot, so freeze simq also. */
2283 xpt_freeze_simq(ch->sim, 1);
2286 mvs_begin_transaction(dev, ccb);
2288 case XPT_EN_LUN: /* Enable LUN as a target */
2289 case XPT_TARGET_IO: /* Execute target I/O request */
2290 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2291 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2292 case XPT_ABORT: /* Abort the specified CCB */
2294 ccb->ccb_h.status = CAM_REQ_INVALID;
2296 case XPT_SET_TRAN_SETTINGS:
2298 struct ccb_trans_settings *cts = &ccb->cts;
2299 struct mvs_device *d;
2301 if (mvs_check_ids(dev, ccb))
2303 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2304 d = &ch->curr[ccb->ccb_h.target_id];
2306 d = &ch->user[ccb->ccb_h.target_id];
2307 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2308 d->revision = cts->xport_specific.sata.revision;
2309 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2310 d->mode = cts->xport_specific.sata.mode;
2311 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) {
2312 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048,
2313 cts->xport_specific.sata.bytecount);
2315 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2316 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags);
2317 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2318 ch->pm_present = cts->xport_specific.sata.pm_present;
2319 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2320 d->atapi = cts->xport_specific.sata.atapi;
2321 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2322 d->caps = cts->xport_specific.sata.caps;
2323 ccb->ccb_h.status = CAM_REQ_CMP;
2326 case XPT_GET_TRAN_SETTINGS:
2327 /* Get default/user set transfer settings for the target */
2329 struct ccb_trans_settings *cts = &ccb->cts;
2330 struct mvs_device *d;
2333 if (mvs_check_ids(dev, ccb))
2335 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2336 d = &ch->curr[ccb->ccb_h.target_id];
2338 d = &ch->user[ccb->ccb_h.target_id];
2339 cts->protocol = PROTO_UNSPECIFIED;
2340 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2341 cts->transport = XPORT_SATA;
2342 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2343 cts->proto_specific.valid = 0;
2344 cts->xport_specific.sata.valid = 0;
2345 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2346 (ccb->ccb_h.target_id == 15 ||
2347 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2348 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK;
2349 if (status & 0x0f0) {
2350 cts->xport_specific.sata.revision =
2351 (status & 0x0f0) >> 4;
2352 cts->xport_specific.sata.valid |=
2353 CTS_SATA_VALID_REVISION;
2355 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2356 // if (ch->pm_level)
2357 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2358 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2359 cts->xport_specific.sata.caps &=
2360 ch->user[ccb->ccb_h.target_id].caps;
2361 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2363 cts->xport_specific.sata.revision = d->revision;
2364 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2365 cts->xport_specific.sata.caps = d->caps;
2366 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* &&
2367 (ch->quirks & MVS_Q_GENIIE) == 0*/)
2368 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN;
2369 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2371 cts->xport_specific.sata.mode = d->mode;
2372 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2373 cts->xport_specific.sata.bytecount = d->bytecount;
2374 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2375 cts->xport_specific.sata.pm_present = ch->pm_present;
2376 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2377 cts->xport_specific.sata.tags = d->tags;
2378 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2379 cts->xport_specific.sata.atapi = d->atapi;
2380 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2381 ccb->ccb_h.status = CAM_REQ_CMP;
2384 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2385 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2387 ccb->ccb_h.status = CAM_REQ_CMP;
2389 case XPT_TERM_IO: /* Terminate the I/O process */
2391 ccb->ccb_h.status = CAM_REQ_INVALID;
2393 case XPT_PATH_INQ: /* Path routing inquiry */
2395 struct ccb_pathinq *cpi = &ccb->cpi;
2397 parent = device_get_parent(dev);
2398 cpi->version_num = 1; /* XXX??? */
2399 cpi->hba_inquiry = PI_SDTR_ABLE;
2400 if (!(ch->quirks & MVS_Q_GENI)) {
2401 cpi->hba_inquiry |= PI_SATAPM;
2402 /* Gen-II is extremely slow with NCQ on PMP. */
2403 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0)
2404 cpi->hba_inquiry |= PI_TAG_ABLE;
2406 cpi->target_sprt = 0;
2407 cpi->hba_misc = PIM_SEQSCAN;
2408 cpi->hba_eng_cnt = 0;
2409 if (!(ch->quirks & MVS_Q_GENI))
2410 cpi->max_target = 15;
2412 cpi->max_target = 0;
2414 cpi->initiator_id = 0;
2415 cpi->bus_id = cam_sim_bus(sim);
2416 cpi->base_transfer_speed = 150000;
2417 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2418 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN);
2419 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2420 cpi->unit_number = cam_sim_unit(sim);
2421 cpi->transport = XPORT_SATA;
2422 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2423 cpi->protocol = PROTO_ATA;
2424 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2425 cpi->maxio = MAXPHYS;
2426 if ((ch->quirks & MVS_Q_SOC) == 0) {
2427 cpi->hba_vendor = pci_get_vendor(parent);
2428 cpi->hba_device = pci_get_device(parent);
2429 cpi->hba_subvendor = pci_get_subvendor(parent);
2430 cpi->hba_subdevice = pci_get_subdevice(parent);
2432 cpi->ccb_h.status = CAM_REQ_CMP;
2436 ccb->ccb_h.status = CAM_REQ_INVALID;
2443 mvspoll(struct cam_sim *sim)
2445 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim);
2446 struct mvs_intr_arg arg;
2449 arg.cause = 2 | 4; /* XXX */
2451 if (ch->resetting != 0 &&
2452 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2453 ch->resetpolldiv = 1000;
2454 mvs_reset_to(ch->dev);