2 * Copyright (C) 2009-2012 Semihalf
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/ioccom.h>
33 #include <sys/types.h>
37 #define MAX_ECC_BYTES 512
38 #define MAX_BAD_BLOCKS 512
39 #define DEV_MODEL_STR_SIZE 21
40 #define MAN_STR_SIZE 13
41 #define FILENAME_SIZE 20
43 #define MAX_CHIPS (MAX_SIM_DEV*MAX_CTRL_CS)
45 #define NANDSIM_OUTPUT_NONE 0x0
46 #define NANDSIM_OUTPUT_CONSOLE 0x1
47 #define NANDSIM_OUTPUT_RAM 0x2
48 #define NANDSIM_OUTPUT_FILE 0x3
50 struct sim_ctrl_chip {
55 #define NANDSIM_BASE 'A'
62 #define NANDSIM_SIM_PARAM _IOW(NANDSIM_BASE, 1, struct sim_param)
70 char filename[FILENAME_SIZE];
71 uint16_t ecc_layout[MAX_ECC_BYTES];
73 #define NANDSIM_CREATE_CTRL _IOW(NANDSIM_BASE, 2, struct sim_ctrl)
74 #define NANDSIM_DESTROY_CTRL _IOW(NANDSIM_BASE, 3, int)
82 char device_model[DEV_MODEL_STR_SIZE];
83 char manufacturer[MAN_STR_SIZE];
84 uint8_t col_addr_cycles;
85 uint8_t row_addr_cycles;
91 uint32_t blks_per_lun;
101 uint32_t bad_block_map[MAX_BAD_BLOCKS];
105 #define NANDSIM_CREATE_CHIP _IOW(NANDSIM_BASE, 3, struct sim_chip)
107 struct sim_chip_destroy {
111 #define NANDSIM_DESTROY_CHIP _IOW(NANDSIM_BASE, 4, struct sim_chip_destroy)
113 #define NANDSIM_START_CTRL _IOW(NANDSIM_BASE, 5, int)
114 #define NANDSIM_STOP_CTRL _IOW(NANDSIM_BASE, 6, int)
115 #define NANDSIM_RESTART_CTRL _IOW(NANDSIM_BASE, 7, int)
117 #define NANDSIM_STATUS_CTRL _IOWR(NANDSIM_BASE, 8, struct sim_ctrl)
118 #define NANDSIM_STATUS_CHIP _IOWR(NANDSIM_BASE, 9, struct sim_chip)
126 #define SIM_MOD_LOG_LEVEL 0
127 #define SIM_MOD_ERASE_TIME 1
128 #define SIM_MOD_PROG_TIME 2
129 #define SIM_MOD_READ_TIME 3
130 #define SIM_MOD_CCS_TIME 4
131 #define SIM_MOD_ERROR_RATIO 5
133 #define NANDSIM_MODIFY _IOW(NANDSIM_BASE, 10, struct sim_mod)
134 #define NANDSIM_FREEZE _IOW(NANDSIM_BASE, 11, struct sim_ctrl_chip)
144 #define NANDSIM_INJECT_ERROR _IOW(NANDSIM_BASE, 20, struct sim_error)
146 #define NANDSIM_GOOD_BLOCK 0
147 #define NANDSIM_BAD_BLOCK 1
148 struct sim_block_state {
155 #define NANDSIM_SET_BLOCK_STATE _IOW(NANDSIM_BASE, 21, struct sim_block_state)
156 #define NANDSIM_GET_BLOCK_STATE _IOWR(NANDSIM_BASE, 22, struct sim_block_state)
163 #define NANDSIM_PRINT_LOG _IOWR(NANDSIM_BASE, 23, struct sim_log)
172 #define NANDSIM_DUMP _IOWR(NANDSIM_BASE, 24, struct sim_dump)
173 #define NANDSIM_RESTORE _IOWR(NANDSIM_BASE, 25, struct sim_dump)
175 #endif /* _NANDSIM_H_ */