2 * Copyright (C) 2012-2014 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __NVME_PRIVATE_H__
30 #define __NVME_PRIVATE_H__
32 #include <sys/param.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
40 #include <sys/systm.h>
41 #include <sys/taskqueue.h>
45 #include <machine/bus.h>
49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
51 MALLOC_DECLARE(M_NVME);
56 #define CHATHAM_PCI_ID 0x20118086
57 #define CHATHAM_CONTROL_BAR 0
60 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
61 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
64 * For commands requiring more than 2 PRP entries, one PRP will be
65 * embedded in the command (prp1), and the rest of the PRP entries
66 * will be in a list pointed to by the command (prp2). This means
67 * that real max number of PRP entries we support is 32+1, which
68 * results in a max xfer size of 32*PAGE_SIZE.
70 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE)
72 #define NVME_ADMIN_TRACKERS (16)
73 #define NVME_ADMIN_ENTRIES (128)
74 /* min and max are defined in admin queue attributes section of spec */
75 #define NVME_MIN_ADMIN_ENTRIES (2)
76 #define NVME_MAX_ADMIN_ENTRIES (4096)
79 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
80 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
81 * will allow outstanding on an I/O qpair at any time. The only advantage in
82 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
83 * the contents of the submission and completion queues, it will show a longer
86 #define NVME_IO_ENTRIES (256)
87 #define NVME_IO_TRACKERS (128)
88 #define NVME_MIN_IO_TRACKERS (4)
89 #define NVME_MAX_IO_TRACKERS (1024)
92 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
93 * for each controller.
96 #define NVME_INT_COAL_TIME (0) /* disabled */
97 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
99 #define NVME_MAX_NAMESPACES (16)
100 #define NVME_MAX_CONSUMERS (2)
101 #define NVME_MAX_ASYNC_EVENTS (8)
103 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
104 #define NVME_MIN_TIMEOUT_PERIOD (5)
105 #define NVME_MAX_TIMEOUT_PERIOD (120)
107 #define NVME_DEFAULT_RETRY_COUNT (4)
109 /* Maximum log page size to fetch for AERs. */
110 #define NVME_MAX_AER_LOG_SIZE (4096)
113 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
116 #ifndef CACHE_LINE_SIZE
117 #define CACHE_LINE_SIZE (64)
121 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O
122 * support and the bus_dmamap_load_bio API are available on the target
123 * kernel. This will ease porting back to earlier stable branches at a
127 #define NVME_UNMAPPED_BIO_SUPPORT
130 extern uma_zone_t nvme_request_zone;
131 extern int32_t nvme_retry_count;
133 struct nvme_completion_poll_status {
135 struct nvme_completion cpl;
139 #define NVME_REQUEST_VADDR 1
140 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */
141 #define NVME_REQUEST_UIO 3
142 #ifdef NVME_UNMAPPED_BIO_SUPPORT
143 #define NVME_REQUEST_BIO 4
146 struct nvme_request {
148 struct nvme_command cmd;
149 struct nvme_qpair *qpair;
155 uint32_t payload_size;
160 STAILQ_ENTRY(nvme_request) stailq;
163 struct nvme_async_event_request {
165 struct nvme_controller *ctrlr;
166 struct nvme_request *req;
167 struct nvme_completion cpl;
168 uint32_t log_page_id;
169 uint32_t log_page_size;
170 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
173 struct nvme_tracker {
175 TAILQ_ENTRY(nvme_tracker) tailq;
176 struct nvme_request *req;
177 struct nvme_qpair *qpair;
178 struct callout timer;
179 bus_dmamap_t payload_dma_map;
182 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES];
183 bus_addr_t prp_bus_addr;
184 bus_dmamap_t prp_dma_map;
189 struct nvme_controller *ctrlr;
195 struct resource *res;
198 uint32_t num_entries;
199 uint32_t num_trackers;
200 uint32_t sq_tdbl_off;
201 uint32_t cq_hdbl_off;
208 int64_t num_intr_handler_calls;
210 struct nvme_command *cmd;
211 struct nvme_completion *cpl;
213 bus_dma_tag_t dma_tag;
215 bus_dmamap_t cmd_dma_map;
216 uint64_t cmd_bus_addr;
218 bus_dmamap_t cpl_dma_map;
219 uint64_t cpl_bus_addr;
221 TAILQ_HEAD(, nvme_tracker) free_tr;
222 TAILQ_HEAD(, nvme_tracker) outstanding_tr;
223 STAILQ_HEAD(, nvme_request) queued_req;
225 struct nvme_tracker **act_tr;
227 boolean_t is_enabled;
229 struct mtx lock __aligned(CACHE_LINE_SIZE);
231 } __aligned(CACHE_LINE_SIZE);
233 struct nvme_namespace {
235 struct nvme_controller *ctrlr;
236 struct nvme_namespace_data data;
240 void *cons_cookie[NVME_MAX_CONSUMERS];
246 * One of these per allocated PCI device.
248 struct nvme_controller {
254 uint32_t ready_timeout_in_ms;
256 bus_space_tag_t bus_tag;
257 bus_space_handle_t bus_handle;
259 struct resource *resource;
262 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
263 * separate from the control registers which are in BAR 0/1. These
264 * members track the mapping of BAR 4/5 for that reason.
266 int bar4_resource_id;
267 struct resource *bar4_resource;
270 bus_space_tag_t chatham_bus_tag;
271 bus_space_handle_t chatham_bus_handle;
272 int chatham_resource_id;
273 struct resource *chatham_resource;
276 uint32_t msix_enabled;
278 uint32_t enable_aborts;
280 uint32_t num_io_queues;
281 boolean_t per_cpu_io_queues;
283 /* Fields for tracking progress during controller initialization. */
284 struct intr_config_hook config_hook;
285 uint32_t ns_identified;
286 uint32_t queues_created;
288 struct task reset_task;
289 struct task fail_req_task;
290 struct taskqueue *taskqueue;
292 struct resource *msi_res[MAXCPU + 1];
294 /* For shared legacy interrupt. */
296 struct resource *res;
299 bus_dma_tag_t hw_desc_tag;
300 bus_dmamap_t hw_desc_map;
302 /** maximum i/o size in bytes */
303 uint32_t max_xfer_size;
305 /** minimum page size supported by this controller in bytes */
306 uint32_t min_page_size;
308 /** interrupt coalescing time period (in microseconds) */
309 uint32_t int_coal_time;
311 /** interrupt coalescing threshold */
312 uint32_t int_coal_threshold;
314 /** timeout period in seconds */
315 uint32_t timeout_period;
317 struct nvme_qpair adminq;
318 struct nvme_qpair *ioq;
320 struct nvme_registers *regs;
322 struct nvme_controller_data cdata;
323 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
327 /** bit mask of warning types currently enabled for async events */
328 union nvme_critical_warning_state async_event_config;
331 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
333 void *cons_cookie[NVME_MAX_CONSUMERS];
335 uint32_t is_resetting;
336 uint32_t is_initialized;
337 uint32_t notification_sent;
340 STAILQ_HEAD(, nvme_request) fail_req;
343 uint64_t chatham_size;
344 uint64_t chatham_lbas;
348 #define nvme_mmio_offsetof(reg) \
349 offsetof(struct nvme_registers, reg)
351 #define nvme_mmio_read_4(sc, reg) \
352 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
353 nvme_mmio_offsetof(reg))
355 #define nvme_mmio_write_4(sc, reg, val) \
356 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
357 nvme_mmio_offsetof(reg), val)
359 #define nvme_mmio_write_8(sc, reg, val) \
361 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
362 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
363 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
364 nvme_mmio_offsetof(reg)+4, \
365 (val & 0xFFFFFFFF00000000UL) >> 32); \
369 #define chatham_read_4(softc, reg) \
370 bus_space_read_4((softc)->chatham_bus_tag, \
371 (softc)->chatham_bus_handle, reg)
373 #define chatham_write_8(sc, reg, val) \
375 bus_space_write_4((sc)->chatham_bus_tag, \
376 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \
377 bus_space_write_4((sc)->chatham_bus_tag, \
378 (sc)->chatham_bus_handle, reg+4, \
379 (val & 0xFFFFFFFF00000000UL) >> 32); \
382 #endif /* CHATHAM2 */
384 #if __FreeBSD_version < 800054
385 #define wmb() __asm volatile("sfence" ::: "memory")
386 #define mb() __asm volatile("mfence" ::: "memory")
389 #define nvme_printf(ctrlr, fmt, args...) \
390 device_printf(ctrlr->dev, fmt, ##args)
392 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
394 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
396 nvme_cb_fn_t cb_fn, void *cb_arg);
397 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
398 uint16_t nsid, void *payload,
399 nvme_cb_fn_t cb_fn, void *cb_arg);
400 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
401 uint32_t microseconds,
405 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
406 struct nvme_error_information_entry *payload,
407 uint32_t num_entries, /* 0 = max */
410 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
412 struct nvme_health_information_page *payload,
415 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
416 struct nvme_firmware_page *payload,
419 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
420 struct nvme_qpair *io_que, uint16_t vector,
421 nvme_cb_fn_t cb_fn, void *cb_arg);
422 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
423 struct nvme_qpair *io_que,
424 nvme_cb_fn_t cb_fn, void *cb_arg);
425 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
426 struct nvme_qpair *io_que,
427 nvme_cb_fn_t cb_fn, void *cb_arg);
428 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
429 struct nvme_qpair *io_que,
430 nvme_cb_fn_t cb_fn, void *cb_arg);
431 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
432 uint32_t num_queues, nvme_cb_fn_t cb_fn,
434 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
435 union nvme_critical_warning_state state,
436 nvme_cb_fn_t cb_fn, void *cb_arg);
437 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
438 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
440 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
442 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
443 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
444 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
445 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr);
446 void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
447 /* ctrlr defined as void * to allow use with config_intrhook. */
448 void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
449 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
450 struct nvme_request *req);
451 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
452 struct nvme_request *req);
453 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
454 struct nvme_request *req);
456 void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
457 uint16_t vector, uint32_t num_entries,
458 uint32_t num_trackers,
459 struct nvme_controller *ctrlr);
460 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
461 struct nvme_tracker *tr);
462 void nvme_qpair_process_completions(struct nvme_qpair *qpair);
463 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
464 struct nvme_request *req);
465 void nvme_qpair_reset(struct nvme_qpair *qpair);
466 void nvme_qpair_fail(struct nvme_qpair *qpair);
467 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
468 struct nvme_request *req,
469 uint32_t sct, uint32_t sc,
470 boolean_t print_on_error);
472 void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
473 void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
474 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
476 void nvme_io_qpair_enable(struct nvme_qpair *qpair);
477 void nvme_io_qpair_disable(struct nvme_qpair *qpair);
478 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
480 int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
481 struct nvme_controller *ctrlr);
482 void nvme_ns_destruct(struct nvme_namespace *ns);
484 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
486 void nvme_dump_command(struct nvme_command *cmd);
487 void nvme_dump_completion(struct nvme_completion *cpl);
490 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
492 uint64_t *bus_addr = (uint64_t *)arg;
494 *bus_addr = seg[0].ds_addr;
497 static __inline struct nvme_request *
498 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
500 struct nvme_request *req;
502 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
505 req->cb_arg = cb_arg;
511 static __inline struct nvme_request *
512 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
513 nvme_cb_fn_t cb_fn, void *cb_arg)
515 struct nvme_request *req;
517 req = _nvme_allocate_request(cb_fn, cb_arg);
519 req->type = NVME_REQUEST_VADDR;
520 req->u.payload = payload;
521 req->payload_size = payload_size;
526 static __inline struct nvme_request *
527 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
529 struct nvme_request *req;
531 req = _nvme_allocate_request(cb_fn, cb_arg);
533 req->type = NVME_REQUEST_NULL;
537 static __inline struct nvme_request *
538 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
540 struct nvme_request *req;
542 req = _nvme_allocate_request(cb_fn, cb_arg);
544 #ifdef NVME_UNMAPPED_BIO_SUPPORT
545 req->type = NVME_REQUEST_BIO;
548 req->type = NVME_REQUEST_VADDR;
549 req->u.payload = bio->bio_data;
550 req->payload_size = bio->bio_bcount;
556 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req)
558 void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
559 const struct nvme_completion *async_cpl,
560 uint32_t log_page_id, void *log_page_buffer,
561 uint32_t log_page_size);
562 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
563 void nvme_notify_new_controller(struct nvme_controller *ctrlr);
565 #endif /* __NVME_PRIVATE_H__ */